CYUSB3033-BZXC_技术文档

CYUSB3035

®

EZ-USB FX3S SuperSpeed USB Controller

■ Selectable clock input frequencies

❐ 19.2, 26, 38.4, and 52 MHz

❐ 19.2-MHz crystal input support

Features

■ Universal serial bus (USB) integration

❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0

■ Ultra low-power in core power-down mode

❐ Less than 60 µA with VBATT on

❐ 20 µA with VBATT off

specification 1.0

❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0

❐ High-speed On-The-Go (HS-OTG) host and peripheral com-

pliant with OTG Supplement Version 2.0

❐ Thirty-two physical endpoints

❐ Support for battery charging Spec 1.1 and accessory charger

adaptor (ACA) detection

■ Independent power domains for core and I/O

❐ Core operation at 1.2 V

❐ I2S, UART, and SPI operation at 1.8 to 3.3 V

❐ I²C operation at 1.2 V

■ General Programmable Interface (GPIF™ II)

❐ Programmable 100-MHz GPIF II enables connectivity to a

wide range of external devices

■ 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA)

package

❐ 8- and 16-bit data bus

■ EZ-USB^®software and development kit (DVK) for easy code

development

❐ As many as 16 configurable control signals

■ Mass storage support

❐ SD 3.0 (SDXC) UHS-1

Applications

❐ eMMC 4.41

■ Digital video camcorders

■ Digital still cameras

■ Printers

❐ Two ports that can support memory card sizes up to 2TB

■ System I/O expansion with two secure digital I/O (SDIO) ports

■ Native USB-attached storage (UAS), mass-storage class

(MSC), human interface device (HID), full, and Turbo-MTP™

support

■ Scanners

■ Video capture cards

■ Test and measurement equipment

■ Surveillance cameras

■ Personal navigation devices

■ Medical imaging devices

■ Video IP phones

■ Fully accessible 32-bit CPU

❐ ARM926EJ core with 200-MHz operation

❐ 512-KB or 256-KB embedded SRAM

■ Additional connectivity to the following peripherals

❐ I²C master controller at 1 MHz

❐ I2S master (transmitter only) at sampling frequencies of

32 kHz, 44.1 kHz, and 48 kHz

❐ UART support of up to 4 Mbps

❐ SPI master at 33 MHz

■ Portable media players

■ Industrial cameras

Logic Block Diagram

Cypress Semiconductor Corporation

Document Number: 001-84160 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•408-943-2600

Revised June 20, 2013

CYUSB3035

Contents

Functional Overview ..........................................................3

Configuration Options .....................................................15

Digital I/Os .........................................................................15

GPIOs .................................................................................15

System-level ESD .............................................................15

Pin Description .................................................................16

Absolute Maximum Ratings ............................................20

Operating Conditions .......................................................20

Application Examples ....................................................3

USB Interface ......................................................................4

OTG ...............................................................................4

ReNumeration ...............................................................5

EZ-Dtect ........................................................................5

VBUS Overvoltage Protection .......................................5

Carkit UART Mode ........................................................5

AC Timing Parameters .....................................................22

GPIF II Timing .............................................................22

Asynchronous SRAM Timing ......................................25

ADMux Timing for Asynchronous Access ...................28

Synchronous ADMux Timing .......................................30

Slave FIFO Interface ...................................................33

Synchronous Slave FIFO

Host Processor Interface (P-Port) .....................................6

GPIF II ...........................................................................6

Slave FIFO interface .....................................................6

Asynchronous SRAM ....................................................6

Asynchronous Address/Data Multiplexed ......................7

Synchronous ADMux Interface ......................................7

Processor MMC (PMMC) Slave Interface .....................7

Write Sequence Description ...............................................34

Asynchronous Slave FIFO

Read Sequence Description ...............................................35

Asynchronous Slave FIFO

Write Sequence Description ...............................................36

Storage Port Timing ....................................................38

Serial Peripherals Timing ............................................41

CPU ......................................................................................8

Storage Port (S-Port) ..........................................................8

SD/MMC Clock Stop .....................................................8

SD_CLK Output Clock Stop ..........................................8

Card Insertion and Removal Detection .........................8

Write Protection (WP) ....................................................9

SDIO Interrupt ...............................................................9

SDIO Read-Wait Feature ..............................................9

Reset Sequence ................................................................45

Package Diagram ..............................................................47

JTAG Interface ....................................................................9

Ordering Information ........................................................48

Other Interfaces ..................................................................9

UART Interface ..............................................................9

I2C Interface ..................................................................9

I2S Interface ..................................................................9

SPI Interface ..................................................................9

Ordering Code Definitions ...........................................48

Acronyms ..........................................................................49

Document Conventions ...................................................49

Units of Measure .........................................................49

Boot Options .....................................................................10

Document History Page ...................................................50

Reset ..................................................................................10

Hard Reset ..................................................................10

Soft Reset ....................................................................10

Sales, Solutions, and Legal Information ........................50

Worldwide Sales and Design Support .........................50

Products ......................................................................50

PSoC Solutions ...........................................................50

Clocking ............................................................................11

32-kHz Watchdog Timer Clock Input ...........................11

Power .................................................................................11

Power Modes ..............................................................12

Document Number: 001-84160 Rev. *B

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CYUSB3035

An integrated USB 2.0 OTG controller enables applications in

which FX3S may serve dual roles; for example, EZ-USB FX3S

may function as an OTG Host to MSC as well as HID-class

devices. FX3S contains 512 KB or 256 KB of on-chip SRAM for

code and data. EZ-USB FX3S also provides interfaces to

connect to serial peripherals such as UART, SPI, I²C, and I2S.

FX3S comes with application development tools. The software

development kit comes with application examples for

accelerating time to market.

Functional Overview

Cypress’s EZ-USB FX3S is the next-generation USB 3.0

peripheral controller, providing integrated and flexible features.

FX3S has a fully configurable, parallel, general programmable

interface called GPIF II, which can connect to any processor,

ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in

FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and

glueless connectivity to popular interfaces, such as

asynchronous SRAM, asynchronous and synchronous address

data multiplexed interfaces, and parallel ATA. FX3S has

integrated the USB 3.0 and USB 2.0 physical layers (PHYs)

along with a 32-bit ARM926EJ-S microprocessor for powerful

data processing and for building custom applications. It

implements an architecture that enables 185-MBps data transfer

from GPIF II to the USB interface.

FX3S complies with the USB 3.0 v1.0 specification and is also

backward compatible with USB 2.0. It also complies with the

Battery Charging Specification v1.1 and USB 2.0 OTG

Specification v2.0.

Application Examples

In a typical application (see Figure 1), FX3S functions as a

coprocessor and connects to an external processor, which

manages system-level functions. Figure 2 shows a typical appli-

cation diagram when FX3S functions as the main processor.

FX3S features an integrated storage controller and can support

up to two independent mass storage devices on its storage ports.

It can support SD 3.0 and eMMC 4.41 memory cards. It can also

support SDIO on these ports.

Figure 1. EZ-USB FX3S as a Coprocessor

Note

1. Assuming that GPIF II is configured for a 16-bit data bus (available with certain part numbers; see Ordering Information on page 48), synchronous interface operating

at 100 MHz. This number also includes protocol overheads.

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Figure 2. EZ-USB FX3S as Main Processor

Figure 3. USB Interface Signals

EZ-USB FX3S

USB Interface

FX3S complies with the following specifications and supports the

following features:

VBATT

■ Supports USB peripheral functionality compliant with the

USB 3.0 Specification Revision 1.0 and is also backward

compatible with the USB 2.0 Specification.

VBUS

OTG_ID

SSRX-

SSRX+

SSTX-

SSTX+

D-

■ Complies with OTG Supplement Revision 2.0. It supports

High-Speed,Full-Speed,andLow-SpeedOTGdual-roledevice

capability. As a peripheral, FX3S is capable of SuperSpeed,

High-Speed, and Full-Speed. As a host, it is capable of

High-Speed, Full-Speed, and Low-Speed.

D+

■ Supports Carkit Pass-Through UART functionality on USB

D+/D– lines based on the CEA-936A specification.

OTG

FX3S is compliant with the OTG Specification Revision 2.0. In

the OTG mode, FX3S supports both A and B device modes and

supports Control, Interrupt, Bulk, and Isochronous data

transfers.

■ Supports up to 16 IN and 16 OUT endpoints.

■ Supports the USB 3.0 Streams feature. It also supports USB

Attached SCSI (UAS) device-class to optimize mass-storage

access performance.

FX3S requires an external charge pump (either standalone or

integrated into a PMIC) to power VBUS in the OTG A-device

mode.

■ As a USB peripheral, FX3S supports UAS, USB Video Class

(UVC), Mass Storage Class (MSC), and Media Transfer

Protocol (MTP) USB peripheral classes. As a USB peripheral,

all other device classes are supported only in the pass-through

mode when handled entirely by a host processor external to

the device.

The Target Peripheral List for OTG host implementation consists

of MSC- and HID-class devices.

FX3S does not support Attach Detection Protocol (ADP).

■ As an OTG host, FX3S supports MSC and HID device classes.

Note When the USB port is not in use, disable the PHY and

transceiver to save power.

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OTG Connectivity

VBUS Overvoltage Protection

In OTG mode, FX3S can be configured to be an A, B, or dual-role

device. It can connect to the following:

The maximum input voltage on FX3S's VBUS pin is 6 V. A

charger can supply up to 9 V on VBUS. In this case, an external

overvoltage protection (OVP) device is required to protect FX3S

from damage on VBUS. Figure 4 shows the system application

diagram with an OVP device connected on VBUS. Refer to

Table 7 for the operating range of VBUS and VBATT.

■ ACA device

■ Targeted USB peripheral

■ SRP-capable USB peripheral

■ HNP-capable USB peripheral

■ OTG host

Figure 4. System Diagram with OVP Device For VBUS

POWER SUBSYSTEM

■ HNP-capable host

■ OTG device

ReNumeration

Because of FX3S's soft configuration, one chip can take on the

identities of multiple distinct USB devices.

EZ-USB FX3S

When first plugged into USB, FX3S enumerates automatically

with the Cypress Vendor ID (0x04B4) and downloads firmware

and USB descriptors over the USB interface. The downloaded

firmware executes an electrical disconnect and connect. FX3S

enumerates again, this time as a device defined by the

downloaded information. This patented two-step process, called

ReNumeration, happens instantly when the device is plugged in.

VBUS

OTG_ID

1

2

OVP device

SSRX-

SSRX+

SSTX-

SSTX+

D-

3

4

5

6

7

8

9

D+

GND

EZ-Dtect

FX3S supports USB Charger and accessory detection

(EZ-Dtect). The charger detection mechanism complies with the

Battery Charging Specification Revision 1.1. In addition to

supporting this version of the specification, FX3S also provides

hardware support to detect the resistance values on the ID pin.

Carkit UART Mode

The USB interface supports the Carkit UART mode (UART over

D+/D–) for non-USB serial data transfer. This mode is based on

the CEA-936A specification.

FX3S can detect the following resistance ranges:

■ Less than 10 Ω

In the Carkit UART mode, the output signaling voltage is 3.3 V.

When configured for the Carkit UART mode, TXD of UART

(output) is mapped to the D– line, and RXD of UART (input) is

mapped to the D+ line.

■ Less than 1 kΩ

■ 65 kΩ to 72 kΩ

■ 35 kΩ to 39 kΩ

In the Carkit UART mode, FX3S disables the USB transceiver

and D+ and D– pins serve as pass-through pins to connect to the

UART of the host processor. The Carkit UART signals may be

routed to the GPIF II interface or to GPIO[48] and GPIO[49], as

shown in Figure 5 on page 6.

■ 99.96 kΩ to 104.4 kΩ (102 kΩ ± 2%)

■ 119 kΩ to 132 kΩ

■ Higher than 220 kΩ

In this mode, FX3S supports a rate of up to 9600 bps.

■ 431.2 kΩ to 448.8 kΩ (440 kΩ ± 2%)

FX3S's charger detects a dedicated wall charger, Host/Hub

charger, and Host/Hub.

Document Number: 001-84160 Rev. *B

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Figure 5. Carkit UART Pass-through Block Diagram

Carkit UART Pass-through

UART_TXD

UART_RXD

TXD

RXD

RXD(DP)

TXD(DM)

(

)

Carkit UART Pass-through

Interface on GPIF II

DP

USB PHY

DM

GPIO[48]

(UART_TX)

Carkit UART Pass-through

Interface on GPIOs

GPIO[49]

(UART_RX)

tions are met. 8 kB of memory (separate from the 512 kB of

embedded SRAM) is dedicated to the GPIF II waveform where

the GPIF II descriptor is stored in a specific format.

Host Processor Interface (P-Port)

A configurable interface enables FX3S to communicate with

various devices such as Sensor, FPGA, Host Processor, or a

Bridge chip. FX3S supports the following P-Port interfaces.

Cypress’s GPIF II Designer Tool enables fast development of

GPIF II descriptors and includes examples for common inter-

faces.

■ GPIF II (16-bit)

Example implementations of GPIF II are the asynchronous slave

FIFO and synchronous slave FIFO interfaces.

■ Slave FIFO Interface

■ 16-bit Asynchronous SRAM Interface

Slave FIFO interface

■ 16-bit Asynchronous address/data multiplexed (ADMux)

The Slave FIFO interface signals are shown in Figure 6. This

interface allows an external processor to directly access up to

four buffers internal to FX3S. Further details of the Slave FIFO

interface are described on page 33.

Interface

■ 16-bit Synchronous address/data multiplexed (ADMux)

Interface

Note Access to all 32 buffers is also supported over the slave

FIFO interface. For details, contact Cypress Applications

Support.

■ Processor MMC slave Interface compatible with MMC System

specification, MMCA Technical Committee, Version 4.2 with

eMMC 4.3 and 4.4 Pass-Through boot

The following sections describe these P-Port interfaces.

Figure 6. Slave FIFO Interface

SLCS#

PKTEND

FLAGB

FLAGA

GPIF II

The high-performance GPIF II interface enables functionality

similar to, but more advanced than, FX2LP's GPIF and Slave

FIFO interfaces.

A[1:0]

External

Processor

D[15:0]

SLWR#

SLRD#

EZ-USB FX3S

The GPIF II is a programmable state machine that enables a

flexible interface that may function either as a master or slave in

industry-standard or proprietary interfaces. Both parallel and

serial interfaces may be implemented with GPIF II.

SLOE#

Here are a list of GPIF II features:

Note: Multiple Flags may be configured.

■ Functions as master or slave

■ Provides 256 firmware programmable states

■ Supports 8-bit and 16-bit parallel data bus

■ Enables interface frequencies up to 100 MHz

Asynchronous SRAM

This interface consists of standard asynchronous SRAM

interface signals as shown in Figure 7 on page 7. This interface

is used to access both the configuration registers and buffer

memory of FX3S. Both single-cycle and burst accesses are

supported by asynchronous interface signals.

■ Supports 16 configurable control pins when a 16/8 data bus is

used. Allcontrolpins can be either input/outputor bi-directional.

GPIF II state transitions are based on control input signals. The

control output signals are driven as a result of the GPIF II state

transitions. The INT# output signal can be controlled by GPIF II.

Refer to the GPIFII Designer tool. The GPIF II state machine’s

behavior is defined by a GPIF II descriptor. The GPIF II

descriptor is designed such that the required interface specifica-

The most significant address bit, A[7], determines whether the

configuration registers or buffer memory are accessed. When

the configuration registers are selected by asserting the address

bit A[7], the address bus bits A[6:0] point to a configuration

register. When A[7] is deasserted, the buffer memory is

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CYUSB3035

accessed as indicated by the P-Port DMA transfer register and

the transfer size is determined by the P-Port DMA transfer size

register.

ADV# must be LOW during the address phase of a read/write

operation. ADV# must be HIGH during the data phase of a

read/write operation, as shown in Figure 18 and Figure 19 on

page 28.

Application processors with a DMA controller that use address

auto-increment during DMA transfers, can override this by

connecting any higher-order address line (such as

Synchronous ADMux Interface

FX3S's P-Port supports a synchronous address/data

multiplexed interface. This operates at an interface frequency of

up to 100 MHz and supports a 16-bit data bus.

A[15]/A[23]/A[31]) of the application processor to FX3S’s A[7].

In the asynchronous SRAM mode, when reading from a buffer

memory, FX3S supports two methods of reading out next data

from the buffer. The next data may be read out on the rising edge

of OE# or by toggling the least significant address bit A[0].

The RDY output signal from the FX3S device indicates a data

valid for read transfers and is acknowledged for write transfers.

In this mode, the P-Port interface works with a 32.5-ns minimum

access cycle providing an interface data rate of up to 61.5 MB

per second.

Figure 9. Synchronous ADMux Interface

CLK

Figure 7. Asynchronous SRAM Interface

CE#

ADV#

A[7:0]

HOST

Processor

West Bridge

FX3S

A[0:7]/DQ[0:15]

HOST

PROCESSOR

WEST BRIDGE

DQ[15:0]

WE#

Benicia

FX3S

BENICIA

WE#

OE#

RDY

OE#

Asynchronous Address/Data Multiplexed

See the Synchronous ADMux Interface timing diagrams for

details.

The physical ADMux memory interface consists of signals shown

in Figure 8. This interface supports processors that implement a

multiplexed address/data bus.

Processor MMC (PMMC) Slave Interface

Figure 8. ADMux Memory Interface

FX3S supports an MMC slave interface on the P-Port. This

interface is named "PMMC" to distinguish it from the S-Port MMC

interface.

CE#

Figure 10 illustrates the signals used to connect to the host

processor.

ADV#

HOST

PROCESSOR

WEST BRIDGE

FX3S

A[7:0]/DQ[15:0]

WE#

The PMMC interface's GO_IRQ_STATE command allows FX3S

to communicate asynchronous events without requiring the INT#

signal. The use of the INT# signal is optional.

BENICIA

Figure 10. PMMC Interface Configuration

OE#

INT#

CLK

FX3S’s ADMux interface supports a 16-bit time-multiplexed

address/data SRAM bus.

CMD

HOST

WEST BRIDGE

FX3S

For read operations, assert both CE# and OE#.

PROCESSOR

BENICIA

For write operations, assert both CE# and WE#. OE# is "Don't

Care" during a write operation (during both address and data

phase of the write cycle). The input data is latched on the rising

edge of WE# or CE#, whichever occurs first. Latch the addresses

prior to the write operation by toggling Address Valid (ADV#).

Assert Address Valid (ADV#) during the address phase of the

write operation, as shown in Figure 19 on page 28.

DAT[7:0]

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The MMC slave interface features are as follows:

Storage Port (S-Port)

■ Interface operations are compatible with the MMC-System

Specification, MMCA Technical Committee, Version 4.2.

FX3S has two independent storage ports (S0-Port and S1-Port).

Both storage ports support the following specifications:

■ Supports booting from an eMMC device connected to the

S-Port. This feature is supported for eMMC devices operating

up to 52-MHz SDR.

■ MMC-system specification, MMCA Technical Committee,

Version 4.41

■ Supports PMMC interface voltage ranges of 1.7 V to 1.95 V

and 2.7 V to 3.6 V.

■ SD specification, Version 3.0

■ SDIOhostcontrollercompliantwithSDIOSpecificationVersion

2.00 (Jan.30, 2007)

■ Supportsopendrain(bothdriveandreceiveopendrainsignals)

on CMD pin to allow GO_IRQ_STATE (CMD40) for PMMC.

Both storage ports support the following features:

■ Interface clock-frequency range: 0 to 52 MHz.

■ Supports 1-bit, 4-bit, or 8-bit mode of operation. This

configuration is determined by the MMC initialization

procedure.

SD/MMC Clock Stop

FX3S supports the stop clock feature, which can save power if

the internal buffer is full when receiving data from the

SD/MMC/SDIO.

■ FX3S responds to standard initialization phase commands as

specified for the MMC 4.2 slave device.

SD_CLK Output Clock Stop

■ PMMC mode MMC 4.2 command classes: Class 0 (Basic),

Class 2 (Block read), and Class 4 (Block write), Class 9 (I/O).

During the data transfer, the SD_CLK clock can be enabled (on)

or disabled (stopped) at any time by the internal flow control

mechanism.

FX3S supports the following PMMC commands:

■ Class 0: Basic

SD_CLK output frequency is dynamically configurable using a

clock divisor from a system clock. The clock choice for the divisor

is user-configurable through a register. For example, the

following frequencies may be configured:

CMD0, CMD1, CMD2, CMD3, CMD4, CMD6, CMD7, CMD8,

CMD9, CMD10, CMD12, CMD13, CMD15, CMD19, CMD5

(wakeup support)

■ Class 2: Block Read

CMD16, CMD17, CMD18, CMD23

■ Class 4: Block Write

CMD16, CMD23, CMD24, CMD25

■ Class 9: I-O

■ 400 kHz – For the SD/MMC card initialization

■ 20 MHz – For a card with 0- to 20-MHz frequency

■ 24 MHz – For a card with 0- to 26-MHz frequency

■ 48 MHz – For a card with 0- to 52-MHz frequency

(48-MHz frequency on SD_CLK is supported when the clock

input to FX3S is 19.2 MHz or 38.4 MHz)

CMD39, CMD40

CPU

■ 52 MHz – For a card with 0- to 52-MHz frequency

(52-MHz frequency on SD_CLK is supported when the clock

input to FX3S is 26 MHz or 52 MHz)

FX3S has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.

The core has direct access to 16 kB of Instruction Tightly

Coupled Memory (TCM) and 8 kB of Data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware

debugging.

■ 100 MHz – For a card with 0- to 100-MHz frequency

If the DDR mode is selected, data is clocked on both the rising

and falling edge of the SD clock. DDR clocks run up to 52 MHz.

FX3S offers the following advantages:

Card Insertion and Removal Detection

■ Integrates 512 KB of embedded SRAM for code and data and

8 KB of Instruction cache and Data cache.

FX3S supports the two-card insertion and removal detection

mechanisms.

■ ImplementsefficientandflexibleDMAconnectivitybetweenthe

various peripherals (such as, USB, GPIF II, I²S, SPI, UART),

requiring firmware only to configure data accesses between

peripherals, which are then managed by the DMA fabric.

■ Use of SD_D[3] data: During system design, this signal must

have an external 470-kΩ pull-down resistor connected to

SD_D[3]. SD cards have an internal 10-kΩ pull-up resistor.

When the card is inserted or removed from the SD/MMC

connector, the voltage level at the SD_D[3] pin changes and

triggers an interrupt to the CPU. The older generations of MMC

cards do not support this card detection mechanism.

■ Allows easy application development on industry-standard

development tools for ARM926EJ-S.

Examples of the FX3S firmware are available with the Cypress

EZ-USB FX3S Development Kit. Software APIs that can be

ported to an external processor are available with the Cypress

EZ-USB FX3S Software Development Kit.

■ UseoftheS0/S1_INSpin:SomeSD/MMCconnectorsfacilitate

a micro switch for card insertion/removal detection. This micro

switch can be connected to S0/S1_INS. When the card is

inserted or removed from the SD/MMC connector, it turns the

micro switch on and off. This changes the voltage level at the

pin that triggers the interrupt tothe CPU. The card-detect micro

switch polarity is assumed to be the same as the write-protect

Document Number: 001-84160 Rev. *B

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CYUSB3035

2

micro switch polarity. A low indicates that the card is inserted.

This S0/S1_INS pin is shared between the two S-Ports.

Register configuration determines which port gets to use this

pin. This pin is mapped to the S1VDDQ power domain; if

S0VDDQ and S1VDDQ are at different voltage levels, this pin

cannot be used as S1_INS.

I C Interface

FX3S’s I²C interface is compatible with the I²C Bus Specification

Revision 3. This I²C interface is capable of operating only as I²C

master; therefore, it may be used to communicate with other I²C

slave devices. For example, FX3S may boot from an EEPROM

connected to the I²C interface, as a selectable boot option.

FX3S’s I²C Master Controller also supports multi-master mode

functionality.

The power supply for the I²C interface is VIO5, which is a

separate power domain from the other serial peripherals. This

gives the I²C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I²C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I²C controller supports the clock-stretching

feature to enable slower devices to exercise flow control.

Write Protection (WP)

The S0_WP/S1_WP (SD Write Protection) on S-Port is used to

connect to the WP micro switch of SD/MMC card connector. This

pin internally connects to a CPU-accessible GPIO for firmware

to detect the SD card write protection.

SDIO Interrupt

The SDIO interrupt functionality is supported as specified in the

SDIO specification Version 2.00 (January 30, 2007).

SDIO Read-Wait Feature

FX3S supports the optional read-wait and suspend-resume

features as defined in the SDIO specification Version 2.00

(January 30, 2007).

The I²C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VIO5.

2

JTAG Interface

I S Interface

FX3S has an I²S port to support external audio codec devices.

FX3S functions as I²S Master as transmitter only. The I²S

interface consists of four signals: clock line (I2S_CLK), serial

data line (I2S_SD), word select line (I2S_WS), and master

system clock (I2S_MCLK). FX3S can generate the system clock

as an output on I2S_MCLK or accept an external system clock

input on I2S_MCLK.

FX3S’s JTAG interface has a standard five-pin interface to

connect to a JTAG debugger in order to debug firmware through

the CPU-core's on-chip-debug circuitry.

Industry-standard debugging tools for the ARM926EJ-S core

can be used for the FX3S application development.

Other Interfaces

The sampling frequencies supported by the I²S interface are

32 kHz, 44.1 kHz, and 48 kHz.

FX3S supports the following serial peripherals:

SPI Interface

■ UART

■ I²C

FX3S supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

■ I²S

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 44 for details on the

■ SPI

modes) with the Start-Stop clock. This controller is

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

a

The SPI, UART, and I²S interfaces are multiplexed on the serial

peripheral port.

UART Interface

The UART interface of FX3S supports full-duplex

communication. It includes the signals noted in Table 1.

Table 1. UART Interface Signals

Signal

TX

Description

Output signal

Input signal

Flow control

RX

CTS

RTS

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then FX3S's UART only transmits data when the CTS

input is asserted. In addition to this, FX3S's UART asserts the

RTS output signal, when it is ready to receive data.

Document Number: 001-84160 Rev. *B

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CYUSB3035

Soft Reset

Boot Options

In a soft reset, the processor sets the appropriate bits in the

PP_INIT control register. There are two types of Soft Reset:

FX3S can load boot images from various sources, selected by

the configuration of the PMODE pins. Following are the FX3S

boot options:

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Boot from USB

■ Boot from I²C

■ Whole Device Reset – This reset is identical to Hard Reset.

■ The firmware must be reloaded following a Whole Device

Reset.

■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),

M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents

Clocking

■ Boot from eMMC (S0-port)

■ Boot from GPIF II ASync ADMux mode

■ Boot from GPIF II Sync ADMux mode

■ Boot from GPIF II ASync SRAM mode

■ Boot from PMMC (P-Port)

FX3S allows either a crystal to be connected between the

XTALIN and XTALOUT pins or an external clock to be connected

at the CLKIN pin. The XTALIN, XTALOUT, CLKIN, and

CLKIN_32 pins can be left unconnected if they are not used.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

Table 2. FX3S Booting Options

FX3S has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3.

PMODE[2:0] ^[2]

Boot From

Sync ADMux (16-bit)

F00

F01

F10

F11

F0F

F1F

1FF

0F1

000

Async ADMux (16-bit)

PMMC Legacy

USB boot

Clock inputs to FX3S must meet the phase noise and jitter

requirements specified in Table 4 on page 11.

Async SRAM (16-bit)

I²C, On Failure, USB Boot is Enabled

I²C only

The input clock frequency is independent of the clock and data

rate of the FX3S core or any of the device interfaces (including

P-Port and S-Port). The internal PLL applies the appropriate

clock multiply option depending on the input frequency.

SPI, On Failure, USB Boot is Enabled

S0-Port (eMMC) On failure, USB boot

is enabled

Table 3. Crystal/Clock Frequency Selection

Crystal/Clock

100

S0-port (eMMC)

FSLC[2]

FSLC[1]

FSLC[0]

Frequency

Reset

0

1

0

1

0

1

0

1

19.2-MHz crystal

19.2-MHz input CLK

26-MHz input CLK

38.4-MHz input CLK

52-MHz input CLK

Hard Reset

A hard reset is initiated by asserting the Reset# pin on FX3S. The

specific reset sequence and timing requirements are detailed in

Figure 31 on page 46 and Table 19 on page 45. All I/Os are

tristated during a hard reset.

Note

2. F indicates Floating.

Document Number: 001-84160 Rev. *B

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CYUSB3035

Table 4. FX3S Input Clock Specifications

Parameter

Specification

Description

Units

Min

–

Max

–75

–104

–120

–128

–130

150

70

Phase noise

100-Hz offset

1- kHz offset

dB

ppm

%

–

10-kHz offset

100-kHz offset

1-MHz offset

–

Maximum frequency deviation

Duty cycle

–

30

–

Overshoot

3

%

Undershoot

–

–3

%

Rise time/fall time

–

3

ns

32-kHz Watchdog Timer Clock Input

Power

FX3S includes a watchdog timer. The watchdog timer can be

used to interrupt the ARM926EJ-S core, automatically wake up

the FX3S in Standby mode, and reset the ARM926EJ-S core.

The watchdog timer runs a 32-kHz clock, which may be

optionally supplied from an external source on a dedicated FX3S

pin.

FX3S has the following power supply domains:

■ IO_VDDQ: This is a group of independent supply domains for

digitalI/Os. Thevoltagelevelonthesesuppliesis1.8 Vto3.3 V.

FX3S provides six independent supply domains for digital I/Os

listed as follows (see Pin Description on page 16 for details on

each of the power domain signals):

The firmware can disable the watchdog timer.

❐ VIO1: GPIF II I/O

❐ VIO2: S0-Port Supply

❐ VIO3: S1-Port Supply

Requirements for the optional 32-kHz clock input are listed in

Table 5.

Table 5. 32-kHz Clock Input Requirements

❐ VIO4: S1-Port and Low Speed Peripherals (UART/SPI/I2S)

Supply

Parameter

Duty cycle

Min

40

–

Max

60

Units

%

❐ VIO5: I²C and JTAG (supports 1.2 V to 3.3 V)

❐ CVDDQ: Clock

Frequency deviation

Rise time/fall time

±200

200

ppm

ns

❐ V_DD: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

–

• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-

tor, and other core analog circuits

• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-

ages for the USB 3.0 interface.

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply for

the USB I/O and analog circuits. This supply powers the USB

transceiver through FX3S's internal voltage regulator. VBATT

is internally regulated to 3.3 V.

Document Number: 001-84160 Rev. *B

Page 11 of 50

CYUSB3035

❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be

turned off when the corresponding interface is not in use.

VIO1 cannot be turned off at any time if the GPIF II interface

is used in the application.

Power Modes

FX3S supports the following power modes:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐ Normal operating power consumption does not exceed the

sum of I_CCCore max and I_CCUSB max (see Table 7 for

current consumption specifications).

■ Low-power modes (see Table 6 on page 12):

❐ Suspend mode with USB 3.0 PHY enabled (L1)

❐ Suspend mode with USB 3.0 PHY disabled (L2)

❐ Standby mode (L3)

❐ Core power-down mode (L4)

Table 6. Entry and Exit Methods for Low-Power Modes

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend Mode

with USB 3.0 PHY

Enabled (L1)

■ The power consumption in this mode

does not exceed ISB₁

■ Firmware executing on ARM926EJ-S ■ D+ transitioning to low

core can put FX3S into suspend mode.

For example, on USB suspend

condition, firmware may decide to put

FX3S into suspend mode

or high

■ USB 3.0 PHY is enabled and is in U3

mode(oneofthesuspendmodesdefined

by the USB 3.0 specification). This one

block alone is operational with its internal ■ External Processor, through the use of

clock while all other clocks are shut down mailbox registers, can put FX3S into

■ D-transitioningtolowor

high

■ Impedance change on

OTG_ID pin

suspend mode

■ Resume condition on

SSRX±

■ All I/Os maintain their previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ Detection of VBUS

■ Level detect on

UART_CTS (program-

mable polarity)

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ GPIF II interface

assertion of CTL[0]

■ All transactions must be completed

before FX3S enters Suspend mode

(state of outstanding transactions are not

preserved)

■ Assertion of RESET#

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion)

because the program counter does not

reset

Document Number: 001-84160 Rev. *B

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CYUSB3035

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend Mode

with USB 3.0 PHY

Disabled (L2)

■ The power consumption in this mode

does not exceed ISB₂

■ Firmware executing on ARM926EJ-S ■ D+ transitioning to low

core can put FX3S into suspend mode.

For example, on USB suspend

condition, firmware may decide to put

FX3S into suspend mode

or high

■ USB 3.0 PHY is disabled and the USB

interface is in suspend mode

■ D-transitioningtolowor

high

■ The clocks are shut off. The PLLs are

disabled

■ Impedance change on

OTG_ID pin

■ External Processor, through the use of

mailbox registers can put FX3S into

suspend mode

■ All I/Os maintain their previous state

■ Resume condition on

SSRX±

■ USB interface maintains the previous

state

■ Detection of VBUS

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ Level detect on

UART_CTS (program-

mable polarity)

■ GPIF II interface

■ The states of the configuration registers,

buffer memory and all internal RAM are

maintained

assertion of CTL[0]

■ Assertion of RESET#

■ All transactions must be completed

before FX3S enters Suspend mode

(state of outstanding transactions are not

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion)

because the program counter does not

reset

Standby Mode

(L3)

■ The power consumption in this mode

does not exceed ISB3

■ Firmware executing on ARM926EJ-S ■ Detection of VBUS

core or external processor configures

the appropriate register

■ Level detect on

UART_CTS (Program-

■ All configuration register settings and

program/data RAM contents are

mable Polarity)

preserved. However, data in the buffers

or other parts of the data path, if any, is

not guaranteed. Therefore, the external

processor should take care that the data

needed is read before putting FX3S into

this Standby Mode

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

■ Theprogramcounterisresetafterwaking

up from Standby

■ GPIO pins maintain their configuration

■ Crystal oscillator is turned off

■ Internal PLL is turned off

■ USB transceiver is turned off

■ ARM926EJ-S core is powered down.

Uponwakeup, thecorere-startsandruns

the program stored in the program/data

RAM

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

Document Number: 001-84160 Rev. *B

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CYUSB3035

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode Characteristics

Core Power Down ■ The power consumption in this mode

Methods of Entry

■ Turn off V_DD

Methods of Exit

■ Reapply VDD

Mode (L4)

does not exceed ISB₄

■ Assertion of RESET#

■ Core power is turned off

■ All buffer memory, configuration

registers, and the program RAM do not

maintain state. After exiting this mode,

reload the firmware

■ Inthismode, allotherpowerdomainscan

be turned on/off individually

Document Number: 001-84160 Rev. *B

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CYUSB3035

Similarly, any unused pins on the serial peripheral interfaces may

be configured as GPIOs. See the Pin Description on page 16 for

pin configuration options.

Configuration Options

Configuration options are available for specific usage models.

Contact Cypress Applications or Marketing for details.

All GPIF II and GPIO pins support an external load of up to 16 pF

for every pin.

Digital I/Os

EMI

FX3S has internal firmware-controlled pull-up or pull-down

resistors on all digital I/O pins. An internal 50-kΩ resistor pulls

the pins high, while an internal 10-kΩ resistor pulls the pins low

to prevent them from floating. The I/O pins may have the

following states:

FX3S meets EMI requirements outlined by FCC 15B (USA) and

EN55022 (Europe) for consumer electronics. FX3S can tolerate

reasonable EMI, conducted by the aggressor, outlined by these

specifications and continue to function as expected.

■ Tristated (High-Z)

System-level ESD

■ Weak pull-up (via internal 50 kΩ)

FX3S has built-in ESD protection on the D+, D–, and GND pins

on the USB interface. The ESD protection levels provided on

these ports are:

■ Pull-down (via internal 10 kΩ)

■ Hold (I/O hold its value) when in low-power modes

■ ±2.2-KV human body model (HBM) based on JESD22-A114

Specification

■ The JTAG TDI, TMC, and TRST# signals have fixed 50-kΩ

internal pull-ups, and the TCK signal has a fixed 10-kΩ

pull-down resistor.

■ ±6-KV contact discharge and ±8-KV air gap discharge based

on IEC61000-4-2 level 3A

All unused I/Os should be pulled high by using the internal

pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength,

half-strength, or quarter-strength. These drive strengths are

configured separately for each interface.

■ ± 8-KV Contact Discharge and ±15-KV Air Gap Discharge

based on IEC61000-4-2 level 4C.

This protection ensures the device continues to function after

ESD events up to the levels stated in this section.

GPIOs

The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to

±2.2-KV HBM internal ESD protection.

EZ-USB enables a flexible pin configuration both on the GPIF II

and the serial peripheral interfaces. Any unused control pins

(except CTL[15]) on the GPIF II interface can be used as GPIOs.

Figure 11. FX3S Ball Map (Top View)

1

2

3

4

5

6

7

8

9

10

11

NC

U3VSSQ

VIO4

U3RXVDDQ

FSLC[0]

GPIO[55]

GPIO[51]

VSS

SSRXM

R_USB3

VDD

SSRXP

SSTXP

SSTXM

VSS

DP

DM

AVDD

AVSS

XTALOUT

CLKIN

A

B

C

D

E

F

G

H

J

FSLC[1]

GPIO[57]

GPIO[53]

GPIO[49]

GPIO[41]

GPIO[30]

GPIO[31]

GPIO[34]

VSS

U3TXVDDQ

RESET#

GPIO[56]

GPIO[48]

GPIO[46]

GPIO[25]

GPIO[29]

GPIO[28]

GPIO[27]

VDD

CVDDQ

XTALIN

CLKIN_32

FSLC[2]

TCK

VSS

TRST#

VIO5

O[60]

VSS

R_USB2

VSS

VDD

GPIO[54]

GPIO[50]

GPIO[47]

VIO2

OTG_ID

TDO

GPIO[52]

VIO3

I2C_GPIO[58] I2C_GPIO[59]

TDI

TMS

VDD

GPIO[1]

GPIO[4]

GPIO[7]

GPIO[9]

GPIO[13]

VIO1

VBATT

GPIO[0]

GPIO[3]

GPIO[6]

GPIO[8]

GPIO[12]

GPIO[11]

VBUS

VDD

GPIO[45]

GPIO[42]

GPIO[39]

GPIO[36]

GPIO[33]

VSS

GPIO[44]

GPIO[43]

GPIO[40]

GPIO[37]

VSS

GPIO[2]

GPIO[21]

GPIO[20]

GPIO[19]

GPIO[18]

VDD

GPIO[5]

GPIO[15]

GPIO[24]

GPIO[14]

GPIO[17]

INT#

VSS

GPIO[22]

GPIO[26]

GPIO[16]

GPIO[23]

VSS

VDD

VIO1

GPIO[38]

GPIO[35]

VSS

VDD

GPIO[10]

VSS

K

L

VSS

GPIO[32]

Document Number: 001-84160 Rev. *B

Page 15 of 50

CYUSB3035

Pin Description

FX3S Pin Description

P-Port

Async SRAM

Power

Domain

I/O

Name

GPIF II

Interface

Slave FIFO

PMMC

Async

ADMux

SyncADMux

Interface

F10

F9

VIO1

I/O

GPIO[0]

GPIO[1]

DQ[0]

DQ[1]

DQ[0]

DQ[1]

MMC_D0

MMC_D1

MMC_D2

MMC_D3

MMC_D4

MMC_D5

MMC_D6

MMC_D7

GPIO

DQ[0]

DQ[1]

DQ[2]

DQ[3]

DQ[4]

DQ[5]

DQ[6]

DQ[7]

DQ[8]

DQ[9]

DQ[10]

DQ[11]

DQ[12]

DQ[13]

DQ[14]

DQ[15]

CLK

DQ[0]/A[0]

DQ[1]/A[1]

DQ[2]/A[2]

DQ[3]/A[3]

DQ[4]/A[4]

DQ[5]/A[5]

DQ[6]/A[6]

DQ[7]/A[7]

DQ[8]/A[8]

DQ[9]/A[9]

DQ[0]/A[0]

DQ[1]/A[1]

DQ[2]/A[2]

DQ[3]/A[3]

DQ[4]/A[4]

DQ[5]/A[5]

DQ[6]/A[6]

DQ[7]/A[7]

DQ[8]/A[8]

DQ[9]/A[9]

F7

GPIO[2]

DQ[2]

G10

G9

F8

GPIO[3]

DQ[3]

GPIO[4]

DQ[4]

GPIO[5]

DQ[5]

H10

H9

J10

J9

GPIO[6]

GPIO[7]

GPIO[8]

GPIO[9]

DQ[6]

DQ[7]

DQ[8]

DQ[9]

GPIO

K11

L10

K10

K9

J8

GPIO[10]

GPIO[11]

GPIO[12]

GPIO[13]

GPIO[14]

GPIO[15]

GPIO[16]

GPIO[17]

GPIO[18]

GPIO[19]

GPIO[20]

GPIO[21]

GPIO[22]

GPIO[23]

GPIO[24]

GPIO[25]

GPIO[26]

GPIO[27]

GPIO[28]

DQ[10]

DQ[11]

DQ[12]

DQ[13]

DQ[14]

DQ[15]

PCLK

DQ[10]

DQ[11]

DQ[12]

DQ[13]

DQ[14]

DQ[15]

CLK

GPIO

DQ[10]/A[10] DQ[10]/A[10]

DQ[11]/A[11] DQ[11]/A[11]

DQ[12]/A[12] DQ[12]/A[12]

DQ[13]/A[13] DQ[13]/A[13]

DQ[14]/A[14] DQ[14]/A[14]

DQ[15]/A[15] DQ[15]/A[15]

GPIO

G8

J6

GPIO

MMC_CLK

GPIO

CLK

CE#

CLK

CE#

K8

K7

J7

CTL[0]

CTL[1]

CTL[2]

CTL[3]

CTL[4]

CTL[5]

CTL[6]

CTL[7]

CTL[8]

CTL[9]

CTL[10]

CTL[11]

SLCS#

SLWR#

SLOE#

SLRD#

FLAGA

FLAGB

GPIO

CE#

MMC_CMD

GPIO

WE#

OE#

H7

G7

G6

K6

H8

G5

H6

K5

J5

GPIO

DACK#

DRQ#

A[7]

DACK#

DRQ#

GPIO

ADV#

GPIO

DACK#

DRQ#

GPIO

RDY

GPIO

A[6]

PKTEND#

GPIO

A[5]

GPIO

ADV#

GPIO

A[4]

GPIO

A[3]

GPIO

A[2]

A1

CARKIT_UART

_RX

A[1]

H5

VIO1

I/O

GPIO[29]

CTL[12]

A0

CARKIT_UART

_TX

A[0]

GPIO

G4

H4

L4

L8

VIO1

I/O

GPIO[30]

GPIO[31]

GPIO[32]

INT#

PMODE[0] PMODE[0]

PMODE[1] PMODE[1]

PMODE[2] PMODE[2]

PMODE[0]

PMODE[1]

PMODE[2]

INT#

PMODE[0]

PMODE[1]

PMODE[2]

INT#

PMODE[0]

PMODE[1]

PMODE[2]

INT#

PMODE[0]

PMODE[1]

PMODE[2]

INT#

CTL[15]

INT#/CTL[15]

C5

I

RESET#

CVDDQ

Document Number: 001-84160 Rev. *B

Page 16 of 50

CYUSB3035

FX3S Pin Description

S0-Port

SD+GPIO

Power

I/O

Name

Domain

8b MMC

S0_SD0

GPIO

K2

J4

VIO2

I/O

GPIO[33]

GPIO[34]

GPIO[35]

GPIO[36]

GPIO[37]

GPIO[38]

GPIO[39]

GPIO[40]

GPIO[41]

GPIO[42]

GPIO[43]

GPIO[44]

GPIO[45]

S0_SD0

S0_SD1

S0_SD2

S0_SD3

GPIO

S0_SD1

K1

J2

S0_SD2

S0_SD3

J3

S0_SD4

J1

S0_SD5

GPIO

H2

H3

F4

G2

G3

F3

F2

S0_SD6

GPIO

S0_SD7

GPIO

S0_CMD

S0_CLK

S0_CMD

S0_CLK

S0_WP

S0S1_INS

GPIO

S0_WP

S0S1_INS

MMC0_RST_OUT

S1-Port

8b MMC SD+UART

SD+SPI SD+GPIO GPIO GPIO+UART SD+I2S UART+SPI

+I2S

F5

E1

VIO3

I/O

GPIO[46] S1_SD0

GPIO[47] S1_SD1

S1_SD0

S1_SD1

S1_SD0 S1_SD0 GPIO

S1_SD1 S1_SD1 GPIO

GPIO

S1_SD0 UART_RT

S

GPIO

S1_SD1 UART_CT

S

E5

E4

D1

D2

D3

VIO3

I/O

GPIO[48] S1_SD2

GPIO[49] S1_SD3

S1_SD2

S1_SD3

S1_SD2 S1_SD2 GPIO

S1_SD3 S1_SD3 GPIO

GPIO

S1_SD2 UART_TX

S1_SD3 UART_RX

S1_CMD I2S_CLK

GPIO[50] S1_CMD S1_CMD S1_CMD S1_CMD GPIO

I2S_CLK

I2S_SD

I2S_WS

GPIO[51] S1_CLK

GPIO[52] S1_WP

S1_CLK

S1_WP

S1_CLK S1_CLK GPIO

S1_WP S1_WP GPIO

S1_CLK

S1_WP

I2S_SD

I2S_WS

D4

C1

VIO4

I/O

GPIO[53] S1_SD4 UART_RTS SPI_SCK

GPIO GPIO UART_RTS

GPIO

SPI_SCK

GPIO[54] S1_SD5

SPI_SSN

GPIO GPIO UART_CTS I2S_CLK SPI_SSN

UART_CTS

C2

D5

C4

VIO4

I/O

GPIO[55] S1_SD6 UART_TX

GPIO GPIO UART_TX

GPIO GPIO UART_RX

I2S_SD SPI_MISO

I2S_WS SPI_MOSI

SPI_MISO

GPIO[56] S1_SD7 UART_RX

SPI_MOSI

GPIO

GPIO[57] MMC1_R

ST_OUT

GPIO

GPIO GPIO I2S_MCLK I2S_MCLK I2S_MCLK

Document Number: 001-84160 Rev. *B

Page 17 of 50

CYUSB3035

FX3S Pin Description

Power

Domain

I/O

Name

USB Port

C9 VBUS/

VBATT

I

OTG_ID

A3

A4

A6

A5

U3RX

VDDQ

I

SSRXM

SSRXP

SSTXM

SSTXP

SSRX-

SSRX+

SSTX-

SSTX+

U3RX

VDDQ

I

U3TX

VDDQ

O

U3TX

VDDQ

A9

VBUS/ I/O

VBATT

DP

DM

NC

D+

D–

A10 VBUS/ I/O

VBATT

A11

No connect

Crystal/Clocks

FSLC[0]

B2 CVDDQ

I

FSLC[0]

XTALIN

C6

C7

AVDD

I/O

XTALIN

I/O

XTALOUT

FSLC[1]

FSLC[2]

CLKIN

XTALOUT

FSLC[1]

B4 CVDDQ

E6 CVDDQ

D7 CVDDQ

D6 CVDDQ

I

FSLC[2]

CLKIN

CLKIN_32

I2C and JTAG

I2C_SCL

D9

VIO5

I/O I2C_GPIO[5

8]

D10

I/O I2C_GPIO[5

9]

I2C_SDA

E7

C10

B11

E8

VIO5

I

O

I

TDI

TDO

TDI

TDO

TRST#

TMS

TRST#

TMS

I

F6

I

TCK

D11

O

O[60]

Charger detect output

Document Number: 001-84160 Rev. *B

Page 18 of 50

CYUSB3035

FX3S Pin Description

Power

Domain

I/O

Name

Power

E10

B10

A1

E11

D8

H11

E2

L9

PWR

VBATT

VDD

U3VSSQ

VBUS

VSS

VIO1

VSS

VIO1

VSS

G1

F1

VIO2

VSS

G11

E3

L1

VIO3

VSS

B1

L6

VIO4

VSS

B6

B5

A2

C11

L11

A7

B7

C3

B8

E9

B9

F11

H1

L7

CVDDQ

PWR U3TXVDDQ

PWR U3RXVDDQ

PWR

VIO5

VSS

AVDD

AVSS

VDD

VSS

VDD

VSS

VDD

VSS

J11

L5

K4

L3

K3

L2

A8

Precision Resistors

C8

B3

VBUS/ I/O

VBATT

R_usb2

R_usb3

Precision resistor for USB 2.0 (Connect a 6.04 kΩ ±1% resistor between this pin and GND)

U3TX

I/O

Precision resistor for USB 3.0 (Connect a 200 Ω ±1% resistor between this pin and GND)

VDDQ

Document Number: 001-84160 Rev. *B

Page 19 of 50

CYUSB3035

■ ± 6-KV contact discharge, ± 8-KV air gap discharge based on

IEC61000-4-2 level 3A, ± 8-KV contact discharge, and ± 15-KV

air gap discharge based on IEC61000-4-2 level 4C

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device.

Latch-up current................................................... .......> 200 mA

Storage temperature..................................... –65 °C to +150 °C

Maximum output short-circuit current

for all I/O configurations. (Vout = 0V).................... ..... –100 mA

Ambient temperature with

power supplied (Industrial).................... ......... –40 °C to +85 °C

Operating Conditions

Supply voltage to ground potential

V_DD, A_VDDQ......................................................................1.25 V

T_A(ambient temperature under bias)

V_IO1,V_IO2, V_IO3, V_IO4, V_IO5........................ .........................3.6 V

Industrial......................................................... –40 °C to +85 °C

U3TX_VDDQ, U3RX_VDDQ......................................... ...........1.25 V

DC input voltage to any input pin..................................VCC+0.3

V

_DD, A_VDDQ, U3TX_VDDQ, U3RX_VDDQ

Supply voltage...................................................1.15 V to 1.25 V

DC voltage applied to

outputs in high Z state.................... ..............................VCC+0.3

V

_BATTsupply voltage................................................3.2 V to 6 V

_IO1, V_IO2, V_IO3, V_IO4, C_VDDQ

V

(VCC is the corresponding I/O voltage)

Supply voltage.......................................................1.7 V to 3.6 V

_IO5supply voltage...................... ...................... 1.15 V to 3.6 V

Static discharge voltage ESD protection levels:

V

■ ± 2.2-KV HBM based on JESD22-A114

■ Additional ESD protectionlevels on D+, D–, and GND pins, and

serial peripheral pins

Table 7. DC Specifications

Parameter

V_DD

Description

Core voltage supply

Min

Max

1.25

3.6

Units

Notes

1.2-V typical

1.15

1.7

V

A_VDD

V_IO1

V_IO2

V_IO3

V_IO4

Analog voltage supply

1.2-V typical

GPIF II I/O power supply domain

S0-Port power supply domain

S1-Port power supply domain

1.8-, 2.5-, and 3.3-V typical

1.7

3.6

1.7

3.6

S1-Port and UART/SPI/I2S power

supply domain

1.7

3.6

V_BATT

USB voltage supply

USB 3.0 1.2-V supply

3.2

4.0

6

V

3.7-V typical

5-V typical

V_BUS

U3TX_VDDQ

1.15

1.25

1.2-V typical. A 22-µF bypass

capacitor is required on this

power supply.

U3RX_VDDQ

USB 3.0 1.2-V supply

1.15

1.25

V

1.2-V typical. A 22-µF bypass

capacitor is required on this

power supply.

C_VDDQ

V_IO5

Clock voltage supply

I²C and JTAG voltage supply

1.7

3.6

V

1.8-, 3.3-V typical

1.15

1.2-, 1.8-, 2.5-, and 3.3-V

typical

V_IH1

V_IH2

V_IL

Input HIGH voltage 1

Input HIGH voltage 2

Input LOW voltage

0.625 × VCC

VCC – 0.4

–0.3

VCC + 0.3

0.25 × VCC

V

For 2.0 V ≤ V_CC≤ 3.6 V

(except USB port).VCC is the

corresponding I/O voltage

supply.

For 1.7 V ≤ V_CC≤ 2.0 V

(except USB port).VCC is the

corresponding I/O voltage

supply.

VCC is the corresponding I/O

voltage supply.

Document Number: 001-84160 Rev. *B

Page 20 of 50

CYUSB3035

Table 7. DC Specifications (continued)

Parameter Description

V_OH

Min

Max

Units

Notes

Output HIGH voltage

0.9 × VCC

–

V

I_OH(max) = –100 µA tested at

quarter drive strength. VCC is

the corresponding I/O voltage

supply.

V_OL

Output LOW voltage

–

0.1 × VCC

V

I_OL(min) = +100 µA tested at

quarter drive strength. VCC is

the corresponding I/O voltage

supply.

I_IX

Input leakage current for all pins except

SSTXP/SSXM/SSRXP/SSRXM

–1

1

µA

All I/O signals held at V_DDQ

(For I/Os with a pull-up or

pull-down resistor connected,

the leakage current increases

by V_DDQ/R_puor V_DDQ/R_PD

I_OZ

Output High-Z leakage current for all

pins except SSTXP/ SSXM/

SSRXP/SSRXM

–1

–

1

µA

All I/O signals held at V_DDQ

I_CCCore

Core and analog voltage operating

current

200

mA

Total current through A_VDD

,

V_DD

I_CCUSB

I_SB1

USB voltage supply operating current

–

60

–

mA

Total suspend current during suspend

mode with USB 3.0 PHY enabled (L1)

Core current: 1.5 mA

I/O current: 20 µA

USB current: 2 mA

For typical PVT (typical silicon,

all power supplies at their

respective nominal levels at

25 °C.)

I_SB2

I_SB3

I_SB4

Total suspend current during suspend

mode with USB 3.0 PHY disabled (L2)

–

mA

µA

Core current: 250 µA

I/O current: 20 µA

USB current: 1.2 mA

For typical PVT (Typical

silicon, all power supplies at

their respective nominal levels

at 25 °C.)

Total standby current during standby

mode (L3)

Core current: 60 µA

I/O current: 20 µA

USB current: 40 µA

For typical PVT (typical silicon,

all power supplies at their

respective nominal levels at

25 °C.)

Total standby current during core

power-down mode (L4)

Core current: 0 µA

I/O current: 20 µA

USB current: 40 µA

For typical PVT (typical silicon,

all power supplies at their

respective nominal levels at

25 °C.)

V_RAMP

V_N

Voltage ramp rate on core and I/O

supplies

0.2

–

50

100

20

V/ms Voltage ramp must be

monotonic

Noise level permitted on V_DDand I/O

supplies

mV

Max p-p noise level permitted

on all supplies except A_VDD

V_{N_AVDD}

Noise level permitted on A_VDDsupply

–

mV

Max p-p noise level permitted

on A_VDD

Document Number: 001-84160 Rev. *B

Page 21 of 50

CYUSB3035

AC Timing Parameters

GPIF II Timing

Figure 12. GPIF II Timing in Synchronous Mode

tCLKH tCLKL

CLK

tCLK

tCO

tHZ

tDOH

tCOE

tDS tDH

tDOH

tLZ

Data1

( OUT)

Data2

( OUT)

D-Q[15:0]

Data(IN)

tS tH

CTL(IN)

tCTLO

tCOH

CTL( OUT)

Table 8. GPIF II Timing Parameters in Synchronous Mode^[3]

Parameter Description

Frequency

Min

–

Max

100

–

Units

MHz

ns

Interface clock frequency

Interface clock period

Clock high time

tCLK

tCLKH

tCLKL

tS

10

4

–

ns

Clock low time

4

–

ns

CTL input to clock setup time

(Sync speed = 1)

2

–

ns

tH

CTL input to clock hold time

(Sync speed = 1)

0.5

2

–

8

9

ns

tDS

tDH

tCO

tCOE

Data in to clock setup time

(Sync speed = 1)

Data in to clock hold time

(Sync speed = 1)

0.5

–

Clock to data out propagation delay when DQ bus is already in

output direction (Sync speed = 1)

Clock to data out propagation delay when DQ lines change to

output from tristate and valid data is available on the DQ bus

(Sync speed = 1)

-

tCTLO

tDOH

tCOH

tHZ

Clock to CTL out propagation delay (Sync speed = 1)

Clock to data out hold

–

2

8

–

ns

Clock to CTL out hold

0

–

Clock to high-Z

–

8

tLZ

Clock to low-Z (Sync speed = 1)

0

–

tS_ss0

tH_ss0

tCO_ss0

CTL input/data input to clock setup time (Sync speed = 0)

CTL input/data input to clock hold time (Sync speed = 0)

5

–

2.5

–

Clock to data out / CTL out

15

propagation delay (sync speed = 0)

tLZ_ss0

Clock to low-Z (sync speed = 0)

2

–

ns

Note

3. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 22 of 50

CYUSB3035

Figure 13. GPIF II Timing in Asynchronous Mode

tAH

tDH/

tDS/ tAS

DATA/ ADDR

DATA IN

tCHZ

tCTLassert_DQlatch

tCTLdeassert_DQlatch

CTL#

(I/P, ALE/ DLE)

tAA/tDO

tCHZ/tOEHZ

tCLZ/ tOELZ

DATA OUT

CTL#

(I/P, non ALE/ DLE

tCTLdeassert

tCTLassert

tCTLalpha

tCTLbeta

ALPHA

O/P

BETA

O/P

1

tCTLassert

tCTLdeassert

tCTL#

(O/P)

1. n is an integer >= 0

tDST

tDHT

DATA/

ADDR

tCTLdeassert_DQassert

tCTLassert_DQassert

CTL#

I/P (non DLE/ALE)

Figure 14. GPIF II Timing in Asynchronous DDR Mode

tDS

tCTLdeassert_DqlatchDDR

tCTLassert_DQlatchDDR

CTL#

(I/P)

tDS

tDH

DATA IN

Document Number: 001-84160 Rev. *B

Page 23 of 50

CYUSB3035

[4]

Table 9. GPIF II Timing in Asynchronous Mode

Note The following parameters assume one state transition

Parameter Description

Min

2.3

2

Max

Units

ns

tDS

tDH

tAS

tAH

Data In to DLE setup time. Valid in DDR async mode.

Data In to DLE hold time. Valid in DDR async mode.

Address In to ALE setup time

–

ns

2.3

2

ns

Address In to ALE hold time

ns

tCTLassert

CTL I/O asserted width for CTRL inputs without DQ input

association and for outputs.

7

ns

tCTLdeassert

CTL I/O deasserted width for CTRL inputs without DQ

input association and for outputs.

7

–

ns

tCTLassert_DQassert

CTL asserted pulse width for CTL inputs that signify DQ

inputs valid at the asserting edge but do not employ

in-built latches (ALE/DLE) for those DQ inputs.

20

tCTLdeassert_DQassert

tCTLassert_DQdeassert

tCTLdeassert_DQdeassert

tCTLassert_DQlatch

CTLdeassertedpulse width for CTL inputs that signify DQ

input valid at the asserting edge but do not employ in-built

latches (ALE/DLE) for those DQ inputs.

7

–

ns

CTL asserted pulse width for CTL inputs that signify DQ

inputs valid at the deasserting edge but do not employ

in-built latches (ALE/DLE) for those DQ inputs.

CTLdeassertedpulse width for CTL inputs that signify DQ

inputs valid at the deasserting edge but do not employ

in-built latches (ALE/DLE) for those DQ inputs.

20

7

CTL asserted pulse width for CTL inputs that employ

in-built latches (ALE/DLE) to latch the DQ inputs. In this

non-DDR case, in-built latches are always close at the

deasserting edge.

tCTLdeassert_DQlatch

CTL deasserted pulse width for CTL inputs that employ

in-built latches (ALE/DLE) to latch the DQ inputs. In this

non-DDR case, in-built latches always close at the

deasserting edge.

10

–

ns

tCTLassert_DQlatchDDR

tCTLdeassert_DQlatchDDR

tAA

CTL asserted pulse width for CTL inputs that employ

in-built latches (DLE) to latch the DQ inputs in DDR mode.

10

–

ns

CTL deasserted pulse width for CTL inputs that employ

in-built latches (DLE) to latch the DQ inputs in DDR mode.

DQ/CTL input to DQ output time when DQ change or CTL

change needs to be detected and affects internal updates

of input and output DQ lines.

30

tDO

CTL to data out when the CTL change merely enables the

output flop update whose data was already established.

–

0

25

–

ns

tOELZ

CTL designated as OE to low-Z. Time when external

devices should stop driving data.

tOEHZ

tCLZ

CTL designated as OE to high-Z

8

0

8

–

ns

CTL (non-OE) to low-Z. Time when external devices

should stop driving data.

tCHZ

CTL (non-OE) to high-Z

30

–

30

25

30

–

ns

tCTLalpha

tCTLbeta

tDST

CTL to alpha change at output

CTL to beta change at output

–

Addr/data setup when DLE/ALE not used

Addr/data hold when DLE/ALE not used

2

tDHT

20

–

Note

4. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 24 of 50

CYUSB3035

Asynchronous SRAM Timing

Figure 15. Non-multiplexed Asynchronous SRAM Read Timing

Socket Read – Address Transition Controlled Timing (OE# is asserted)

A[0]

tAA

tAH

tOH

HIGH

DATA

OUT

IMPEDANCE

DATA VALID

tOE

OE#

OE# Controlled Timing

ADDRESS

WE# (HIGH)

CE#

tAOS

tOHC

tRC

OE#

tOHH

tOEZ

tOE

tOLZ

HIGH

IMPEDANCE

HIGH

IMPEDANCE

HIGH

IMPEDANCE

DATA OUT

DATA

VALID

DATA

VALID

Document Number: 001-84160 Rev. *B

Page 25 of 50

CYUSB3035

Figure 16. Non-multiplexed Asynchronous SRAM Write Timing (WE# and CE# Controlled)

Write Cycle 1 WE# Controlled, OE# High During Write

tWC

ADDRESS

tCW

CE#

tAW

tAH

tDH

tWP

WE#

tAS

tWPH

OE#

tDS

VALID DATA

DATA I/O

VALID DATA

tWHZ

Write Cycle 2 CE# Controlled, OE# High During Write

tWC

ADDRESS

tAS

tCW

tCPH

CE#

tAW

tAH

tDH

tWP

WE#

OE#

tDS

VALID DATA

DATA I/O

VALID DATA

tWHZ

Document Number: 001-84160 Rev. *B

Page 26 of 50

CYUSB3035

Figure 17. Non-multiplexed Asynchronous SRAM Write Timing (WE# controlled, OE# LOW)

Write Cycle 3 WE# Controlled. OE# Low

tWC

tCW

CE#

tAW

tAH

tAS

tWP

WE#

tDS

tDH

DATA I/O

VALID DATA

tOW

tWHZ

Note: tWP must be adjusted such that tWP > tWHZ + tDS

[5]

Table 10. Asynchronous SRAM Timing Parameters

Parameter Description

SRAM interface bandwidth

Min

–

Max

61.5

–

Units

MBps

ns

tRC

Read cycle time

32.5

–

tAA

Address to data valid

30

–

ns

tAOS

tOH

Address to OE# LOW setup time

Data output hold from address change

OE# HIGH hold time

7

ns

3

–

ns

tOHH

tOHC

tOE

7.5

2

–

ns

OE# HIGH to CE# HIGH

OE# LOW to data valid

OE# LOW to LOW-Z

–

ns

–

25

–

ns

tOLZ

tWC

tCW

tAW

0

ns

Write cycle time

30

7

–

ns

CE# LOW to write end

Address valid to write end

Address setup to write start

Address hold time from CE# or WE#

WE# pulse width

–

ns

–

ns

tAS

–

ns

tAH

2

–

ns

tWP

tWPH

tCPH

tDS

20

10

7

–

ns

WE# HIGH time

–

ns

CE# HIGH time

–

ns

Data setup to write end

Data hold to write end

–

ns

tDH

2

–

ns

tWHZ

tOEZ

tOW

Write to DQ HIGH-Z output

OE# HIGH to DQ HIGH-Z output

End of write to LOW-Z output

–

22.5

–

ns

–

ns

0

ns

Note

5. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 27 of 50

CYUSB3035

ADMux Timing for Asynchronous Access

Figure 18. ADMux Asynchronous Random Read

tRC

tACC

Valid Address

tAVS

tVP

Valid

Addr

Valid Data

A[0:7]/DQ[0:15]

ADV#

tAVH

WE# (HIGH)

CE#

tCEAV

tCPH

tHZ

tCO

tHZ

tOLZ

tOE

OE#

tAVOE

Note:

1. Multiple read cycles can be executed while keeping CE# low.

2. Read operation ends with either de-assertion of either OE# or CE#, whichever comes earlier.

Figure 19. ADMux Asynchronous Random Write

tWC

Valid

Addr

Address Valid

Data Valid

tDS

A[0:7]/DQ[0:15]

ADV#

tAW

tAVH

tAVS

tVP

tDH

tVPH

tCEAV

CE#

tCPH

tCW

tWP

tWPH

WE#

tAVWE

Note:

1. Multiple write cycles can be executed while keeping CE# low.

2. Write operation ends with de-assertion of either WE# or CE#, whichever comes earlier.

Document Number: 001-84160 Rev. *B

Page 28 of 50

CYUSB3035

[6]

Table 11. Asynchronous ADMux Timing Parameters

Parameter

Description

Min

Max

Units

Notes

ADMux Asynchronous READ Access Timing Parameters

tRC

Read cycle time (address valid to address

valid)

54.5

–

ns

This parameter is dependent on when

the P-port processors deasserts OE#

tACC

tCO

Address valid to data valid

CE# assert to data valid

–

2

0

–

32

34.5

–

ns

tAVOE

tOLZ

tOE

ADV# deassert to OE# assert

OE# assert to data LOW-Z

OE# assert to data valid

–

25

tHZ

Read cycle end to data HIGH-Z

22.5

ADMux Asynchronous WRITE Access Timing Parameters

tWC

Write cycle time (Address Valid to Address

Valid)

–

52.5

ns

tAW

Address valid to write end

CE# assert to write end

30

2

–

ns

tCW

tAVWE

tWP

ADV# deassert to WE# assert

WE# LOW pulse width

20

10

18

2

tWPH

tDS

WE# HIGH pulse width

Data valid setup to WE# deassert

Data valid hold from WE# deassert

tDH

ADMux Asynchronous Common READ/WRITE Access Timing Parameters

tAVS

tAVH

tVP

Address valid setup to ADV# deassert

Address valid hold from ADV# deassert

ADV# LOW pulse width

5

2

–

ns

7.5

10

15

0

tCPH

tVPH

tCEAV

CE# HIGH pulse width

ADV# HIGH pulse width

CE# assert to ADV# assert

Note

6. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 29 of 50

CYUSB3035

Synchronous ADMux Timing

Figure 20. Synchronous ADMux Interface – Read Cycle Timing

tCLK

2- cycle latency from OE# to DATA

tCLKH

tCLKL

CLK

tCO

tS

tH

Valid Data

Valid Address

A[0:7]/DQ[0:15]

tS

tH

tOHZ

ADV#

CE#

tS

tAVOE

tOLZ

OE#

RDY

tKW

tCH

WE# (HIGH)

Note:

1) External P-Port processor and FX3S operate on the same clock edge

2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the data appears on the output

3) Valid output data appears 2 cycle after OE # asserted. The data is held until OE # deasserts

4) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Figure 21. Synchronous ADMux Interface – Write Cycle Timing

2-cycle latency between

WE# and data being latched

2-cycle latency between this clk edge and RDY deassertion seen by

the host

CLK

tCLK

tDS

tDH

tS

tH

Valid Address

Valid Data

A[0:7]/DQ[0:15]

tS

tH

ADV#

CE#

tS

tAVWE

tS

tH

WE#

RDY

tKW

Note:

1) External P-Port processor and FX3S operate on the same clock edge

2) External processor sees RDY assert 2 cycles after WE # asserts and deassert 3 cycles after the edge sampling the data.

3) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Document Number: 001-84160 Rev. *B

Page 30 of 50

CYUSB3035

Figure 22. Synchronous ADMux Interface – Burst Read Timing

2-cycle latency fromOE# to Data

tCLK

tCLKH

tCLKL

CLK

tCO

tCH

tS

tH

Valid Address

D0

D1

D2

D3

A[0:7]/DQ[0:15]

tS

tH

ADV#

CE#

tHZ

tS

tAVOE

tOLZ

OE#

RDY

tKW

Note:

1) External P-Port processor and FX3S work operate on the same clock edge

2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the last burst data appears on the output

3) Valid output data appears 2 cycle after OE # asserted. The last burst data is held until OE # deasserts

4) Burst size of 4 is shown. Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst.

5) External processor cannot deassert OE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

6) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Figure 23. Sync ADMux Interface – Burst Write Timing

2-cycle latency between

WE# and data being latched

2-cycle latency between this clk edge and RDY

deassertion seen by the host

tCLKH

tCLKL

CLK

tCLK

tDS

tDH

tS

tH

D0

Valid Address

D1

D2

D3

A[0:7]/DQ[0:15]

tS

tH

ADV#

CE#

tS

tAVWE

WE#

RDY

tKW

Note:

1) External P-Port processor and FX3S operate on the same clock edge

2) External processor sees RDY assert 2 cycles after WE # asserts and deasserts 3 cycles after the edge sampling the last burst data.

3) Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst. Burst size of 4 is shown

4) External processor cannot deassert WE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

5)Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Document Number: 001-84160 Rev. *B

Page 31 of 50

CYUSB3035

[3]

Table 12. Synchronous ADMux Timing Parameters

Parameter Description

FREQ Interface clock frequency

Min

–

Max

100

–

Unit

MHz

ns

tCLK

tCLKH

tCLKL

tS

Clock period

10

4

Clock HIGH time

–

ns

Clock LOW time

4

–

ns

CE#/WE#/DQ setup time

CE#/WE#/DQ hold time

Clock to data output hold time

Data input setup time

Clock to data input hold

ADV# HIGH to OE# LOW

ADV# HIGH to WE# LOW

CE# HIGH to Data HIGH-Z

OE# HIGH to Data HIGH-Z

OE# LOW to Data LOW-Z

Clock to RDY valid

2

–

ns

tH

0.5

0

–

ns

tCH

–

ns

tDS

2

–

ns

tDH

0.5

0

–

ns

tAVDOE

tAVDWE

tHZ

–

ns

0

–

ns

–

8

ns

tOHZ

tOLZ

tKW

–

8

ns

0

–

ns

–

8

ns

Note

7. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 32 of 50

CYUSB3035

PCLK), the new data value is present. N is the first data value

read from the FIFO. To have data on the FIFO data bus, SLOE

must also be asserted.

Slave FIFO Interface

Synchronous Slave FIFO Sequence Description

The same sequence of events is shown for a burst read.

■ FIFO address is stable and SLCS is asserted

Note For burst mode, the SLRD# and SLOE# are asserted

during the entire duration of the read. When SLOE# is asserted,

the data bus is driven (with data from the previously addressed

FIFO). For each subsequent rising edge of PCLK, while the

SLRD# is asserted, the FIFO pointer is incremented and the next

data value is placed on the data bus.

■ SLOE is asserted. SLOE is an output-enable only, whose sole

function is to drive the data bus.

■ SLRD is asserted

■ The FIFO pointer is updated on the rising edge of the PCLK,

while the SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a

propagation delay of tco (measured from the rising edge of

Figure 24. Synchronous Slave FIFO Read Mode

Synchronous Read Cycle Timing

t_CYC

PCLK

t_CHt_CL

2-cycle latency

from SLRD to data

cycle latency

3-

from addr to data

SLCS

t

_ASt_AH

FIFO ADDR

An

Am

t_RDH

t_RDS

SLRD

SLOE

2

cycle latency from

t_CFLG

SLRD to FLAG

FLAGA

(dedicated thread Flag for An)

( 1 = Not Empty0 = Empty)

t_CFLG

FLAGB

(dedicated thread Flag for Am)

( 1 = Not Empty0= Empty)

t_CDH

t_OEZ

t_OELZ

t_OEZ

t_CO

t_OELZ

High-Z

Data

driven:D_N(An)

D_N+2(Am)

D_N+1(Am)

D_N+1(An)

D_N(Am)

Data Out

SLWR (HIGH)

Document Number: 001-84160 Rev. *B

Page 33 of 50

CYUSB3035

edge of PCLK. The FIFO pointer is updated on each rising edge

of PCLK.

Synchronous Slave FIFO Write Sequence Description

■ FIFO address is stable and the signal SLCS# is asserted

■ External master or peripheral outputs the data to the data bus

■ SLWR# is asserted

Short Packet: A short packet can be committed to the USB host

by using the PKTEND#. The external device or processor should

be designed to assert the PKTEND# along with the last word of

data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND#

assertion.

■ While the SLWR# is asserted, data is written to the FIFO and

on the rising edge of the PCLK, the FIFO pointer is incremented

Zero-Length Packet: The external device or processor can

signal a Zero-Length Packet (ZLP) to FX3S simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and address must

be driven as shown in Figure 25 on page 34.

■ The FIFO flag is updated after a delay of t

edge of the clock

from the rising

WFLG

The same sequence of events is also shown for burst write

Note For the burst mode, SLWR# and SLCS# are asserted for

the entire duration, during which all the required data values are

written. In this burst write mode, after the SLWR# is asserted, the

data on the FIFO data bus is written to the FIFO on every rising

FLAG Usage: The FLAG signals are monitored for flow control

by the external processor. FLAG signals are outputs from FX3S

that may be configured to show empty, full, or partial status for a

dedicated thread or the current thread that is addressed.

Figure 25. Synchronous Slave FIFO Write Mode

Synchronous Write Cycle Timing

t_CYC

PCLK

t_CHt_CL

SLCS

t_AH

t_AS

Am

An

t_WRS

FIFO ADDR

SLWR

t_WRH

t_CFLG

3 cycle latency from SLWR# to FLAG

FLAGA

dedicated thread FLAG for An

(1 = Not Full 0= Full)

t_CFLG

3 cycle latency from SLWR # to FLAG

FLAGB

current thread FLAG for Am

(1 = Not Full 0= Full)

t_DSt_DH

D_N(Am) D_N+1(Am) D_N+2(Am)

t_PES

t_DH

D_N(An)

Data IN

High-Z

t_PEH

PKTEND

SLOE

(HIGH)

Synchronous ZLP Write Cycle Timing

t_CYC

PCLK

t_CHt_CL

SLCS

t_AH

t_AS

An

FIFO ADDR

SLWR

(HIGH)

t

_PESt_PEH

PKTEND

t_CFLG

FLAGA

dedicated thread FLAG for An

(1 = Not Full 0= Full)

FLAGB

current thread FLAG for Am

(1 = Not Full 0= Full)

High-Z

Data IN

SLOE

(HIGH)

Document Number: 001-84160 Rev. *B

Page 34 of 50

CYUSB3035

[8]

Table 13. Synchronous Slave FIFO Parameters

Parameter

Description

Min

–

Max

100

–

Units

MHz

ns

FREQ

tCYC

tCH

Interface clock frequency

Clock period

10

4

Clock high time

–

ns

tCL

Clock low time

4

–

ns

tRDS

tRDH

tWRS

tWRH

tCO

SLRD# to CLK setup time

SLRD# to CLK hold time

SLWR# to CLK setup time

SLWR# to CLK hold time

Clock to valid data

2

–

ns

0.5

2

–

ns

–

ns

0.5

–

ns

8

ns

tDS

Data input setup time

CLK to data input hold

2

–

ns

tDH

0.5

2

–

ns

tAS

Address to CLK setup time

CLK to address hold time

SLOE# to data low-Z

–

ns

tAH

0.5

0

–

ns

tOELZ

tCFLG

tOEZ

tPES

tPEH

tCDH

–

ns

CLK to flag output propagation delay

SLOE# deassert to Data Hi Z

PKTEND# to CLK setup

CLK to PKTEND# hold

–

8

ns

–

8

ns

2

–

ns

0.5

2

–

CLK to data output hold

–

ns

Note Three-cycle latency from ADDR to DATA/FLAGS

.

In Figure 26 on page 36, data N is the first valid data read from

the FIFO. For data to appear on the data bus during the read

cycle, SLOE# must be in an asserted state. SLRD# and SLOE#

can also be tied.

Asynchronous Slave FIFO Read Sequence

Description

■ FIFO address is stable and the SLCS# signal is asserted.

■ SLOE# is asserted. This results in driving the data bus.

■ SLRD # is asserted.

The same sequence of events is also shown for a burst read.

Note In the burst read mode, during SLOE# assertion, the data

bus is in a driven state (data is driven from a previously

addressed FIFO). After assertion of SLRD# data from the FIFO

is driven on the data bus (SLOE# must also be asserted). The

FIFO pointer is incremented after deassertion of SLRD#.

■ Data from the FIFO is driven after assertion of SLRD#. This

data is valid after a propagation delay of tRDO from the falling

edge of SLRD#.

■ FIFO pointer is incremented on deassertion of SLRD#

Note

8. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 35 of 50

CYUSB3035

Figure 26. Asynchronous Slave FIFO Read Mode

SLCS

t_AS

t_AH

An

Am

FIFO ADDR

t_RDlt_RDh

SLRD

SLOE

t_FLG

t_RFLG

FLAGA

dedicated thread Flag for An

(1=Not empty 0 = Empty)

FLAGB

dedicated thread Flag for Am

(1=Not empty 0 = Empty)

t_RDO

t_OH

t_OE

t_LZ

t_OE

t_RDO

t_OH

D_N(An)

D_N(Am)

D_N+1(Am)

D_N+2(Am)

Data Out

High-Z

SLWR

(HIGH)

Short Packet: A short packet can be committed to the USB host

by using the PKTEND#. The external device or processor should

be designed to assert the PKTEND# along with the last word of

data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND#

assertion.

Asynchronous Slave FIFO Write Sequence

Description

■ FIFO address is driven and SLCS# is asserted

■ SLWR# is asserted. SLCS# must be asserted with SLWR# or

before SLWR# is asserted

Zero-Length Packet: The external device or processor can

signal a zero-length packet (ZLP) to FX3S simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and the address

must be driven as shown in Figure 27 on page 37.

■ Data must be present on the tWRS bus before the deasserting

edge of SLWR#

■ Deassertion of SLWR# causes the data to be written from the

data bus to the FIFO, and then the FIFO pointer is incremented

FLAG Usage: The FLAG signals are monitored by the external

processor for flow control. FLAG signals are FX3S outputs that

can be configured to show empty, full, and partial status for a

dedicated address or the current address.

■ The FIFO flag is updated after the tWFLG from the deasserting

edge of SLWR.

The same sequence of events is shown for a burst write.

Note that in the burst write mode, after SLWR# deassertion, the

data is written to the FIFO, and then the FIFO pointer is incre-

mented.

Document Number: 001-84160 Rev. *B

Page 36 of 50

CYUSB3035

Figure 27. Asynchronous Slave FIFO Write Mode

Asynchronous Write Cycle Timing

SLCS

t_AS

t_AH

An

FIFO ADDR

Am

t_WRl

t_WRh

SLWR

t_FLG

t_WFLG

FLAGA

dedicated thread Flag for An

(1=Not Full 0 = Full)

t_WFLG

FLAGB

dedicated thread Flag for Am

(1=Not Full 0 = Full)

t_WR

t_WRH

S

High-Z

D_N(An)

D_N(Am)

D_N+1(Am)

D_N+2(Am)

DATA In

t_WRPE

t_PEh

PKTEND

SLOE

(HIGH)

tWRPE: SLWR# de-assert to PKTEND deassert = 2ns min (This means that PKTEND should not be be deasserted before SLWR#)

Note: PKTEND must be asserted at the same time as SLWR#.

Asynchronous ZLP Write Cycle Timing

SLCS

t_AS

t_AH

An

FIFO ADDR

SLWR

(HIGH)

t_PEl

t_PEh

PKTEND

t_WFLG

FLAGA

dedicated thread Flag for An

(1=Not Full 0 = Full)

FLAGB

dedicated thread Flag for Am

(1=Not Full 0 = Full)

High-Z

DATA In

SLOE

(HIGH)

Document Number: 001-84160 Rev. *B

Page 37 of 50

CYUSB3035

[9]

Table 14. Asynchronous Slave FIFO Parameters

Parameter

Description

Min

20

10

7

Max

–

Units

ns

tRDI

SLRD# low

SLRD# high

tRDh

tAS

–

ns

Address to SLRD#/SLWR# setup time

SLRD#/SLWR#/PKTEND to address hold time

SLRD# to FLAGS output propagation delay

ADDR to FLAGS output propagation delay

SLRD# to data valid

–

ns

tAH

2

–

ns

tRFLG

tFLG

tRDO

tOE

–

35

22.5

25

–

ns

–

ns

OE# low to data valid

–

tLZ

OE# low to data low-Z

0

tOH

SLOE# deassert data output hold

SLWR# low

–

22.5

–

tWRI

tWRh

tWRS

tWRH

tWFLG

tPEI

20

10

7

SLWR# high

–

Data to SLWR# setup time

SLWR# to Data Hold time

–

2

–

SLWR#/PKTEND to Flags output propagation delay

PKTEND low

–

35

–

20

7.5

2

tPEh

tWRPE

PKTEND high

–

SLWR# deassert to PKTEND deassert

–

Storage Port Timing

The S0-Port and S1-Port support the MMC Specification Version 4.41 and SD Specification Version 3.0. Table 15 lists the timing

parameters for S-Port of the FX3S device.

[10]

Table 15. S-Port Timing Parameters

Parameter

Description

Min

Max

Units

MMC-20

tSDIS CMD

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

4.8

4.4

5

–

ns

MHz

%

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

–

5

–

5

–

5

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

50

–

SDFREQ

Clock frequency

20

60

tSDCLKOD

Clock duty cycle

40

MMC-26

tSDIS CMD

tSDIS DAT

Host input setup time for CMD

Host input setup time for DAT

10

–

ns

Note

9. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 38 of 50

CYUSB3035

[10]

Table 15. S-Port Timing Parameters

(continued)

Description

Parameter

Min

9

Max

–

Units

ns

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

9

–

ns

3

–

ns

3

–

ns

3

–

ns

3

–

ns

–

2

ns

tSCLKF

Clock fall time

–

2

ns

tSDCK

Clock cycle time

38.5

–

ns

SDFREQ

Clock frequency

26

60

MHz

%

tSDCLKOD

Clock duty cycle

40

MC-HS

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

4

–

ns

MHz

%

3

–

3

–

3

–

3

–

3

–

3

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

19.2

–

SDFREQ

Clock frequency

52

60

tSDCLKOD

Clock duty cycle

40

MMC-DDR52

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

4

0.56

3

–

ns

MHz

%

–

2.58

3

–

2.5

3

–

2.5

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

19.2

–

SDFREQ

Clock frequency

52

55

tSDCLKOD

Clock duty cycle

45

SD-Default Speed (SDR12)

Host input setup time for CMD

Host input setup time for DAT

tSDIS CMD

tSDIS DAT

24

–

ns

Document Number: 001-84160 Rev. *B

Page 39 of 50

CYUSB3035

[10]

Table 15. S-Port Timing Parameters

(continued)

Description

Parameter

Min

2.5

5

Max

–

Units

ns

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

–

ns

–

ns

5

–

ns

5

–

ns

5

–

ns

–

2

ns

tSCLKF

Clock fall time

–

2

ns

tSDCK

Clock cycle time

40

–

ns

SDFREQ

Clock frequency

25

60

MHz

%

tSDCLKOD

Clock duty cycle

40

SD-High-Speed (SDR25)

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

4

–

ns

MHz

%

2.5

6

–

6

–

2

–

2

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

20

–

SDFREQ

Clock frequency

50

60

tSDCLKOD

Clock duty cycle

40

SD-SDR50

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

1.5

2.5

3

–

ns

MHz

%

–

3

–

0.8

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

10

–

SDFREQ

Clock frequency

100

60

tSDCLKOD

Clock duty cycle

40

SD-DDR50

tSDIS CMD

tSDIS DAT

Host input setup time for CMD

Host input setup time for DAT

4

–

ns

0.92

Document Number: 001-84160 Rev. *B

Page 40 of 50

CYUSB3035

[10]

Table 15. S-Port Timing Parameters

(continued)

Description

Parameter

Min

2.5

6

Max

–

Units

ns

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

–

ns

–

ns

3

–

ns

0.8

–

ns

–

ns

2

ns

tSCLKF

Clock fall time

–

2

ns

tSDCK

Clock cycle time

20

–

ns

SDFREQ

Clock frequency

50

55

MHz

%

tSDCLKOD

Clock duty cycle

45

Serial Peripherals Timing

I²C Timing

Figure 28. I²C Timing Definition

Note

10. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 41 of 50

CYUSB3035

[11]

Table 16. I²C Timing Parameters

Parameter

Description

Min

Max

Units

I²C Standard Mode Parameters

fSCL

SCL clock frequency

0

4

100

–

kHz

µs

ns

µs

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

4.7

4

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

–

Setup time for a repeated START condition

Data hold time

4.7

0

–

Data setup time

250

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

1000

300

–

tf

–

tSU:STO

tBUF

4

4.7

–

tVD:DAT

tVD:ACK

tSP

3.45

n/a

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

I²C Fast Mode Parameters

n/a

fSCL

SCL clock frequency

0

0.6

1.3

0.6

0

400

–

kHz

µs

ns

µs

ns

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

HIGH period of the SCL

–

Setup time for a repeated START condition

Data hold time

–

Data setup time

100

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

300

–

tf

–

tSU:STO

tBUF

0.6

1.3

–

tVD:DAT

tVD:ACK

tSP

0.9

50

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

0

I²C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2 V)

fSCL

SCL clock frequency

0

1000

kHz

µs

ns

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

Setup time for a repeated START condition

Data hold time

0.26

0.5

0.26

0

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

Data setup time

50

Note

11. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 42 of 50

CYUSB3035

[11]

Table 16. I²C Timing Parameters

Parameter

(continued)

Description

Min

–

Max

120

–

Units

ns

tr

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

tf

–

ns

tSU:STO

tBUF

tVD:DAT

tVD:ACK

tSP

0.26

0.5

–

µs

Bus-free time between a STOP and START condition

Data valid time

–

µs

0.45

0.55

50

µs

Data valid ACK

–

µs

Pulse width of spikes that must be suppressed by input filter

0

ns

I²S Timing Diagram

Figure 29. I²S Transmit Cycle

t_T

t_TRt_TF

t_TH

t_TL

SCK

t_Thd

SA,

WS (output)

t_Td

[12]

Table 17. I²S Timing Parameters

Parameter

Description

Min

Ttr

Max

Units

2

tT

I S transmitter clock cycle

–

ns

2

tTL

tTH

tTR

tTF

tThd

tTd

I S transmitter cycle LOW period

0.35 Ttr

–

2

I S transmitter cycle HIGH period

0.35 Ttr

2

I S transmitter rise time

–

0

–

0.15 Ttr

–

2

I S transmitter fall time

2

I S transmitter data hold time

2

I S transmitter delay time

0.8tT

Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).

Note

12. All parameters guaranteed by design and validated through characterization.

Document Number: 001-84160 Rev. *B

Page 43 of 50

CYUSB3035

SPI Timing Specification

Figure 30. SPI Timing

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

SCK

(CPOL=0,

Output)

t_rf

t_wsck

SCK

(CPOL=1,

Output)

t_sdi

t_hoi

LSB

MISO

(input)

MSB

t_d

t_dis

t_sdd

t_di

v

MOSI

(output)

LSB

SPI Master Timing for CPHA = 0

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

t_rf

SCK

(CPOL=0,

Output)

t_wsck

SCK

(CPOL=1,

Output)

t_hoi

LSB

t_sdi

MISO

(input)

MSB

t_dis

t_di

t_dv

MOSI

(output)

LSB

SPI Master Timing for CPHA = 1

Document Number: 001-84160 Rev. *B

Page 44 of 50

CYUSB3035

[13]

Table 18. SPI Timing Parameters

Parameter

Description

Min

0

Max

33

–

Units

MHz

ns

fop

Operating frequency

tsck

twsck

tlead

tlag

trf

Cycle time

30

Clock high/low time

SSN-SCK lead time

Enable lag time

Rise/fall time

13.5

–

ns

[14 ]

[14]

1/2 tsck

-5

1.5 tsck + 5

ns

[14]

0.5

–

1.5 tsck +5

ns

8

5

–

ns

tsdd

tdv

Output SSN to valid data delay time

Output data valid time

–

ns

–

ns

tdi

Output data invalid

0

ns

tssnh

tsdi

thoi

tdis

Minimum SSN high time

Data setup time input

10

8

ns

Data hold time input

0

ns

Disable data output on SSN high

0

ns

Reset Sequence

FX3S’s hard reset sequence requirements are specified in this section.

Table 19. Reset and Standby Timing Parameters

Parameter

Definition

Conditions

Clock Input

Crystal Input

–

Min (ms)

Max (ms)

tRPW

Minimum RESET# pulse width

1

5

1

5

–

tRH

tRR

Minimum high on RESET#

Reset recovery time (after which Boot loader begins

firmware download)

Clock Input

Crystal Input

–

tSBY

tWU

Time to enter standby/suspend (from the time

MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)

1

Time to wakeup from standby

Clock Input

Crystal Input

–

1

5

–

tWH

Minimum time before Standby/Suspend source may

be reasserted

Notes

13. All parameters guaranteed by design and validated through characterization.

14. Depends on LAG and LEAD setting in the SPI_CONFIG register.

Document Number: 001-84160 Rev. *B

Page 45 of 50

CYUSB3035

Figure 31. Reset Sequence

VDD

( core )

xVDDQ

XTALIN/

CLKIN

XTALIN/ CLKIN must be stable

before exiting Standby/Suspend

tRh

tRR

Mandatory

Reset Pulse

Hard Reset

RESET #

tWH

tWU

tRPW

tSBY

Standby/

Suspend

Source

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit

is set)

Standby/Suspend

source Is deasserted

Document Number: 001-84160 Rev. *B

Page 46 of 50

CYUSB3035

Package Diagram

Figure 32. 121-ball FBGA (10 × 10 × 1.2 mm (0.30 mm Ball Diameter)) Package Outline, 001-54471

001-54471 *D

Document Number: 001-84160 Rev. *B

Page 47 of 50

CYUSB3035

Ordering Information

Table 20. Device Ordering Information

Ordering Code

CYUSB3035-BZXI

CYUSB3035-BZXC

CYUSB3033-BZXC

CYUSB3031-BZXC

SRAM (KB)

512

Storage Ports

HS-USB OTG GPIF II Data Bus Width

Package Type

121-ball BGA

2

1

Yes

No

16-bit

512

256

Ordering Code Definitions

3

CY USB

XXX BZX I/C

Temperature range

Industrial/Commercial

:

Package type: BGA

Marketing Part Number

Base part number for USB 3.0

Marketing Code: USB = USB Controller

Company ID: CY = Cypress

Document Number: 001-84160 Rev. *B

Page 48 of 50

CYUSB3035

Acronyms

Document Conventions

Units of Measure

Acronym

DMA

HNP

Description

direct memory access

Symbol

°C

Unit of Measure

host negotiation protocol

multimedia card

degree Celsius

microamperes

microseconds

milliamperes

Megabits per second

Megabytes per second

mega hertz

MMC

MTP

µA

media transfer protocol

phase locked loop

power management IC

secure digital

µs

PLL

mA

Mbps

MBps

MHz

ms

ns

PMIC

SD

secure digital

SDIO

SLC

secure digital input / output

single-level cell

milliseconds

nanoseconds

ohms

SLCS

SLOE

SLRD

SLWR

SPI

Slave Chip Select

Ω

Slave Output Enable

Slave Read

pF

pico Farad

V

volts

Slave Write

serial peripheral interface

session request protocol

universal serial bus

wafer level chip scale package

SRP

USB

WLCSP

Document Number: 001-84160 Rev. *B

Page 49 of 50

CYUSB3035

Document History Page

Document Title: CYUSB3035, EZ-USB^®FX3S SuperSpeed USB Controller

Document Number: 001-84160

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

3786345

3900859

4027072

SAMT

12/06/2012 New data sheet.

*A

*B

02/11/2013 Updated Ordering Information (Updated part numbers).

06/20/2013 Added new MPNs in Ordering Information.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Lighting & Power Control

Community | Forums | Blogs | Video | Training

Technical Support

Memory

cypress.com/go/memory

cypress.com/go/psoc

cypress.com/go/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-84160 Rev. *B

Revised June 20, 2013

Page 50 of 50

®

EZ-USB™ is a trademark and West Bridge is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their

respective holders.


型号：	CYUSB3033-BZXC
厂家：	CYPRESS
描述：	EZ-USBÂ® FX3S SuperSpeed USB Controller EZ- USBÂ® FX3S超高速USB控制器控制器
文件：	总50页 (文件大小：1014K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYUSB3033-BZXC [CYPRESS]

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