CYUSB3065-BZXC [INFINEON]
EZ-USB™ CX3 MIPI CSI2至USB 5 Gbps相机控制器;
| 型号： | CYUSB3065-BZXC |
| 厂家： | 
Infineon |
| 描述： | EZ-USB™ CX3 MIPI CSI2至USB 5 Gbps相机控制器 时钟 控制器 外围集成电路 |
| 文件： | 总52页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYUSB306X
EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB
bridge controller
Features
• Universal Serial Bus (USB) integration
- USB 3.0 and USB 2.0 peripherals, compliant with USB 3.0 specification 1.0
- 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
- Thirty-two physical endpoints
• MIPI CSI-2 RX interface
- MIPI CSI-2 compliant (Version 1.01, Revision 0.04 – 2nd April 2009)
- Supports up to four data lanes (CYUSB3065 supports up to four lanes; CYUSB3064 supports up to two lanes)
- Each lane supports up to 1 Gbps (CYUSB3065 supports up to four lanes; CYUSB3064 supports up to two lanes)
- CCI interface for image sensor configuration
• Supports the following video data formats:
- User-defined 8-bit
- RAW8/10/12/14
- YUV422 (CCIR/ITU 8/10bit), YUV444
- RGB888/666/565
• Fully accessible 32-bit CPU
- ARM926EJ-S core with 200-MHz operation
- 512-KB or 256-KB embedded SRAM
• Additional connectivity to the following peripherals:
- I2C master controller at 1 MHz
- I2S master (transmitter only) at sampling frequencies of 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and
192 kHz
- UART support of up to 4 Mbps
- SPI master at 33 MHz
• 12 GPIOs
• Ultra-low-power in core power-down mode
• Independent power domains for core and I/O
- Core operation at 1.2 V
- I2S, UART, and SPI operation at 1.8 to 3.3 V
- I2C, I/O operation at 1.8 to 3.3 V
• 10 × 10 mm, 0.8-mm pitch Pb-free ball grid array (BGA) package
• EZ-USB™ software development kit (SDK) for easy code development
Errata: For information on silicon errata, see “Errata” on page 46. Details include trigger conditions, devices
affected, and proposed workaround.
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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Applications
Applications
• Digital video cameras
• Digital still cameras
• Webcams
• Scanners
• Video conference systems
• Gesture-based control
• Surveillance cameras
• Medical imaging devices
• Video IP phones
• USB microscopes
• Industrial cameras
Logic block diagram
JTAG
CPU
ARM926EJ-S
SSRX-
CP / CM
SSRX+
SSTX-
SS
Peripheral
D0P / D0M
USB
Port
32
EPs
MIPI CSI-2 RX
D1P / D1M
SSTX+
interface
HS/FS
Peripheral
D2P / D2M
D+
D-
D3P / D3M
MCLK
XRST
XSHUTDOWN
Program
RAM
RESET#
CLKIN
CLKIN_32
REFCLK
I2S
SPI
UART
I2C
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More information
More information
Infineon provides a wealth of data at www.infineon.com to help you to select the right device for your design,
and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of
resources refer to the Infineon web page for CX3 at www.infineon.com/CX3.
• Overview: USB Portfolio
• USB 3.0 Product Selectors: FX3, FX3S, CX3, HX3
• Application notes: Infineon offers a large number of USB application notes covering a broad range of topics,
from basic to advanced level. Recommended application notes for getting started with CX3 are:
- AN75705 - Getting Started with EZ-USB™ FX3
- AN90369 - How to Interface a MIPI CSI-2 Image Sensor With EZ-USB™ CX3
- AN75779 - How to Implement an Image Sensor Interface with EZ-USB™ FX3 in a USB Video Class (UVC)
Framework
- AN76405 - EZ-USB™ FX3 Boot Options
- AN70707 - EZ-USB™ FX3/FX3S Hardware Design Guidelines and Schematic Checklist
- AN86947 - Optimizing USB 3.0 Throughput with EZ-USB™ FX3
- AN231295 - Getting started with EZ-USB™ SX3
• Code Examples:
- USB Super-Speed
• Technical Reference Manual (TRM):
- EZ-USB™ CX3 Technical Reference Manual
• Knowledge Base Articles:
- Analysis of CX3 Video Timing Parameters - KBA226779
- Analysis of CX3 Clocking Parameters - KBA226758
- CX3 Firmware: Frequently Asked Questions - KBA91297
- CX3 Hardware: Frequently Asked Questions - KBA91295
- CX3 Application Software / USB Driver: Frequently Asked Questions - KBA91298
- Knowledge Base - Cypress Semiconductor Cage Code - KBA89258
• Development Kits:
- EZ-USB™ CX3 THEIA-CAM - 13MP PDAF UVC Camera Solution
- Denebola - USB 3.0 UVC Reference Design Kit (RDK)
• Models:
- CX3 Device OrCad Schematic Symbol
- CYUSB306x - IBIS
EZ-USB™ Software Development Kit
Infineon delivers the complete firmware stack for CX3, in order to easily integrate SuperSpeed USB into any
embedded MIPI image sensor application. The Software Development Kit (FX3 SDK) comes with tools, drivers
and application examples, which help accelerate application development. The FX3 SDK Setup includes CX3 APIs
and example firmware for OmniVision OV5640 and Aptina AS0260 image sensor interface. The CX3 MIPI
Configuration Tool Eclipse plugin for the FX3 SDK accelerates CX3 firmware development for any other image
sensor.
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Table of contents
Table of contents
Features ...........................................................................................................................................1
Applications......................................................................................................................................2
Logic block diagram ..........................................................................................................................2
More information ..............................................................................................................................3
EZ-USB™ Software Development Kit....................................................................................................3
Table of contents...............................................................................................................................4
1 Functional overview .......................................................................................................................6
2 Application examples......................................................................................................................7
3 USB interface .................................................................................................................................8
3.1 ReNumeration.........................................................................................................................................................8
3.2 VBUS overvoltage protection.................................................................................................................................8
4 MIPI CSI-2 RX interface ....................................................................................................................9
4.1 Additional outputs..................................................................................................................................................9
5 CPU .............................................................................................................................................10
6 JTAG interface ..............................................................................................................................11
7 Other interfaces............................................................................................................................12
7.1 UART interface ......................................................................................................................................................12
7.2 I2C interface ..........................................................................................................................................................12
7.3 I2S interface ..........................................................................................................................................................12
7.4 SPI interface ..........................................................................................................................................................13
8 Boot options.................................................................................................................................14
9 Reset ...........................................................................................................................................15
9.1 Hard Reset.............................................................................................................................................................15
9.2 Soft Reset ..............................................................................................................................................................15
10 Clocking .....................................................................................................................................16
10.1 32-kHz watchdog timer clock input ...................................................................................................................16
11 Power ........................................................................................................................................17
11.1 Power modes ......................................................................................................................................................17
12 Configuration options .................................................................................................................19
13 Digital I/Os .................................................................................................................................20
14 GPIOs.........................................................................................................................................21
15 EMI ............................................................................................................................................22
16 System-level ESD ........................................................................................................................23
17 Pin configuration ........................................................................................................................24
18 Pin description ...........................................................................................................................25
19 Electrical specifications...............................................................................................................29
19.1 Absolute maximum ratings ................................................................................................................................29
19.2 Operating conditions..........................................................................................................................................29
19.3 DC specifications.................................................................................................................................................30
19.4 MIPI D-PHY electrical characteristics .................................................................................................................32
20 Thermal characteristics...............................................................................................................33
21 AC timing parameters..................................................................................................................34
21.1 MIPI data to clock timing reference ...................................................................................................................34
21.2 Reference clock specifications...........................................................................................................................34
21.3 MIPI CSI signal low power AC characteristics....................................................................................................35
21.4 AC specifications.................................................................................................................................................35
21.5 Serial peripherals timing ....................................................................................................................................36
22 Reset sequence...........................................................................................................................41
23 Ordering Information ..................................................................................................................42
23.1 Ordering code definitions...................................................................................................................................42
24 Package diagram ........................................................................................................................43
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Table of contents
25 Acronyms ...................................................................................................................................44
26 Document conventions................................................................................................................45
26.1 Units of measure .................................................................................................................................................45
27 Errata ........................................................................................................................................46
27.1 Part numbers affected........................................................................................................................................46
27.2 Qualification status.............................................................................................................................................46
27.3 Errata ...................................................................................................................................................................46
Revision history ..............................................................................................................................51
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Functional overview
1
Functional overview
Infineon’s EZ-USB™ CX3 is the next-generation bridge controller that can connect devices with the Mobile
Industry Processor Interface – Camera Serial Interface 2 (MIPI CSI-2) interface to any USB 3.0 Host.
CX3 has a 4-lane CSI-2 receiver with up to 1 Gbps on each lane. It supports video data formats such as
RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-bit), RGB888/666/565, and user-defined 8-bit.
CX3 has integrated the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S micropro-
cessor for powerful data processing and for building custom applications.
CX3 contains 512 KB of on-chip SRAM (see “Ordering Information” on page 42) for code and data. EZ-USB™ CX3
also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S.
CX3 comes with application development tools. The software development kit comes with application examples
for accelerating time-to-market.
CX3 complies with the USB 3.0 v1.0 specification and is also backward compatible with USB 2.0. It also complies
with the MIPI CSI-2 v1.01, revision 0.04 specification dated 2nd April 2009.
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Application examples
2
Application examples
In a typical application (see Figure 1), CX3 acts as the main processor and connects to an image sensor, an audio
device, or camera control devices amongst others.
Clock
6-40 MHz
Clock
19.2 MHz
Power
subsystem
VDD
REFCLK
CLKIN
MIPI CSI-2
RX
USB
Host
USB
EZ-USB CX3
Image
sensor
I2C
I2S
SPI
Audio
output
Audio
input
Autofocus, Pan, Tilt, Zoom,
Shutter control, Lighting, etc.
Figure 1
EZ-USB™ CX3 example application
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USB interface
3
USB interface
CX3 complies with the following specifications and supports the following features:
• Supports USB peripheral functionality compliant with USB 3.0 Specification, Revision 1.0, and is also backward
compatible with the USB 2.0 Specification.
• As a peripheral, CX3 is capable of SuperSpeed, High-Speed, and Full-Speed.
• Supports up to 16 IN and 16 OUT endpoints
• As a USB peripheral, CX3 supports USB-attached storage (UAS), USB Video Class (UVC), and Media Transfer
Protocol (MTP) USB peripheral classes. As a USB peripheral, all other device classes are supported only in
pass-through mode when handled entirely by a host processor external to the device.
EZ-USB CX3
VUSB
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
Figure 2
USB interface signals
3.1
ReNumeration
Because of CX3’s soft configuration, one chip can take on the identities of multiple distinct USB devices.
When first plugged into USB, CX3 enumerates automatically with the Cypress Vendor ID (0x04B4) and downloads
the firmware and USB descriptors over the USB interface. The downloaded firmware executes an electrical
disconnect and connect. CX3 enumerates again, this time as a device defined by the downloaded information.
This patented two-step process, called ReNumeration, happens instantly when the device is plugged in.
3.2
VBUS overvoltage protection
The maximum input voltage on CX3's VUSB pin is 6 V. A charger can supply up to 9 V on VUSB. In this case, an
external overvoltage protection (OVP) device is required to protect CX3 from damage on VUSB. Figure 3 shows
the system application diagram with an OVP device connected on VUSB. Refer to “DC specifications” on page 30
for the operating range of VUSB.
Note The VBUS pin of the USB connector should be connected to the VUSB pin of CX3.
POWER SUBSYSTEM
EZ-USB CX3
VUSB
1
2
OVP device
SSRX-
SSRX+
SSTX-
SSTX+
D-
3
4
5
6
7
8
9
D+
GND
Figure 3
System diagram with OVP device for VUSB
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MIPI CSI-2 RX interface
4
MIPI CSI-2 RX interface
The Mobile Industry Processor Interface (MIPI) association defined the Camera Serial Interface 2 (CSI-2) standard
to enable image data to be sent on high-bandwidth serial lines.
CX3 implements a MIPI CSI-2 Receiver with the following features:
1. It can receive clock and data in 1, 2, 3, or 4 lanes. (CYUSB3065 part supports up to four lanes; CYUSB3064 part
supports up to two lanes)
2. Up to 1 Gbps of data on each CSI lane is supported (total maximum bandwidth should not exceed 2.4 Gbps).
3. Video formats such as RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-bit), RGB888/666/565, and User-Defined 8-bit
are supported
4. A CCI interface (compatible with 100-kHz or 400-kHz I2C interface with 7-bit addressing) is provided to
configure the sensor.
5. GPIOs are available for synchronization of external flash or lighting system with image sensors to illuminate
the scene that improves the image quality by improving Signal to noise ratio.
6. GPIOs can also be used to synchronize the image sensor with external events, so that image can be captured
based on external event.
7. Serial interfaces (such as I2C, I2S, SPI, UART) are available to implement camera functions such as Auto focus
and Pan, Tilt, Zoom (PTZ)
4.1
Additional outputs
In addition to the standard MIPI CSI-2 signals, the following three additional outputs are provided:
1. XRST: this can be used to reset the image sensor
2. XSHUTDOWN: this pin can be used to put the sensor to a standby/shutdown mode
3. MCLK: this pin can provide the clock output. It can be used only for testing the image sensor. For production,
use an external clock generator as clock input for image sensors.
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CPU
5
CPU
CX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU. The core has direct access to 16 KB of Instruction
Tightly Coupled Memory (TCM) and 8 KB of data TCM. The ARM926EJ-S core provides a JTAG interface for
firmware debugging.
CX3 offers the following advantages:
• Integrates 512 KB of embedded SRAM for code and data and 8 KB of instruction cache and data cache.
• Implements efficient and flexible DMA connectivity between the various peripherals (such as, USB, CSI-2 Rx, I2S,
SPI, and UART), requiring firmware only to configure data accesses between peripherals, which are then
managed by the DMA fabric.
• Allows easy application development on industry-standard development tools for ARM926EJ-S.
Examples of the CX3 firmware are available with the Infineon EZ-USB™ CX3 Development Kit. Software APIs that
can be ported to an external processor are available with the Infineon EZ-USB™ CX3 Software Development Kit.
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JTAG interface
6
JTAG interface
CX3’s JTAG interface has a standard five-pin interface to connect to a JTAG debugger in order to debug firmware
through the CPU-core's on-chip-debug circuitry.
Industry-standard debugging tools for the ARM926EJ-S core can be used for the CX3 application development.
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Other interfaces
7
Other interfaces
CX3 supports the following serial peripherals:
• UART
• I2C
• I2S
• SPI
The “CYUSB306X pin list” on page 25 shows the details of how these interfaces are mapped.
7.1
UART interface
The UART interface of CX3 supports full-duplex communication. It includes the signals noted in Table 1.
Table 1
UART interface signals
Signal
TX
RX
CTS
RTS
Description
Output signal
Input signal
Flow control
Flow control
The UART is capable of generating a range of baud rates, from 300 bps to 4608 Kbps, selectable by the firmware.
If flow control is enabled, then CX3's UART only transmits data when the CTS input is asserted. In addition to this,
CX3's UART asserts the RTS output signal, when it is ready to receive data.
7.2
I2C interface
CX3’s I2C interface is compatible with the I2C Bus Specification Revision 3. This I2C interface is capable of
operating only as I2C master; therefore, it may be used to communicate with other I2C slave devices. For example,
CX3 may boot from an EEPROM connected to the I2C interface, as a selectable boot option.
CX3’s I2C Master Controller also supports multi-master mode functionality.
The power supply for the I2C interface is VDDIO1, which is a separate power domain from the other serial periph-
erals. This gives the I2C interface the flexibility to operate at a different voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 400 kHz, and 1 MHz. When VDDIO1 is 1.8 V, 2.5 V, or 3.3 V, the
operating frequencies supported are 400 kHz and 1 MHz. The I2C controller supports the clock-stretching feature
to enable slower devices to exercise flow control.
The I2C interface’s SCL and SDA signals require external pull-up resistors. The pull-up resistors must be
connected to VDDIO1
.
Note I2C addresses with the pattern 0x0000111x are used internally and no slave devices with those addresses
should be connected to the bus.
7.3
I2S interface
CX3 has an I2S port to support external audio codec devices. CX3 functions as I2S Master as transmitter only. The
I2S interface consists of four signals: clock line (I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS), and
master system clock (I2S_MCLK). CX3 can generate the system clock as an output on I2S_MCLK or accept an
external system clock input on I2S_MCLK.
The sampling frequencies supported by the I2S interface are 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and
192 kHz.
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Other interfaces
7.4
SPI interface
CX3 supports an SPI Master interface on the Serial Peripherals port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication (see “SPI timing specification” on page 39 for
details on the modes) with the Start-Stop clock. This controller is a single-master controller with a single
automated SSN control. It supports transaction sizes ranging from 4 bits to 32 bits.
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Boot options
8
Boot options
CX3 can load boot images from various sources, selected by the configuration of the PMODE pins. Following are
the CX3 boot options:
• Boot from USB
• Boot from I2C
• Boot from SPI
- Infineon SPI flash parts supported are S25FS064S (64-Mb), S25FS128S (128-Mb) and S25LFL064L (64-Mb).
- W25Q32FW (32-Mb) is also supported.
Table 2
CX3 booting options
PMODE[2:0][1]
Boot from
USB boot
I2C, On failure, USB boot is enabled
I2C only
F11
F1F
1FF
0F1
SPI, On failure, USB boot is enabled
Note
1. F indicates Floating.
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Reset
9
Reset
9.1
Hard Reset
A hard reset is initiated by asserting the RESET# pin on CX3. The specific reset sequence and timing requirements
are detailed in Figure 11 and Table 18. All I/Os are tristated during a hard reset.
An additional reset pin called MIPI_RESET is provided that resets the MIPI CSI-2 core. It should be pulled down
with a resistor for normal operation.
9.2
Soft Reset
There are two types of Soft Reset:
• CPU Reset – The CPU Program Counter is reset. Firmware does not need to be reloaded following a CPU Reset.
• Whole Device Reset – This reset is identical to Hard Reset. The firmware must be reloaded following a Whole
Device Reset.
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Clocking
10
Clocking
CX3 requires two clocks for normal operation:
1. A 19.2-MHz clock to be connected at the CLKIN pin
2. A 6-MHz to 40-MHz clock to be connected at the REFCLK pin
Clock inputs to CX3 must meet the phase noise and jitter requirements specified in Table 3.
The input clock frequency is independent of the clock and data rate of the CX3 core or any of the device interfaces
(including the CSI-2 Rx Port). The internal PLL applies the appropriate clock-multiply option depending on the
input frequency.
Note REFCLK belongs to VDDIO1 power domain and CLKIN belongs to CVDDQ power domain. If same source is
used, the clock must be passed through a buffer with two outputs and then connected to the clock pins. Make
sure to power the clock buffer, CVDDQ and VDDIO1 with same voltage.
Table 3
CX3 input clock specifications
Specification
Min
Parameter
Description
Unit
Max
–75
100-Hz offset
1-kHz offset
10-kHz offset
100-kHz offset
1-MHz offset
–
–
–
–
–
dB
dB
dB
dB
dB
–104
–120
–128
–130
Phase noise
Maximum frequency
deviation
–
–
150
ppm
Duty cycle
Overshoot
Undershoot
Rise time/fall time
–
–
–
–
30
–
–
70
3
–3
3
%
%
%
ns
–
10.1
32-kHz watchdog timer clock input
CX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically
wake up the CX3 in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock,
which may be optionally supplied from an external source on a dedicated CX3 pin.
The firmware can disable the watchdog timer.
Table 4 provides the requirements for the optional 32-kHz clock input.
Table 4
32-kHz clock input requirements
Parameter
Duty cycle
Min
40
Max
60
Unit
%
Frequency deviation
Rise time/fall time
–
–
±200
200
ppm
ns
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Power
11
Power
CX3 has the following power supply domains:
• IO_VDDQ: This is a group of independent supply domains for digital I/Os.
- VDDIO1: GPIO, I2C, JTAG, XRST, XSHUTDOWN and REFCLK
- VDDIO2: UART and I2S (except MCLK)
- VDDIO3: I2S_MCLK and SPI
- CVDDQ: CLKIN
- VDD_MIPI: MIPI CSI-2 clock and data lanes
• VDD: This is the supply voltage for the logic core. The nominal supply-voltage level is 1.2 V. This supplies the core
logic circuits. The same supply must also be used for the following:
- AVDD: This is the 1.2 V supply for the PLL, crystal oscillator, and other core analog circuits.
- U3TXVDDQ/U3RXVDDQ: These are the 1.2 V supply voltages for the USB 3.0 interface.
• VUSB: This is the 4 V to 6 V power supply for the USB I/O and analog circuits. This supply powers the USB
transceiver through CX3’s internal voltage regulator. VUSB is internally regulated to 3.3 V.
Note The different power supplies have to be powered on or off in a specific sequence as illustrated in Figure 4.
11.1
Power modes
CX3 supports the following power modes:
• Normal mode: This is the full-functional operating mode. The internal CPU clock and the internal PLLs are
enabled in this mode.
- Normal operating power consumption does not exceed the sum of ICC Core max and ICC USB max
(see “DC specifications” on page 30 for current consumption specifications).
- The I/O power supplies VDDIO2 and VDDIO3 can be turned off when the corresponding interface is not in use.
VDDIO1 should never be turned off for normal operation.
• Low-power modes (see Table 5):
- Suspend mode with USB 3.0 PHY enabled
- Standby mode
- Core power-down mode
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Power
VUSB
(VBUS)
VDD
(VDD, AVDD,
VDD_MIPI)
VDDIO1
<= 10 ms
<= 10 ms
CVDDQ, VDDIO2,
VDDIO3
CLK_IN, REFCLK
RESET#
MIPI_RESET
>= 1 ms
XRST
(Image Sensor RESET)
User programmable
in firmware
Figure 4
Power-up sequence
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Configuration options
12
Configuration options
Table 5
Entry and exit methods for Low-Power modes
Low-Power mode Characteristics
Methods of Entry
Methods of Exit
• Power consumption in this mode does not
exceed ISB1
• USB 3.0 PHY is enabled and is in U3 mode
(one of the suspend modes defined by the
USB 3.0 specification). This one block
alone is operational with its internal clock,
while all other clocks are shut down
• D+ transitioning to low
or high
• All I/Os maintain their previous state
• D- transitioning to low
or high
• Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on or off
individually
• Firmware executing on ARM926EJ-S
core can put CX3 into the suspend
mode. For example, on USB suspend
condition, the firmware may decide
to put CX3 into suspend mode
• Resume condition on
SSRX±
Suspend Mode with
USB 3.0 PHY Enabled
• Detection of VBUS
• The states of the configuration registers,
buffer memory, and all internal RAM are
maintained
• Level detect on
UART_CTS
(programmable
polarity)
• All transactions must be completed before
CX3 enters suspend mode (state of
outstanding transactions are not
preserved)
• Assertion of RESET#
• The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
• The power consumption in this mode does
not exceed ISB3
• All configuration register settings and
program/data RAM contents are
preserved. However, data in the buffers or
other parts of the data path, if any, is not
guaranteed. Therefore, the external
processor should take care that the data
needed is read before putting CX3 into the
standby mode
• Detection of VBUS
• The firmware executing on
ARM926EJ-S core or external
processor configures the appropriate
register
• Level detect on
• The program counter is reset after waking
up from the standby mode
UART_CTS
Standby Mode
(programmable
polarity)
• GPIO pins maintain their configuration
• Internal PLL is turned off
• USB transceiver is turned off
• Assertion of RESET#
• ARM926EJ-S core is powered down. Upon
wakeup, the core re-starts and runs the
program stored in the program/data RAM
• Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on or off
individually
• The power consumption in this mode does
not exceed ISB4
• Core power is turned off
• Reapply VDD
• Assertion of RESET#
• All buffer memory, configuration registers,
and the program RAM do not maintain
state. After exiting this mode, reload the
firmware
Core Power-down
Mode
• Turn off VDD
• In this mode, all other power domains can
be turned on or off individually
Configuration options are available for specific usage models.
Datasheet
19
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Digital I/Os
13
Digital I/Os
CX3 has internal firmware-controlled pull-up or pull-down resistors on all digital I/O pins. An internal 50-k
resistor pulls the pins high, while an internal 10-k resistor pulls the pins low to prevent them from floating. The
I/O pins may have the following states:
• Tristated (High-Z)
• Weak pull-up (via internal 50 k)
• Pull-down (via internal 10 k)
• Hold (I/O hold its value) when in low-power modes
• The JTAG TDI, TMC, and TRST# signals have fixed 50-kinternal pull-ups, and the TCK signal has a fixed 10-k
pull-down resistor.
All unused I/Os should be pulled high by using the internal pull-up resistors. All unused outputs should be left
floating. All I/Os can be driven at full-strength, three-quarter strength, half-strength, or quarter-strength. These
drive strengths are configured separately for each interface.
Datasheet
20
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
GPIOs
14
GPIOs
CX3 provides 12 pins for general purpose I/O (for example, can be used for lighting, sync-in, sync-out and so on).
See “Pin configuration” on page 24 for pinout details.
All GPIO pins support an external load of up to 16 pF for every pin.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
EMI
15
EMI
CX3 can meet EMI requirements outlined by FCC 15B (USA) and EN55022 (Europe) for consumer electronics at
system level. CX3 can tolerate reasonable EMI, conducted by the aggressor, outlined by these specifications and
continue to function as expected.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
System-level ESD
16
System-level ESD
CX3 has built-in ESD protection on the D+, D–, and GND pins on the USB interface. The ESD protection levels
provided on these ports are:
• ±2.2-kV human body model (HBM) based on JESD22-A114 specification
• ±6-kV contact discharge and ±8-kV air gap discharge based on IEC61000-4-2 level 3A using external system-level
protection devices
• ± 8-kV contact discharge and ±15-kV air gap discharge based on IEC61000-4-2 level 4C using external
system-level protection devices
This protection ensures that the device continues to function after ESD events up to the levels stated in this
section.
The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to ±2.2-kV HBM internal ESD protection.
Datasheet
23
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Pin configuration
17
Pin configuration
Figure 5
CX3 ball map (top view)
A1
U3VSSQ
B1
A2
U3RXVDDQ
B2
A3
SSRXM
B3
A4
SSRXP
B4
A5
SSTXP
B5
A6
SSTXM
B6
A7
AVDD
B7
A8
VSS
B8
A9
DP
B9
A10
DM
A11
GPIO[24]
B11
B10
VDD
C10
VDDIO3
C1
VSS
GPIO[23]
C3
GPIO[21]
C4
U3TXVDDQ
C5
CVDDQ
C6
AVSS
C7
VSS
C8
VSS
C9
TRST#
C11
C2
SPI_SSN /
GPIO[54]
SPI_MISO /
GPIO[55]
I2S_MCLK
/ GPIO[57]
VDD
GPIO[26]
RESET#
GPIO[18]
D6
GPIO[19]
D7
GPIO[22]
D8
GPIO[45]
D9
TDO
D1
D2
D3
D4
D5
D10
D11
I2S_CLK /
GPIO[50]
I2S_SD /
GPIO[51]
I2S_WS /
GPIO[52]
SPI_SCK /
GPIO[53]
SPI_MOSI /
GPIO[56]
CLKIN_32
E6
CLKIN
E7
VSS
I2C_SCL
E9
I2C_SDA GPIO[17]
E1
E2
E3
VDDIO2
F3
E4
E5
E8
E10
VUSB
F10
E11
VSS
UART_CTS /
GPIO[47]
UART_RX /
GPIO[49]
UART_TX /
GPIO[48]
VSS
GPIO[20]
F6
TDI
TMS
F8
VDD
F9
F1
DNU
G1
F2
F4
XRST
G4
F5
F7
F11
UART_RTS /
GPIO[46]
REFCLK
G2
GPIO[44]
G3
TCK
DNU
G7
DNU
G8
DNU
G9
DNU
G10
VDD
G5
GPIO[25]
H5
G6
G11
PMODE[0] /
GPIO[30]
VSS
H1
XSHUTDOWN
H2
MCLK
H3
HSYNC_test
H6
DNU
H7
DNU
H8
DNU
H9
DNU
H10
DNU
VSS
H4
H11
PMODE[1] /
GPIO[31]
VDD
DNU
DNU
VSYNC_test
MIPI RESET
J6
DNU
PCLK_test
J8
DNU
J9
VDDIO1
J1
DNU
K1
J2
DNU
K2
J3
DNU
K3
J4
DNU
K4
J5
MIPI_D0P
K5
J7
MIPI_CP
K7
J10
DNU
K10
DNU
L10
J11
VDD
K11
DNU
L11
MIPI_D1P1
MIPI_D2P1, 2 MIPI_D2N1, 2
K6
K8
K9
DNU
L9
MIPI_D1N1
MIPI_D3N1, 2
DNU
L1
DNU
L2
VSS
L3
VSS
L4
MIPI_D0N
L5
MIPI_CN
L7
L6
L8
PMODE[2] /
GPIO[32]
MIPI_D3P1, 2
VSS
VSS
VSS
VDD_MIPI
VSS
VDD
VDDIO1
DNU
VSS
1. Unused MIPI input data lanes to be connected to GND.
2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available in the CYUSB3064 part. These pins should be left "open" in the customer board.
Legend
Ground
USB PHY power supply; Clock power supply
Power supply
Datasheet
24
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Pin description
18
Pin description
Table 6
CYUSB306X pin list
Pin#
Pin name
I/O
CX3
F10
F9
DNU
DNU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
F7
DNU
G10
G9
F8
DNU
DNU
DNU
H10
H9
J10
H7
K11
L10
K10
K9
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
G7
G8
K2
DNU
DNU
DNU
J4
DNU
K1
DNU
J2
DNU
J3
DNU
J1
DNU
H2
H3
G6
H5
H8
DNU
DNU
HSYNC_test
VSYNC_test
PCLK_test
VDDIO1 power domain
D11
C6
C7
E6
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[44]
GPIO[45]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B4
C8
B3
A11
G5
C4
F3
C9
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Pin description
Table 6
CX3
CYUSB306X pin list (continued)
Pin#
Pin name
I/O
G4
H4
L4
F1
H6
C5
F4
G2
G3
PMODE[0] / GPIO[30]
PMODE[1] / GPIO[31]
PMODE[2] / GPIO[32]
DNU
I/O
I/O
I/O
I/O
I/O
I
MIPI RESET
RESET#
XRST
O
XSHUTDOWN
MCLK
O
O
VDDIO2 power domain
F5
UART_RTS / GPIO[46]
UART_CTS / GPIO[47]
UART_TX / GPIO[48]
UART_RX / GPIO[49]
I2S_CLK / GPIO[50]
I2S_SD / GPIO[51]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
E1
E5
E4
D1
D2
D3
I2S_WS / GPIO[52]
VDDIO3 power domain
D4
C1
SPI_SCK / GPIO[53]
SPI_SSN / GPIO[54]
SPI_MISO / GPIO[55]
SPI_MOSI / GPIO[56]
I2S_MCLK / GPIO[57]
I/O
I/O
I/O
I/O
I/O
C2
D5
C11
USB port (U3TXVDDQ/U3RXVDDQ power domain)
A3
SSRXM
SSRXP
SSTXM
SSTXP
I
A4
I
A6
O
O
A5
USB port (VUSB power domain)
A9
DP
I/O
I/O
A10
DM
VDDIO1 power domain
F2
REFCLK
I
VDD_MIPI power domain
J7
K7
J5
K5
J6
K6
J9
MIPI_CP
MIPI_CN
MIPI_D0P
MIPI_D0N
I
I
I
I
I
I
I
1
MIPI_D1P
MIPI_D1N
1
1, 2
MIPI_D2N
Datasheet
26
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Pin description
Table 6
CX3
CYUSB306X pin list (continued)
Pin#
Pin name
I/O
1, 2
J8
L8
K8
MIPI_D2P
MIPI_D3P
MIPI_D3N
I
I
I
1, 2
1, 2
CVDDQ power domain
D7
CLKIN
I
I
D6
CLKIN_32
VDDIO1 power domain
D9
I2C_SCL
I2C_SDA
TDI
I/O
D10
I/O
E7
I
O
I
C10
TDO
B11
TRST#
TMS
E8
I
F6
TCK
I
Power domains
E10
A1
VUSB
U3VSSQ
VDDIO1
VDDIO1
VDDIO2
VDDIO3
CVDDQ
U3TXVDDQ
U3RXVDDQ
AVDD
AVSS
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
H11
L9
E3
B1
B6
B5
A2
A7
B7
L5
VDD_MIPI
VDD
B10
J11
C3
VDD
VDD
E9
VDD
F11
H1
L7
VDD
VDD
VDD
D8
E2
VSS
VSS
E11
G1
A8
VSS
VSS
VSS
G11
L1
VSS
VSS
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Pin description
Table 6
CX3
CYUSB306X pin list (continued)
Pin#
Pin name
I/O
B8
L6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
B2
L11
B9
K4
L3
K3
L2
1. Unused MIPI input data lanes to be connected to GND.
2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available in the CYUSB3064 part. These pins should be
left "open" in the customer board.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Electrical specifications
19
Electrical specifications
19.1
Absolute maximum ratings
Exceeding maximum ratings may shorten the useful life of the device.
Storage temperature
–65°C to +150°C
1.25 V
Supply voltage to ground potential
VDD, AVDDQ
VDDIO1, VDDIO2, VDDIO3
3.6 V
U3TXVDDQ, U3RXVDDQ
1.25 V
DC input voltage to any input pin
VCC + 0.3
DC voltage applied to outputs in high-Z state
(VCC is the corresponding I/O voltage)
VCC + 0.3
Maximum latch-up current
140 mA
Maximum output short-circuit current for all I/O configurations. (VOUT = 0 V)
–100 mA
19.2
Operating conditions
TA (ambient temperature under bias)
Commercial
Industrial
0°C to +70°C
–40°C to +85°C
V
V
V
DD, AVDDQ, U3TXVDDQ, U3RXVDDQ Supply voltage
USB supply voltage
DDIO1, VDDIO2, VDDIO3, CVDDQ Supply voltage
1.15 V to 1.25 V
4 V to 6 V
1.7 V to 3.6 V
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Electrical specifications
19.3
DC specifications
Table 7
DC specifications
Parameter Description
Min
1.15
1.15
Max
1.25
1.25
Unit Notes
VDD
Core voltage supply
V
V
1.2-V typical
1.2-V typical
AVDD
Analog voltage supply
MIPI bridge D-PHY supply
voltage
VDD_MIPI
VDDIO1
VDDIO2
1.15
1.7
1.25
3.6
V
V
V
1.2-V typical
I2C, JTAG and GPIO power
domain
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
UART/I2S power supply
domain
SPI/I2S power supply
domain
1.7
3.6
VDDIO3
VUSB
1.7
4
3.6
6
V
V
1.8-, 2.5-, and 3.3-V typical
5-V typical
USB voltage supply
1.2-V typical. A 22-µF bypass
capacitor is required on this power
supply.
1.2-V typical. A 22-µF bypass
capacitor is required on this power
supply.
U3TXVDDQ USB 3.0 1.2-V supply
U3RXVDDQ USB 3.0 1.2-V supply
1.15
1.25
V
1.15
1.7
1.25
3.6
V
V
V
CVDDQ
VIH1
Clock voltage supply
Input HIGH voltage 1
1.8-, 3.3-V typical
For 2.0 V VCC 3.6 V (except USB
and MIPI CSI-2 pins).VCC is the
corresponding I/O voltage supply.
0.625 × VCC VCC + 0.3
For 1.7 V VCC 2.0 V
(except USB USB and MIPI CSI-2
pins).VCC is the corresponding I/O
voltage supply.
VCC is the corresponding I/O voltage
supply.
VIH2
Input HIGH voltage 2
Input LOW voltage
VCC – 0.4
–0.3
VCC + 0.3
V
V
0.25 ×
VCC
VIL
I
OH (max) = –100 µA tested at quarter
drive strength. VCC is the corre-
sponding I/O voltage supply.
See Table 8 for values of IOH at
VOH
VOL
IIX
Output HIGH voltage
Output LOW voltage
0.9 × VCC
–
0.1 × VCC
1
V
V
various drive strength and VCC
.
I
OL (min) = +100 µA tested at quarter
drive strength. VCC is the
–
corresponding I/O voltage supply.
See Table 8 for values of IOL at
various drive strength and VCC
.
All I/O signals held at VDDQ
(For I/Os with a pull-up or pull-down
Input leakage current for all
pins except
SSTXP/SSXM/SSRXP/SSRX
M
–1
µA resistor connected, the leakage
current increases by VDDQ/RPU or
VDDQ/RPD
)
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Electrical specifications
Table 7
DC specifications (continued)
Parameter Description
Min
Max
Unit Notes
Output High-Z leakage
current for all pins except
SSTXP/ SSXM/
SSRXP/SSRXM and MIPI
CSI-2 signals
IOZ
–1
1
µA All I/O signals held at VDDQ
Core and analog voltage
operating current
USB voltage supply
operating current
ICC Core
ICC USB
–
–
192
60
–
mA Total current through AVDD, VDD
mA
µA
–
Core: 558.35
µA
I/O: 4.58 µA
USB: 4672 µA
Core: 148.31
µA
Total suspend current
during suspend mode with
USB 3.0 PHY enabled
Core Current is measured through
VDD, AVDD and VDD_MIPI
ISB1
.
–
–
µA
µA
I/O Current is measured through
VDDIO1 to VDDIO3
.
–
µA
Total standby current
during core power-down
mode
USB Current is measured through
ISB3
I/O: 3.16 µA
USB: 15.8 µA
–
–
µA
µA
VUSB, U3TXVDDQ and U3RXVDDQ
.
Voltage ramp rate on core
and I/O supplies
Noise level permitted on
VDD and I/O supplies
Noise level permitted on
AVDD supply
V/m
s
VRAMP
VN
0.2
–
12
100
20
Voltage ramp must be monotonic
Max p-p noise level permitted on all
supplies except AVDD
Max p-p noise level permitted on
AVDD
mV
mV
VN_AVDD
–
Table 8
IOH/IOL values for different drive strength and VDDIO values
V
DDIO (V)
VOH (V)
VOL (V)
Drive strength
Quarter
Half
Three-Quarters
Full
Quarter
Half
Three-Quarters
Full
Quarter
Half
Three-Quarters
Full
IOH max (mA)
1.02
IOL min (mA)
2.21
1.51
1.83
2.28
5.03
7.38
8.89
11.07
7.80
11.36
13.64
16.92
3.28
3.85
4.73
3.96
5.84
6.89
8.61
5.74
1.7
2.5
3.6
1.53
0.17
2.25
3.24
0.25
0.36
8.64
10.15
12.67
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Electrical specifications
19.4
MIPI D-PHY electrical characteristics
Table 9
MIPI D-PHY electrical characteristics
Specifications
Nom
Parameter Description
Unit
Min
Max
MIPI D-PHY RX DC characteristics
VPIN
VIH
Pin signal voltage range
Logic 1 input voltage
–50
880
–
–
–
–
–
–
–
–
–
1350
–
mV
mV
mV
mV
mV
mV
mV
mV
VIL
Logic 0 input voltage
550
330
70
–
460
–
VCMRX (DC)
VIDTH
VIDTL
VIHHS
VILHS
Common-mode voltage HS receiver mode
Differential input high threshold
Differential input low threshold
Single-ended input high voltage
Single-ended input low voltage
70
–70
–40
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Thermal characteristics
20
Thermal characteristics
Table 10
Thermal characteristics
Value
125
24.4
17.27
5.5
Unit
C
C/W
C/W
C/W
Parameter Description
TJ MAX
JA
Maximum Junction Temperature
Thermal resistance (junction to ambient)
Thermal resistance (junction to board)
Thermal resistance (junction to case)
JB
JC
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
AC timing parameters
21
AC timing parameters
21.1
MIPI data to clock timing reference
Reference Time
TSETUP
THOLD
0.5UIINST
TSKEW
+
CLKp
CLKn
1 UIINST
TCLKp
Figure 6
Table 11
MIPI CSI signal data to clock timing reference
MIPI data to clock timing reference
Parameter Description
Min
Max
Unit
TSKEW
TSETUP
THOLD
UIINST
TCLKp
Data to clock skew measured at the transmitter
–0.15
0.15
0.15
1
0.15
–
–
12.5
25
UIINST
UIINST
UIINST
ns
Data to clock setup time at receiver
Clock to data hold time at receiver
One data bit time (instantaneous)
Period of dual data rate clock
2
ns
21.2
Reference clock specifications
Table 12
Reference clock specifications
Parameter
Description
Min
Max
Unit Notes
RefClk
RefclkDutyCyl
Reference clock frequency
Duty cycle
6
40%
40
60%
MHz –
–
–
Reference clock input
period jitter
RefClkPJ
-100
100
ps
–
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
AC timing parameters
21.3
MIPI CSI signal low power AC characteristics
2*TLPX
2*TLPX
eSPIKE
VIH
VIL
Input
eSPIKE
TMIN-RX
TMIN-RX
Output
Figure 7
Table 13
MIPI CSI bus input glitch rejection
MIPI CSI signal low power AC characteristics
Parameter Description
Min
Max
Unit Notes
Time-voltage integration of a spike
above VIL when being in LP-0 or below
V.ps VIH when being in LP-1 state.
An impulse less than this will not change
the receiver state.
eSPIKE
Input noise rejection
–
300
Minimum pulse width
response
An input pulse greater than this shall
toggle the output.
TMIN-RX
20
–
ns
peak interference
amplitude
Interference frequency
Length of any low power
state period
VINT
FINT
TLPX
–
200
–
mV
MHz –
ns
–
450
50
–
–
21.4
AC specifications
Table 14
AC specifications
Parameter Description
Min
Max
Unit Details / conditions
Common-mode
interference beyond
450 MHz
ΔVCMRX(HF) is the peak amp. Of a sine
mV wave superimposed on the receiver
inputs.
ΔVCMRX(HF)
–
100
Common-mode inter-
ference beyond
50 - 450 MHz
Excluding static ground shift of 50 mV.
mV Voltage difference compared to the DC
average common-mode potential
ΔVCMRX(LF)
-50
50
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
AC timing parameters
21.5
Serial peripherals timing
I2C timing
21.5.1
Figure 8
Table 15
I2C timing definition
I2C timing parameters[2]
Parameter Description
I2C Standard Mode parameters
Min
Max
Unit
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
SCL clock frequency
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
Setup time for a repeated START condition
Data hold time
0
4
4.7
4
4.7
0
250
–
–
4
4.7
–
–
100
–
–
–
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
–
–
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
1000
300
–
tf
tSU:STO
tBUF
tVD:DAT
tVD:ACK
tSP
–
3.45
3.45
n/a
Data valid ACK
Pulse width of spikes that must be suppressed by input filter
n/a
Note
2. All parameters guaranteed by design and validated through characterization.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
AC timing parameters
Table 15
I2C timing parameters[2] (continued)
Parameter Description
I2C Fast Mode parameters
Min
Max
Unit
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
SCL clock frequency
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
Setup time for a repeated START condition
Data hold time
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
0
0.6
1.3
0.6
0.6
0
100
–
–
0.6
1.3
–
–
0
400
–
–
–
–
–
–
300
300
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tf
tSU:STO
tBUF
tVD:DAT
tVD:ACK
tSP
–
0.9
0.9
50
Data valid ACK
Pulse width of spikes that must be suppressed by input filter
I2C Fast Mode Plus parameters
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
SCL clock frequency
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
Setup time for a repeated START condition
Data hold time
0
0.26
0.5
0.26
0.26
0
50
–
–
0.26
0.5
–
–
0
1000
–
–
–
–
–
–
120
120
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus-free time between a STOP and START condition
Data valid time
tf
tSU:STO
tBUF
tVD:DAT
tVD:ACK
tSP
–
0.45
0.55
50
Data valid ACK
Pulse width of spikes that must be suppressed by input filter
Note
2. All parameters guaranteed by design and validated through characterization.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
AC timing parameters
21.5.2
I2S timing diagram
tT
tTR
tTF
tTH
tTL
SCK
tThd
SA,
WS (output)
tTd
Figure 9
Table 16
I2S transmit cycle
I2S timing parameters[3]
Parameter Description
tT
Min
tTR
0.35 tTR
0.35 tTR
Max
–
–
–
0.15 tTR
0.15 tTR
–
Unit
ns
ns
ns
ns
ns
ns
ns
I2S transmitter clock cycle
I2S transmitter cycle LOW period
tTL
tTH
tTR
tTF
tThd
tTd
I2S transmitter cycle HIGH period
I2S transmitter rise time
–
–
0
–
I2S transmitter fall time
I2S transmitter data hold time
I2S transmitter delay time
0.8 tT
Note tT is selectable through clock gears. Max tTR is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
3. All parameters guaranteed by design and validated through characterization.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
AC timing parameters
21.5.3
SPI timing specification
SSN
(output)
tssnh
tsck
tlag
tlead
SCK
(CPOL=0,
Output)
trf
twsck
twsck
SCK
(CPOL=1,
Output)
tsdi
thoi
LSB
MISO
(input)
MSB
MSB
td
tdis
tsdd
tdi
v
MOSI
(output)
LSB
SPI Master Timing for CPHA = 0
SSN
(output)
tssnh
tsck
tlag
tlead
trf
SCK
(CPOL=0,
Output)
twsck
twsck
SCK
(CPOL=1,
Output)
thoi
LSB
tsdi
MISO
(input)
MSB
MSB
tdis
tdi
tdv
MOSI
(output)
LSB
SPI Master Timing for CPHA = 1
Figure 10
SPI timing
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
AC timing parameters
Table 17
Parameter Description
SPI timing parameters[4]
Min
0
30
Max
33
–
Unit
MHz
ns
ns
ns
fop
Operating frequency
tsck
twsck
tlead
tlag
trf
Cycle time
Clock HIGH/LOW time
SSN-SCK lead time
13.5
–
1/2 tsck[5] – 5 1.5 tsck[5] + 5
Enable lag time
0.5
–
–
–
0
10
8
0
1.5 tsck[5] + 5
ns
Rise/fall time
8
5
5
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
tsdd
tdv
tdi
Output SSN to valid data delay time
Output data valid time
Output data invalid
tssnh
tsdi
thoi
tdis
Minimum SSN HIGH time
Data setup time input
Data hold time input
Disable data output on SSN HIGH
0
Notes
4. All parameters guaranteed by design and validated through characterization.
5. Depends on LAG and LEAD setting in the SPI_CONFIG register.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Reset sequence
22
Reset sequence
CX3’s hard reset sequence requirements are specified in this section.
Table 18 Reset and standby timing parameters
Parameter Definition
tRPW Minimum RESET# pulse width
tRH
Conditions
Clock Input
–
Min (ms) Max (ms)
1
5
–
–
Minimum HIGH on RESET#
Reset recovery time (after which the boot loader
begins firmware download)
tRR
Clock Input
1
–
Time to enter standby/suspend mode (from the
time MAIN_CLOCK_EN/ MAIN_POWER_EN bit is
set)
tSBY
–
–
1
tWU
tWH
Time to wakeup from standby
Minimum time before standby/suspend source
may be reasserted
Clock Input
–
1
5
–
–
VDD
( core )
xVDDQ
CLKIN
CLKIN must be stable before
exiting Standby/Suspend
tRR
tRh
Mandatory
Reset Pulse
Hard Reset
RESET#
tWH
tWU
tRPW
tSBY
Standby/
Suspend
Source
Standby/Suspend
source Is deasserted
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit is set)
Figure 11
Reset sequence
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Ordering Information
23
Ordering Information
Table 19
Ordering Information
Ordering code
CYUSB3065-BZXI
MIPI CSI-2 lanes
Package type
121-ball BGA
121-ball BGA
121-ball BGA
121-ball BGA
Temperature grade
Industrial
4
4
2
2
CYUSB3065-BZXC
CYUSB3064-BZXI
CYUSB3064-BZXC
Commercial
Industrial
Commercial
23.1
Ordering code definitions
X
BZ
I
3
USB
CY
06X -
Temperature grade:
I = Industrial
C = Commercial
Pb-free
Package type: BZ = 121-ball BGA
X = 4 for up to 2 MIPI CSI-2 lanes
X = 5 for up to 4 MIPI CSI-2 lanes
Density: Base part number for USB 3.0
Marketing code: USB = USB controller
Company ID: CY = CYPRESS (an Infineon company)
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Package diagram
24
Package diagram
001-87293 **
Figure 12
121-ball BGA (10 × 10 × 1.7 mm) package outline, 001-87293
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Acronyms
25
Acronyms
Table 20
Acronym
CSI - 2
DMA
DNU
HNP
Acronyms used in this document
Description
Camera Serial Interface - 2
Direct Memory Access
Do Not Use
Host Negotiation Protocol
Mobile Industry Processor Interface
Multimedia Card
Media Transfer Protocol
Phase Locked Loop
MIPI
MMC
MTP
PLL
PMIC
SD
Power Management IC
Secure Digital
SDIO
SLC
Secure Digital Input / Output
Single-Level Cell
SPI
SRP
USB
Serial Peripheral Interface
Session Request Protocol
Universal Serial Bus
WLCSP
Wafer Level Chip Scale Package
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Document conventions
26
Document conventions
26.1
Table 21
Symbol
°C
Mbps
MBps
MHz
µA
Units of measure
Units of measure
Units of measure
degree Celsius
Megabits per second
Megabytes per second
megahertz
microampere
microsecond
milliampere
µs
mA
ms
millisecond
ns
nanosecond
ohm
pF
picofarad
V
volt
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Errata
27
Errata
This section describes the errata for CX3. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability. Contact your local Infineon Sales Representative if you have
questions.
27.1
Part numbers affected
Part number
Device characteristics
CYUSB306x-xxxx
All variants
27.2
Qualification status
Product Status: Production
27.3
Errata
The following table defines the errata applicability to available EZ-USB™ CX3 SuperSpeed USB Controller family
devices.
Silicon
Items
Part number
Fix status
revision
1. Turning off VDDIO1 during Normal, Suspend,
and Standby modes causes the CX3 to stop CYUSB306x-xxxx
All
Workaround provided
working.
2. USB enumeration failure in USB boot mode
CYUSB306x-xxxx
All
All
All
Workaround provided
Workaround provided
Workaround provided
when CX3 is self-powered.
3. Extra ZLP is generated by the COMMIT action
CYUSB306x-xxxx
in the GPIF II state.
4. Invalid PID Sequence in USB 2.0 ISOC data
CYUSB306x-xxxx
transfer.
5. USB data transfer errors are seen when ZLP
is followed by data packet within same
microframe.
CYUSB306x-xxxx
CYUSB306x-xxxx
All
All
Workaround provided
6. Bus collision is seen when the I2C block is
used as a master in the I2C Multi-master
configuration.
Use CX3 in single-master
configuration
7. Low Power U1 Fast-Exit Issue with USB3.0
CYUSB306x-xxxx
CYUSB306x-xxxx
CYUSB306x-xxxx
CYUSB306x-xxxx
All
All
All
All
Workaround provided
Workaround provided
Workaround provided
No workaround needed
host controller.
8. USB data corruption when operating on
hosts with poor link quality.
9. Device treats Rx Detect sequence from the
USB 3.0 host as a valid U1 exit LFPS burst.
10. I2C Data Valid (tVD:DAT) specification
violation at 400 kHz with a 40/60 duty cycle.
11. CX3 Device does not respond correctly to
Port Capability Request from Host after
multiple power cycles.
CYUSB306x-xxxx
All
Workaround provided
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Errata
1. Turning off VDDIO1 during Normal, Suspend, and Standby modes causes the CX3 to stop working.
Turning off the VDDIO1 during Normal, Suspend, and Standby modes will cause the CX3
to stop working.
Problem definition
Parameters affected N/A
This condition is triggered when the VDDIO1 is turned off during Normal, Suspend, and
Standby modes.
Trigger condition(s)
Scope of impact
Workaround
Fix status
CX3 stops working.
VDDIO1 must stay on during Normal, Suspend, and Standby modes.
No fix. Workaround is required.
2. USB enumeration failure in USB boot mode when CX3 is self-powered.
When CX3 is self-powered and not connected to the USB host, it enters low-power mode
and does not wake up when connected to USB host afterwards. This is because the
bootloader does not check the VBUS pin on the connector to detect USB connection. It
expects that the USB bus is connected to the host when it is powered on.
Problem definition
Parameters affected N/A
This condition is triggered when the VDDIO1 is turned off during Normal, Suspend, and
Standby modes.
Trigger condition(s)
Scope of impact
Workaround
Fix status
Device does not enumerate.
CX3 stops working.
No fix. Workaround is required.
3. Extra ZLP is generated by the COMMIT action in the GPIF II state.
When COMMIT action is used in a GPIF-II state without IN_DATA action then an extra Zero
Length Packet (ZLP) is committed along with the data packets.
Problem definition
Parameters affected N/A
Trigger condition(s) This condition is triggered when COMMIT action is used in a state without IN_DATA action.
Scope of impact
Workaround
Fix status
Extra ZLP is generated.
Use IN_DATA action along with COMMIT action in the same state.
No fix. Workaround is required.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Errata
4. Invalid PID Sequence in USB 2.0 ISOC data transfer.
When the CX3 device is functioning as a high speed USB device with high bandwidth
isochronous endpoints, the PID sequence of the ISO data packets is governed solely by
Problem definition the isomult setting. The length of the data packet is not considered while generating the
PID sequence during each microframe. For example, even if a short packet is being sent
on an endpoint with MULT set to 2; the PID used will be DATA2.
Parameters affected N/A
Trigger condition(s) This condition is triggered when high bandwidth ISOC transfer endpoints are used.
Scope of impact
Workaround
Fix status
ISOC data transfers failure.
This problem can be worked around by reconfiguring the endpoint with a lower isomult
setting prior to sending short packets, and then switching back to the original value.
No fix. Workaround is required.
5. USB data transfer errors are seen when ZLP is followed by data packet within same microframe.
Some data transfer errors may be seen if a Zero Length Packet is followed very quickly
Problem definition (within one microframe or 125 µs) by another data packet on a burst enabled USB IN
endpoint operating at super speed.
Parameters affected N/A
Trigger condition(s) This condition is triggered in SuperSpeed transfer with ZLPs.
Scope of impact
Workaround
Fix status
Data failure and lower data speed.
The solution is to ensure that some time is allowed to elapse between a ZLP and the next
data packet on burst enabled USB IN endpoints. If this cannot be ensured at the data
source, the CyU3PDmaChannelSetSuspend() API can be used to suspend the corre-
sponding USB DMA socket on seeing the EOP condition. The channel operation can then
be resumed as soon as the suspend callback is received.
No fix. Workaround is required.
6. Bus collision is seen when the I2C block is used as a master in the I2C Multi-master configuration.
When CX3 is used as a master in the I2C multi-master configuration, there can be
occasional bus collisions.
Problem definition
Parameters affected N/A
This condition is triggered only when the CX3 I2C block operates in Multi-master
Trigger condition(s)
configuration.
Scope of impact
Workaround
Fix status
The CX3 I2C block can transmit data when the I2C bus is not idle leading to bus collision.
Use CX3 as a single master.
No fix.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Errata
7. Low Power U1 Fast-Exit Issue with USB3.0 host controller.
When CX3 device transitions from Low power U1 state to U0 state within 5 µs after
Problem definition entering U1 state, the device sometimes fails to transition back to U0 state, resulting in
USB Reset
Parameters affected N/A
Trigger condition(s) This condition is triggered during low power transition mode.
Scope of impact
Workaround
Fix status
Unexpected USB warm reset during data transfer.
This problem can be worked around in the FW by disabling LPM (Link Power
Management) during data transfer.
FW workaround is proven and reliable.
8. USB data corruption when operating on hosts with poor link quality.
If CX3 is operating on a USB 3.0 link with poor signal quality, the device could send
corrupted data on any of the IN endpoints (including the control endpoint).
Problem definition
Parameters affected N/A
Trigger condition(s) This condition is triggered when the USB3.0 link signal quality is very poor.
Scope of impact
Workaround
Fix status
Data corruption in any of the IN endpoints (including the control endpoint).
The application firmware should perform an error recovery by stalling the endpoint on
receiving CYU3P_USBEPSS_RESET_EVT event (available only with SDK 1.3.3 and above),
and then stop and restart DMA path when the CLEAR_FEATURE request is received.
Note For more details in application firmware, refer to GpiftoUsb example available with
FX3 SDK.
FW workaround is proven and reliable.
9. Device treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS burst.
The USB 3.0 PHY in the CX3 device uses an electrical idle detector to determine whether
LFPS is being received. The duration for which the receiver does not see an electrical idle
Problem definition
condition is timed to detect various LFPS bursts. This implementation causes the device
to treat an Rx Detect sequence from the USB host as a valid U1 exit LFPS burst.
Parameters affected N/A
This condition is triggered when the USB host is initiating an Rx Detect sequence while
the USB 3.0 Link State Machine on the CX3 is in the U1 state. Since the host will only
Trigger condition(s) perform Rx Detect sequence in the RX Detect and U2 states, the error condition is seen
only in cases where the USB link on the host has moved into the U2 state while the link
on CX3 is in the U1 state.
CX3 moves into Recovery prematurely leading to a Recovery failure followed by Warm
Reset and USB re-enumeration. This sequence can repeat multiple times resulting in data
transfer failures.
Scope of impact
CX3 can be configured to transition from U1 to U2 a few microseconds before the host
does so. This will ensure that the link will be in U2 on the device side before the host
attempts any Rx Detect sequence; thereby preventing a false detection of U1 exit.
Workaround
Fix status
Workaround is implemented in SDK library 1.3.4 and above.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Errata
10.I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60 duty cycle.
I2C Data Valid (tVD:DAT) parameter at 400 kHz with a 40/60 duty cycle is 1.0625 µs, which
Problem definition
exceeds the I2C specification limit of 0.9 µs.
Parameters affected N/A
Trigger condition(s) This violation occurs only at 400 kHz with a 40/60 duty cycle of the I2C clock.
Setup time (tSUDAT) is met with a huge margin for the transmitted data for 400 kHz and
so tvd:DAT violation will not cause any data integrity issues.
Scope of impact
Workaround
Fix status
No workaround needed.
No fix needed.
11.CX3 Device does not respond correctly to Port Capability Request from Host after multiple power
cycles.
During multiple power cycles, sometimes the CX3 device does not respond correctly to
the Port Capability request (Link Packet) from the USB Controller. In view of this, CX3 does
Problem definition not get the subsequent Port Configuration request from the USB controller, resulting in
SS.Disabled state. The device fails to recover from this state and finally results in
enumeration failure.
Parameters affected N/A
This condition is triggered when the CX3 provides an incorrect response to the Port
Capability request from the host.
Trigger condition(s)
Scope of impact
Workaround
Fix status
Device fails to enumerate after multiple retries.
Since the host does not send the Port Configuration request to the CX3 device, it causes
a Port Configuration request timeout interrupt to be triggered in the device. This
interrupt is handled in the FX3 SDK 1.3.4 onwards to generate and signal
CY_U3P_USB_EVENT_LMP_EXCH_FAIL event to the application. This event should be
handled in the user application such that it does a USB Interface Block Restart. Refer
KBA225778 for more details and the firmware workaround example project.
Suggested firmware work-around is proven and reliable.
Datasheet
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EZ-USB™ CX3 MIPI CSI-2 to SuperSpeed USB bridge controller
Revision history
Revision history
Document
Date
Description of changes
revision
*P
2023-04-27 Release to web.
Datasheet
51
001-87516 Rev. *P
2023-04-27
Please read the Important Notice and Warnings at the end of this document
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IMPORTANT NOTICE
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Edition 2023-04-27
Published by
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characteristics (“Beschaffenheitsgarantie”).
in question please contact your nearest Infineon
Technologies office.
With respect to any examples, hints or any typical
Infineon Technologies AG
81726 Munich, Germany
values stated herein and/or any information Except as otherwise explicitly approved by Infineon
regarding the application of the product, Infineon Technologies in
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Document reference
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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