CYV15G0203TB-BGXC [CYPRESS]
Independent Clock Dual HOTLink II⑩ Serializer; 独立时钟双的HOTLink II™串行型号: | CYV15G0203TB-BGXC |
厂家: | CYPRESS |
描述: | Independent Clock Dual HOTLink II⑩ Serializer |
文件: | 总20页 (文件大小:654K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CYV15G0203TB
Independent Clock Dual HOTLink II™
Serializer
Features
Functional Description
• Second-generation HOTLink® technology
The CYV15G0203TB Independent Clock Dual HOTLink II™
Serializer is a point-to-point or point-to-multipoint communica-
• Compliant to SMPTE 292M and SMPTE 259M video
standards
tions building block enabling transfer of data over a variety of
high-speed serial links including SMPTE 292M and SMPTE
259M video applications. It supports signaling rates in the
range of 195 to 1500 Mbps per serial link. The two channels
are independent and can simultaneously operate at different
rates. Each channel accepts 10-bit parallel characters in an
Input Register and converts them to serial data. Figure 1 illus-
trates typical connections between independent video
co-processors and corresponding CYV15G0203TB Serializer
and CYV15G0204RB Reclocking Deserializer chips.
• Dual-channel video serializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Redundant differential PECL-compatible serial outputs per
channel
The CYV15G0203TB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
As
a
second-generation
HOTLink
device,
the
CYV15G0203TB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data, and BIST) with other HOTLink
devices. Each channel of the CYV15G0203TB Dual HOTLink
II device accepts scrambled 10-bit transmission characters.
These characters are serialized and output from dual Positive
ECL (PECL) compatible differential transmission-line drivers
at a bit-rate of either 10- or 20-times the input reference clock
for that channel.
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low-power 1.4W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• 0.25μ BiCMOS technology
Each channel contains an independent BIST pattern
generator. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each transmit section of this
device, each receive section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0203TB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, and
cameras.
Figure 1. HOTLink II™ System Connections
Reclocked
Output
10
10
Independent
Channel
Independent
Channel
CYV15G0204RB
Serial Links
CYV15G0203TB
Serializer
Reclocking Deserializer
10
10
Reclocked
Output
Cypress Semiconductor Corporation
Document #: 38-02105 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 2, 2007
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CYV15G0203TB
CYV15G0203TB Serializer Logic Block Diagram
x10
x10
Phase
Align
Buffer
Phase
Align
Buffer
Serializer
TX
Serializer
TX
Document #: 38-02105 Rev. *C
Page 2 of 20
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CYV15G0203TB
Serializer Path Block Diagram
Bit-Rate Clock A
OE[2..1]A
= Internal Signal
REFCLKA+
REFCLKA–
TXRATEA
Transmit PLL
Clock Multiplier A
RESET
SPDSELA
TXCLKOA
Character-Rate Clock A
PABRSTA
TXERRA
TXCLKA
OE[2..1]A
TXBISTA
0
1
TXCKSELA
OUTA1+
OUTA1–
10
10
10
TXDA[9:0]
10
OUTA2+
OUTA2–
Bit-Rate Clock B
OE[2..1]B
REFCLKB+
REFCLKB–
Transmit PLL
TXRATEB
Clock Multiplier B
SPDSELB
TXCLKOB
Character-Rate Clock B
PABRSTB
TXERRB
TXCLKB
OE[2..1]B
TXBISTB
0
1
TXCKSELB
OUTB1+
OUTB1–
10
10
10
TXDB[9:0]
10
OUTB2+
OUTB2–
JTAG and Device Configuration and Control Block Diagram
= Internal Signal
RESET
TRST
TXRATE[A..B]
TXCKSEL[A..B]
PABRST[A..B]
TXBIST[A..B]
OE[2..1][A..B]
JTAG
Boundary
Scan
WREN
TMS
TCLK
TDI
Device Configuration
and Control Interface
ADDR[2:0]
DATA[3:0]
Controller
TDO
Document #: 38-02105 Rev. *C
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CYV15G0203TB
Pin Configuration (Top View)[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
OUT
B1–
OUT
B2–
OUT
A1–
OUT
A2–
NC
NC
NC
NC
V
NC
GND GND
GND
GND GND
V
V
NC
V
NC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
OUT
B1+
OUT
B2+
OUT
A1+
OUT
A2+
V
NC
V
NC
V
V
V
V
GND
GND
NC
NC
NC
GND
GND
NC
NC
V
V
V
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
TDI
TMS
DATA
[2]
DATA
[0]
SPD
SELB
TRST
TDO
V
V
V
V
NC
NC
NC
NC
NC
NC
GND
CC
CC
CC
TCLK RESET
DATA
[3]
DATA
[1]
SCAN TMEN3
EN2
V
V
V
GND GND
GND GND GND
NC
NC
CC
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
F
G
H
J
NC
NC
V
NC
NC
NC
NC
NC
NC
NC
CC
WREN
SPD
SELA
GND
GND GND
NC
GND GND GND GND
GND GND GND GND
GND GND GND GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
NC
NC
NC
NC
NC
NC
GND GND
NC
NC
GND
NC
GND
GND
M
N
P
R
T
GND GND GND GND
GND GND GND GND
GND GND GND GND
NC
NC
NC
NC
NC
NC
NC
NC
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
U
V
TX
DB[0]
TX
DB[1]
TX
DB[2]
TX
DB[9]
TX
DA[9]
ADDR
[0]
REF
CLKB– DA[1]
TX
TX
DA[4]
TX
DA[8]
V
V
V
V
NC
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GND
GND
V
V
V
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
CC
CC
TX
DB[3]
TX
DB[4]
TX
DB[8]
REF TX
CLKB+ CLKOA
TX
DA[3]
TX
DA[7]
NC
GND
GND
GND
NC
GND
NC
W
Y
TX
DB[5]
TX
DB[7]
ADDR ADDR
[2]
TX
ERRA
TX
DA[2]
TX
DA[6]
REF
CLKA+
NC
NC
NC
NC
NC
NC
TX
[1]
TX
TX
TX
CLKOB
NC
TX
CLKA
TX
DA[0]
TX
DA[5]
REF
NC
DB[6] CLKB
ERRB CLKA–
Note
1. NC = Do not connect.
Document #: 38-02105 Rev. *C
Page 4 of 20
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CYV15G0203TB
Pin Configuration (Bottom View)[1]
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUT
A2–
OUT
A1–
OUT
B2–
OUT
B1–
NC
V
NC
V
V
GND GND
GND
GND GND
NC
V
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
A
B
C
D
E
F
OUT
A2+
OUT
A1+
OUT
B2+
OUT
B1+
NC
NC
NC
NC
V
V
V
NC
NC
GND
GND
NC
NC
NC
GND
GND
V
V
V
V
NC
V
NC
V
CC
CC
CC
CC
CC
CC
CC
TDO
TRST
SPD
SELB
DATA
[0]
DATA
[2]
TMS
TDI
GND
NC
NC
NC
NC
NC
NC
V
V
V
V
V
CC
CC
CC
TMEN3 SCAN
EN2
DATA
[1]
DATA
[3]
RESET TCLK
NC
NC
GND GND GND
GND GND
V
V
V
CC
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SPD
SELA
WREN
NC
GND GND
GND
G
H
J
GND GND GND GND
GND GND GND GND
GND GND GND GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND GND
NC
NC
NC
NC
NC
NC
K
L
GND
GND
GND
NC
NC
NC
M
N
P
R
T
GND GND GND GND
GND GND GND GND
GND GND GND GND
NC
NC
NC
NC
NC
NC
NC
NC
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
V
V
V
CC
CC
CC
CC
TX
DA[8]
TX
DA[4]
TX
REF
ADDR
[0]
TX
DA[9]
TX
TX
TX
TX
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
V
V
V
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
U
V
W
Y
DA[1] CLKB–
DB[9]
DB[2]
DB[1]
DB[0]
TX
DA[7]
TX
DA[3]
TX
REF
TX
DB[8]
TX
DB[4]
TX
DB[3]
NC
GND
NC
GND
GND
GND
NC
CLKOA CLKB+
REF
CLKA+
TX
DA[6]
TX
DA[2]
TX
ERRA
ADDR ADDR
[1]
TX
DB[7]
TX
DB[5]
NC
TX
NC
NC
NC
NC
NC
[2]
REF
TX
DA[5]
TX
DA[0]
TX
CLKA
NC
TX
CLKOB
TX
TX
NC
CLKA– ERRB
CLKB DB[6]
Document #: 38-02105 Rev. *C
Page 5 of 20
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CYV15G0203TB
Pin Definitions
CYV15G0203TB Dual HOTLink II Serializer
Name
I/O Characteristics
Signal Description
Transmit Path Data and Status Signals
TXDA[9:0]
TXDB[9:0]
LVTTL Input,
synchronous,
sampled by the
associated
Transmit Data Inputs. TXDx[9:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx
latch via the device configuration interface.
TXCLKx↑ or
REFCLKx↑[2]
TXERRA
TXERRB
LVTTL Output,
synchronous to
Transmit Path Error. TXERRx is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted
until the transmit Phase-Align Buffer is re-centered with the PABRSTx latch via the
device configuration interface. When TXBISTx = 0, the BIST progress is presented
on the associated TXERRx output. The TXERRx signal pulses HIGH for one
REFCLKx↑ [3]
,
asynchronous to
transmit channel
enable / disable,
asynchronous to loss transmit-character clock period to indicate a pass through the BIST sequence once
or return of REFCLKx± every 511 character times.
TXERRx is also asserted HIGH, when any of the following conditions is true:
• The TXPLL for the associated channel is powered down. This occurs when OE2x
and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0.
• The absence of the REFCLKx± signal.
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
DifferentialLVPECLor Reference Clock. REFCLKx± clock inputs are used as the timing references for the
single-ended
associated transmit PLL. These input clocks may also be selected to clock the
transmit parallel interface. When driven by a single-ended LVCMOS or LVTTL clock
source, connect the clock source to either the true or complement REFCLKx input,
and leave the alternate REFCLKx input open (floating). When driven by an LVPECL
clock source, the clock must be a differential clock, using both inputs.
LVTTL input clock
TXCLKA
TXCLKB
LVTTL Clock Input,
internal pull-down
Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the associated
TXCLKx input is selected as the character-rate input clock for the TXDB[9:0] input. In
this mode, the TXCLKx input must be frequency-coherent to its associated TXCLKOx
output clock, but may be offset in phase by any amount. Once initialized, TXCLKx is
allowed to drift in phase as much as ±180 degrees. If the input phase of TXCLKx drifts
beyond the handling capacity of the Phase Align Buffer, TXERRx is asserted to
indicate the loss of data, and remains asserted until the Phase Align Buffer is
initialized. The phase of the TXCLKx input clock relative to its associated REFCLKx±
is initialized when the configuration latch PABRSTx is written as 0. When the
associated TXERRx is deasserted, the Phase Align Buffer is initialized and input
characters are correctly captured.
TXCLKOA
TXCLKOB
LVTTL Output
Transmit Clock Output. TXCLKOx output clock is synthesized by each channel’s
transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATEx = 0), or
at twice the frequency of REFCLKx± (TXRATEx = 1). The transmit clock outputs have
no fixed phase relationship to REFCLKx±.
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Asynchronous Device Reset. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. As per the JTAG specifications the
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has
to be reset separately. Refer to “JTAG Support” on page 10 for the methods to reset
the JTAG state machine. See Table 2 on page 10 for the initialize values of the device
configuration latches.
Notes
2. When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
3. When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
Document #: 38-02105 Rev. *C
Page 6 of 20
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CYV15G0203TB
Pin Definitions (continued)
CYV15G0203TB Dual HOTLink II Serializer
Name
I/O Characteristics
Signal Description
SPDSELA
SPDSELB
3-Level Select[4]
static control input
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range
of each channel’s PLL.
LOW = 195–400 MBd
MID = 400–800 MBd
HIGH = 800–1500 MBd.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
Control Write Enable. The WREN input writes the values of the DATA[3:0] bus into
the latch specified by the address location on the ADDR[2:0] bus.[5]
internal pull-up
ADDR[2:0]
LVTTL input
asynchronous,
internal pull-up
Control Addressing Bus. The ADDR[2:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[3:0] bus into the
latch specified by the address location on the ADDR[2:0] bus.[5] Table 2 on page 10
lists the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET. Table 3 on page 11 shows how the latches are
mapped in the device.
DATA[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[3:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[3:0] bus into the latch
specified by address location on the ADDR[2:0] bus.[5] Table 2 on page 10 lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET. Table 3 on page 11 shows how the latches are mapped in
the device.
Internal Device Configuration Latches
TXCKSEL[A..B] Internal Latch[6]
Transmit Clock Select.
TXRATE[A..B]
TXBIST[A..B]
OE2[A..B]
Internal Latch[6]
Internal Latch[6]
Internal Latch[6]
Internal Latch[6]
Internal Latch[6]
Transmit PLL Clock Rate Select.
Transmit Bist Disabled.
Differential Serial Output Driver 2 Enable.
Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
OE1[A..B]
PABRST[A..B]
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Analog I/O
OUTA1±
OUTB1±
CML Differential
Output
Primary Differential Serial Data Output. The OUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
OUTA2±
OUTB2±
CML Differential
Output
Secondary Differential Serial Data Output. The OUTx2± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connec-
tions.
Notes
4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). The MID level is usually
SS
CC
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
5. See “Device Configuration and Control Interface” on page 9 for detailed information on the operation of the Configuration Interface.
6. See “Device Configuration and Control Interface” on page 9 for detailed information on the internal latches.
Document #: 38-02105 Rev. *C
Page 7 of 20
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CYV15G0203TB
Pin Definitions (continued)
CYV15G0203TB Dual HOTLink II Serializer
Name
I/O Characteristics
Signal Description
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained
high for ≥5 TCLK cycles, the JTAG test controller is reset.
TCLK
LVTTL Input,
internal pull-down
JTAG Test Clock.
TDO
TDI
3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected.
LVTTL Input,
Test Data In. JTAG data input port.
internal pull-up
TRST
LVTTL Input,
internal pull-up
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
VCC
+3.3V Power.
GND
Signal and Power Ground for all internal circuits.
reset. While the error remains active, the transmitter for that
CYV15G0203TB HOTLink II Operation
channel outputs a continuous “1001111000” character (LSB
first) to indicate to the remote receiver that an error condition
is present in the link.
The CYV15G0203TB is a highly configurable, independent
clocking, dual-channel serializer, designed to support reliable
transfer of large quantities of digital video data, using
high-speed serial links from multiple sources to multiple desti-
nations. This device supports two 10-bit channels.
Transmit BIST
Each channel contains an internal pattern generator that can
be used to validate both the link and device operation. These
generators are enabled by the associated TXBISTx latch via
the device configuration interface. When enabled, a register in
CYV15G0203TB Transmit Data Path
Input Register
the associated channel becomes
a signature pattern
The parallel input bus TXDx[9:0] can be clocked in using
TXCLKx (TXCKSELx = 0) or REFCLKx (TXCKSELx = 1).
generator by logically converting to a Linear Feedback Shift
Register (LFSR). This LFSR generates a 511-character
sequence. This provides a predictable yet pseudo-random
sequence that can be matched to an identical LFSR in the
attached Receiver(s).
Phase-Align Buffer
Data from each Input Register is passed to the associated
Phase-Align Buffer, when the TXDx[9:0] input registers are
clocked using TXCLKx (TXCKSELx = 0 and TXRATEx = 0).
When the TXDx[9:0] input registers are clocked using
REFCLKx± (TXCKSELx = 1) and REFCLKx± is a full-rate
clock, the associated Phase Alignment Buffer in the transmit
path is bypassed. These buffers are used to absorb clock
phase differences between the TXCLKx input clock and the
internal character clock for that channel.
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on both channels.
All data present at the associated TXDx[9:0] inputs are ignored
when BIST is active on that channel.
Transmit PLL Clock Multiplier
Each Transmit PLL Clock Multiplier accepts a character-rate
or half-character-rate external clock at the associated
REFCLKx± input, and that clock is multiplied by 10 or 20 (as
selected by TXRATEx) to generate a bit-rate clock for use by
the transmit shifter. It also provides a character-rate clock used
by the transmit paths, and outputs this character rate clock as
TXCLKOx.
Once initialized, TXCLKx is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKx drifts beyond
the handling capacity of the Phase Align Buffer, TXERRx is
asserted to indicate the loss of data, and remains asserted
until the Phase Align Buffer is initialized. The phase of the
TXCLKx relative to its associated internal character rate clock
is initialized when the configuration latch PABRSTx is written
as 0. When the associated TXERRx is deasserted, the Phase
Align Buffer is initialized and input characters are correctly
captured.
Each clock multiplier PLL can accept a REFCLKx± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0203TB clock
multiplier (TXRATEx) and by the level on the associated
SPDSELx input.
SPDSELx are 3-level select[4] inputs that select one of three
operating ranges for the serial data outputs and inputs of the
associated channel. The serial signaling-rate and allowable
range of REFCLKx± frequencies are listed in Table 1 on page
9.
If the phase offset, between the initialized location of the input
clock and REFCLKx, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on that
channel’s TXERRx output. This output indicates an error
continuously until the Phase-Align Buffer for that channel is
Document #: 38-02105 Rev. *C
Page 8 of 20
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CYV15G0203TB
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Table 1. Operating Speed Settings
REFCLKx±
Frequency
(MHz)
Signaling
SPDSELx
TXRATEx
Rate (Mbps)
Note. When a disabled channel (i.e., both outputs disabled) is
re-enabled:
LOW
1
0
1
0
1
0
reserved
19.5–40
20–40
195–400
400–800
800–1500
• data on the serial outputs may not meet all timing specifi-
cations for up to 250 μs
• the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
MID (Open)
HIGH
40–80
40–75
Device Configuration and Control Interface
80–150
The CYV15G0203TB is highly configurable via the configu-
ration interface. The configuration interface allows each
channel to be configured independently. Table 2 on page 10
lists the configuration latches within the device including the
initialization value of the latches upon the assertion of RESET.
Table 3 on page 11 shows how the latches are mapped in the
device. Each row in the Table 3 maps to a 4-bit latch bank.
There are 6 such write-only latch banks. When WREN = 0, the
logic value in the DATA[3:0] is latched to the latch bank
specified by the values in ADDR[2:0]. The second column of
Table 3 specifies the channels associated with the corre-
sponding latch bank. For example, the first three latch banks
(0,1 and 2) consist of configuration bits for channel A.
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 5, and 6) are the static control latches. The third row of
latches for each channel (address numbers 2 and 7) are the
dynamic control latches. Address numbers 3 and 4 are internal
test registers.
Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
Transmit Shifter, which shifts the data out LSB first. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Static Latch Values
There are some latches in the table that have a static value
(i.e. 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
Document #: 38-02105 Rev. *C
Page 9 of 20
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CYV15G0203TB
Table 2. Device Configuration and Control Latch Descriptions
Name
Signal Description
TXCKSELA
TXCKSELB
Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input
register TXDx[9:0] is clocked by REFCLKx↑. In this mode, the phase alignment buffer is bypassed. When
TXCKSELx = 0, the associated TXCLKx↑ is used to clock in the input register TXDx[9:0].
TXRATEA
TXRATEB
Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used
to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the
TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated
REFCLKx± input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by
20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the
frequency rate of the REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data
Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx =
LOW, is an invalid state and this combination is reserved.
TXBISTA
TXBISTB
Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When
TXBISTx = 0, the transmit BIST function is enabled.
OE2A
OE2B
Secondary Differential Serial Data Output Driver Enable. The initialization value of the OE2x latch =
0. OE2x selects if the OUT2x± secondary differential output drivers are enabled or disabled. When OE2x
= 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via
the configuration interface, it is internally powered down to reduce device power. If both serial drivers for
a channel are in this disabled state, the associated internal logic for that channel is also powered down.
A device reset (RESET sampled LOW) disables all output drivers.
OE1A
OE1B
Primary Differential Serial Data Output Driver Enable. The initialization value of the OE1x latch = 0.
OE1x selects if the OUT1x± primary differential output drivers are enabled or disabled. When OE1x = 1,
the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When OE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic for that channel is also powered down.
A device reset (RESET sampled LOW) disables all output drivers.
PABRSTA
PABRSTB
Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx
is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal
clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete
the initialization of the Phase Alignment Buffer.
Device Configuration Strategy
outputs are not part of the JTAG test chain. To ensure valid
device operation after power-up (including non-JTAG
operation), the JTAG state machine should also be initialized
to a reset state. This should be done in addition to the device
reset (using RESET). The JTAG state machine can be
initialized using TRST (asserting it LOW and de-asserting it or
leaving it asserted), or by asserting TMS HIGH for at least 5
consecutive TCLK cycles. This is necessary in order to ensure
that the JTAG controller does not enter any of the test modes
after device power-up. In this JTAG reset state, the rest of the
device will be in normal operation.
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets both channels. Initialize the JTAG state machine to
its reset state as detailed in the JTAG Support section.
2. Set the static latch banks for the target channel.
3. Set the dynamic bank of latches for the target channel.
Enable the output drivers. [Required step.]
4. Reset the Phase Alignment Buffer for the target channel.
[Optional if phase align buffer is bypassed.]
Note. The order of device reset (using RESET) and JTAG
initialization does not matter.
JTAG Support
3-Level Select Inputs
The CYV15G0203TB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the REFCLKx± clock input. The high-speed serial inputs and
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
Document #: 38-02105 Rev. *C
Page 10 of 20
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CYV15G0203TB
JTAG ID
The JTAG device ID for the CYV15G0203TB is ‘0C810069’x.
Table 3. Device Control Latch Configuration Table
Reset
Value
ADDR
Channel
Type
DATA3
DATA2
DATA1
DATA0
0
A
S
X
X
0
X
1111
(000b)
1
A
A
B
B
B
S
D
S
S
D
X
TXBISTA
X
0
OE2A
X
TXCKSELA
OE1A
TXRATEA
PABRSTA
X
0110
1001
1111
0110
1001
(001b)
2
(010b)
9
0
(101b)
10
(110b)
X
0
TXCKSELB
OE1B
TXRATEB
PABRSTB
11
(111b)
TXBISTB
OE2B
Document #: 38-02105 Rev. *C
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CYV15G0203TB
Static Discharge Voltage..........................................> 2000 V
(per MIL-STD-883, Method 3015)
Maximum Ratings
Above which the useful life may be impaired. User guidelines
only, not tested
Latch-up Current.....................................................> 200 mA
Power-up Requirements
Storage Temperature ..................................–65°C to +150°C
The CYV15G0203TB requires one power-supply. The Voltage
on any input or I/O pin cannot exceed the power pin during
power-up.
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +3.8V
Operating Range
DC Voltage Applied to LVTTL Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Range
Ambient Temperature
VCC
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to VCC + 0.5V
CYV15G0203TB DC Electrical Characteristics
Commercial
0°C to +70°C
+3.3V ±5%
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL-compatible Outputs
VOHT
VOLT
IOST
IOZL
Output HIGH Voltage
Output LOW Voltage
IOH = − 4 mA, VCC = Min.
IOL = 4 mA, VCC = Min.
VOUT = 0V[7], VCC = 3.3V
VOUT = 0V, VCC
2.4
V
V
0.4
–100
20
Output Short Circuit Current
–20
–20
mA
µA
High-Z Output Leakage Current
LVTTL-compatible Inputs
VIHT
VILT
IIHT
Input HIGH Voltage
2.0
VCC + 0.3
0.8
V
Input LOW Voltage
Input HIGH Current
–0.5
V
REFCLKx Input, VIN = VCC
Other Inputs, VIN = VCC
REFCLKx Input, VIN = 0.0V
Other Inputs, VIN = 0.0V
1.5
mA
µA
mA
µA
µA
µA
+40
IILT
Input LOW Current
–1.5
–40
IIHPDT
IILPUT
Input HIGH Current with internal pull-down VIN = VCC
+200
–200
Input LOW Current with internal pull-up
VIN = 0.0V
LVDIFF Inputs: REFCLKx±
[8]
VDIFF
Input Differential Voltage
400
1.2
0.0
1.0
VCC
VCC
mV
V
VIHHP
Highest Input HIGH Voltage
Lowest Input LOW voltage
Common Mode Range
VILLP
VCC/2
V
[9]
VCOMREF
VCC – 1.2V
V
3-Level Inputs
VIHH
VIMM
VILL
IIHH
IIMM
IILL
Three-Level Input HIGH Voltage
Min. ≤ VCC ≤ Max.
Min. ≤ VCC ≤ Max.
Min. ≤ VCC ≤ Max.
VIN = VCC
0.87 * VCC
0.47 * VCC
0.0
VCC
0.53 * VCC
0.13 * VCC
200
V
V
Three-Level Input MID Voltage
Three-Level Input LOW Voltage
Input HIGH Current
V
µA
µA
µA
Input MID current
VIN = VCC/2
–50
50
Input LOW current
VIN = GND
–200
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
VOHC
Output HIGH Voltage
(Vcc Referenced)
100Ω differential load
150Ω differential load
VCC – 0.5
VCC – 0.5
VCC – 0.2
VCC – 0.2
V
V
Notes
7. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
8. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.
9. The common mode range defines the allowable range of REFCLKx+ and REFCLKx− when REFCLKx+ = REFCLKx−. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02105 Rev. *C
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CYV15G0203TB
CYV15G0203TB DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
100Ω differential load
150Ω differential load
100Ω differential load
150Ω differential load
Min.
Max.
VCC – 0.7
VCC – 0.7
900
Unit
V
VOLC
Output LOW Voltage
(VCC Referenced)
VCC – 1.4
V
CC – 1.4
V
VODIF
Output Differential Voltage
|(OUT+) − (OUT−)|
450
mV
mV
560
1000
Power Supply
Typ.
435
Max.
[10,11]
ICC
Max Power Supply Current
REFCLKx= Commercial
MAX
530
mA
mA
[10,11]
ICC
Typical Power Supply Current
REFCLKx= Commercial
125 MHz
425
520
AC Test Loads and Waveforms
3.3V
RL = 100Ω
R
L
R1
R2
R1 = 590Ω
R2 = 435Ω
CL ≤ 7 pF
(Includes fixture and
probe capacitance)
(b) CML Output Test Load[12]
CL
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load[12]
VIHE
3.0V
VIHE
2.0V
0.8V
2.0V
0.8V
80%
80%
Vth = 1.4V
Vth = 1.4V
20%
20%
VILE
≤ 270 ps
GND
VILE
≤ 270 ps
≤ 1 ns
≤ 1 ns
(c) LVTTL Input Test Waveform[13]
(d) CML/LVPECL Input Test Waveform
CYV15G0203TB AC Electrical Characteristics
Parameter
Description
Min.
Max.
Unit
CYV15G0203TB Transmitter LVTTL Switching Characteristics Over the Operating Range
fTS
TXCLKx Clock Cycle Frequency
TXCLKx Period=1/fTS
19.5
6.66
2.2
150
MHz
ns
tTXCLK
51.28
[14]
tTXCLKH
TXCLKx HIGH Time
ns
[14]
tTXCLKL
TXCLKx LOW Time
2.2
ns
[14, 15, 16, 17]
tTXCLKR
tTXCLKF
tTXDS
TXCLKx Rise Time
0.2
1.7
1.7
ns
[14, 15, 16, 17]
TXCLKx Fall Time
0.2
ns
Transmit Data Set-up Time to TXCLKx↑ (TXCKSELx = 0)
Transmit Data Hold Time from TXCLKx↑ (TXCKSELx = 0)
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
TXCLKOx Period = 1/fTOS
2.2
ns
tTXDH
1.0
ns
fTOS
19.5
6.66
–1.9
150
51.28
0
MHz
ns
tTXCLKO
tTXCLKOD
TXCLKO Duty Cycle centered at 60% HIGH time
ns
Notes
10. Maximum I is measured with V = MAX, T = 25°C, with both channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
CC
CC
A
outputs unloaded.
11. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C, with both channels enabled and one Serial Line Driver per channel sending
CC
CC
A
a continuous alternating 01 pattern. The redundant outputs on each channel are powered down.
12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15. The ratio of rise time to falling time must not vary by greater than 2:1.
16. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
17. All transmit AC timing parameters measured with 1 ns typical rise time and fall time.
Document #: 38-02105 Rev. *C
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CYV15G0203TB
CYV15G0203TB AC Electrical Characteristics (continued)
Parameter
Description
Min.
Max.
Unit
CYV15G0203TB REFCLKx Switching Characteristics Over the Operating Range
fREF
REFCLKx Clock Frequency
19.5
6.6
150
MHz
ns
ns
ns
ns
ns
%
tREFCLK
tREFH
REFCLKx Period = 1/fREF
51.28
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
REFCLKx Duty Cycle
5.9
2.9[14]
tREFL
5.9
2.9[14]
30
[18]
tREFD
70
2
[14, 15, 16, 17]
tREFR
REFCLKx Rise Time (20%–80%)
ns
ns
ns
[14, 15, 16, 17]
tREFF
tTREFDS
REFCLKx Fall Time (20%–80%)
2
Transmit Data Set-up Time to REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
2.4
2.3
1.0
1.6
Transmit Data Set-up Time to REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
ns
ns
ns
tTREFDH
Transmit Data Hold Time from REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
Transmit Data Hold Time from REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
CYV15G0203TB Bus Configuration Write Timing Characteristics Over the Operating Range
tDATAH
tDATAS
tWRENP
Bus Configuration Data Hold
0
ns
ns
ns
Bus Configuration Data Setup
Bus Configuration WREN Pulse Width
10
10
CYV15G0203TB JTAG Test Clock Characteristics Over the Operating Range
fTCLK
tTCLK
JTAG Test Clock Frequency
JTAG Test Clock Period
20
MHz
ns
50
30
CYV15G0203TB Device RESET Characteristics Over the Operating Range
tRST Device RESET Pulse Width
ns
CYV15G0203TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
Parameter
Description
Condition
Min.
5128
50
Max.
660
Unit
ps
tB
tRISE
Bit Time
[14]
CML Output Rise Time 20−80% (CML Test Load)
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
270
ps
100
180
50
500
ps
1000
270
ps
[14]
tFALL
CML Output Fall Time 80−20% (CML Test Load)
ps
100
180
500
ps
1000
ps
Note
18. The duty cycle specification is a simultaneous condition with the t
and t
parameters. This means that at faster character rates the REFCLKx± duty cycle
REFH
REFL
cannot be as large as 30%–70%.
Document #: 38-02105 Rev. *C
Page 14 of 20
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CYV15G0203TB
PLL Characteristics
Parameter
Description
Condition
Min. Typ.
Max. Unit
CYV15G0203TB Transmitter PLL Characteristics
[14, 19]
tJTGENSD
tJTGENHD
tTXLOCK
Transmit Jitter Generation - SD Data Rate
Transmit Jitter Generation - HD Data Rate
Transmit PLL lock to REFCLKx±
REFCLKx = 27 MHz
200
76
ps
ps
[14, 19]
REFCLKx = 148.5 MHz
200
μs
Capacitance[14]
Parameter
CINTTL
Description
Test Conditions
Max.
Unit
pF
TTL Input Capacitance
PECL input Capacitance
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
7
4
CINPECL
pF
CYV15G0203TB HOTLink II Transmitter Switching Waveforms
t
TXCLK
Transmit Interface
Write Timing
TXCLKx selected
t
t
TXCLKL
TXCLKH
TXCLKx
t
t
TXDH
TXDS
TXDx[9:0]
Transmit Interface
Write Timing
REFCLKx selected
TXRATEx = 0
t
REFCLK
t
t
REFL
REFH
REFCLKx
TXDx[9:0]
t
t
TREFDS
TREFDH
Transmit Interface
Write Timing
REFCLKx selected
TXRATEx = 1
t
REFCLK
t
t
REFL
REFH
REFCLKx
TXDx[9:0]
Note 20
t
t
t
TREFDS
t
TREFDH
TREFDS
TREFDH
Notes
19. While sending BIST data at the corresponding data rate, after 10,000 histogram hits on a digital sampling oscilloscope, time referenced to REFCLKx± input.
20. When REFCLKx± is configured for half-rate operation (TXRATEx = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using
both the rising and falling edges of REFCLKx.
Document #: 38-02105 Rev. *C
Page 15 of 20
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CYV15G0203TB
CYV15G0203TB HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface
TXCLKOx Timing
tREFCLK
tREFH
tREFL
TXRATEx = 1
REFCLKx
Note 21
tTXCLKO
Note 22
TXCLKOx
(internal)
Transmit Interface
TXCLKOx Timing
t
REFCLK
t
t
REFH
REFL
TXRATEx = 0
Note 21
REFCLKx
tTXCLKO
Note 22
TXCLKOx
CYV15G0203TB HOTLink II Bus Configuration Switching Waveforms
Bus Configuration
Write Timing
ADDR[2:0]
DATA[3:0]
tWRENP
tDATAS
WREN
tDATAH
Notes
21. The TXCLKOx output remains at the character rate regardless of the state of TXRATEx and does not follow the duty cycle of REFCLKx±.
22. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input.
Document #: 38-02105 Rev. *C
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CYV15G0203TB
Table 4. Package Coordinate Signal Allocation
Ball
ID
Ball
ID
Ball
ID
Signal Name
Signal Type
Signal Name
Signal Type
Signal Name
Signal Type
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
C02
C03
NC
NC
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
POWER
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
E02
E03
E04
E17
E18
E19
E20
F01
NC
GND
NC
NO CONNECT
GROUND
F17
F18
F19
F20
G01
G02
G03
G04
G17
G18
G19
G20
H01
H02
H03
H04
H17
H18
H19
H20
J01
J02
J03
J04
J17
J18
J19
J20
K01
K02
K03
K04
K17
K18
K19
K20
L01
L02
L03
L04
L17
L18
L19
NC
NC
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
GROUND
NC
NO CONNECT
NO CONNECT
LVTTL IN PU
LVTTL IN PU
GROUND
NC
NC
NC
NC
VCC
NC
DATA[2]
DATA[0]
GND
NC
GND
WREN
GND
GND
NC
NO CONNECT
CML OUT
LVTTL IN PU
GROUND
OUTB1–
GND
GND
OUTB2–
GND
OUTA1–
GND
GND
OUTA2–
VCC
VCC
NC
GROUND
NO CONNECT
3-LEVEL SEL
POWER
GROUND
GROUND
SPDSELB
VCC
NO CONNECT
NO CONNECT
3-LEVEL SEL
NO CONNECT
GROUND
CML OUT
NC
GROUND
NC
NO CONNECT
LVTTL IN PU
GROUND
SPDSELA
NC
CML OUT
TRST
GND
TDO
GROUND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
GROUND
LVTTL 3-S OUT
LVTTL IN PD
LVTTL IN PU
POWER
GROUND
CML OUT
TCLK
RESET
VCC
GROUND
POWER
GROUND
POWER
GROUND
NO CONNECT
POWER
VCC
POWER
GROUND
VCC
NC
VCC
POWER
GROUND
NO CONNECT
POWER
VCC
POWER
GROUND
VCC
NC
NC
NO CONNECT
GROUND
GROUND
NO CONNECT
POWER
GND
GND
DATA[3]
DATA[1]
GND
GND
GND
NC
GROUND
VCC
NC
GROUND
GROUND
NO CONNECT
POWER
LVTTL IN PU
LVTTL IN PU
GROUND
GROUND
VCC
VCC
OUTB1+
GND
NC
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
GROUND
POWER
NC
CML OUT
GROUND
NC
GROUND
GROUND
NC
NO CONNECT
CML OUT
NO CONNECT
POWER
NC
OUTB2+
NC
VCC
NC
NO CONNECT
CML OUT
NC
NO CONNECT
NO CONNECT
LVTTL IN PD
LVTTL IN PD
POWER
GND
GND
NC
OUTA1+
GND
NC
NC
GROUND
GROUND
SCANEN2
TMEN3
VCC
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
GROUND
NO CONNECT
CML OUT
NC
OUTA2+
VCC
NC
NC
POWER
VCC
POWER
NC
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
LVTTL IN PU
LVTTL IN PU
POWER
VCC
POWER
NC
NC
VCC
POWER
NC
NC
VCC
POWER
NC
NC
VCC
POWER
GND
NC
TDI
VCC
POWER
NO CONNECT
NO CONNECT
NO CONNECT
TMS
VCC
VCC
POWER
NC
NC
NO CONNECT
NC
Document #: 38-02105 Rev. *C
Page 17 of 20
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CYV15G0203TB
Table 4. Package Coordinate Signal Allocation (continued)
Ball
ID
Ball
ID
Ball
ID
Signal Name
Signal Type
Signal Name
Signal Type
Signal Name
Signal Type
C04
C05
C06
M03
M04
M17
M18
M19
M20
N01
N02
N03
N04
N17
N18
N19
N20
P01
P02
P03
P04
P17
P18
P19
P20
R01
R02
R03
R04
R17
R18
R19
R20
T01
T02
T03
T04
T17
T18
T19
T20
U01
U02
VCC
VCC
NC
POWER
POWER
F02
F03
F04
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W01
W02
NC
VCC
NO CONNECT
POWER
L20
M01
M02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
GND
NC
GROUND
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
POWER
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
GROUND
NC
NO CONNECT
LVTTL IN
NC
NC
TXDB[2]
TXDB[9]
VCC
NC
NC
LVTTL IN
NC
NC
POWER
VCC
NC
NC
NO CONNECT
NO CONNECT
GROUND
NC
NO CONNECT
NO CONNECT
GROUND
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
GND
GND
ADDR [2]
ADDR [1]
NC
GROUND
TXDA[9]
ADDR [0]
REFCLKB–
TXDA[1]
GND
LVTTL IN
LVTTL IN PU
LVTTL IN PU
NO CONNECT
LVTTL OUT
GROUND
GROUND
LVTTL IN PU
PECL IN
GROUND
GROUND
LVTTL IN
TXERRA
GND
TXDA[2]
TXDA[6]
VCC
GROUND
GROUND
GROUND
TXDA[4]
TXDA[8]
VCC
LVTTL IN
LVTTL IN
GROUND
LVTTL IN
LVTTL IN
GROUND
POWER
POWER
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
GROUND
NC
NO CONNECT
POWER
NC
NO CONNECT
PECL IN
NC
VCC
W18 REFCLKA+
NC
NC
NO CONNECT
NO CONNECT
LVTTL IN
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
NC
NC
NO CONNECT
NO CONNECT
LVTTL IN
NC
NC
GND
GND
GND
GND
NC
TXDB[3]
TXDB[4]
TXDB[8]
NC
TXDB[6]
TXCLKB
NC
GROUND
LVTTL IN
LVTTL IN PD
NO CONNECT
NO CONNECT
POWER
GROUND
LVTTL IN
GROUND
NO CONNECT
POWER
NC
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
POWER
VCC
VCC
NC
NC
NO CONNECT
NO CONNECT
GROUND
NC
NO CONNECT
NO CONNECT
GROUND
NC
NC
NC
NC
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TXDB[0]
TXDB[1]
NC
NO CONNECT
GROUND
TXCLKOB
NC
LVTTL OUT
NO CONNECT
LVTTL IN PD
NO CONNECT
GROUND
POWER
GND
POWER
REFCLKB+
TXCLKOA
GND
PECL IN
TXCLKA
NC
POWER
LVTTL OUT
GROUND
POWER
GND
POWER
TXDA[3]
TXDA[7]
VCC
LVTTL IN
TXDA[0]
TXDA[5]
VCC
LVTTL IN
POWER
LVTTL IN
LVTTL IN
POWER
POWER
POWER
POWER
NC
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
LVTTL IN
TXERRB
REFCLKA–
NC
LVTTL OUT
PECL IN
POWER
NC
POWER
NC
NO CONNECT
NO CONNECT
POWER
NC
NC
LVTTL IN
TXDB[5]
TXDB[7]
LVTTL IN
LVTTL IN
Document #: 38-02105 Rev. *C
Page 18 of 20
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CYV15G0203TB
Ordering Information
Package
Name
Operating
Range
Speed
Ordering Code
Package Type
Standard
Standard
CYV15G0203TB-BGC
CYV15G0203TB-BGXC
BL256
BL256
256-Ball Thermally Enhanced Ball Grid Array
Commercial
Pb-Free 256-Ball Thermally Enhanced Ball Grid Array
Commercial
Package Diagram
Figure 2. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256
TOP VIEW
0.20ꢀ4ꢁX
BOTTOM VIEW ꢀBALL SIDEX
A
27.00 0.13
Ø0.15 M C
Ø0.30 M C
A
B
A1 CORNER I.D.
A1 CORNER I.D.
24.13
Ø0.75 0.15ꢀ256ꢁX
20 18
19
16
14
12
10
8
6
4
2
17
15
13
11
9
7
5
3
1
A
B
C
D
E
F
G
H
J
R 2.5 Max ꢀ4ꢁX
K
L
M
N
P
R
T
A
U
V
W
Y
A
0.50 MIN.
B
1.57 0.175
0.97 REF.
0.15
C
26°
0.15
C
0.60 0.10
C
0.20 MIN
TOP OF MOLD COMPOUND
TO TOP OF BALLS
TYP.
SEATING PLANE
SIDE VIEW
SECTION A-A
51-85123-*E
HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-02105 Rev. *C
Page 19 of 20
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYV15G0203TB
Document History Page
Document Title: CYV15G0203TB Independent Clock Dual HOTLink II™ Serializer
Document Number: 38-02105
ISSUE
DATE
ORIG. OF
CHANGE
REV.
ECN NO.
DESCRIPTION OF CHANGE
**
246850
338721
384307
1034145
See ECN
See ECN
See ECN
See ECN
FRE
SUA
AGT
UKK
New Data Sheet
Added Pb-Free package option availability
*A
*B
*C
Revised setup and hold times (tTXDH, tTREFDS, tTREFDH
)
Added clarification for the necessity of JTAG controller reset and the
methods to implement it.
Document #: 38-02105 Rev. *C
Page 20 of 20
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