FPT-24P-M34_技术文档

MB95650L Series

New 8FX 8-bit Microcontrollers

The MB95650L Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the

microcontrollers of this series contain a variety of peripheral functions.

Features

2

F MC-8FX CPU core

I Cbusinterface 2channels(Oneofthetwochannels

2

can be used either as an I C bus interface channel or

as a UART/SIO channel.)

Instruction set optimized for controllers

■ Multiplication and division instructions

■ 16-bit arithmetic operations

■ Supports Standard-mode and Fast-mode (400 kHz).

■ Built-in wake-up function

■ Bit test branch instructions

LIN-UART

■ Bit manipulation instructions, etc.

■ Full duplex double buffer

Clock

■ Capable of clock asynchronous serial data transfer and clock

synchronous serial data transfer

■ Selectable main clock source

❐ Main oscillation clock (up to 16.25 MHz, maximum machine

clock frequency: 8.125 MHz)

External interrupt  6 channels

❐ External clock (up to 32.5 MHz, maximum machine clock

■ Interrupt by edge detection (rising edge, falling edge, and both

edges can be selected)

frequency: 16.25 MHz)

❐ Main CR clock (4 MHz 2%)

❐ Main CR PLL clock

• The main CR PLL clock frequency becomes 8 MHz 2%

when the PLL multiplication rate is 2.

• The main CR PLL clock frequency becomes 10 MHz 2%

when the PLL multiplication rate is 2.5.

■ Can be used to wake up the device from different low power

consumption (standby) modes

8/12-bit A/D converter  6 channels

8-bit or 12-bit resolution can be selected.

• The main CR PLL clock frequency becomes 12 MHz 2%

when the PLL multiplication rate is 3.

Low power consumption (standby) modes

There are four standby modes as follows:

• The main CR PLL clock frequency becomes 16 MHz 2%

when the PLL multiplication rate is 4.

■ Stop mode

❐ Main PLL clock (maximum machine clock frequency:

16 MHz)

■ Sleep mode

■ Selectable subclock source

■ Watch mode

❐ Suboscillation clock (32.768 kHz)

❐ External clock (32.768 kHz)

■ Time-base timer mode

❐ Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)

I/O port

■ MB95F652E/F653E/F654E/F656E (number of I/O ports: 21)

Timer

❐ General-purpose I/O ports (CMOS I/O)

❐ General-purpose I/O ports (N-ch open drain)

: 17

: 4

■ 8/16-bit composite timer  2 channels

■ Time-base timer  1 channel

■ Watch prescaler  1 channel

■ MB95F652L/F653L/F654L/F656L (number of I/O ports: 20)

❐ General-purpose I/O ports (CMOS I/O)

❐ General-purpose I/O ports (N-ch open drain)

: 17

: 3

UART/SIO  1 channel (The channel can be used either

2

as a UART/SIO channel or as an I C bus interface

On-chip debug

channel.)

■ 1-wire serial control

■ The function of this channel can be switched between

■ Serial writing supported (asynchronous mode)

UART/SIO and I²C bus interface.

Hardware/software watchdog timer

■ Built-in hardware watchdog timer

■ Built-in software watchdog timer

■ Full duplex double buffer

■ Capableofclockasynchronous(UART)serialdatatransferand

clock synchronous (SIO) serial data transfer

Cypress Semiconductor Corporation

Document Number: 002-04696 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 12, 2016

MB95650L Series

Power-on reset

Clock supervisor counter

A power-on reset is generated when the power is switched on.

Built-in clock supervisor counter

Low-voltage detection reset circuit and low-voltage

detection interrupt circuit (only available on

MB95F652E/F653E/F654E/F656E)

Dual operation Flash memory

The program/erase operation and the read operation can be

executed in different banks (upper bank/lower bank)

simultaneously.

Built-in low-voltage detection function

Flash memory security function

Protects the content of the Flash memory.

Document Number: 002-04696 Rev. *A

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MB95650L Series

Contents

Product Line-up ................................................................4

Packages and Corresponding Products ........................6

Differences among Products and

I/O Ports ...........................................................................29

Port 0 .........................................................................30

Port 1 .........................................................................36

Port 6 .........................................................................42

Port F .........................................................................46

Port G ........................................................................50

Interrupt Source Table ...................................................53

Pin States in each Mode ................................................54

Electrical Characteristics ...............................................56

Absolute Maximum Ratings .......................................56

Recommended Operating Conditions .......................58

DC Characteristics ....................................................59

AC Characteristics .....................................................62

A/D Converter ............................................................86

Flash Memory Program/Erase Characteristics ..........90

Sample Characteristics ..................................................91

Mask Options ..................................................................98

Ordering Information ......................................................99

Package Dimension ......................................................100

Major Changes ..............................................................103

Document History .........................................................104

Notes on Product Selection .............................................7

Pin Assignment ................................................................8

Pin Functions ....................................................................9

I/O Circuit Type ...............................................................12

Handling Precautions .....................................................15

Precautions for Product Design .................................15

Precautions for Package Mounting ...........................16

Precautions for Use Environment ..............................17

Notes On Device Handling .............................................18

Pin Connection ...............................................................19

Block Diagram ................................................................20

CPU Core .........................................................................21

Memory Space ................................................................22

Areas for Specific Applications ....................................24

I/O Map .............................................................................25

Document Number: 002-04696 Rev. *A

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MB95650L Series

1. Product Line-up

Part number

MB95F652E MB95F653E MB95F654E MB95F656E MB95F652L MB95F653L MB95F654L MB95F656L

Parameter

Type

Flash memory product

Clock supervisor

counter

It supervises the main clock oscillation and the subclock oscillation.

Flash memory

capacity

8 Kbyte

12 Kbyte

512 bytes

20 Kbyte

36 Kbyte

8 Kbyte

12 Kbyte

512 bytes

20 Kbyte

36 Kbyte

RAM capacity

256 bytes

1024 bytes 1024 bytes

Yes

256 bytes

1024 bytes 1024 bytes

Power-on reset

Low-voltage

detection reset

Yes

No

With dedicated reset input

Reset input

Selected through software

• Number of basic instructions

• Instruction bit length

: 136

: 8 bits

• Instruction length

• Data bit length

: 1 to 3 bytes

: 1, 8 and 16 bits

CPU functions

• Minimum instruction execution time

• Interrupt processing time

: 61.5 ns (machine clock frequency = 16.25 MHz)

: 0.6 µs (machine clock frequency = 16.25 MHz)

• I/O port

• CMOS I/O

• N-ch open drain

: 21

: 17

: 4

• I/O port

• CMOS I/O

• N-ch open drain

: 20

: 17

: 3

General-purpose

I/O

Time-base timer

Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)

• Reset generation cycle

Main oscillation clock at 10 MHz: 105 ms (Min)

• The sub-CR clock can be used as the source clock of the software watchdog timer.

Hardware/software

watchdog timer

Wild register

It can be used to replace 3 bytes of data.

• A wide range of communication speed can be selected by a dedicated reload timer.

• It has a full duplex double buffer.

• Both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled.

• The LIN function can be used as a LIN master or a LIN slave.

LIN-UART

6 channels

8/12-bit

A/D converter

8-bit or 12-bit resolution can be selected.

2 channels

• The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”.

• It has the following functions: interval timer function, PWC function, PWM function and input capture function.

• Count clock: it can be selected from internal clocks (seven types) and external clocks.

• It can output square wave.

8/16-bit

composite timer

6 channels

External interrupt

On-chip debug

• Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.)

• It can be used to wake up the device from different standby modes.

• 1-wire serial control

• It supports serial writing (asynchronous mode).

(Continued)

Document Number: 002-04696 Rev. *A

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MB95650L Series

(Continued)

Part number

MB95F652E MB95F653E MB95F654E MB95F656E MB95F652L MB95F653L MB95F654L MB95F656L

Parameter

1 channel (The channel can be used either as a UART/SIO channel or as an I²C bus interface channel.)

• Data transfer with UART/SIO is enabled.

• It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an

error detection function.

• It uses the NRZ type transfer format.

UART/SIO

• LSB-first data transfer and MSB-first data transfer are available to use.

• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer are

enabled.

2 channels (One of the two channels can be used either as an I²C bus interface channel or as a UART/SIO

channel.)

I²C bus

interface

• Master/slave transmission and reception

• It has the following functions: bus error function, arbitration function, transmission direction detection function,

wake-up function, and functions of generating and detecting repeated START conditions.

Watch prescaler

Flash memory

Eight different time intervals can be selected.

• It supports automatic programming (Embedded Algorithm), and program/erase/erase-suspend/erase-resume

commands.

• It has a flag indicating the completion of the operation of Embedded Algorithm.

• Flash security feature for protecting the content of the Flash memory

Number of program/erase cycles

Data retention time

1000

10000

100000

5 years

20 years

10 years

There are four standby modes as follows:

• Stop mode

Standby mode

Package

• Sleep mode

• Watch mode

• Time-base timer mode

FPT-24P-M10

FPT-24P-M34

LCC-32P-M19

Document Number: 002-04696 Rev. *A

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MB95650L Series

2. Packages and Corresponding Products

Part number

MB95F652E MB95F653E MB95F654E MB95F656E MB95F652L MB95F653L MB95F654L MB95F656L

Package

FPT-24P-M10

FPT-24P-M34

LCC-32P-M19



: Available

Document Number: 002-04696 Rev. *A

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MB95650L Series

3. Differences among Products and Notes on Product Selection

Current consumption

When using the on-chip debug function, take account of the current consumption of Flash memory program/erase.

For details of current consumption, see “18. Electrical Characteristics”.

Package

For details of information on each package, see “2. Packages and Corresponding Products” and “22. Package Dimension”.

Operating voltage

The operating voltage varies, depending on whether the on-chip debug function is used or not.

For details of operating voltage, see “18. Electrical Characteristics”.

On-chip debug function

The on-chip debug function requires that V_CC, V_SSand one serial wire be connected to an evaluation tool. For details of the connection

method, refer to “Chapter 20 Example Of Serial Programming Connection” in “New 8FX MB95650L Series Hardware Manual”.

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MB95650L Series

4. Pin Assignment

PF0/X0

PF1/X1

Vss

1

2

24

23

22

21

20

19

18

17

16

15

14

13

P12/DBG/EC0

P07/INT07/TO10

P06/INT06/TO01

3

(TOP VIEW)

PG2/X1A

PG1/X0A

Vcc

4

P05/INT05/AN05/TO00

P04/INT04/AN04/SIN/EC0

P03/INT03/AN03/SOT

P02/INT02/AN02/SCK

P01/AN01

5

TSSOP24

FPT-24P-M10

6

C

7

PF2/RST

8

SOP24

FPT-24P-M34

P17/SCL1/UI0

P16/SDA1/UO0

P62/TO10/UCK0

P63/TO11

9

P00/AN00

10

11

12

P64/EC1

P14/SDA0

P15/SCL0

Vss

1

24

23

22

21

20

19

18

17

P06/INT06/TO01

P05/INT05/AN05/TO00

P04/INT04/AN04/SIN/EC0

P03/INT03/AN03/SOT

P02/INT02/AN02/SCK

P01/AN01

PG2/X1A

PG1/X0A

Vcc

2

3

4

5

6

7

8

(TOP VIEW)

C

QFN32

LCC-32P-M19

PF2/RST

P17/SCL1/UI0

P16/SDA1/UO0

P00/AN00

P64/EC1

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MB95650L Series

5. Pin Functions

Pin no.

I/O type

I/O

circuit

SOP24*¹,

QFN32*³

Pin name

Function

OD*⁵PU*⁶

Output

type*⁴

Input

TSSOP24*²

PF0

X0

General-purpose I/O port

Main clock input oscillation pin

General-purpose I/O port

Main clock I/O oscillation pin

Power supply pin (GND)

General-purpose I/O port

Subclock I/O oscillation pin

General-purpose I/O port

Subclock input oscillation pin

Power supply pin

1

32

B

Hysteresis

CMOS

—

PF1

X1

2

3

4

31

1

B

—

C

Hysteresis

—

CMOS

—



V_SS

PG2

X1A

PG1

X0A

V_CC

C

2

Hysteresis

CMOS

5

3

C

Hysteresis

CMOS

—



6

7

4

5

—

Decoupling capacitor connection pin

General-purpose I/O port

PF2

Reset pin

Dedicated reset pin on

MB95F652L/F653L/F654L/F656L

8

6

A

Hysteresis

CMOS



—

RST

P17

SCL1

UI0

General-purpose I/O port

9

7

8

J

I²C bus interface ch. 1 clock I/O pin

UART/SIO ch. 0 data input pin

General-purpose I/O port

CMOS

CMOS —/*⁷

—

P16

10

SDA1

UO0

I²C bus interface ch. 1 data I/O pin

UART/SIO ch. 0 data output pin

General-purpose I/O port

High-current pin

P62

11

12

10

9

D

Hysteresis

CMOS

—



TO10

UCK0

8/16-bit composite timer ch. 1 output pin

UART/SIO ch. 0 clock I/O pin

General-purpose I/O port

High-current output

P63

TO11

P15

8/16-bit composite timer ch. 1 output pin

General-purpose I/O port

13

14

16

15

I

CMOS



—

SCL0

P14

I²C bus interface ch. 0 clock I/O pin

General-purpose I/O port

I²C bus interface ch. 0 data I/O pin

SDA0

P64

General-purpose I/O port

15

17

D

Hysteresis

CMOS

—



8/16-bit composite timer ch. 1 clock input

EC1

(Continued)

Document Number: 002-04696 Rev. *A

Page 9 of 105

MB95650L Series

Pin no.

I/O type

I/O

circuit

SOP24*¹,

Pin name

Function

QFN32*³

OD*⁵PU*⁶

Output

type*⁴

Input

TSSOP24*²

P00

AN00

P01

General-purpose I/O port

Hysteresis/

analog

16

18

E

CMOS

—



8/12-bit A/D converter analog input pin

General-purpose I/O port

Hysteresis/

analog

17

18

20

E

AN01

P02

8/12-bit A/D converter analog input pin

General-purpose I/O port

INT02

AN02

SCK

P03

External interrupt input pin

Hysteresis/

analog

CMOS

—



8/12-bit A/D converter analog input pin

LIN-UART clock I/O pin

General-purpose I/O port

INT03

AN03

SOT

P04

External interrupt input pin

Hysteresis/

analog

19

20

21

22

E

F

8/12-bit A/D converter analog input pin

LIN-UART data output pin

General-purpose I/O port

INT04

AN04

SIN

External interrupt input pin

8/12-bit A/D converter analog input pin

LIN-UART data input pin

CMOS/

analog

CMOS

—



8/16-bit composite timer ch. 0 clock input

EC0

P05

General-purpose I/O port

High-current pin

Hysteresis/

analog

INT05

AN05

TO00

External interrupt input pin

21

23

K

8/12-bit A/D converter analog input pin

8/16-bit composite timer ch. 0 output pin

General-purpose I/O port

High-current pin

P06

22

23

24

26

D

K

Hysteresis

CMOS

—



INT06

TO01

External interrupt input pin

8/16-bit composite timer ch. 0 output pin

General-purpose I/O port

High-current pin

P07

INT07

TO10

External interrupt input pin

8/16-bit composite timer ch. 1 output pin

(Continued)

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Page 10 of 105

MB95650L Series

(Continued)

Pin no.

I/O type

I/O

circuit

SOP24*¹,

Pin name

Function

QFN32*³

OD*⁵PU*⁶

Output

type*⁴

Input

TSSOP24*²

P12

General-purpose I/O port

DBG input pin

DBG

24

25

H

Hysteresis

CMOS



—

8/16-bit composite timer ch. 0 clock input

EC0

11

12

13

14

27

28

29

30

It is an internally connected pin. Always

leave it unconnected.

—

NC

—

: Available

*1: FPT-24P-M34

*2: FPT-24P-M10

*3: LCC-32P-M19

*4: For the I/O circuit types, see “6. I/O Circuit Type”.

*5: N-ch open drain

*6: Pull-up

*7: In I²C mode, the pin becomes an N-ch open drain pin.

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MB95650L Series

6. I/O Circuit Type

Type

Circuit

Remarks

• N-ch open drain output

• Hysteresis input

• Reset output

Reset input / Hysteresis input

Reset output / Digital output

A

N-ch

Port select

P-ch

Digital output

N-ch

Standby control

Hysteresis input

• Oscillation circuit

• High-speed side

Feedback resistance:

approx. 1 M

Clock input

X1

B

X0

• CMOS output

• Hysteresis input

Standby control / Port select

P-ch

Port select

Digital output

N-ch

Standby control

Hysteresis input

Port select

R

Pull-up control

P-ch

N-ch

P-ch

Digital output

Standby control

Hysteresis input

• Oscillation circuit

• Low-speed side

Feedback resistance:

approx. 5 M

Clock input

X1A

C

X0A

• CMOS output

• Hysteresis input

• Pull-up control

Standby control / Port select

Port select

R

Pull-up control

Digital output

N-ch

P-ch

Digital output

Standby control

Hysteresis input

(Continued)

Page 12 of 105

Document Number: 002-04696 Rev. *A

MB95650L Series

Type

Circuit

Remarks

Pull-up control

R

• CMOS output

• Hysteresis input

• Pull-up control

P-ch

N-ch

Digital output

D

P-ch

• High current output

Standby control

Hysteresis input

Pull-up control

R

P-ch

N-ch

Digital output

P-ch

• CMOS output

• Hysteresis input

• Pull-up control

• Analog input

E

Analog input

A/D control

Standby control

Hysteresis input

Pull-up control

R

P-ch

N-ch

Digital output

P-ch

• CMOS output

• CMOS input

• Pull-up control

• Analog input

F

Analog input

A/D control

Standby control

CMOS input

Standby control

Hysteresis input

• N-ch open drain output

• Hysteresis input

H

Digital output

N-ch

Digital output

Standby control

CMOS input

• N-ch open drain output

• CMOS input

I

(Continued)

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MB95650L Series

(Continued)

Type

Circuit

Remarks

I²C mode control

Digital output

• CMOS output

J

• CMOS input

P-ch

N-ch

• N-ch open drain output in I²C mode

Digital output

Standby control

CMOS input

Pull-up control

R

P-ch

N-ch

Digital output

• CMOS output

• Hysteresis input

• Pull-up control

• Analog input

P-ch

K

• High current output

Analog input

A/D control

Standby control

Hysteresis input

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MB95650L Series

7. Handling Precautions

Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in

which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to

minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

7.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain

established limits, called absolute maximum ratings. Do not exceed these ratings.

Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical character-

istics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely

affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering

application outside the listed conditions are advised to contact their sales representative beforehand.

Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output

functions.

1. Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and

in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the

design stage.

2. Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such

conditions if present for extended periods of time can damage the device.

Therefore, avoid this type of connection.

3. Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected

through an appropriate resistance to a power supply pin or ground pin.

Latch-up

Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally

high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of

several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage

from high heat, smoke or flame. To prevent this from happening, do the following:

1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise,

surge levels, etc.

2. Be sure that abnormal current flows do not occur during the power-on sequence.

Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference,

etc. Customers are requested to observe applicable regulations and standards in the design of products.

Fail-Safe Design

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

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MB95650L Series

Precautions Related to Usage of Devices

Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office

equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are

requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such

use without prior approval.

7.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you

should only mount under Cypress’s recommended conditions. For detailed information about mount conditions, contact your sales

representative.

Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or

mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow

soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected

to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress

recommended mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact

deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be

verified before mounting.

Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed

or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections

caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of

mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended

conditions.

Lead-Free Packaging

CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength

may be reduced under some conditions of use.

Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of

moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing

moisture resistance and causing packages to crack. To prevent, do the following:

1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations

where temperature changes are slight.

2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and

30°C.

When you open Dry Package that recommends humidity 40% to 70% relative humidity.

3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel

desiccant. Devices should be sealed in their aluminum laminate bags for storage.

4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

Baking

Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions

for baking.

Condition: 125°C/24 h

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Page 16 of 105

MB95650L Series

Static Electricity

Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:

1. Maintain relative humidity in the working environment between 40% and 70%.

Use of an apparatus for ion generation may be needed to remove electricity.

2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.

3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ).

Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is

recommended.

4. Ground all fixtures and instruments, or protect with anti-static measures.

5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

7.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.

For reliable performance, do the following:

1. Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are

anticipated, consider anti-humidity processing.

2. Discharge of Static Electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use

anti-static measures or processing to prevent discharges.

3. Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you

use devices in such conditions, consider ways to prevent such exposure or to protect the devices.

4. Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding

as appropriate.

5. Smoke, Flame

CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin

to smoke or burn, there is danger of the release of toxic gases.

Customers considering the use of Cypress products in other special environmental conditions should consult with sales

representatives.

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Page 17 of 105

MB95650L Series

8. Notes On Device Handling

Preventing latch-ups

When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.

In a CMOS IC, if a voltage higher than V_CCor a voltage lower than V_SSis applied to an input/output pin that is neither a

medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned

in “18.1 Absolute Maximum Ratings” of “18. Electrical Characteristics” is applied to the V_CCpin or the V_SSpin, a latch-up may occur.

When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed.

Stabilizing supply voltage

Supply voltage must be stabilized.

A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating

range of the V_CCpower supply voltage.

As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in V_CCripple (p-p value) at the commercial

frequency (50 Hz/60 Hz) does not exceed 10% of the standard V_CCvalue, and the transient fluctuation rate does not exceed 0.1 V/ms

at a momentary fluctuation such as switching the power supply.

Notes on using the external clock

When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop

mode.

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Page 18 of 105

MB95650L Series

9. Pin Connection

Treatment of unused pins

If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull

up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave

it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it

unconnected.

Power supply pins

To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and

conform to the total output current standard, always connect the V_CCpin and the V_SSpin to the power supply and ground outside the

device. In addition, connect the current supply source to the V_CCpin and the V_SSpin with low impedance.

It is also advisable to connect a ceramic capacitor of approximately 1.0 µF as a bypass capacitor between the V_CCpin and the V_SS

pin at a location close to this device.

DBG pin

Connect the DBG pin to an external pull-up resistor of 2 k or above.

After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.

The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the

interconnection length, refer to the tool document when selecting a pull-up resistor.

RST pin

Connect the RST pin to an external pull-up resistor of 2 k or above.

To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up

resistor and the RST pin and that between a pull-up resistor and the V_CCpin when designing the layout of the printed circuit board.

The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled

by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O function can be selected by the

RSTEN bit in the SYSC register.

C pin

Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the V_CCpin must have

a capacitance equal to or larger than the capacitance of C_S. For the connection to a decoupling capacitor C_S, see the diagram below.

To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance

between the C pin and C_Sand the distance between C_Sand the V_SSpin when designing the layout of a printed circuit board.

DBG/RST/C pins connection diagram

DBG

C

RST

Cs

Note on serial communication

In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed circuit board

to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as adding a checksum to the end

of data in order to detect errors. If an error is detected, retransmit the data.

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Page 19 of 105

MB95650L Series

10. Block Diagram

F²MC-8FX CPU

PF2^*1/RST^*2

Reset with LVD

Dual operation Flash with

security function

(36/20/12/8 Kbyte)

PF0/X0^*2

PF1/X1^*2

PG1/X0A^*2

PG2/X1A^*2

Oscillator

circuit

CR oscillator

RAM (1024/512/256 bytes)

8/16-bit composite timer ch. 0

(P05/TO00)

Clock control

(P06/TO01)

(P04/EC0), P12^*1/EC0

(P12^*1/DBG)

On-chip debug

Wild register

(P62^*3/TO10), P62^*3/TO10

P63^*3/TO11

8/16-bit composite timer ch. 1

P64/EC1

P02/INT02 to P07/INT07

C

External interrupt

P14*¹/SDA0

P15*¹/SCL0

I²C bus interface ch. 0

I²C bus interface ch. 1

(P00/AN00 to P05^*3/AN05)

8/12-bit A/D converter

LIN-UART

(P16/SDA1)

(P17/SCL1)

(P04/SIN)

(P03/SOT)

(P02/SCK)

P17/UI0

UART/SIO ch. 0

Port

P16/UO0

P62/UCK0

Port

Vcc

Vss

P12, P14, P15 and PF2 are N-ch open drain pins.

Software select

*1:

*2:

*3:

P05 to P07, P62 and P63 are high-current pins.

Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.

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Page 20 of 105

MB95650L Series

11. CPU Core

Memory space

The memory space of the MB95650L Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and

a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector

table. The memory maps of the MB95650L Series are shown below.

Memory maps

MB95F652E/F652L

MB95F653E/F653L

MB95F654E/F654L

MB95F656E/F656L

0x0000

0x0080

0x0000

0x0080

0x0000

0x0080

0x0000

0x0080

I/O area

Access prohibited

RAM 256 bytes

Registers

Access prohibited

RAM 512 bytes

Registers

Access prohibited

RAM 1024 bytes

Registers

Access prohibited

RAM 1024 bytes

Registers

0x0090

0x0100

0x0190

0x0090

0x0100

0x0090

0x0100

0x0090

0x0100

0x0200

0x0290

Access prohibited

0x0490

Access prohibited

0x0F80

0x1000

0x0F80

0x1000

0x0F80

0x1000

0x0F80

0x1000

Extended I/O area

Flash memory 4 Kbyte

0x2000

Access prohibited

0x8000

Access prohibited

0xC000

Flash memory 32 Kbyte

0xE000

0xFFFF

Flash memory 16 Kbyte

0xF000

0xFFFF

Flash memory 8 Kbyte

Flash memory 4 Kbyte

0xFFFF

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Page 21 of 105

MB95650L Series

12. Memory Space

The memory space of the MB95650L Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and

a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table.

I/O area (addresses: 0x0000 to 0x007F)

• This area contains the control registers and data registers for built-in peripheral functions.

• As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also be accessed

at high-speed by using direct addressing instructions.

Extended I/O area (addresses: 0x0F80 to 0x0FFF)

• This area contains the control registers and data registers for built-in peripheral functions.

• As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory.

Data area

• Static RAM is incorporated in the data area as the internal data area.

• The internal RAM size varies according to product.

• The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions.

• In MB95F656E/F656L, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed

by direct addressing instructions with a direct bank pointer set.

• In MB95F654E/F654L, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed

by direct addressing instructions with a direct bank pointer set.

• In MB95F653E/F653L, the area from 0x0090 to 0x028F is an extended direct addressing area. It can be accessed at high-speed

by direct addressing instructions with a direct bank pointer set.

• In MB95F652E/F652L, the area from 0x0090 to 0x018F is an extended direct addressing area. It can be accessed at high-speed

by direct addressing instructions with a direct bank pointer set.

• In MB95F653E/F653L/F654E/F654L/F656E/F656L, the area from 0x0100 to 0x01FF can be used as a general-purpose register

area.

• In MB95F652E/F652L, the area from 0x0100 to 0x018F can be used as a general-purpose register area.

Program area

• The Flash memory is incorporated in the program area as the internal program area.

• The Flash memory size varies according to product.

• The area from 0xFFC0 to 0xFFFF is used as the vector table.

• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register.

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MB95650L Series

Memory space map

0x0000

0x0080

I/O area

Direct addressing area

Access prohibited

0x0090

0x0100

Registers

(General-purpose register area)

Extended direct addressing area

0x0200

Data area

0x047F

0x048F

0x0490

Access prohibited

Extended I/O area

0x0F80

0x0FFF

0x1000

Program area

0xFFC0

0xFFFF

Vector table area

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MB95650L Series

13. Areas for Specific Applications

The general-purpose register area and vector table area are used for the specific applications.

1

General-purpose register area (Addresses: 0x0100 to 0x01FF* )

• This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.

• As this area forms part of the RAM area, it can also be used as conventional RAM.

• When the area is used as general-purpose registers, general-purpose register addressing enables high-speed access with short

instructions.

Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF)

• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “Chapter 23 Non-volatile

Register (NVR) Interface” in “New 8FX MB95650L Series Hardware Manual”.

Vector table area (Addresses: 0xFFC0 to 0xFFFF)

• This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets.

• The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set to an address

in the vector table in the form of data.

“16. Interrupt Source Table” lists the vector table addresses corresponding to vector call instructions, interrupts, and resets.

For details, refer to “Chapter 4 Reset”, “Chapter 5 Interrupts” and “A.2 Special Instruction Special Instruction CALLV #vct” in “New

8FX MB95650L Series Hardware Manual”.

Direct bank pointer and access area

Direct bank pointer (DP[2:0])

0bXXX (It does not affect mapping.)

Operand-specified dir

0x0000 to 0x007F

Access area

0x0000 to 0x007F

0b000 (Initial value)

0b001

0x0090 to 0x00FF

0x0100 to 0x017F

0x0180 to 0x01FF*¹

0x0200 to 0x027F

0x0280 to 0x02FF*²

0x0300 to 0x037F

0x0380 to 0x03FF

0x0400 to 0x047F

0b010

0b011

0b100

0x0080 to 0x00FF

0b101

0b110

0b111

*1: Due to the memory size limit, the available access area is up to “0x018F” in MB95F652E/F652L.

*2: Due to the memory size limit, the available access area is up to “0x028F” in MB95F653E/F653L.

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Page 24 of 105

MB95650L Series

14. I/O Map

Register

abbreviation

Address

Register name

R/W

Initial value

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

PDR0

DDR0

PDR1

DDR1

—

Port 0 data register

R/W

—

0b00000000

—

Port 0 direction register

Port 1 data register

Port 1 direction register

(Disabled)

WATR

PLLC

SYCC

STBC

RSRR

TBTC

WPCR

WDTC

SYCC2

Oscillation stabilization wait time setting register

PLL control register

R/W

0b11111111

0b000X0000

0bXXX11011

0b00000000

0b000XXXXX

0b00000000

0b00XX0000

0bXXXX0011

System clock control register

Standby control register

Reset source register

Time-base timer control register

Watch prescaler control register

Watchdog timer control register

System clock control register 2

0x000E

to

—

(Disabled)

—

0x0015

0x0016

0x0017

PDR6

DDR6

Port 6 data register

R/W

0b00000000

Port 6 direction register

0x0018

to

—

(Disabled)

—

0x0027

0x0028

0x0029

0x002A

0x002B

0x002C

PDRF

DDRF

PDRG

DDRG

PUL0

Port F data register

R/W

0b00000000

Port F direction register

Port G data register

Port G direction register

Port 0 pull-up register

0x002D

to

—

(Disabled)

—

0x0032

0x0033

0x0034

0x0035

0x0036

0x0037

0x0038

0x0039

PUL6

—

Port 6 pull-up register

R/W

—

0b00000000

—

(Disabled)

PULG

Port G pull-up register

R/W

0b00000000

T01CR1

T00CR1

T11CR1

T10CR1

8/16-bit composite timer 01 status control register 1

8/16-bit composite timer 00 status control register 1

8/16-bit composite timer 11 status control register 1

8/16-bit composite timer 10 status control register 1

0x003A

to

—

(Disabled)

—

0x0048

(Continued)

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Page 25 of 105

MB95650L Series

Register

abbreviation

Address

Register name

R/W

Initial value

0x0049

0x004A

0x004B

EIC10

EIC20

EIC30

External interrupt circuit control register ch. 2/ch. 3

External interrupt circuit control register ch. 4/ch. 5

External interrupt circuit control register ch. 6/ch. 7

R/W

0b00000000

0x004C

to

—

(Disabled)

—

0x004E

0x004F

0x0050

0x0051

0x0052

LVDC

SCR

LVD control register

R/W

0b00000100

0b00000000

0b00001000

LIN-UART serial control register

SMR

LIN-UART serial mode register

SSR

LIN-UART serial status register

RDR

LIN-UART receive data register

0x0053

R/W

0b00000000

TDR

LIN-UART transmit data register

0x0054

0x0055

0x0056

0x0057

0x0058

0x0059

0x005A

ESCR

ECCR

SMC10

SMC20

SSR0

TDR0

RDR0

LIN-UART extended status control register

LIN-UART extended communication control register

UART/SIO serial mode control register 1 ch. 0

UART/SIO serial mode control register 2 ch. 0

UART/SIO serial status and data register ch. 0

UART/SIO serial output data register ch. 0

UART/SIO serial input data register ch. 0

R/W

R

0b00000100

0b000000XX

0b00000000

0b00100000

0b00000001

0b00000000

0x005B

to

—

(Disabled)

—

0x005F

0x0060

0x0061

0x0062

0x0063

0x0064

0x0065

0x0066

0x0067

0x0068

0x0069

0x006A

0x006B

0x006C

0x006D

0x006E

0x006F

0x0070

IBCR00

IBCR10

IBSR0

IDDR0

IAAR0

ICCR0

IBCR01

IBCR11

IBSR1

IDDR1

IAAR1

ICCR1

ADC1

I²C bus control register 0 ch. 0

I²C bus control register 1 ch. 0

I²C bus status register ch. 0

I²C data register ch. 0

I²C address register ch. 0

I²C clock control register ch. 0

I²C bus control register 0 ch. 1

I²C bus control register 1 ch. 1

I²C bus status register ch. 1

I²C data register ch. 1

I²C address register ch. 1

I²C clock control register ch. 1

8/12-bit A/D converter control register 1

8/12-bit A/D converter control register 2

8/12-bit A/D converter data register (upper)

8/12-bit A/D converter data register (lower)

8/12-bit A/D converter control register 3

R/W

0b00000000

0b01111100

ADC2

ADDH

ADDL

ADC3

(Continued)

Document Number: 002-04696 Rev. *A

Page 26 of 105

MB95650L Series

Register

Address

Register name

Flash memory status register 2

R/W

Initial value

abbreviation

0x0071

0x0072

0x0073

0x0074

0x0075

0x0076

0x0077

0x0078

0x0079

0x007A

0x007B

0x007C

0x007D

0x007E

0x007F

0x0F80

0x0F81

0x0F82

0x0F83

0x0F84

0x0F85

0x0F86

0x0F87

0x0F88

FSR2

FSR

R/W

R

0b00000000

0b000X0000

0b00000000

0b000XXXXX

0b00000000

—

Flash memory status register

SWRE0

FSR3

Flash memory sector write control register 0

Flash memory status register 3

FSR4

Flash memory status register 4

R/W

—

WREN

WROR

—

Wild register address compare enable register

Wild register data test setting register

Mirror of register bank pointer (RP) and direct bank pointer (DP)

Interrupt level setting register 0

ILR0

R/W

—

0b11111111

—

ILR1

Interrupt level setting register 1

ILR2

Interrupt level setting register 2

ILR3

Interrupt level setting register 3

ILR4

Interrupt level setting register 4

ILR5

Interrupt level setting register 5

—

(Disabled)

WRARH0

WRARL0

WRDR0

WRARH1

WRARL1

WRDR1

WRARH2

WRARL2

WRDR2

Wild register address setting register (upper) ch. 0

Wild register address setting register (lower) ch. 0

Wild register data setting register ch. 0

Wild register address setting register (upper) ch. 1

Wild register address setting register (lower) ch. 1

Wild register data setting register ch. 1

Wild register address setting register (upper) ch. 2

Wild register address setting register (lower) ch. 2

Wild register data setting register ch. 2

R/W

0b00000000

0x0F89

to

—

(Disabled)

—

0x0F91

0x0F92

0x0F93

0x0F94

0x0F95

0x0F96

0x0F97

0x0F98

0x0F99

0x0F9A

0x0F9B

T01CR0

T00CR0

T01DR

T00DR

TMCR0

T11CR0

T10CR0

T11DR

8/16-bit composite timer 01 status control register 0

8/16-bit composite timer 00 status control register 0

8/16-bit composite timer 01 data register

R/W

0b00000000

8/16-bit composite timer 00 data register

8/16-bit composite timer 00/01 timer mode control register

8/16-bit composite timer 11 status control register 0

8/16-bit composite timer 10 status control register 0

8/16-bit composite timer 11 data register

T10DR

TMCR1

8/16-bit composite timer 10 data register

8/16-bit composite timer 10/11 timer mode control register

(Continued)

Document Number: 002-04696 Rev. *A

Page 27 of 105

MB95650L Series

(Continued)

Register

abbreviation

Address

Register name

R/W

Initial value

0x0F9C

to

—

(Disabled)

—

0x0FBB

0x0FBC

0x0FBD

BGR1

BGR0

LIN-UART baud rate generator register 1

LIN-UART baud rate generator register 0

R/W

0b00000000

UART/SIO dedicated baud rate generator prescaler select register ch.

0

0x0FBE

0x0FBF

PSSR0

BRSR0

R/W

0b00000000

UART/SIO dedicated baud rate generator baud rate setting register

ch. 0

0x0FC0

to

0x0FC2

—

AIDRL

—

(Disabled)

A/D input disable register (lower)

(Disabled)

—

R/W

—

0b00000000

—

0x0FC3

0x0FC4

to

0x0FE3

0x0FE4

0x0FE5

0x0FE6

0x0FE7

0x0FE8

0x0FE9

0x0FEA

0x0FEB

0x0FEC

CRTH

CRTL

Main CR clock trimming register (upper)

Main CR clock trimming register (lower)

System configuration register 2

R/W

R

0b000XXXXX

0b00000000

0b000XXXXX

0b00111111

SYSC2

CRTDA

SYSC

Main CR clock temperature dependent adjustment register

System configuration register

CMCR

CMDR

WDTH

WDTL

Clock monitoring control register

0b00000000

0bXXXXXXXX

Clock monitoring data register

Watchdog timer selection ID register (upper)

Watchdog timer selection ID register (lower)

R

0x0FED

to

—

(Disabled)

—

0x0FFF

R/W access symbols

R/W

: Readable/Writable

R

: Read only

Initial value symbols

0

1

X

: The initial value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.

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Page 28 of 105

MB95650L Series

15. I/O Ports

List of port registers

Register name

Read/Write

R, RM/W

R/W

Initial value

0b00000000

Port 0 data register

PDR0

DDR0

PDR1

DDR1

PDR6

DDR6

PDRF

DDRF

PDRG

DDRG

PUL0

PUL6

PULG

AIDRL

Port 0 direction register

Port 1 data register

R, RM/W

R/W

Port 1 direction register

Port 6 data register

R, RM/W

R/W

Port 6 direction register

Port F data register

R, RM/W

R/W

Port F direction register

Port G data register

Port G direction register

Port 0 pull-up register

Port 6 pull-up register

Port G pull-up register

R, RM/W

R/W

A/D input disable register (lower)

R/W

R/W : Readable/writable (The read value is the same as the write value.)

R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write

(RMW) type of instruction.)

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MB95650L Series

15.1 Port 0

Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral

functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.1.1 Port 0 configuration

Port 0 is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins

• Port 0 data register (PDR0)

• Port 0 direction register (DDR0)

• Port 0 pull-up register (PUL0)

• A/D input disable register (lower) (AIDRL)

15.1.2 Block diagrams of port 0

P00/AN00 pin

This pin has the following peripheral function:

• 8/12-bit A/D converter analog input pin (AN00)

P01/AN01 pin

This pin has the following peripheral function:

• 8/12-bit A/D converter analog input pin (AN01)

Block diagram of P00/AN00 and P01/AN01

A/D analog input

Hysteresis

0

Pull-up

1

PDR0 read

PDR0

PDR0 write

Executing bit manipulation instruction

DDR0 read

DDR0

DDR0 write

PUL0 read

PUL0 write

AIDRL read

AIDRL write

Stop mode, watch mode (SPL = 1)

PUL0

AIDRL

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MB95650L Series

P02/INT02/AN02/SCK pin

This pin has the following peripheral functions:

• External interrupt input pin (INT02)

• 8/12-bit A/D converter analog input pin (AN02)

• LIN-UART clock I/O pin (SCK)

P03/INT03/AN03/SOT pin

This pin has the following peripheral functions:

• External interrupt input pin (INT03)

• 8/12-bit A/D converter analog input pin (AN03)

• LIN-UART data output pin (SOT)

P05/INT05/AN05/TO00 pin

This pin has the following peripheral functions:

• External interrupt input pin (INT05)

• 8/12-bit A/D converter analog input pin (AN05)

• 8/16-bit composite timer ch. 0 output pin (TO00)

Block diagram of P02/INT02/AN02/SCK, P03/INT03/AN03/SOT and P05/INT05/AN05/TO00

Peripheral function input

Peripheral function input enable

(INT02, INT03 and INT05)

Peripheral function output enable

Peripheral function output

A/D analog input

Hysteresis

Pull-up

0

1

PDR0 read

PDR0

1

0

PDR0 write

Executing bit manipulation instruction

DDR0 read

DDR0

DDR0 write

PUL0 read

PUL0 write

AIDRL read

AIDRL write

Stop mode, watch mode (SPL = 1)

PUL0

AIDRL

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MB95650L Series

P04/INT04/AN04/SIN/EC0 pin

This pin has the following peripheral functions:

• External interrupt input pin (INT04)

• 8/12-bit A/D converter analog input pin (AN04)

• LIN-UART data input pin (SIN)

• 8/16-bit composite timer ch. 0 clock input pin (EC0)

Block diagram of P04/INT04/AN04/SIN/EC0

Peripheral function input

Peripheral function input enable (INT04)

A/D analog input

0

Pull-up

1

CMOS

PDR0 read

PDR0

PDR0 write

Executing bit manipulation instruction

DDR0 read

DDR0

DDR0 write

PUL0 read

PUL0 write

AIDRL read

AIDRL write

Stop mode, watch mode (SPL = 1)

PUL0

AIDRL

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MB95650L Series

P06/INT06/TO01 pin

This pin has the following peripheral functions:

• External interrupt input pin (INT06)

• 8/16-bit composite timer ch. 0 output pin (TO01)

P07/INT07/TO10 pin

This pin has the following peripheral functions:

• External interrupt input pin (INT07)

• 8/16-bit composite timer ch. 1 output pin (TO10)

Block diagram of P06/INT06/TO01 and P07/INT07/TO10

Peripheral function input

Peripheral function input enable

(INT06 and INT07)

Peripheral function output enable

Peripheral function output

Hysteresis

Pull-up

0

1

PDR0 read

PDR0 write

1

0

PDR0

Executing bit manipulation instruction

DDR0 read

DDR0

DDR0 write

PUL0 read

PUL0 write

Stop mode, watch mode (SPL = 1)

PUL0

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MB95650L Series

15.1.3 Port 0 registers

Port 0 register functions

Register

Data

Read by read-modify-write

(RMW) instruction

Read

Write

abbreviation

0

Pin state is “L” level.

Pin state is “H” level.

PDR0 value is “0”.

PDR0 value is “1”.

Port input enabled

Port output enabled

Pull-up disabled

As output port, outputs “L” level.

As output port, outputs “H” level.

PDR0

1

0

DDR0

1

0

PUL0

1

Pull-up enabled

0

Analog input enabled

Port input enabled

AIDRL

1

Correspondence between registers and pins for port 0

Correspondence between related register bits and pins

Pin name

PDR0

P07

bit7

-

P06

bit6

-

P05

P04

P03

P02

P01

P00

DDR0

bit5

bit4

bit3

bit2

bit1

bit0

PUL0

AIDRL

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MB95650L Series

15.1.4 Port 0 operations

Operation as an output port

• A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• When a pin is used as an output port, it outputs the value of the PDR0 register to external pins.

• If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is.

• Reading the PDR0 register returns the PDR0 register value.

Operation as an input port

• A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• When using a pin shared with the analog input function as an input port, set the corresponding bit in the A/D input disable register

(lower) (AIDRL) to “1”.

• If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port.

• Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read

the PDR0 register, the PDR0 register value is returned.

Operation as a peripheral function output pin

• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a

peripheral function corresponding to that pin.

• The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value

of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type

of instruction is used to read the PDR0 register, the PDR0 register value is returned.

Operation as a peripheral function input pin

• To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”.

• When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by

setting the bit in the AIDRL register corresponding to that pin to “1”.

• Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.

However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is re-

turned.

Operation at reset

If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with analog input,

its port input is disabled because the AIDRL register is initialized to “0”.

Operation in stop mode and watch mode

• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for

the external interrupt (INT02 to INT07), the input is enabled and not blocked.

• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

Operation as an analog input pin

• Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL

register to “0”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the correspond-

ing bit in the PUL0 register to “0”.

Operation as an external interrupt input pin

• Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the

external interrupt function corresponding to that pin.

Operation of the pull-up register

Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L”

level, the pull-up resistor is disconnected regardless of the value of the PUL0 register.

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MB95650L Series

15.2 Port 1

Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral

functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.2.1 Port 1 configuration

Port 1 is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins

• Port 1 data register (PDR1)

• Port 1 direction register (DDR1)

15.2.2 (2)Block diagrams of port 1

P12/DBG/EC0 pin

This pin has the following peripheral functions:

• DBG input pin (DBG)

• 8/16-bit composite timer ch. 0 clock input pin (EC0)

Block diagram of P12/DBG/EC0

Peripheral function input

Hysteresis

0

1

PDR1 read

PDR1

OD

PDR1 write

Executing bit manipulation instruction

DDR1 read

DDR1

DDR1 write

Stop mode, watch mode (SPL = 1)

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MB95650L Series

P14/SDA0 pin

This pin has the following peripheral function:

• I²C bus interface ch. 0 data I/O pin (SDA0)

P15/SCL0 pin

This pin has the following peripheral function:

• I²C bus interface ch. 0 clock I/O pin (SCL0)

Block diagram of P14/SDA0 and P15/SCL0

Peripheral function input

Peripheral function input enable

Peripheral function output enable

Peripheral function output

CMOS

0

1

PDR1 read

PDR1

1

0

OD

PDR1 write

Executing bit manipulation instruction

DDR1 read

DDR1

DDR1 write

Stop mode, watch mode (SPL = 1)

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MB95650L Series

P16/SDA1/UO0 pin

This pin has the following peripheral functions:

• I²C bus interface ch. 1 data I/O pin (SDA1)

• UART/SIO ch. 0 data output pin (UO0)

Block diagram of P16/SDA1/UO0

I2C_SEL bit in SYSC2 register

UART/SIO function output enable

UART/SIO function output

0

1

Peripheral function input enable

Peripheral function output enable

Peripheral function output

I²C function input

I²C function input enable

I²C function output enable

I²C function output

Peripheral function input

0

1

CMOS

PDR1 read

PDR1 write

1

0

P-ch

PDR1

Executing bit manipulation instruction

N-ch

DDR1 read

DDR1

DDR1 write

Stop mode, watch mode (SPL = 1)

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MB95650L Series

P17/SCL1/UI0 pin

This pin has the following peripheral functions:

• I²C bus interface ch. 1 clock I/O pin (SCL1)

• UART/SIO ch. 0 data input pin (UI0)

Block diagram of P17/SCL1/UI0

I2C_SEL bit in SYSC2 register

UART/SIO function input

UART/SIO function input enable

0

Peripheral function input enable

Peripheral function output enable

Peripheral function output

I²C function input

I²C function input enable

I²Cfunction output enable

I²C function output

1

Peripheral function input

0

1

CMOS

PDR1 read

PDR1 write

1

0

P-ch

PDR1

Executing bit manipulation instruction

N-ch

DDR1 read

DDR1

DDR1 write

Stop mode, watch mode (SPL = 1)

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MB95650L Series

15.2.3 Port 1 registers

Port 1 register functions

Register

Data

Read by read-modify-write

(RMW) instruction

Read

Write

abbreviation

0

Pin state is “L” level.

Pin state is “H” level.

PDR1 value is “0”.

PDR1 value is “1”.

Port input enabled

Port output enabled

As output port, outputs “L” level.

As output port, outputs “H” level.*

PDR1

1

0

DDR1

1

*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.

Correspondence between registers and pins for port 1

Correspondence between related register bits and pins

Pin name

PDR1

P17

P16

P15

P14

-

P12

-

bit7

bit6

bit5

bit4

-

bit2

-

DDR1

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MB95650L Series

15.2.4 Port 1 operations

Operation as an output port

• A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.

• If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is.

• Reading the PDR1 register returns the PDR1 register value.

Operation as an input port

• A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port.

• Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read

the PDR1 register, the PDR1 register value is returned.

Operation as a peripheral function output pin

• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a

peripheral function corresponding to that pin.

• The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value

of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type

of instruction is used to read the PDR1 register, the PDR1 register value is returned.

Operation as a peripheral function input pin

• To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”.

• Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.

However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is

returned.

Operation at reset

If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled.

Operation in stop mode and watch mode

• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open.

• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

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MB95650L Series

15.3 Port 6

Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral

functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.3.1 Port 6 configuration

Port 6 is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins

• Port 6 data register (PDR6)

• Port 6 direction register (DDR6)

• Port 6 pull-up register (PUL6)

15.3.2 Block diagrams of port 6

P62/TO10/UCK0 pin

This pin has the following peripheral functions:

• 8/16-bit composite timer ch. 1 output pin (TO10)

• UART/SIO ch. 0 clock I/O pin (UCK0)

P63/TO11 pin

This pin has the following peripheral function:

• 8/16-bit composite timer ch. 1 output pin (TO11)

Block diagram of P62/TO10/UCK0 and P63/TO11

Peripheral function input

Peripheral function input enable

Peripheral function output enable

Peripheral function output

Hysteresis

Pull-up

0

1

PDR6 read

PDR6 write

1

0

PDR6

Executing bit manipulation instruction

DDR6 read

DDR6

DDR6 write

PUL6 read

PUL6 write

Stop mode, watch mode (SPL = 1)

PUL6

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MB95650L Series

P64/EC1 pin

This pin has the following peripheral function:

• 8/16-bit composite timer ch. 1 clock input pin (EC1)

Block diagram of P64/EC1

Peripheral function input

Hysteresis

0

1

PDR6 read

PDR6

PDR6 write

Executing bit manipulation instruction

DDR6 read

DDR6

DDR6 write

Stop mode, watch mode (SPL = 1)

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MB95650L Series

15.3.3 Port 6 registers

Port 6 register functions

Register

Data

Read by read-modify-write

(RMW) instruction

Read

Write

abbreviation

0

Pin state is “L” level.

Pin state is “H” level.

PDR6 value is “0”.

PDR6 value is “1”.

Port input enabled

Port output enabled

Pull-up disabled

As output port, outputs “L” level.

As output port, outputs “H” level.*

PDR6

1

0

DDR6

1

0

PUL6

1

Pull-up enabled

*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.

Correspondence between registers and pins for port 6

Correspondence between related register bits and pins

Pin name

PDR6

-

P64

P63

P62

-

DDR6

-

bit4

bit3

bit2

-

PUL6

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MB95650L Series

15.3.4 Port 6 operations

Operation as an output port

• A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• When a pin is used as an output port, it outputs the value of the PDR6 register to external pins.

• If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is.

• Reading the PDR6 register returns the PDR6 register value.

Operation as an input port

• A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port.

• Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read

the PDR6 register, the PDR6 register value is returned.

Operation as a peripheral function output pin

• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a

peripheral function corresponding to that pin.

• The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the output value

of a peripheral function can be read by the read operation on the PDR6 register. However, if the read-modify-write (RMW) type

of instruction is used to read the PDR6 register, the PDR6 register value is returned.

Operation as a peripheral function input pin

• To set a pin as an input port, set the bit in the DDR6 register corresponding to the input pin of a peripheral function to “0”.

• Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.

However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is re-

turned.

Operation at reset

If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled.

Operation in stop mode and watch mode

• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open.

• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

Operation of the pull-up register

Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L”

level, the pull-up resistor is disconnected regardless of the value of the PUL6 register.

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MB95650L Series

15.4 Port F

Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral

functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.4.1 Port F configuration

Port F is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins

• Port F data register (PDRF)

• Port F direction register (DDRF)

15.4.2 Block diagrams of port F

PF0/X0 pin

This pin has the following peripheral function:

• Main clock input oscillation pin (X0)

PF1/X1 pin

This pin has the following peripheral function:

• Main clock I/O oscillation pin (X1)

Block diagram of PF0/X0 and PF1/X1

Hysteresis

0

1

PDRF read

PDRF

PDRF write

Executing bit manipulation instruction

DDRF read

DDRF

DDRF write

Stop mode, watch mode (SPL = 1)

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MB95650L Series

PF2/RST pin

This pin has the following peripheral function:

• Reset pin (RST)

Block diagram of PF2/RST

Reset input

Reset input enable

le

Reset output enab

Reset output

Hysteresis

0

1

PDRF read

PDRF write

1

0

OD

PDRF

Executing bit manipulation instruction

DDRF read

DDRF

DDRF write

Stop mode, watch mode (SPL = 1)

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MB95650L Series

15.4.3 Port F registers

Port F register functions

Register

Data

Read by read-modify-write

(RMW) instruction

Read

Write

abbreviation

0

Pin state is “L” level.

Pin state is “H” level.

PDRF value is “0”.

PDRF value is “1”.

Port input enabled

Port output enabled

As output port, outputs “L” level.

As output port, outputs “H” level.*

PDRF

1

0

DDRF

1

*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.

Correspondence between registers and pins for port F

Correspondence between related register bits and pins

Pin name

PDRF

-

PF2*

PF1

PF0

-

bit2

bit1

bit0

DDRF

*: PF2/RST is the dedicated reset pin on MB95F652L/F653L/F654L/F656L.

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MB95650L Series

15.4.4 Port F operations

Operation as an output port

• A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• When a pin is used as an output port, it outputs the value of the PDRF register to external pins.

• If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is.

• Reading the PDRF register returns the PDRF register value.

Operation as an input port

• A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port.

• Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read

the PDRF register, the PDRF register value is returned.

Operation at reset

If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled.

Operation in stop mode and watch mode

• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open.

• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

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MB95650L Series

15.5 Port G

Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral

functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.5.1 Port G configuration

Port G is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins

• Port G data register (PDRG)

• Port G direction register (DDRG)

• Port G pull-up register (PULG)

15.5.2 Block diagram of port G

PG1/X0A pin

This pin has the following peripheral function:

• Subclock input oscillation pin (X0A)

PG2/X1A pin

This pin has the following peripheral function:

• Subclock I/O oscillation pin (X1A)

Block diagram of PG1/X0A and PG2/X1A

Hysteresis

0

Pull-up

1

PDRG read

PDRG

PDRG write

Executing bit manipulation instruction

DDRG read

DDRG

DDRG write

PULG read

PULG write

Stop mode, watch mode (SPL = 1)

PULG

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MB95650L Series

15.5.3 Port G registers

Port G register functions

Register

Data

Read by read-modify-write

(RMW) instruction

Read

Write

abbreviation

0

Pin state is “L” level.

Pin state is “H” level.

PDRG value is “0”.

PDRG value is “1”.

Port input enabled

Port output enabled

Pull-up disabled

As output port, outputs “L” level.

As output port, outputs “H” level.

PDRG

1

0

DDRG

1

0

PULG

1

Pull-up enabled

Correspondence between registers and pins for port G

Correspondence between related register bits and pins

Pin name

PDRG

-

PG2

PG1

-

DDRG

-

bit2

bit1

-

PULG

Document Number: 002-04696 Rev. *A

Page 51 of 105

MB95650L Series

15.5.4 Port G operations

Operation as an output port

• A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• When a pin is used as an output port, it outputs the value of the PDRG register to external pins.

• If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output

port as it is.

• Reading the PDRG register returns the PDRG register value.

Operation as an input port

• A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.

• For a pin shared with other peripheral functions, disable the output of such peripheral functions.

• If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an

input port.

• Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read

the PDRG register, the PDRG register value is returned.

Operation at reset

If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled.

Operation in stop mode and watch mode

• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open.

• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

Operation of the pull-up register

Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L”

level, the pull-up resistor is disconnected regardless of the value of the PULG register.

Document Number: 002-04696 Rev. *A

Page 52 of 105

MB95650L Series

16. Interrupt Source Table

Interrupt level setting Priority order of interrupt

Interrupt Vector table address

register

sources of the same level

(occurring

Interrupt source

request

number

Upper

Lower

Register

Bit

simultaneously)

External interrupt ch. 4

External interrupt ch. 5

External interrupt ch. 2

External interrupt ch. 6

External interrupt ch. 3

External interrupt ch. 7

Low-voltage detection interrupt circuit

UART/SIO ch. 0

IRQ00

IRQ01

0xFFFA

0xFFF8

0xFFFB

0xFFF9

ILR0

L00 [1:0]

L01 [1:0]

High

IRQ02

IRQ03

IRQ04

0xFFF6

0xFFF4

0xFFF2

0xFFF7

0xFFF5

0xFFF3

ILR0

ILR1

L02 [1:0]

L03 [1:0]

L04 [1:0]

8/16-bit composite timer ch. 0 (lower)

8/16-bit composite timer ch. 0 (upper)

LIN-UART (reception)

LIN-UART (transmission)

—

IRQ05

IRQ06

IRQ07

IRQ08

IRQ09

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ16

IRQ17

IRQ18

IRQ19

IRQ20

IRQ21

IRQ22

IRQ23

0xFFF0

0xFFEE

0xFFF1

0xFFEF

ILR1

ILR2

ILR3

ILR4

ILR5

L05 [1:0]

L06 [1:0]

L07 [1:0]

L08 [1:0]

L09 [1:0]

L10 [1:0]

L11 [1:0]

L12 [1:0]

L13 [1:0]

L14 [1:0]

L15 [1:0]

L16 [1:0]

L17 [1:0]

L18 [1:0]

L19 [1:0]

L20 [1:0]

L21 [1:0]

L22 [1:0]

L23 [1:0]

0xFFEC 0xFFED

0xFFEA

0xFFE8

0xFFE6

0xFFE4

0xFFE2

0xFFE0

0xFFEB

0xFFE9

0xFFE7

0xFFE5

0xFFE3

0xFFE1

I²C bus interface ch. 1

—

8/16-bit composite timer ch. 1 (upper)

0xFFDE 0xFFDF

0xFFDC 0xFFDD

0xFFDA 0xFFDB

—

I²C bus interface ch. 0

—

0xFFD8

0xFFD6

0xFFD4

0xFFD2

0xFFD0

0xFFD9

0xFFD7

0xFFD5

0xFFD3

0xFFD1

8/12-bit A/D converter

Time-base timer

Watch prescaler

—

8/16-bit composite timer ch. 1 (lower)

Flash memory

0xFFCE 0xFFCF

0xFFCC 0xFFCD

Low

Document Number: 002-04696 Rev. *A

Page 53 of 105

MB95650L Series

17. Pin States in each Mode

Stop mode

Watch mode

Normal

operation

Pin name

Sleep mode

On reset

SPL=0

SPL=1

SPL=0

SPL=1

Oscillation input Oscillation input

Hi-Z

—

- Hi-Z

- Previous state

kept

- Previous state

kept

- Input

- Hi-Z

enabled*³

(However, it

does not

function.)

PF0/X0

I/O port*¹

- Input

blocked*^1,

*

blocked*^1,

*

2

blocked*^1,

*

blocked*^1,

*

Oscillation input Oscillation input

Hi-Z

—

- Hi-Z

- Input

- Previous state

kept

- Previous state

kept

- Hi-Z

enabled*³

(However, it

does not

function.)

PF1/X1

I/O port*¹

Reset input

I/O port*¹

Reset input

I/O port*¹

- Input

blocked*^1,

2

blocked*^1,

*

blocked*^1,

*

Reset input

Reset input*⁴

- Hi-Z

- Input

- Previous state

kept

- Previous state

kept

- Hi-Z

enabled*³

(However, it

does not

function.)

PF2/RST

PG1/X0A

PG2/X1A

- Input

blocked*^1,

*

blocked*^1,

*

2

blocked*^1,

*

blocked*^1,

*

Oscillation input Oscillation input

Hi-Z

—

- Hi-Z

- Input

- Previous state

kept

- Previous state

kept

- Hi-Z

enabled*³

(However, it

does not

function.)

I/O port*¹

- Input

blocked*^1,

2

blocked*^1,

*

blocked*^1,

*

Oscillation input Oscillation input

Hi-Z

—

- Hi-Z

- Input

- Previous state

kept

- Previous state

kept

- Hi-Z

enabled*³

(However, it

does not

function.)

I/O port*¹

- Input

blocked*^1,

2

blocked*^1,

*

blocked*^1,

*

P00/AN00

P01/AN01

P02/INT02/

AN02/SCK

I/O port/

peripheral

function I/O/

analog input

I/O port/

peripheral

function I/O/

analog input

- Previous state

kept

- Previous state

kept

- Hi-Z*⁶

- Input

- Hi-Z*⁶

- Input

- Hi-Z

P03/INT03/

AN03/SOT

- Input

5

blocked*^2,

*

blocked*^2,

*

blocked*²

5

blocked*^2,

*

blocked*^2,

*

P04/INT04/

AN04/SIN/

EC0

P05/INT05/

AN05/TO00

Document Number: 002-04696 Rev. *A

Page 54 of 105

MB95650L Series

Stop mode

SPL=0 SPL=1

Watch mode

Normal

operation

Pin name

Sleep mode

On reset

SPL=0

SPL=1

P06/INT06/

TO01

- Previous state

kept

- Previous state

kept

I/O port/

peripheral

function I/O

I/O port/

peripheral

function I/O

- Hi-Z*⁶

- Hi-Z

- Input

P07/INT07/

TO10

5

7

5

7

blocked*^2,

*

blocked*^2,

*

blocked*²

5

blocked*^2,

*

blocked*^2,

*

P14/SDA0

P15/SCL0

- Hi-Z

- Input

- Previous state

kept

- Previous state

kept

I/O port/

peripheral func- peripheral func-

tion I/O

I/O port/

- Hi-Z

enabled*³

(However, it

does not

function.)

P16/SDA1/

UO0

- Input

tion I/O

blocked*^2,

*

blocked*^2,

*

7

blocked*^2,

*

blocked*^2,

*

P17/SCL1/

UI0

P12/DBG/

EC0

- Hi-Z

- Input

- Previous state

kept

- Previous state

kept

I/O port/

peripheral

function I/O

I/O port/

peripheral

function I/O

- Hi-Z

enabled*³

(However, it

does not

function.)

P62/TO10/

UCK0

- Input

blocked*²

P63/TO11

P64/EC1

SPL: Pin state setting bit in the standby control register (STBC:SPL)

Hi-Z: High impedance

*1: The pin stays at the state shown when configured as a general-purpose I/O port.

*2: “Input blocked” means direct input gate operation from the pin is disabled.

*3: “Input enabled” means that the input function is enabled. While the input function is enabled, perform a pull-up or pull-down

operation in order to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other

ports.

*4: The PF2/RST pin stays at the state shown when configured as a reset pin.

*5: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled.

*6: The pull-up control setting is still effective.

*7: The I²C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled.

For details of the MCU standby mode wakeup function, refer to “Chapter 19 I²c Bus Interface” in “New 8FX MB95650L Series

Hardware Manual”.

Document Number: 002-04696 Rev. *A

Page 55 of 105

MB95650L Series

18. Electrical Characteristics

18.1 Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V_SS 6

2

Power supply voltage*¹

Input voltage*¹

Output voltage*¹

V_CC

V_I

V_SS0.3

2

V

*2

V_O

Maximum clamp current

I_CLAMP

mA Applicable to specific pins*³

Total maximum clamp current |I_CLAMP

|

—

20

“L” level maximum output

current

I_OL

—

15

mA

Other than P05 to P07, P62 and P63

Average output current =

operating current  operating ratio (1 pin)

I_OLAV1

“L” level average current

I_OLAV2

4

—

mA

P05 to P07, P62 and P63

Average output current =

operating current  operating ratio (1 pin)

12

100

37

“L” level total maximum output

current

I_OL

—

mA

Total average output current =

mA operating current  operating ratio

(Total number of pins)

“L” level total average output

current

I_OLAV

“H” level maximum output

current

I_OH

15

4

mA

Other than P05 to P07, P62 and P63

Average output current =

operating current  operating ratio (1 pin)

I_OHAV1

“H” level average current

I_OHAV2

—

mA

P05 to P07, P62 and P63

Average output current =

8

operating current  operating ratio (1 pin)

“H” level total maximum output

current

I_OH

—

100

47

mA

Total average output current =

mA operating current  operating ratio

(Total number of pins)

“H” level total average output

current

I_OHAV

Power consumption

Operating temperature

Storage temperature

P_d

T_A

—

320

85

mW

C

40

55

T_stg

150

*1: These parameters are based on the condition that V_SSis 0.0 V.

*2: V₁and V₀must not exceed V_CC 0.3 V. V₁must not exceed the rated voltage. However, if the maximum current to/from an input

is limited by means of an external component, the I_CLAMPrating is used instead of the V_Irating.

(Continued)

Document Number: 002-04696 Rev. *A

Page 56 of 105

MB95650L Series

(Continued)

*3: Specific pins: P00 to P07, P14, P15, P62 to P64, PF0, PF1, PG1, PG2

• Use under recommended operating conditions.

• Use with DC voltage (current).

• The HV (High Voltage) signal is an input signal exceeding the V

voltage. Always connect a limiting resistor

CC

between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.

• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin

when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient

current or stationary current.

• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage)

input potential may pass through the protective diode to increase the potential of the V pin, affecting other devices.

CC

• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power

is supplied from the pins, incomplete operations may be executed.

• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power

supply may not be sufficient to enable a power-on reset.

• Do not leave the HV (High Voltage) input pin unconnected.

• Example of a recommended circuit:

Input/Output equivalent circuit

Protective diode

VCC

P-ch

Limiting

resistor

HV(High Voltage) input (0 V to 16 V)

N-ch

R

WARNING:

Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage,

current or temperature) in excess of absolute maximum ratings.

Do not exceed any of these ratings.

Document Number: 002-04696 Rev. *A

Page 57 of 105

MB95650L Series

18.2 Recommended Operating Conditions

(V_SS= 0.0 V)

Value

Parameter

Power supply voltage

Symbol

Unit

Remarks

Min

1.8*¹

0.2

Max

5.5

V_CC

C_S

V

In normal operation

Decoupling capacitor

10

µF A capacitor of about 1.0 µF is recommended. *²

40

5

85

35

Other than on-chip debug mode

Operating temperature

T_A

C

On-chip debug mode

*1: The minimum power supply voltage becomes 2.18 V when a product with the low-voltage detection reset is used or when the

on-chip debug mode is used.

*2: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. For the connection to a decoupling capacitor C_S,

see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance

between the C pin and C_Sand the distance between C_Sand the V_SSpin when designing the layout of a printed circuit board.

DBG / RST / C pins connection diagram

*

DBG

C

RST

Cs

*: Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the DBG pin

does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug

mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the

tool document when selecting a pull-up resistor.

WARNING:

The recommended operating conditions are required in order to ensure the normal operation of the semiconductor

device. All of the device's electrical characteristics are warranted when the device is operated under these conditions.

Any use of semiconductor devices will be under their recommended operating condition.

Operation under any conditions other than these conditions may adversely affect reliability of device and could result

in device failure.

No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet.

If you are considering application under any conditions other than listed herein, please contact sales representatives

beforehand.

Document Number: 002-04696 Rev. *A

Page 58 of 105

MB95650L Series

18.3 DC Characteristics

(V_CC= 3.0 V10%, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min

Typ

—

Max

V_IHI1

V_IHI2

P04, P16, P17

P14, P15

*1

0.7 V_CC

V_CC 0.3

V_CC 5.5

V

CMOS input level

—

P00 to P03,

P05 to P07,

P12,

P62 to P64,

PF0, PF1,

PG1, PG2

“H” level input

voltage

V_IHS

*1

0.8 V_CC

—

V_CC 0.3

V

Hysteresis input

V_IHM

V_ILI

PF2

—

*1

0.8 V_CC

—

V_CC 0.3

V

Hysteresis input

CMOS input level

P04, P14 to P17

V_SS0.3

0.3 V_CC

P00 to P03,

P05 to P07,

P12,

P62 to P64,

PF0, PF1,

PG1, PG2

“L” level input

voltage

V_ILS

*1

V_SS0.3

—

0.2 V_CC

V

Hysteresis input

V_ILM

V_D1

V_D2

PF2

—

V_SS0.3

—

0.2 V_CC

V_SS 5.5

V

Open-drain

output

application

voltage

P12, PF2

P14, P15

V_D3

P16, P17

—

V_SS0.3

—

V_SS 5.5

V

In I²C mode

Output pins other

V_OH1

than P05 to P07, I_OH= 4 mA*²

P12, P62, P63

V_CC0.5

—

V

“H”leveloutput

voltage

P05 to P07, P62,

I_OH= 8 mA*³

P63

V_OH2

V_OL1

V_OL2

V_CC0.5

—

V

Output pins other

than P05 to P07, I_OL= 4 mA*⁴

P62, P63

—

0.4

“L” level output

voltage

P05 to P07, P62,

I_OL= 12 mA*⁵

P63

Input leak

current (Hi-Z

output leak

current)

When the internal

µA pull-up resistor is

disabled

I_LI

All input pins

0.0 V < V_I< V_CC

5

—

5

P00 to P07,

R_PULLP62 to P64,

PG1, PG2

When the internal

k pull-up resistor is

enabled

Internal

pull-up resistor

V_I= 0 V

75

—

100

5

150

15

Input

capacitance

Other than V_CC

and V_SS

C_IN

f = 1 MHz

pF

(Continued)

Document Number: 002-04696 Rev. *A

Page 59 of 105

MB95650L Series

(V_CC= 3.0 V10%, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Typ*¹Max*⁶

Min

Except during Flash

—

4.2

6.8

mA memory programming

and erasing

F_CH= 32 MHz

_MP= 16 MHz

Main clock mode

(divided by 2)

F

I_CC

During Flash memory

mA programming and

erasing

—

9.3

6

14.7

10

mA At A/D conversion

F_CH= 32 MHz

F_MP= 16 MHz

Main sleep mode

(divided by 2)

I_CCS

—

1.7

3

mA

V_CC

(External clock

operation)

F_CL= 32 kHz

F_MPL= 16 kHz

Subclock mode

(divided by 2)

T_A= 25 °C

I_CCL

—

35

60

µA

F_CL= 32 kHz

F_MPL= 16 kHz

Subsleep mode

(divided by 2)

T_A= 25 °C

I_CCLS

—

2

7

6

µA

Power supply

current*⁷

F_CL= 32 kHz

Watch mode

Main stop mode

T_A= 25 °C

I_CCT

1

F_MCRPLL= 16 MHz

F_MP= 16 MHz

Main CR PLL clock

mode

I_CCMCRPLL

4.3

4.1

7.7

7

mA

(multiplied by 4)

F_MPLL= 16 MHz

F_MP= 16 MHz

Main PLL clock mode

(multiplied by 4)

I_CCMPLL

mA

V_CC

F_CRH= 4 MHz

F_MP= 4 MHz

Main CR clock mode

I_CCMCR

—

1.5

50

3

Sub-CR clock mode

(divided by 2)

I_CCSCR

100

µA

T_A= 25 °C

(Continued)

Document Number: 002-04696 Rev. *A

Page 60 of 105

MB95650L Series

(V_CC= 3.0 V10%, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

Condition

F_CH= 32 MHz

Unit

Remarks

Typ*¹Max*⁶

Min

I_CCTS

Time-base timer mode

T_A= 25 °C

—

450

0.7

500

5

µA

V_CC

(External clock

operation)

Substop mode

T_A= 25 °C

I_CCH

—

Current consumption of

the low-voltage

detection reset circuit in

operation

I_PLVD

6

26

14

µA

Current consumption of

the low-voltage

detection interrupt

circuit operating in

normal mode

I_ILVD

—

Power supply

current*⁷

Current consumption of

the low-voltage

detection interrupt

circuit operating in low

power consumption

mode

V_CC

I_ILVDL

3

10

µA

Current consumption of

the main CR oscillator

I_CRH

—

270

5

320

20

7

µA

Current consumption of

the sub-CR oscillator

oscillating at 100 kHz

I_CRL

Current consumption of

the suboscillator

I_SOSC

0.8

*1: V_CC= 3.0 V, T_A= 25 °C

*2: When V_CCis smaller than 4.5 V, the condition becomes I_OH= 2 mA.

*3: When V_CCis smaller than 4.5 V, the condition becomes I_OH= 4 mA.

*4: When V_CCis smaller than 4.5 V, the condition becomes I_OL= 2 mA.

*5: When V_CCis smaller than 4.5 V, the condition becomes I_OH= 6 mA.

*6: V_CC= 3.3 V, T_A= 85 °C (unless otherwise specified)

*7: • The power supply current is determined by the external clock. When the low-voltage detection reset circuit is selected, the power

supply current is the sum of adding the current consumption of the low-voltage detection reset circuit (I_PLVD) to one of the values

from I_CCto I_CCH. In addition, when the low-voltage detection reset circuit and a CR oscillator are selected, the power supply

current is the sum of adding up the current consumption of the low-voltage detection reset circuit (I_PLVD), the current

consumption of the CR oscillator (I_CRHor I_CRL) and one of the values from I_CCto I_CCH. In on-chip debug mode, the main CR

oscillator (I_CRH) and the low-voltage detection reset circuit are always in operation, and current consumption therefore increases

accordingly.

• See “18.4. AC Characteristics 18.4.1. Clock Timing” for F_CH, F_CL, F_CRH, F_MCRPLLand F_MPLL

.

• See “18.4. AC Characteristics 18.4.2. Source Clock/Machine Clock” for F_MPand F_MPL

.

• The power supply current in subclock mode is determined by the external clock. In subclock mode, current consumption in using

the crystal oscillator is higher than that in using the external clock. When the crystal oscillator is used, the power supply current

is the sum of adding I_SOSC(current consumption of the suboscillator) to the power supply current in using the external clock.

For details of controlling the subclock, refer to “Chapter 3 Clock Controller” And “chapter 24 System Configuration Register” in

“New 8FX MB95650L Series Hardware Manual”.

Document Number: 002-04696 Rev. *A

Page 61 of 105

MB95650L Series

18.4 AC Characteristics

18.4.1 Clock Timing

(V_CC= 1.8 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min

Max

When the main oscillation circuit is

used

X0, X1

—

1

—

16.25 MHz

F_CH

When the main external clock is

used

X0

—

1

—

4

32.5

—

MHz

X0, X1

—

MHz When the main PLL clock is used

Operating conditions

MHz • The main CR clock is used.

^{• 0}C T_A70C

3.92

4

4.08

F_CRH

—

Operating conditions

• The main CR clock is used.

3.8

4

4.2

MHz

• ⁴⁰C  T_A 0C,

⁷⁰C  T_A 85C

Operating conditions

MHz • PLL multiplication rate: 2

^{• 0}C T_A70C

7.84

7.6

8

8.16

8.4

Operating conditions

• PLL multiplication rate: 2

8

MHz

• ⁴⁰C  T_A 0C,

70C  T_A 85C

Operating conditions

MHz • PLL multiplication rate: 2.5

^{• 0}C T_A70C

Clock frequency

9.8

10

12

16

10.2

10.5

Operating conditions

• PLL multiplication rate: 2.5

9.5

MHz

• ⁴⁰C  T_A 0C,

70C  T_A 85C

F_MCRPLL

—

Operating conditions

12.24 MHz • PLL multiplication rate: 3

11.76

11.4

15.68

^{• 0}C T_A70C

Operating conditions

• PLL multiplication rate: 3

12.6

MHz

• ⁴⁰C  T_A 0C,

⁷⁰C  T_A 85C

Operating conditions

16.32 MHz • PLL multiplication rate: 4

^{• 0}C T_A70C

Operating conditions

• PLL multiplication rate: 4

15.2

8

16

—

16.8

16

MHz

• ⁴⁰C  T_A 0C,

⁷⁰C  T_A 85C

F_MPLL

—

MHz When the main PLL clock is used

(Continued)

Document Number: 002-04696 Rev. *A

Page 62 of 105

MB95650L Series

(Continued)

(V_CC= 1.8 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min

Max

When the suboscillation circuit is

used

—

32.768

—

kHz

F_CL

X0A, X1A

—

Clock frequency

Clock cycle time

—

32.768

100

—

kHz When the sub-external clock is used

kHz When the sub-CR clock is used

F_CRL

—

50

150

When the main oscillation circuit is

used

X0, X1

61.5

—

1000

ns

t_HCYL

X0

—

30.8

—

1000

—

ns When an external clock is used

ns When the main PLL clock is used

µs When the subclock is used

X0, X1

X0A, X1A

250

30.5

t_LCYL

—

When an external clock is used, the

ns duty ratio should range between

40% and 60%.

X0

—

12.4

—

t

_WH1, t_WL1

Input clock

pulse width

X0, X1

125

15.2

ns When the main PLL clock is used

When an external clock is used, the

µs duty ratio should range between

40% and 60%.

t_WH2, t_WL2X0A

—

Input clock

rising time and

falling time

t_CR, t_CFX0, X0A

—

5

ns When an external clock is used

t_CRHWK

t_CRLWK

—

50

30

µs When the main CR clock is used

µs When the sub-CR clock is used

CR oscillation

start time

PLL oscillation

start time

When the main CR PLL clock is

used

t_MCRPLLWK

—

100

µs

Document Number: 002-04696 Rev. *A

Page 63 of 105

MB95650L Series

Input waveform generated when an external clock (main clock) is used

t

HCYL

t

WH1

t

WL1

t

CR

t

CF

0.8 VCC 0.8 VCC

0.2 VCC

X0, X1

0.2 VCC

Figure of main clock input port external connection

When a crystal oscillator or

a ceramic oscillator is used

When an external clock

is used

X0

X1

X0

FCH

Input waveform generated when an external clock (subclock) is used

t

LCYL

tWH2

t

WL2

t

CR

t

CF

0.8 VCC 0.8 VCC

0.2 VCC

X0A

0.2 VCC

Figure of subclock input port external connection

When a crystal oscillator or

a ceramic oscillator is used

When an external clock

is used

X0A X1A

X0A

FCL

Document Number: 002-04696 Rev. *A

Page 64 of 105

MB95650L Series

Input waveform generated when an internal clock (main CR clock) is used

tCRHWK

1/FCRH

Main CR clock

Oscillation starts

Oscillation stabilizes

Input waveform generated when an internal clock (sub-CR clock) is used

tCRLWK

1/FCRL

Sub-CR clock

Oscillation starts

Oscillation stabilizes

Input waveform generated when an internal clock (main CR PLL clock) is used

1/FMCRPLL

tMCRPLLWK

Main CR PLL clock

Oscillation starts

Oscillation stabilizes

Document Number: 002-04696 Rev. *A

Page 65 of 105

MB95650L Series

18.4.2 Source Clock/Machine Clock

(V_CC= 1.8 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

Parameter

Symbol

Unit

Remarks

name

Min

61.5

—

Max

2000

—

When the main external clock is used

—

250

—

ns Min: F_CH= 32.5 MHz, divided by 2

Max: F_CH= 1 MHz, divided by 2

ns When the main CR clock is used

When the main PLL clock is used

ns Min: F_CH= 4 MHz, multiplied by 4

Max: F_CH= 4 MHz, no division

62.5

250

Source clock cycle

time*¹

t_SCLK

—

When the main CR PLL clock is used

ns Min: F_CRH= 4 MHz, multiplied by 4

Max: F_CRH= 4 MHz, no division

62.5

—

250

When the suboscillation clock is used

F_CL= 32.768 kHz, divided by 2

—

61

20

—

µs

When the sub-CR clock is used

µs

F_CRL= 100 kHz, divided by 2

0.5

—

4

—

4

16.25

—

MHz When the main oscillation clock is used

MHz When the main CR clock is used

MHz When the main PLL clock is used

MHz When the main CR PLL clock is used

kHz When the suboscillation clock is used

F_SP

—

16

Source clock

frequency

—

4

—

16

—

16.384

—

F_SPL

When the sub-CR clock is used

kHz

—

50

—

F_CRL= 100 kHz, divided by 2

When the main oscillation clock is used

ns Min: F_SP= 16.25 MHz, no division

Max: F_SP= 0.5 MHz, divided by 16

61.5

—

32000

When the main CR clock is used

ns Min: F_SP= 4 MHz, no division

Max: F_SP= 4 MHz, divided by 16

250

62.5

61

—

4000

976.5

320

When the main PLL clock is used

ns Min: F_SP= 4 MHz, multiplied by 4

Max: F_SP= 4 MHz, divided by 16

Machine clock

cycle time*²

(minimum

t_MCLK

—

When the main CR PLL clock is used

ns Min: F_SP= 4 MHz, multiplied by 4

Max: F_SP= 4 MHz, divided by 16

instruction

execution time)

When the suboscillation clock is used

µs Min: F_SPL= 16.384 kHz, no division

Max: F_SPL= 16.384 kHz, divided by 16

When the sub-CR clock is used

µs Min: F_SPL= 50 kHz, no division

Max: F_SPL= 50 kHz, divided by 16

20

(Continued)

Document Number: 002-04696 Rev. *A

Page 66 of 105

MB95650L Series

(Continued)

(V_CC= 1.8 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

—

Parameter

Symbol

Unit

Remarks

name

Min

0.031

0.25

Max

16.25

4

MHz When the main oscillation clock is used

MHz When the main CR clock is used

MHz When the main PLL clock is used

MHz When the main CR PLL clock is used

kHz When the suboscillation clock is used

—

F_MP

0.25

—

16

Machine clock

frequency

—

0.25

—

16

1.024

—

16.384

F_MPL

When the sub-CR clock is used

F_CRL= 100 kHz

3.125

—

50

kHz

*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits

(SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock

division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following.

• Main clock divided by 2

• PLL multiplication of main clock (Select a multiplication rate from 2, 2.5, 3 and 4.)

• Main CR clock

• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)

• Subclock divided by 2

• Sub-CR clock divided by 2

*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

Document Number: 002-04696 Rev. *A

Page 67 of 105

MB95650L Series

Schematic diagram of the clock generation block

FCH

Divided by 2

(Main oscillation clock)

FMPLL

(Main PLL clock)

FCRH

(Main CR clock)

Division circuit

SCLK

(Source clock)

×

1

1/4

1/8

MCLK

(Machine clock)

FMCRPLL

(Main CR PLL clock)

× 1/16

FCL

Machine clock divide ratio select bits

(SYCC:DIV[1:0])

Divided by 2

(Suboscillation clock)

FCRL

(Sub-CR clock)

Clock mode select bits

(SYCC:SCS[2:0])

Operating voltage - Operating frequency (T = 40 °C to 85 °C)

A

5.5

5.0

4.5

4.0

A/D converter operation range

3.5

3.0

2.5

2.0

1.8

1.5

≈

0.0

16 kHz

3 MHz

10 MHz

16.25 MHz

Source clock frequency (FSP/FSPL)

Document Number: 002-04696 Rev. *A

Page 68 of 105

MB95650L Series

18.4.3 External Reset

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Unit

Remarks

Min

Max

RST “L” level

pulse width

t_RSTL

2 t_MCLK

*

ns



*: See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

tRSTL

RST

0.2 VCC

0.2 V^CC

Document Number: 002-04696 Rev. *A

Page 69 of 105

MB95650L Series

18.4.4 Power-on Reset

(V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

name

Parameter

Symbol

Unit

Remarks

Min

Max

Power supply

rising time

dV/dt

T_off

0.1

—

V/ms

ms

V

Power supply

cutoff time

1

—

1.76

1.71

10

Reset release

voltage

V_deth

V_detl

T_ond

T_offd

1.44

1.39

—

1.60

1.55

—

At voltage rise

At voltage fall

V_CC

Reset detection

voltage

V

Reset release

delay time

ms dV/dt  0.1 mV/µs

Reset detection

delay time

—

0.4

ms dV/dt  0.04 mV/µs

T

off

V

deth

dV

V

detl

V

CC

0.2 V

dt

T

ond

Toffd

Power-on reset

Document Number: 002-04696 Rev. *A

Page 70 of 105

MB95650L Series

18.4.5 Peripheral Input Timing

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

Unit

Min

Max



Peripheral input “H” pulse width

Peripheral input “L” pulse width

t_ILIH

t_IHIL

2 t_MCLK

*

ns

INT02 to INT07, EC0, EC1

2 t_MCLK

*



*: See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

t

ILIH

t

IHIL

0.8 VCC 0.8 VCC

INT02 to INT07,

EC0, EC1

0.2 VCC

Document Number: 002-04696 Rev. *A

Page 71 of 105

MB95650L Series

18.4.6 LIN-UART Timing

Sampling is executed at the rising edge of the sampling clock*¹, and serial clock delay is disabled*².

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

SCK

Condition

Unit

Min

5 t_MCLK

50

Max

3

Serial clock cycle time

SCK  SOT delay time

Valid SIN  SCK

t_SCYC

*

—

ns

Internal clock operation

output pin:

C_L= 80 pF  1 TTL

t_SLOVISCK, SOT

50

t_IVSHI

t_SHIXI

t_SLSH

t_SHSL

SCK, SIN

SCK

t_MCLK*³ 80

—

SCK  valid SIN hold time

Serial clock “L” pulse width

Serial clock “H” pulse width

SCK  SOT delay time

Valid SIN  SCK

0

—

3 t_MCLK*³t_R

t_MCLK*³ 10

—

SCK

—

t_SLOVESCK, SOT

t_IVSHESCK, SIN

t_SHIXESCK, SIN

—

2 t_MCLK*³ 60

External clock operation

output pin:

C_L= 80 pF  1 TTL

30

—

10

SCK  valid SIN hold time

SCK fall time

t_MCLK*³ 30

t_F

SCK

—

SCK rise time

t_R

*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the

serial clock.

*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.

*3: See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

Document Number: 002-04696 Rev. *A

Page 72 of 105

MB95650L Series

Internal shift clock mode

tSCYC

0.8 VCC

SCK

0.2 VCC

t

SLOVI

0.8 VCC

0.2 VCC

SOT

tIVSHI

tSHIXI

0.7 VCC 0.7 VCC

SIN

0.3 VCC 0.3 VCC

External shift clock mode

t

SLSH

t

SHSL

0.8 VCC

SCK

SOT

SIN

0.2 VCC

t

R

t

F

t

SLOVE

0.8 VCC

0.2 VCC

t

IVSHE

t

SHIXE

0.7 VCC 0.7 VCC

0.3 VCC 0.3 VCC

Document Number: 002-04696 Rev. *A

Page 73 of 105

MB95650L Series

Sampling is executed at the falling edge of the sampling clock*¹, and serial clock delay is disabled*².

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

SCK

Condition

Unit

Min

5 t_MCLK

50

Max

3

Serial clock cycle time

SCK  SOT delay time

Valid SIN  SCK

t_SCYC

*

—

ns

Internal clock operation

output pin:

C_L= 80 pF  1 TTL

t_SHOVISCK, SOT

50

t_IVSLI

t_SLIXI

t_SHSL

t_SLSH

SCK, SIN

SCK

t_MCLK*³ 80

—

SCK valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK  SOT delay time

Valid SIN  SCK

0

—

3 t_MCLK*³t_R

t_MCLK*³ 10

—

SCK

—

t_SHOVESCK, SOT

t_IVSLESCK, SIN

t_SLIXESCK, SIN

—

2 t_MCLK*³ 60

External clock operation

output pin:

C_L= 80 pF  1 TTL

30

—

10

SCK valid SIN hold time

SCK fall time

t_MCLK*³ 30

t_F

SCK

—

SCK rise time

t_R

*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the

serial clock.

*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.

*3: See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

Document Number: 002-04696 Rev. *A

Page 74 of 105

MB95650L Series

Internal shift clock mode

tSCYC

0.8 VCC

SCK

0.2 VCC

t

SHOVI

0.8 VCC

0.2 VCC

SOT

SIN

tIVSLI

tSLIXI

0.7 VCC 0.7 VCC

0.3 VCC 0.3 VCC

External shift clock mode

t

SHSL

t

SLSH

0.8 VCC

SCK

0.2 VCC

t

F

tR

tSHOVE

0.8 VCC

0.2 VCC

SOT

SIN

t

IVSLE

tSLIXE

0.7 VCC 0.7 VCC

0.3 VCC 0.3 VCC

Document Number: 002-04696 Rev. *A

Page 75 of 105

MB95650L Series

Sampling is executed at the rising edge of the sampling clock*¹, and serial clock delay is enabled*².

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

SCK

Condition

Unit

Min

5 t_MCLK

50

Max

—

3

Serial clock cycle time

SCK SOT delay time

Valid SIN  SCK

t_SCYC

*

ns

t_SHOVISCK, SOT

50

—

Internal clock operation

output pin:

C_L= 80 pF  1 TTL

t_IVSLI

t_SLIXI

SCK, SIN

t_MCLK*³ 80

SCK valid SIN hold time

SOT  SCKdelay time

0

—

t_SOVLISCK, SOT

3t_MCLK*³70

—

*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the

serial clock.

*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.

*3: See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

t

SCYC

0.8 VCC

SCK

0.2 VCC

t

SHOVI

t

SOVLI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SOT

SIN

t

IVSLI

t

SLIXI

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

Document Number: 002-04696 Rev. *A

Page 76 of 105

MB95650L Series

Sampling is executed at the falling edge of the sampling clock*¹, and serial clock delay is enabled*².

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

SCK

Condition

Unit

Min

5 t_MCLK

50

Max

—

3

Serial clock cycle time

SCK  SOT delay time

Valid SIN  SCK

t_SCYC

*

ns

t_SLOVISCK, SOT

50

—

Internal clock operation

output pin:

C_L= 80 pF  1 TTL

t_IVSHI

t_SHIXI

SCK, SIN

t_MCLK*³ 80

SCK  valid SIN hold time

SOT  SCKdelay time

0

—

t_SOVHISCK, SOT

3t_MCLK*³70

—

*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the

serial clock.

*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.

*3: See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

t

SCYC

0.8 VCC

SCK

0.2 VCC

tSOVHI

t

SLOVI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SOT

SIN

t

IVSHI

t

SHIXI

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

Document Number: 002-04696 Rev. *A

Page 77 of 105

MB95650L Series

18.4.7 Low-vo ltage Detection

Normal mode

(V_CC= 1.8 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

2.03

1.93

2.3

2.2

2.6

2.5

2.9

2.8

3.3

3.2

3.7

3.6

4.1

4

Parameter

Symbol

Unit

Remarks

Min

1.88

1.8

Max

2.18

2.06

2.47

2.35

2.79

2.67

3.11

2.99

3.54

3.42

3.97

3.85

4.39

4.27

1.6

Reset release voltage

V_PDL

V_PDL

V_IDL0

V_IDL0

V_IDL1

V_IDL1

V_IDL2

V_IDL2

V_IDL3

V_IDL3

V_IDL4

V_IDL4

V_IDL5

V_IDL5

V_off

V

At power supply rise

Reset detection voltage

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

Interrupt release voltage 0

Interrupt detection voltage 0

Interrupt release voltage 1

Interrupt detection voltage 1

Interrupt release voltage 2

Interrupt detection voltage 2

Interrupt release voltage 3

Interrupt detection voltage 3

Interrupt release voltage 4

Interrupt detection voltage 4

Interrupt release voltage 5

Interrupt detection voltage 5

Power supply start voltage

Power supply end voltage

2.13

2.05

2.41

2.33

2.69

2.61

3.06

2.98

3.43

3.35

3.81

3.73

—

V_on

4.39

—

Slope of power supply that the reset

Power supply voltage change time

(at power supply rise)

t_r

t_f

697.5

—

µs release signal generates within the

rating (V_PDL/V_IDL

)

Slope of power supply that the reset

µs release signal generates within the

Power supply voltage change time

(at power supply fall)

rating (V_PDL/V_IDL

)

Reset release delay time

Reset detection delay time

Interrupt release delay time

Interrupt detection delay time

t_dp1

t_dp2

t_di1

t_di2

—

30

µs

LVD reset threshold voltage transition

stabilization time

t_stb

—

30

µs

Document Number: 002-04696 Rev. *A

Page 78 of 105

MB95650L Series

Low power consumption mode

Parameter

(V_CC= 1.8 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

2.3

2.2

2.6

2.5

2.9

2.8

3.3

3.2

3.7

3.6

4.1

4

Symbol

Unit

Remarks

Min

2.06

1.98

2.33

2.25

2.6

Max

2.54

2.42

2.87

2.75

3.2

Interrupt release voltage 0

Interrupt detection voltage 0

Interrupt release voltage 1

Interrupt detection voltage 1

Interrupt release voltage 2

Interrupt detection voltage 2

Interrupt release voltage 3

Interrupt detection voltage 3

Interrupt release voltage 4

Interrupt detection voltage 4

Interrupt release voltage 5

Interrupt detection voltage 5

Power supply start voltage

Power supply end voltage

V_IDLL0

V_IDLL0

V_IDLL1

V_IDLL1

V_IDLL2

V_IDLL2

V_IDLL3

V_IDLL3

V_IDLL4

V_IDLL4

V_IDLL5

V_IDLL5

V_offL

V

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

At power supply rise

At power supply fall

2.52

2.96

2.88

3.32

3.24

3.68

3.6

3.08

3.64

3.52

4.08

3.96

4.52

4.4

—

1.6

V_onL

4.52

—

Slope of power supply that the

Power supply voltage change time

(at power supply rise)

t_rL

7300

—

µs interrupt release signal generates

within the rating (V_IDLL

)

Slope of power supply that the

µs interrupt detection signal generates

Power supply voltage change time

(at power supply fall)

t_fL

within the rating (V_IDLL

)

Interrupt release delay time

Interrupt detection delay time

t_diL1

t_diL2

—

400

µs

Interrupt threshold voltage transition

stabilization time

t_stbL

—

400

µs

Interrupt low-voltage detection mode

switch time

Normal mode  Low power

consumption mode

t_mdsw

Note: When used for interrupt, the low-voltage detection circuit can be switched between the normal mode and the low power

consumption mode. Compared with the normal mode, while the low power consumption mode has lower detection voltage

accuracy and lower release voltage accuracy, it has the lower power consumption. See “18.3 DC Characteristics” for the

difference in current consumption between the normal mode and the low power consumption mode. For details of the method

for switching between the normal mode and the low power consumption mode, refer to “Chapter 17 Low-voltage Detection

Circuit” in “New 8FX MB95650L Series Hardware Manual”.

Document Number: 002-04696 Rev. *A

Page 79 of 105

MB95650L Series

V

CC

Von/VonL

Voff/VoffL

Time

tf/tfL

tr/trL

V

PDL+/VIDL+

PDL−/VIDL−

V

Internal reset signal or interrupt signal

Time

tdp2/tdi2/tdiL2

tdp1/tdi1/tdiL1

Document Number: 002-04696 Rev. *A

Page 80 of 105

MB95650L Series

18.4.8 I²C Bus Interface Timing

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

Condition

Standard-mode

Fast-mode

Unit

Min

Max

Min

Max

SCL clock frequency

f_SCL

SCL0, SCL1

0

100

0

400

kHz

µs

(Repeated) START condition hold time

SDA  SCL 

SCL0, SCL1,

SDA0, SDA1

t_HD;STA

4.0

—

0.6

—

SCL clock “L” width

SCL clock “H” width

t_LOW

t_HIGH

SCL0, SCL1

4.7

4.0

—

1.3

0.6

—

µs

(Repeated) START condition setup time

SCL  SDA 

SCL0, SCL1,

SDA0, SDA1

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

4.7

0

—

3.45^*2

—

0.6

0

—

0.9^*3

—

µs

R = 1.7 k,

C = 50 pF*¹

Data hold time

SCL  SDA 

SCL0, SCL1,

SDA0, SDA1

Data setup time

SDA  SCL 

SCL0, SCL1,

SDA0, SDA1

0.25

4

0.1

0.6

1.3

STOP condition setup time

SCL   SDA 

SCL0, SCL1,

SDA0, SDA1

—

Bus free time between STOP condition and

START condition

SCL0, SCL1,

SDA0, SDA1

4.7

—

*1: R represents the pull-up resistor of the SCL0/1 and SDA0/1 lines, and C the load capacitor of the SCL0/1 and SDA0/1 lines.

*2: The maximum t_HD;DATin the Standard-mode is applicable only when the time during which the device is holding the SCL signal

at “L” (t_LOW) does not extend.

*3: A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, provided that the condition of t_SU;DAT 250 ns is

fulfilled.

t^WAKEUP

SDA0,

SDA1

tHD;STA

tHD;DAT

tHIGH

tBUF

tLOW

SCL0,

SCL1

tSU;STO

tHD;STA

tSU;DAT

fSCL

tSU;STA

Document Number: 002-04696 Rev. *A

Page 81 of 105

MB95650L Series

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value*²

name

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

SCL clock “L”

width

SCL0,

SCL1

t_LOW

t_HIGH

(2  nm/2)t_MCLK 20

—

ns Master mode

SCL clock “H”

width

SCL0,

SCL1

(nm/2)t_MCLK 20

(nm/2)t_MCLK 20

ns Master mode

Master mode

Maximum value is

applied when m, n =

ns 1, 8.

SCL0,

SCL1,

SDA0,

SDA1

START

condition hold

time

t_HD;STA

(-1  nm/2)t_MCLK 20

(-1  nm)t_MCLK 20

Otherwise, the

minimum value is

applied.

SCL0,

SCL1,

STOPcondition

setup time

t_SU;STO

(1  nm/2)t_MCLK 20

(1  nm/2)t_MCLK 20

ns Master mode

SDA0, ^{R = 1.7 k},

SDA1 C = 50 pF*¹

SCL0,

SCL1,

SDA0,

SDA1

START

condition setup t_SU;STA

time

Bus free time

between STOP

condition and

START

condition

SCL0,

SCL1,

SDA0,

SDA1

t_BUF

(2 nm  4) t_MCLK 20

—

ns

SCL0,

SCL1,

SDA0,

SDA1

Data hold time t_HD;DAT

3 t_MCLK 20

ns Master mode

(Continued)

Document Number: 002-04696 Rev. *A

Page 82 of 105

MB95650L Series

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value*²

name

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

Master mode

It is assumed that “L”

of SCL is not

SCL0,

SCL1,

SDA0,

SDA1

extended. The

minimum value is

applied to the first bit

of continuous data.

Otherwise, the

maximum value is

applied.

Data setup time t_SU;DAT

(-2  nm/2) t_MCLK 20 (-1  nm/2) t_MCLK 20

ns

The minimum value

is applied to the

interrupt at the ninth

Setup time

between

clearing

interrupt and

SCL rising

SCL0,

SCL1

t_SU;INT

(nm/2) t_MCLK 20

(1  nm/2) t_MCLK 20

ns SCL. Themaximum

value is applied to

the interrupt at the

eighth SCL.

^{R = 1.7 k},

C = 50 pF*¹

SCL clock “L”

width

SCL0,

SCL1

t_LOW

t_HIGH

4 t_MCLK 20

—

ns At reception

SCL clock “H”

width

SCL0,

SCL1

ns At reception

SCL0,

SCL1,

SDA0,

SDA1

No START condition

is detected when

1 t_MCLKis used at

reception.

START

condition

detection

t_HD;STA

t_SU;STO

t_SU;STA

2 t_MCLK 20

—

ns

SCL0,

SCL1,

SDA0,

SDA1

NoSTOPconditionis

detected when

1 t_MCLKis used at

reception.

STOPcondition

detection

ns

RESTART

condition

detection

condition

SCL0,

SCL1,

SDA0,

SDA1

No RESTART

condition is detected

when 1 t_MCLKis used

at reception.

ns

(Continued)

Document Number: 002-04696 Rev. *A

Page 83 of 105

MB95650L Series

(Continued)

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value*²

name

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

SCL0,

SCL1,

SDA0,

SDA1

Bus free time

Data hold time

Data setup time

Data hold time

t_BUF

2 t_MCLK 20

—

ns At reception

SCL0,

SCL1,

SDA0,

SDA1

At slave transmission

mode

t_HD;DAT

t_SU;DAT

t_HD;DAT

t_SU;DAT

2 t_MCLK 20

t_LOW 3 t_MCLK 20

0

—

ns

SCL0,

SCL1,

SDA0,

SDA1

At slave transmission

mode

R = 1.7 k,

C = 50 pF*¹

SCL0,

SCL1,

SDA0,

SDA1

ns At reception

ns

SCL0,

SCL1,

SDA0,

SDA1

Data setup time

t_MCLK 20

SCL0,

SCL1,

SDA0,

SDA1

SDA  SCL

(with wakeup function t_WAKEUP

in use)

Oscillation stabilizationwait

time

2 t_MCLK 20

*1: R represents the pull-up resistor of the SCL0/SCL1 and SDA0/SDA1 lines, and C the load capacitor of the SCL0/SCL1 and

SDA0/SDA1 lines.

*2: • See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

• m represents the CS[4:3] bits in the I²C clock control register ch. 0/ch. 1 (ICCR0/ICCR1).

• n represents the CS[2:0] bits in the I²C clock control register ch. 0/ch. 1 (ICCR0/ICCR1).

• The actual timing of the I²C bus interface is determined by the values of m and n set by the machine clock (t_MCLK) and the

CS[4:0] bits in the ICCR0/ICCR1 register.

• Standard-mode:

m and n can be set to values in the following range: 0.9 MHz  t

(machine clock)  16.25 MHz.

MCLK

The usable frequencies of the machine clock are determined by the settings of m and n as shown below.

(m, n) = (1, 8)

: 0.9 MHz < t

 1 MHz

 2 MHz

 4 MHz

 10 MHz

 16.25 MHz

MCLK

(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)

(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)

(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)

(m, n) = (8, 22)

• Fast-mode:

m and n can be set to values in the following range: 3.3 MHz < t

(machine clock) < 16.25 MHz.

MCLK

The usable frequencies of the machine clock are determined by the settings of m and n as shown below.

(m, n) = (1, 8)

: 3.3 MHz < t

 4 MHz

 8 MHz

 10 MHz

 16.25 MHz

MCLK

(m, n) = (1, 22), (5, 4)

(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)

(m, n) = (5, 8)

Document Number: 002-04696 Rev. *A

Page 84 of 105

MB95650L Series

18.4.9 UART/SIO, Serial I/O Timing

(V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Min

4 t_MCLK

190

Max

—

Serial clock cycle time

UCK  UO time

t_SCYCUCK0

*

ns

t_SLOVUCK0, UO0

190

—

Internal clock operation

Valid UI  UCK 

t_IVSH

t_SHIX

UCK0, UI0

2 t_MCLK

4 t_MCLK

—

*

UCK  valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK  UO time

—

t_SHSLUCK0

—

t_SLSHUCK0

—

t_SLOVUCK0, UO0

External clock operation

190

—

Valid UI  UCK 

t_IVSH

t_SHIX

UCK0, UI0

2 t_MCLK

*

UCK  valid UI hold time

2 t_MCLK

—

*: See “18.4.2. Source Clock/Machine Clock” for t_MCLK

.

Internal shift clock mode

t

SCYC

0.8 VCC

UCK0

0.2 VCC

t

SLOV

0.8 VCC

0.2 VCC

UO0

UI0

t

IVSH

t

SHIX

0.7 VCC 0.7 VCC

0.3 VCC 0.3 VCC

External shift clock mode

tSLSH

t

SHSL

0.8 VCC

UCK0

0.2 VCC

t

SLOV

0.8 VCC

0.2 VCC

UO0

UI0

tIVSH

t

SHIX

0.7 VCC 0.7 VCC

0.3 VCC 0.3 VCC

Document Number: 002-04696 Rev. *A

Page 85 of 105

MB95650L Series

18.5 A/D Converter

18.5.1 A/D Converter Electrical Characteristics

(V_CC= 1.8 V to 5.5 V, V_SS= 0.0 V, T_A= 40 °C to 85 °C)

Value

Typ

—

Parameter

Resolution

Symbol

Unit

Remarks

Min

Max

—

6

12

bit

—

6

LSB V_CC 2.7 V

LSB V_CC 2.7 V

LSB V_CC 2.7 V

LSB V_CC 2.7 V

LSB V_CC 2.7 V

LSB V_CC 2.7 V

mV

Total error

10

—

10

—

3

—

3

5

Linearity error

5

—

1.9

—

1.9

Differential linearity error

Zero transition voltage

2.9

—

2.9

V_0T

V_FST

T_S

V_SS 6 LSB

—

V_SS 8.2 LSB

Full-scale transition

voltage

V_CC 6.2 LSB

—

V_CC 9.2 LSB

mV

Sampling time

*

—

10

14

µs

0.861

2.8

µs V_CC 2.7 V

µs V_CC 2.7 V

Compare time

T_cck

T_stt

Time of transiting to

operation enabled state

1

—

µs

Analog input current

Analog input voltage

I_AIN

0.3

—

0.3

µA

V

V_AIN

V_SS

V_CC

*: See “18.4.2. Notes on Using A/D Converter” for details of the minimum sampling time.

Document Number: 002-04696 Rev. *A

Page 86 of 105

MB95650L Series

18.5.2 Notes on Using A/D Converter

External impedance of analog input and its sampling time

The A/D converter of the MB95650L Series has a sample and hold circuit. If the external impedance is too high to keep sufficient

sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting

A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the

external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external

impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured,

connect a capacitor of about 0.1 µF to the analog input pin.

Analog input equivalent circuit

Comparator

Rext

Rin

Analog input pins

(AN00 to AN05)

Analog signal source

Cin

VCC

Rin

Cin

0.9 kΩ (Max)

1.6 kΩ (Max)

4.0 kΩ (Max)

4.5 V ≤ VCC ≤ 5.5 V

2.7 V ≤ VCC < 4.5 V

1.8 V ≤ VCC < 2.7 V

13 pF (Max)

Note: The values are reference values.

Relationship between external impedance and minimum sampling time

The sampling required varies according to external impedance. Ensure that the following condition is met when setting the sampling

time.

Ts  Rin + Rext  Cin  9

Ts

: Sampling time

Rin : Input resistance of A/D converter

Cin : Input capacitance of A/D converter

Rext : Output impedance of external circuit

A/D conversion error

As |V_CC V_SS| decreases, the A/D conversion error increases proportionately.

Document Number: 002-04696 Rev. *A

Page 87 of 105

MB95650L Series

18.5.3 Definitions of A/D Converter Terms

Resolution

It indicates the level of analog variation that can be distinguished by the A/D converter.

When the number of bits is 12, analog voltage can be divided into 2¹²= 4096.

Linearity error (unit: LSB)

It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point

(“000000000000”   “000000000001”) of a device to the full-scale transition point (“111111111111”   “111111111110”) of the same

device.

Differential linear error (unit: LSB)

It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value.

Total error (unit: LSB)

It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a

full-scale transition errors, a linearity error, a quantum error, or noise.

Ideal I/O characteristics

VFST

Total error

0xFFF

0xFFE

0xFFD

0xFFF

0xFFE

0xFFD

Actual conversion

characteristic

2 LSB

{1 LSB × (N − 1) + 0.5 LSB}

0x004

0x003

0x002

0x001

0x004

0x003

0x002

0x001

V0T

VNT

Actual conversion

characteristic

1 LSB

Ideal characteristic

0.5 LSB

VSS

Analog input

VCC

VSS

Analog input

VCC

VNT − {1 LSB × (N − 1) + 0.5 LSB}

VCC − VSS

4096

1 LSB =

V

Total error of digital output N =

LSB

1 LSB

N

: A/D converter digital output value

VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN

(Continued)

Document Number: 002-04696 Rev. *A

Page 88 of 105

MB95650L Series

(Continued)

Zero transition error

Full-scale transition error

0x004

Ideal characteristic

Actual conversion

characteristic

0xFFF

0xFFE

0xFFD

0xFFC

Actual conversion

characteristic

0x003

0x002

0x001

VFST

(measurement

value)

Actual conversion

Ideal

characteristic

Actual conversion

characteristic

V0T (measurement value)

Analog input

VSS

VCC

VSS

Analog input

VCC

Linearity error

Differential linearity error

Ideal characteristic

Actual conversion

characteristic

0xFFF

0xFFE

0xFFD

0x(N+1)

0xN

Actual conversion

characteristic

{1 LSB × N + V0T}

V(N+1)T

VFST

(measurement

value)

VNT

0x004

0x003

0x002

0x001

VNT

0x(N−1)

0x(N−2)

Actual conversion

characteristic

Ideal

Actual conversion

characteristic

V0T (measurement value)

Analog input

VSS

VCC

VSS

Analog input

VCC

VNT − {1 LSB × N + V0T}

Linearity error of digital output N =

1 LSB

V(N+1)T − VNT

Differential linearity error of digital output N =

: A/D converter digital output value

− 1

1 LSB

N

V^NT: Voltage at which the digital output transits from 0x(N − 1) to 0xN

V^0T(ideal value) = VSS + 0.5 LSB [V]

V^FST(ideal value) = VCC − 2 LSB [V]

Document Number: 002-04696 Rev. *A

Page 89 of 105

MB95650L Series

18.6 Flash Memory Program/Erase Characteristics

Value

Parameter

Unit

Remarks

Min

Typ

Max

Sector erase time

(2 Kbyte sector)

—

0.3*¹

1.6*²

s

The time of writing “0x00” prior to erasure is excluded.

Sector erase time

(32 Kbyte sector)

—

0.6*¹

3.1*²

Byte writing time

—

17

—

272

—

µs System-level overhead is excluded.

cycle

Program/erase cycle

100000

Power supply voltage at

program/erase

1.8

20*³

10*³

5*³

—

5.5

—

V

Average T_A= 85 °C

Number of program/erase cycles: 1000 or below

Flash memory data

retention time

Average T_A= 85 °C

Number of program/erase cycles: 1001 to 10000 inclusive

year

Average T_A= 85 °C

Number of program/erase cycles: 10001 or above

*1: V_CC= 5.5 V, T_A= 25 °C, 0 cycle

*2: V_CC= 1.8 V, T_A= 85 °C, 100000 cycles

*3: These values were converted from the result of a technology reliability assessment. (These values were converted from the result

of a high temperature accelerated test using the Arrhenius equation with the average temperature being 85 °C.)

Document Number: 002-04696 Rev. *A

Page 90 of 105

MB95650L Series

19. Sample Characteristics

Power supply current temperature characteristics

I_CC V_CC

I_CC T_A

T_A 25 C, F_MP 2, 4, 8, 10, 16 MHz (divided by 2)

V_CC 3.3V, F_MP 2, 4, 8, 10, 16 MHz (divided by 2)

Main clock mode with the external clock operating

10

FMP = 16 MHz

FMP = 10 MHz

FMP = 8 MHz

FMP = 16 MHz

FMP = 10 MHz

FMP = 8 MHz

FMP = 4 MHz

FMP = 2 MHz

FMP = 4 MHz

FMP = 2 MHz

8

6

4

2

0

8

6

4

2

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

I_CCS V_CC

I_CCS T_A

T_A 25 C, F_MP 2, 4, 8, 10, 16 MHz (divided by 2)

V_CC 3.3 V, F_MP 2, 4, 8, 10, 16 MHz (divided by 2)

Main sleep mode with the external clock operating

4

FMP = 16 MHz

FMP = 10 MHz

FMP = 8 MHz

FMP = 4 MHz

FMP = 16 MHz

FMP = 10 MHz

FMP = 8 MHz

FMP = 4 MHz

FMP = 2 MHz

3

2

1

0

2

1

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

I_CCL V_CC

I_CCL T_A

T_A 25 C, F_MPL 16 kHz (divided by 2)

V_CC 3.3 V, F_MPL 16 kHz (divided by 2)

Subclock mode with the external clock operating

140

120

100

80

140

120

100

80

60

40

20

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

(Continued)

Document Number: 002-04696 Rev. *A

Page 91 of 105

MB95650L Series

I_CCLS V_CC

I_CCLS T_A

V_CC 3.3 V, F_MPL 16 kHz (divided by 2)

Subsleep mode with the external clock operating

T_A 25 C, F_MPL 16 kHz (divided by 2)

Subsleep mode with the external clock operating

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

I_CCT V_CC

I_CCT T_A

T_A 25 C, F_MPL 16 kHz (divided by 2)

V_CC 3.3 V, F_MPL 16 kHz (divided by 2)

Watch mode with the external clock operating

5

4

3

2

1

0

5

4

3

2

1

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

I_CCTS V_CC

I_CCTS T_A

T_A 25 C, F_MP 2, 4, 8, 10, 16 MHz (divided by 2)

V_CC 3.3 V, F_MP 2, 4, 8, 10, 16 MHz (divided by 2)

Time-base timer mode with the external clock operating

600

FMP = 16 MHz

FMP = 10 MHz

FMP = 16 MHz

FMP = 10 MHz

FMP = 8 MHz

FMP = 4 MHz

FMP = 8 MHz

FMP = 4 MHz

500

FMP = 2 MHz

400

300

200

100

0

300

200

100

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

Document Number: 002-04696 Rev. *A

Page 92 of 105

MB95650L Series

I_CCH V_CC

I_CCH T_A

T_A 25 C, F_MPL (stop)

V_CC 3.3 V, F_MPL (stop)

Substop mode with the external clock stopping

5

4

3

2

1

0

5

4

3

2

1

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

I_CCMCR V_CC

I_CCMCR T_A

T_A 25 C, F_MP 4 MHz (no division)

V_CC 3.3 V, F_MP 4 MHz (no division)

Main CR clock mode

5

4

3

2

1

0

5

4

3

2

1

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

I_CCMCRPLL V_CC

I_CCMCRPLL T_A

V_CC 3.3 V, F_MP 16 MHz (PLL multiplication rate: 4)

T_A 25 C, F_MP 16 MHz (PLL multiplication rate: 4)

Main CR PLL clock mode

10

8

6

4

2

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

(Continued)

Document Number: 002-04696 Rev. *A

Page 93 of 105

MB95650L Series

(Continued)

I_CCMPLL V_CC

I_CCMPLL T_A

T_A 25 C, F_MP 16 MHz (PLL multiplication rate: 4)

V_CC 3.3 V, F_MP 16 MHz (PLL multiplication rate: 4)

Main PLL clock mode

10

8

6

4

2

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

I_CCSCR V_CC

I_CCSCR T_A

V_CC 3.3 V, F_MPL 50 kHz (divided by 2)

T_A 25 C, F_MPL 50 kHz (divided by 2)

Sub-CR clock mode

200

150

100

50

200

150

100

50

0

1

2

3

4

5

6

7

−50

0

+50

+100

+150

VCC[V]

T^A[°C]

Document Number: 002-04696 Rev. *A

Page 94 of 105

MB95650L Series

Input voltage characteristics

V_IHI1 V_CCand V_ILI V_CC

V_IHI2 V_CCand V_ILI V_CC

T_A 25 C

5

4

3

2

1

0

5

4

3

2

1

0

VIHI1

VILI

VIHI2

VILI

1

2

3

4

5

6

1

2

3

4

5

6

VCC[V]

V_IHS V_CCand V_ILS V_CC

T_A 25 C

V_IHM V_CCand V_ILM V_CC

T_A 25 C

5

4

3

2

1

0

5

4

3

2

1

0

VIHS

VILS

VIHM

VILM

1

2

3

4

5

6

1

2

3

4

5

6

VCC[V]

Document Number: 002-04696 Rev. *A

Page 95 of 105

MB95650L Series

Output voltage characteristics

(V_CC V_OH1)  I_OH

(V_CC V_OH2)  I_OH

T_A 25 C

1.0

0.8

0.6

0.4

0.2

0.0

1.0

0.8

0.6

0.4

0.2

0.0

0

−1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15

0

−1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15

IOH[mA]

VCC = 1.8 V

VCC = 2.0 V

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.6 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

VCC = 1.8 V

VCC = 2.0 V

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.6 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

V_OL1 I_OL

V_OL2 I_OL

T_A 25 C

1.0

0.8

0.6

0.4

0.2

0.0

0.8

0.6

0.4

0.2

0.0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

IOL[mA]

VCC = 1.8 V

VCC = 2.0 V

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.6 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

VCC = 1.8 V

VCC = 2.0 V

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.6 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

Document Number: 002-04696 Rev. *A

Page 96 of 105

MB95650L Series

Pull-up characteristics

R_PULL V_CC

T_A 25 C

300

250

200

150

100

50

0

1

2

3

4

5

6

VCC[V]

Document Number: 002-04696 Rev. *A

Page 97 of 105

MB95650L Series

20. Mask Options

MB95F652E

MB95F653E

MB95F654E

MB95F656E

MB95F652L

MB95F653L

MB95F654L

MB95F656L

Part number

No.

Selectable/Fixed

Fixed

Without low-voltage detection

1

2

Low-voltage detection reset/interrupt With low-voltage detection reset/interrupt

reset/interrupt

Reset

Without dedicated reset input

With dedicated reset input

Document Number: 002-04696 Rev. *A

Page 98 of 105

MB95650L Series

21. Ordering Information

Part number

Package

MB95F652EPFT-G-SNE2

MB95F652LPFT-G-SNE2

MB95F653EPFT-G-SNE2

MB95F653LPFT-G-SNE2

MB95F654EPFT-G-SNE2

MB95F654LPFT-G-SNE2

MB95F656EPFT-G-SNE2

MB95F656LPFT-G-SNE2

24-pin plastic TSSOP

(FPT-24P-M10)

MB95F652EPF-G-SNE2

MB95F652LPF-G-SNE2

MB95F653EPF-G-SNE2

MB95F653LPF-G-SNE2

MB95F654EPF-G-SNE2

MB95F654LPF-G-SNE2

MB95F656EPF-G-SNE2

MB95F656LPF-G-SNE2

24-pin plastic SOP

(FPT-24P-M34)

MB95F652EWQN-G-SNE1

MB95F652EWQN-G-SNERE1

MB95F652LWQN-G-SNE1

MB95F652LWQN-G-SNERE1

MB95F653EWQN-G-SNE1

MB95F653EWQN-G-SNERE1

MB95F653LWQN-G-SNE1

MB95F653LWQN-G-SNERE1

MB95F654EWQN-G-SNE1

MB95F654EWQN-G-SNERE1

MB95F654LWQN-G-SNE1

MB95F654LWQN-G-SNERE1

MB95F656EWQN-G-SNE1

MB95F656EWQN-G-SNERE1

MB95F656LWQN-G-SNE1

MB95F656LWQN-G-SNERE1

32-pin plastic QFN

(LCC-32P-M19)

Document Number: 002-04696 Rev. *A

Page 99 of 105

MB95650L Series

22. Package Dimension

24-pin plastic TSSOP

Lead pitch

0.65 mm

4.40 mm × 7.80 mm

Gullwing

Package width

package length

×

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.20 mm MAX

0.10 g

(FPT-24P-M10)

24-pin plastic TSSOP

Note 1) Pins width and pins thickness include plating thickness.

Note 2) Pins width do not include tie bar cutting remainder.

Note 3) #: These dimensions do not include resin protrusion.

(FPT-24P-M10)

#

+0.06

–0.03

7.80 0.10(.307 .004)

0.13

+.002

–.001

.005

24

13

BTM E-MARK

#

4.40 0.10

(.173 .004)

INDEX

Details of "A" part

6.40 0.20

(.252 .008)

1.20(.047)

(Mounting height)

MAX

0~8°

"A"

1

12

+0.07

0.65(.026)

0.22 ^–0.02

0.10(.004)

+.003

.008

–.001

0.10 0.05

(.004 .002)

0.60 0.15

(Stand off)

(.024 .006)

0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2008-2010 FUJITSU SEMICONDUCTOR LIMITED F24033S-c-1-2

(Continued)

Document Number: 002-04696 Rev. *A

Page 100 of 105

MB95650L Series

24-pin plastic SOP

Lead pitch

1.27 mm

7.50 mm × 15.34 mm

Gullwing

Package width ×

package length

Lead shape

Lead bend

direction

Normal bend

Plastic mold

2.80 mm MAX

0.44 g

Sealing method

Mounting height

Weight

(FPT-24P-M34)

24-pin plastic SOP

(FPT-24P-M34)

Note 1) * : These dimensions do not include resin protrusion.

*15.34 0.10(.604 .004)

0.27 0.07

(.011 .003)

24

13

10.20 0.40

(.402 .016)

INDEX ø1.20 0.1 DEP0.20 ⁺^–0⁰^.^.⁰¹⁵⁰

ø.047 .004 DEP.008 ⁺^–.^.⁰⁰⁰⁰²⁴

7.50 0.10

(.295 .004)

Details of "A" part

+0.20

2.60

–0.25

+.008

.102 ^–.010

0.25(.010)

0~8°

1

12

"A"

1.27(.050)

0.42 0.07

(.017 .003)

M

0.25(.010)

0.60 0.20

(.024 .008)

0.15 ⁺^–0⁰.^.1¹0⁵

+.006

.006

–.004

0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2009-2010 FUJITSU SEMICONDUCTOR LIMITED F24034S-c-1-2

(Continued)

Document Number: 002-04696 Rev. *A

Page 101 of 105

MB95650L Series

(Continued)

32-pin plastic QFN

Lead pitch

0.50 mm

5.00 mm × 5.00 mm

Plastic mold

Package width ×

package length

Sealing method

Mounting height

Weight

0.80 mm MAX

0.06 g

(LCC-32P-M19)

32-pin plastic QFN

(LCC-32P-M19)

3.50 0.10

(.138 .004)

5.00 0.10

(.197 .004)

3.50 0.10

(.138 .004)

5.00 0.10

(.197 .004)

+0.05

0.25 ^–0.07

+.002

INDEX AREA

(.010

)

–.003

(3-R0.20)

((3-R.008))

0.40 0.05

(.016 .002)

1PIN CORNER

0.50(.020)

(TYP)

(C0.30(C.012))

0.75 0.05

(.030 .002)

+0.03

0.02 ^–0.02

+.001

(0.20(.008))

(.001

)

–.001

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2

Document Number: 002-04696 Rev. *A

Page 102 of 105

MB95650L Series

23. Major Changes

Spansion Publication Number: DS702–00016–3v0-E

Page

Section

Details

Corrected the following statement.

The bypass capacitor for the V_CCpin must have a capacitance

Pin Connection

• C pin

larger than C_S.

19



The decoupling capacitor for the V_CCpin must have a capacitance

equal to or larger than the capacitance of C_S.

Electrical Characteristics

4. AC Characteristics

(1) Clock Timing

Corrected the pin name of the parameter “Input clock rising time

and falling time”.

X0  X0, X0A

64

NOTE: Please see “Document History” about later revised information.

Document Number: 002-04696 Rev. *A

Page 103 of 105

MB95650L Series

Document History

Document Title: MB95650L Series New 8FX 8-bit Microcontrollers

Document Number: 002-04696

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

—

AKIH

06/14/2013 Migrated to Cypress and assigned document number 002-04696.

No change to document contents or format.

*A

5216808

AKIH

04/12/2016 Updated to Cypress format.

Document Number: 002-04696 Rev. *A

Page 104 of 105

MB95650L Series

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Lighting & Power Control

Memory

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United

States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-04696 Rev. *A

Revised April 12, 2016

Page 105 of 105


型号：	FPT-24P-M34
厂家：	CYPRESS
描述：	F2MC-8FX CPU core
文件：	总105页 (文件大小：12176K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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