GVT71512C18TA-5I [CYPRESS]
Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | GVT71512C18TA-5I |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总29页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K x 36/512K x 18 Synchronous
Pipelined SRAM
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
Features
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x
18 SRAM cells with advanced synchronous peripheral circuitry
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
and
a 2-bit counter for internal burst operation. All
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150
MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for performance (two cycle chip deselect,
depth expansion without wait state)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE3), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW). However, the CE3 Chip Enable input is only available
for the TA(GVTI)/A(CY) package version.
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down feature available using ZZ
mode or CE select.
• JTAG boundary scan for B/BG and T/AJ package
version
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide, as controlled by the write control inputs.
Individual byte write allows an individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc.
BWd controls DQd. BWa, BWb, BWc, and BWd can be active
only with BWE being LOW. GW being LOW causes all bytes
to be written. The x18 version only has 18 data inputs/outputs
(DQa and DQb) along with BWa and BWb (no BWc, BWd,
DQc, and DQd).
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package
versions, four pins are used to implement JTAG test capabil-
ities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock
(TCK), and Test Data-Out (TDO). The JTAG circuitry is used
to serially shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode
of operation. The TA package version does not offer the JTAG
capability.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Selection Guide
7C1366A-225/
71256C36-4.4
7C1367A-225/
71512C18-4.4
7C1366A-200/
71256C36-5
7C1367A-200/
71512C18-5
7C1366A-166/
71256C36-6
7C1367A-166/
71512C18-6
7C1366A-150/
71256C36-6.7
7C1367A-150/
71512C18-6.7
Unit
ns
Maximum Access Time
2.5
570
10
3.0
510
10
3.5
425
10
3.5
380
10
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05264 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 17, 2003
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Functional Block Diagram—256K x 36[1, 2]
B Y TE
a
b
c
d
W R ITE
BW
a
D
Q
BWE
CLK
B Y TE
W RITE
BW
b
D
Q
GW
B Y TE
W R ITE
BW
c
D
Q
B Y TE
W RITE
BW
d
D
Q
CE
EN A B LE
1
D
Q
D
Q
CE
2
CE
3
OE
ZZ
Pow er D ow n Logic
Input
R egister
ADSP
16
A
A ddress
R egister
O U TPU T
R EG ISTER
ADSC
DQa,DQb,
DQc,DQd
C LR
D
Q
ADV
B inary
C ounter
A0-A1
&
Logic
MODE
Functional Block Diagram—512K x 18[1]
BYTE b
WRITE
BW
b
D
D
Q
BWE
CLK
BYTE a
WRITE
BW
a
Q
GW
ENABLE
CE
1
CE
D
Q
D
Q
2
CE
3
ZZ
Power Down Logic
OE
ADSP
Input
Register
17
A
Address
Register
OUTPUT
REGISTER
ADSC
DQa, DQb,
CLR
D
Q
ADV
Binary
Counter
& Logic
A0-A1
MODE
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See the Truth Table, pin descriptions, and timing diagrams for detailed information.
2. CE3 is for the TA version only.
Document #: 38-05264 Rev. *A
Page 2 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Pin Configurations
CY7C1366A/GVT71256C36
256Kx 36 100-pin TQFP
Top View
DQc
DQc
DQc
DQc
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
DQb
DQb
DQb
DQb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
3
4
5
6
7
8
9
V
CCQ
V
V
V
CCQ
V
CCQ
CCQ
V
V
SS
SS
V
SS
SS
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQc
V
V
SS
V
SS
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
SS
V
V
DQc
DQc
NC
V
CCQ
V
CCQ
V
CCQ
CCQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
V
V
SS
SS
V
CC
NC
CC
NC
NC
100-pin TQFP
NC
V
V
100-pin TQFP
TA Package Version
CC
CC
V
V
SS
SS
ZZ
DQa
DQa
17
64
ZZ
DQa
DQd
DQd
V
CCQ
DQd
DQd
T Package Version
18
19
20
21
22
23
24
25
26
63
62
61
60
59
58
57
56
55
DQa
V
V
V
CCQ
CCQ
CCQ
V
V
SS
V
SS
V
SS
SS
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQd
V
V
SS
V
SS
V
SS
SS
V
V
CCQ
DQd
DQd
DQd
V
CCQ
V
27
28
29
30
54
53
52
51
CCQ
CCQ
DQd
DQd
DQd
DQa
DQa
DQa
DQa
DQa
DQa
CY7C1367A/GVT71512C18
512K x 18 100- pin TQFP
Top View
NC
1
A
NC
80
NC
A
1
80
79
NC
NC
2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
2
3
4
NC
NC
NC
V
3
4
5
6
7
8
9
78
77
V
CCQ
CCQ
V CCQ
V SS
V CCQ
V SS
NC
V
SS
V
SS
5
6
76
75
NC
NC
DQb
DQb
NC
NC
NC
DPa
DQa
DQa
7
8
74
73
DPa
DQa
DQb
DQb
DQa
V SS
9
10
72
71
V
SS
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V SS
V CCQ
DQb
V
CCQ
V
CCQ
11
12
70
69
V CCQ
DQa
DQb
DQb
NC
DQa
DQa
DQb
NC
DQa
V SS
NC
13
14
68
67
V
SS
V
CC
100-pin TQFP
NC
V CC
NC
15
16
66
65
100-pin TQFP
NC
V
CC
V CC
ZZ
V
SS
TA Package Version
ZZ
DQa
DQa
V SS
17
18
64
63
DQb
DQb
T Package Version
DQb
DQb
DQa
19
20
62
61
DQa
V CCQ
V SS
DQa
V
V
CCQ
CCQ
V CCQ
V SS
V
SS
V
SS
21
22
60
59
DQb
DQb
DQb
NC
DQa
DQa
NC
DQb
DQb
23
24
58
57
DQa
NC
DQb
NC
NC
NC
25
26
56
55
V
SS
V
SS
V SS
V CCQ
NC
NC
NC
V SS
V
CCQ
NC
NC
NC
V
CCQ
27
28
54
53
V DDQ
NC
NC
NC
NC
NC
NC
29
30
52
51
Document #: 38-05264 Rev. *A
Page 3 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Pin Configurations (continued)
CY7C1366A/GVT71256C36
256K x 36 119-ball BGA
Top View
256Kx36
1
2
3
A
4
ADSP
ADSC
VCC
NC
5
6
7
A
B
C
D
E
F
VCCQ
A
A
A
VCCQ
NC
NC
NC
CE2
A
A
A
A
A
A
A
NC
DQc
DQc
VCCQ
DQc
DQc
VCCQ
DQd
DQd
VCCQ
DQd
DQd
NC
DQc
DQc
DQc
DQc
DQc
VCC
DQd
DQd
DQd
DQd
DQd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQb
DQb
DQb
DQb
DQb
VCC
DQa
DQa
DQa
DQa
DQa
A
DQb
DQb
VCCQ
DQb
DQb
VCCQ
DQa
DQa
VCCQ
DQa
DQa
NC
CE1
OE
G
H
J
ADV
GW
VCC
CLK
NC
K
L
VSS
BWd
VSS
VSS
VSS
MODE
A
M
N
P
R
T
BWE
A1
A0
VCC
A
NC
NC
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1367A/GVT71512C18 512Kx18 119-Ball BGA
Top View
1
2
3
A
4
ADSP
ADSC
VCC
NC
5
6
7
A
B
C
D
E
F
VCCQ
NC
A
A
A
VCCQ
NC
CE2
A
A
A
CE3
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VCC
DQb
NC
DQb
NC
DQb
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQa
NC
DQa
NC
DQa
VCC
NC
DQa
NC
DQa
NC
A
NC
CE1
OE
DQa
VCCQ
DQa
NC
VCCQ
NC
G
H
J
ADV
GW
VCC
CLK
NC
DQb
VCCQ
NC
VCCQ
DQa
NC
K
L
DQb
VCCQ
DQb
NC
M
N
P
R
T
BWE
A1
VCCQ
NC
A0
DQa
NC
NC
VCC
NC
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05264 Rev. *A
Page 4 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K × 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the set
Synchronous up and hold times around the rising edge of CLK. The burst
countergeneratesinternaladdressesassociatedwithA0andA1,
during burst cycle and wait cycle.
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32,
5B, 6B, 2C, 3C, 5C, 100, 99, 82, 81,
6C, 2R, 6R, 3T, 4T, 44, 45, 46, 47, 48,
5T
49, 50
92 (T/AJ Version)
43 (TA/A Version)
5L
5G
3G
3L
93
94
95
96
BWa
Input-
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for
BWb Synchronous a READ cycle. BWa controls DQa. BWb controls DQb. BWc
BWc
BWd
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
4K
87
88
89
BWE
GW
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge
of CLK.
Input-
Global Write: This active LOW input allows a full 36-bit Write to
Synchronous occur independent of the BWE and BWn lines and must meet the
set-up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control, and burst control inputs on its rising edge. All
synchronous inputs must meet set up and hold times around the
clock’s rising edge.
4E
2B
98
97
CE1
CE2
CE3
OE
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
Input-
Synchronous device.
Chip Enable: This active HIGH input is used to enable the
(not available for
PBGA)
92 (for TA/A
Version only)
Input-
Chip Enable:This activeLOWinput is used toenable the device.
Synchronous Not available for B and T package versions.
4F
86
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be registered
and a READ cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes
Synchronous device to be deselected or selected along with new external
address to be registered. A Read or Write cycle is initiated
depending upon write control inputs.
3R
7T
31
64
MOD
E
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin
selects LinearBurst. ANC orHIGH onthis pinselects Interleaved
Burst.
ZZ
Input-
Sleep: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
(a) 6P, 7P, 7N, 6N, (a) 51, 52, 53, 56, DQa
6M, 6L, 7L, 6K, 7K, 57, 58, 59, 62, 63 DQb
(b) 7H, 6H, 7G, 6G, (b) 68, 69, 72, 73, DQc
6F, 6E, 7E, 7D, 6D, 74, 75, 78, 79, 80 DQd
(c) 2D, 1D, 1E, 2E, (c) 1, 2, 3, 6, 7, 8,
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
2F, 1G, 2G, 1H, 2H,
9, 12, 13
(d) 1K, 2K, 1L, 2L, (d) 18, 19, 22, 23,
2M, 1N, 2N, 1P, 2P 24, 25, 28, 29, 30
Document #: 38-05264 Rev. *A
Page 5 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K × 36 Pin Descriptions (continued)
X36 PBGA Pins
X36 QFP Pins Name
Type
Description
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not available for
TA/A package version.
for BG/B and
T/AJ
version
5U
42
for BG/B and
T/AJ
TDO Output Power IEEE 1149.1 Test Output: LVTTL-level output. Not available for
TA/A package version.
version
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC Power Supply Core Power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26, VSS
5F, 3H, 5H, 3K, 5K, 40, 55, 60, 67, 71,
Ground
Ground: GND.
3M,5M,3N,5N,3P,
5P
76, 90
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54, VCCQ
I/O Power Power supply for the circuitry.
Supply
7J, 1M, 7M, 1U, 7U
61, 70, 77
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
14, 16, 66
NC
–
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS
.
38, 39, 42 for
TA/A Version
512K × 18 Pin Descriptions
X18 PBGA Pins
X18 QFP Pins Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the
Synchronous set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32,
5B, 6B, 2C, 3C, 5C, 100, 99, 82, 81,
6C, 2R, 6R, 2T, 3T, 80, 48, 47, 46, 45,
5T, 6T
44, 49, 50
92 (T/AJ Version)
43 (TA/A Version)
5L
3G
93
94
BWa
BWb
Input-
Byte Write Enables: A byte write enable is LOW for a WRITE
Synchronous cycle and HIGH for a READ cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
4M
4H
4K
87
88
89
BWE
GW
Input-
Write Enable: This active LOW input gates byte write opera-
Synchronous tions and must meet the set up and hold times around the rising
edge of CLK.
Input-
Global Write: This active LOW input allows a full 18-bit WRITE
Synchronous to occur independent of the BWE and WEn lines and mustmeet
the set up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All
synchronous inputsmust meet setup and holdtimes aroundthe
clock’s rising edge.
4E
2B
98
97
CE1
CE2
CE3
OE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
Input-
Synchronous device.
Chip Enable: This active HIGH input is used to enable the
(not available for
PBGA)
92 (for TA/A
Version only)
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device. Not available for B/BG and T/AJ package versions.
4F
86
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Document #: 38-05264 Rev. *A
Page 6 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
512K × 18 Pin Descriptions (continued)
X18 PBGA Pins
X18 QFP Pins Name
Type
Description
4G
83
84
85
ADV
ADSP
ADSC
Input-
Address Advance: This active LOW input is used to control
Synchronous the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
4A
4B
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes anew externaladdress tobe registered
and a Read cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes
Synchronous device to be deselected or selected along with new external
address to be registered. A Read or Write cycle is initiated
depending upon write control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects Inter-
linear Burst.
Input-
Sleep: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
(a) 6D, 7E, 6F, 7G, (a) 58, 59, 62, 63, DQa
6H, 7K, 6L, 6N, 7P 68, 69, 72, 73, 74 DQb
(b) 1D, 2E, 2G, 1H, (b) 8, 9, 12, 13,
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb.
Input data must meet set up and hold times around the rising
edge of CLK.
2K, 1L, 2M, 1N, 2P 18, 19, 22, 23, 24
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not available for
TA/A package version.
for B/BG and
T/AJ
version
5U
42
for B/BG and
T/AJ
TDO Power Output IEEE 1149.1 Test Output: LVTTL-level output. Not available
for TA/A package version.
version
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
VSS
Power Supply Core Power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26,
5F, 5G, 3H, 5H, 3K, 40, 55, 60, 67, 71,
Ground
Ground: GND.
5K,3L,3M, 5M,3N,
5N, 3P, 5P
76, 90
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54, VCCQ
7J, 1M, 7M, 1U, 7U 61, 70, 77
I/O Power
Supply
Output Buffer Supply: +2.5V or +3.3V.
1B, 7B, 1C, 7C, 2D, 1-3, 6, 7, 14, 16,
4D, 7D, 1E, 6E, 2F, 25, 28-30, 51-53,
1G, 6G, 2H, 7H, 3J, 56, 57, 66, 75, 78,
NC
-
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS
.
5J, 1K, 6K, 2L, 4L,
7L, 6M, 2N, 7N, 1P,
79, 80, 95, 96
6P, 1R, 5R, 7R, 1T, 38, 39, 42 for TA
4T, 6U Version
Document #: 38-05264 Rev. *A
Page 7 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 4.5 ns
(150-MHz device).
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx
signals. The CY7C1366/CY7C1367A provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWa,b,c,d for CY7C1366 and BWa,b for
CY7C1367A) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The CY7C1366A/CY7C1367A supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Because the CY7C1366/CY7C1367A is a common I/O device,
the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for 1366B and BWa,b
for 1367B) inputs. A Global Write Enable (GW) overrides all
byte write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self-timed write circuitry.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a global write is conducted, the
data presented to the DQ[x:0] is written into the corresponding
address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 4.5 ns (150-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Because the CY7C1366/CY7C1367B is a common I/O device,
the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ[x:0] inputs. Doing so will three-state
the output drivers. As a safety precaution, DQ[x:0] are automat-
ically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1366B/CY7C1367B are double-cycle deselect
parts. Once the SRAM is deselected at clock rise by the chip
select and either ADSP or ADSC signals, its output will
three-state immediately after the next clock rise.
The
CY7C1366/GVT71256C36
provides
a
two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel® Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
Document #: 38-05264 Rev. *A
Page 8 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
X
L
L
L
H
H
L
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
External
L
X
X
L
External
External
External
External
Next
L
L
L
H
X
L
High-Z
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
WRITE Cycle, Continue Burst Next
WRITE Cycle, Continue Burst Next
L
L
L
D
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
Current
H
H
H
H
H
H
H
H
H
H
L
Q
Current
Current
Current
H
L
High-Z
Q
H
X
X
High-Z
D
WRITE Cycle, Suspend Burst Current
WRITE Cycle, Suspend Burst Current
L
D
Partial Truth Table for READ/WRITE[10]
Function (1366)
GW
1
BWE
BWa
BWb
BWc
BWd
Read
Read
1
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
0
X
1
1
1
1
0
0
0
0
1
X
1
1
0
0
1
1
0
0
1
X
1
1
1
0
1
0
1
0
1
1
Write Byte 0 – DQa
Write Byte 0 – DQb
Write Byte 1, 0
1
1
1
Write Byte 2 – DQc
Write Byte 2, 0
1
1
Write Byte 2, 1
1
Write Byte 2, 1, 0
Write Byte 3 – DQd
1
1
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
5. All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.
7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
10. For the X18 product, There are only BWa and BWb.
Document #: 38-05264 Rev. *A
Page 9 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Partial Truth Table for READ/WRITE[10] (continued)
Function (1366)
Write Byte 3, 0
GW
1
BWE
BWa
BWb
BWc
BWd
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
X
1
1
1
0
0
0
0
X
1
0
0
1
1
0
0
X
0
1
0
1
0
1
0
X
Write Byte 3, 1
Write Byte 3, 1, 0
Write Byte 3, 2
Write Byte 3, 2, 0
Write Byte 3, 2, 1
Write All Byte
1
1
1
1
1
1
Write All Byte
0
Function (1367)
GW
1
BWE
BWb
BWa
Read
1
0
0
0
0
X
X
1
1
0
0
X
x
1
0
1
0
X
Read
1
Write Byte 0 – DQ [7:0] and DP0
Write Byte 0 – DQ [15:8] and DP1
Write All Byte
1
1
1
Write All Byte
0
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
Clock cycles are required to enter into or exit from this “sleep”
mode.
While in this mode, data integrity is guarantee. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep”
mode.CEs,ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ inputs returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode stand-by current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
Min.
Max
10
Unit
mA
ns
IDDZZ
tZZS
2 tcyc
tZZREC
2 tcyc
ns
Disabling the JTAG Feature
IEEE 1149.1 Serial Boundary Scan (JTAG)
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Never-
theless, the device supports the standard TAP controller archi-
tecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/ LVCMOS logic level signaling.
Test Access Port (TAP)
TCK – Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Document #: 38-05264 Rev. *A
Page 10 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
TMS – Test Mode Select (INPUT)
Bypass Register
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
TDI – Test Data In (INPUT)
Boundary Scan Register
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register see Figure 1. It is allowable to leave this pin uncon-
nected if it is not used in an application. The pin is pulled up
internally, resulting in a logic HIGH level. TDI is connected to
the Most Significant Bit (MSB) of any register (see Figure 2).
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the
control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
TDO – Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed
between TDI and TDO. TDO is connected to the Least Signif-
icant Bit (LSB) of any register (see Figure 2).
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name, the third column is the
TQFP pin number, and the fourth column is the BGA bump
number.
Performing a TAP Reset
Identification (ID) Register
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
performed for the TAP controller by forcing TMS HIGH (VCC
)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
TAP Controller Instruction Set
Overview
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows IEEE 1149.1
conventions, it is not IEEE 1149.1-compliant because some of
the mandatory instructions are not fully implemented. The TAP
on this device may be used to monitor all input and I/O pads,
but can not be used to load address, data, or control signals
into the device or to preload the I/O buffers. In other words, the
device will not perform IEEE 1149.1 EXTEST, INTEST, or the
preload portion of the SAMPLE/PRELOAD command.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
Document #: 38-05264 Rev. *A
Page 11 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
EXTEST
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not imple-
mented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1-mandatory
instruction. The PRELOAD portion of the command is not
implemented in this device, so the device TAP controller is not
fully IEEE 1149.1-compliant.
Reserved
Do not use these instructions. They are reserved for future
use.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
Document #: 38-05264 Rev. *A
Page 12 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
TEST-LOGIC
RESET
1
0
0
1
1
1
REUN-TEST/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Figure 1. TAP Controller State Diagram[11]
Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05264 Rev. *A
Page 13 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
TDO
2
1
0
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register[12]
TDI
TDI
TAP Controller
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
2.0
Max.
VCC + 0.3
0.8
Unit
V
VIH
VIl
Input High (Logic 1) Voltage[13, 14]
Input Low (Logic 0) Voltage[13, 14]
Input Leakage Current
–0.3
–5.0
–30
–5.0
V
ILI
0V < VIN < VCC
5.0
µA
µA
µA
ILI
TMS and TDI Input Leakage Current 0V < VIN < VCC
30
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
5.0
VOLC
VOHC
VOLT
LVCMOS Output Low Voltage[13, 15] IOLC = 100 µA
LVCMOS Output High Voltage[13, 15] IOHC = 100 µA
0.2
0.4
V
V
V
V
VCC – 0.2
2.4
LVTTL Output Low Voltage[13]
IOLT = 8.0 mA
IOHT = 8.0 mA
VOHT
LVTTL Output High Voltage[13]
Notes:
12. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
13. All voltage referenced to VSS (GND).
14. Overshoot: VIH(AC) < VCC+1.5V for t<tKHKH/2; undershoot: VIL(AC) < –0.5V for t < tKHKH/2; power-up: VIH < 3.6V and VCC < 3.135V and VCCQ < 1.4V for
t < 200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD) may not have pulse widths less than tKHKL (min.).
15. This parameter is sampled.
Document #: 38-05264 Rev. *A
Page 14 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
TAP AC Switching Characteristics Over the Operating Range[16, 17]
Parameter
Clock
tTHTH
Description
Min.
Max
Unit
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
fTF
50
tTHTL
8
8
tTLTH
ns
Output Times
tTLQX
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
tTLQV
10
tDVTH
5
5
tTHDX
Set-up Times
tMVTH
TMS Set-up
TDI Set-up
5
5
5
ns
ns
ns
tTDIS
tCS
Capture Set-up
Hold Times
tTHMX
TMS Hold
TDI Hold
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold
TAP Timing and Test Conditions
ALL INPUT PULSES
1.5V
TDO
3.0V
50Ω
Z =
50Ω
20 pF
0
V
SS
Vt = 1.5V
1.5 ns
1.5 ns
(b)
(a)
t
t
THTL
TLTH
t
THTH
TEST CLOCK
(TCK)
t
t
MVTH
THMX
TEST MODE SELECT
(TMS)
t
t
DVTH
THDX
TEST DATA IN
(TDI)
t
TLQV
t
TLQX
TEST DATA OUT
(TDO)
Notes:
16.
tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions.
Document #: 38-05264 Rev. *A
Page 15 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
256K x 36
512K x 18
XXXX
Description
XXXX
00110
Reserved for revision number.
00111
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
Reserved for future use.
Device Width (22:18)
00100
00011
Reserved (17:12)
XXXXXX
00011100100
1
XXXXXX
00011100100
1
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size (x36)
Bit Size (x18)
3
1
3
1
ID
32
70
32
51
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant.
IDCODE
001 Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction
does not affect device operations.
SAMPLE-Z
010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
device outputs to High-Z state.
RESERVED
011 Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction does not affect device operations. This instruction does not implement IEEE 1149.1
PRELOAD function and is therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101 Do not use these instructions; they are reserved for future use.
110 Do not use these instructions; they are reserved for future use.
111 Places the bypass register between TDI and TDO. This instruction does not affect device opera-
tions.
Document #: 38-05264 Rev. *A
Page 16 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Boundary Scan Order (256K × 36) (continued)
Boundary Scan Order (256K × 36)
Bit#
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Signal Name
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
TQFP
1
Bump ID
2D
1E
Bit#
1
Signal Name
A
TQFP
44
45
46
47
48
49
50
51
52
53
56
57
58
59
62
63
64
68
69
72
73
74
75
78
79
80
81
82
83
84
85
86
87
88
89
92
93
94
95
96
97
98
99
100
Bump ID
2R
3T
2
2
A
3
2F
3
A
4T
6
1G
2H
1D
2E
4
A
5T
7
5
A
6R
3B
5B
6P
7N
6M
7L
8
6
A
9
7
A
12
13
14
18
19
22
23
24
25
28
29
30
31
32
33
34
35
36
37
2G
1H
5R
2K
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
1L
6K
7P
6N
6L
2M
1N
2P
1K
7K
7T
2L
2N
1P
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
6H
7G
6F
3R
2C
3C
5C
6C
4N
4P
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
A
A
A
A1
A0
Boundary Scan Order (512K × 18)
A
Bit#
1
Signal Name
TQFP
44
45
46
47
48
49
50
58
59
62
63
64
68
69
72
Bump ID
2R
2T
ADV
ADSP
ADSC
OE
A
A
2
3
A
3T
4
A
5T
BWE
GW
CLK
A
4M
4H
4K
6B
5L
5
A
6R
3B
6
A
7
A
5B
8
DQa
DQa
DQa
DQa
ZZ
7P
BWa
BWb
BWc
BWd
CE2
CE1
A
9
6N
6L
5G
3G
3L
10
11
12
13
14
15
7K
7T
2B
4E
3A
2A
DQa
DQa
DQa
6H
7G
6F
A
Document #: 38-05264 Rev. *A
Page 17 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Boundary Scan Order (512K × 18) (continued)
Bit#
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal Name
DQa
DQa
A
TQFP
73
74
80
81
82
83
84
85
86
87
88
89
92
93
94
97
98
99
100
8
Bump ID
7E
6D
6T
A
6A
5A
4G
4A
4B
4F
A
ADV
ADSP
ADSC
OE
BWE
GW
CLK
A
4M
4H
4K
6B
5L
BWa
BWb
CE2
CE1
A
3G
2B
4E
3A
2A
1D
2E
2G
1H
5R
2K
1L
A
DQb
DQb
DQb
DQb
NC
9
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
DQb
DQb
DQb
DQb
DQb
MODE
A
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
A
A
A
A1
A0
Document #: 38-05264 Rev. *A
Page 18 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Short Circuit Output Current........................................ 50 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current..................................................... >200 mA
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
VIN ................................................................... –0.5V to 5.5V
Storage Temperature (plastic) ...................... –55°C to +150°
Junction Temperature ..................................................+150°
Power Dissipation .........................................................1.0W
Operating Range
Ambient
Range Temperature[18]
VCC
VCCQ
Com’l
Ind’I
0°C to +70°C
3.3V
–5%/+10%
2.5V-5%/3.3V
+10%
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
VIH
VIHD
Description
Input High (Logic 1) Voltage[13, 19]
Test Conditions
Min.
2.0
Max.
Unit
V
All Other Inputs
3.3V I/O
5+0.5
2.0
V
2.5V I/O
1.7
V
VIl
Input Low (Logic 0) Voltage[13, 19]
Input Leakage Current
3.3V I/O
–0.3
–0.3
0.8
0.7
5
2.5V
ILI
0V < VIN < VCC
µA
µA
µA
V
IL
MODE and ZZ Input Leakage Current[20] 0V < VIN < VCC
–
30
5
ILO
VOH
Output Leakage Current
Output High Voltage[13]
Output(s) disabled, 0V < VOUT < VCC
IOH = –5.0 mA for 3.3V I/O
IOH = –1.0 mA for 2.5V I/O
IOL = 8.0 mA for 3.3V I/O
2.4
2.0
VOL
Output Low Voltage[13]
0.4
0.4
V
IOL = 1.0 mA for 2.5V I/O
VCC
Supply Voltage[13]
I/O Supply Voltage [13]
3.135
3.135
2.375
3.465
3.465
2.9
V
V
V
VCCQ
3.3V I/O
2.5V I/O
–4.4
225
–5
–6
166
–6.7
150
200
Parameter
Description
Conditions
Typ. MHz MHz MHz MHz Unit
ICC
Power Supply Current:
Operating[21, 22, 23]
Device selected; all inputs < VIL
or> VIH; cycle time > tKC min.;
VCC = Max.; outputs open
150 570
510
265
10
425
200
10
380 mA
ISB1
ISB2
ISB3
Automatic CE
Device deselected;
all inputs < VIL or > VIH; VCC = Max.;
CLK cycle time > tKC Min.
80
5
295
10
160 mA
Power-down Current—TTL
Inputs[22,23]
CMOS Standby[22, 23]
TTL Standby[22, 23]
Clock Running[22, 23]
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
all inputs static; CLK frequency = 0
10
30
80
mA
mA
mA
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = MAX; CLK frequency = 0
15
40
30
30
30
ISB4
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
CLK cycle time > tKC Min.
125
110
90
Notes:
18.
TA is the case temperature.
19. Overshoot: VIH < +6.0V for t < tKC /2.
Undershoot:VIL < –2.0V for t < tKC /2.
20. Output loading is specified with CL=5 pF as in AC Test Loads.
21. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
22. “Device Deselected” means the device is in power-down mode as defined in the truth table. “Device Selected” means the device is active.
23. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
Document #: 38-05264 Rev. *A
Page 19 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Capacitance[15]
Parameter
Description
Input Capacitance
Test Conditions
Typ.
5
Max.
Unit
pF
CI
TA = 25°C, f = 1 MHz,
VCC = 3.3V
7
8
CI/O
Input/Output Capacitance (DQ)
7
pF
Thermal Resistance
Parameter
Description
Test Conditions
TQFP Typ.
Unit
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
25
9
°C/W
°C/W
4-layer PCB
Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
317Ω
V
CCQ
DQ
ALL INPUT PULSES
V
CCQ
DQ
90%
10%
Z =50Ω
90%
0
50Ω
10%
≤ 1.0 ns
0V
5 pF
351Ω
≤ 1.0 ns
V = 1.5V
t
(c)
(a)
(b)
Switching Characteristics Over the Operating Range[24]
-4.4
225 MHz
-5
200 MHz
-6
-6.7
150 MHz
166 MHz
Parameter
Clock
tKC
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock Cycle Time
ns
ns
ns
4.4
1.7
1.7
5.0
2.0
2.0
6.0
2.4
2.4
6.7
2.6
2.6
tKH
Clock HIGH Time
Clock LOW Time
tKL
Output Times
tKQ
Clock to Output Valid
VCCQ = 3.3V
VCCQ = 2.5V
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.8
2.8
3.0
3.5
3.5
4.0
3.5
4.5
tKQX
Clock to Output Invalid
1.25
0
1.25
0
1.25
0
1.25
0
tKQLZ
tKQHZ
tOEQ
Clock to Output in Low-Z[15, 25, 26]
Clock to Output in High-Z[15, 25, 26]
OE to Output Valid[27]
1.25
3.0
2.8
2.8
1.25
3.0
3.0
3.5
1.25
4.0
3.5
4.0
1.25
4.0
3.5
4.5
VCCQ = 3.3V
VCCQ = 2.5V
tOELZ
tOEHZ
Set-up Times
OE to Output in Low-Z[15, 25, 26]
OE to Output in High-Z[15, 25, 26]
0
0
0
0
2.5
3.0
3.5
3.5
tS
Address, Controls, and Data In[28]
ns
ns
1.5
0.5
1.5
0.5
1.5
0.5
2.0
0.5
Hold Times
tH
Address, Controls, and Data In[28]
Notes:
24. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
25. Output loading is specified with CL = 5 pF as in (a) of AC Test Loads.
26. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
27. OE is a “Don’t Care” when a byte write enable is sampled LOW.
.
28. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “Don’t Care” as defined in the truth table.
Document #: 38-05264 Rev. *A
Page 20 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Typical Output Buffer Characteristics
Output High Voltage
OH(V)
Pull-up Current
Output Low Voltage
Pull-down Current
V
IOH(mA) Min. IOH(mA) Max.
VOL(V)
–0.5
0
IOL(mA) Min. IOL(mA) Max.
–0.5
0
–38
–38
–38
–26
–20
0
–105
–105
–105
–83
–70
–30
–10
0
0
0
0
0
0.8
1.25
1.5
2.3
2.7
2.9
3.4
0.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
0.8
1.25
1.6
0
2.8
0
3.2
0
0
3.4
Switching Waveforms
Read Timing[29, 30]
tKC
tKL
CLK
tKH
tS
ADSP
tH
ADSC
tS
A
A1
A2
tH
BWx
BWE
GW
tS
CE
tS
ADV
tH
OE
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
DQx
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Notes:
29. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
30. For the X18 product, there are only BWa and BWb for byte write control.
Document #: 38-05264 Rev. *A
Page 21 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Write Timing[29, 30]
CLK
tS
ADSP
tH
ADSC
tS
A
A1
A2
A3
tH
,
BWx
,
BWE
GW
CE
tS
ADV
tH
OE
tOEHZ
tKQX
Q
D(A1)
D(A2) D(A2+1) D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1) D(A3+2)
DQx
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05264 Rev. *A
Page 22 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Read/Write Timing[29, 30]
CLK
tS
ADSP
tH
ADSC
tS
A
A2
A3
A4
A5
A1
tH
BWx
,
,
BWE
#
GW
CE
ADV
OE
DQx
Q(A1)
Q(A2)
D(A3)
Single Write
Q(A4)
Q(A4+1) Q(A4+2)
D(A5)
D(A5+1)
Single Reads
Burst Read
Burst Write
Document #: 38-05264 Rev. *A
Page 23 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
ZZ Mode Timing [31, 32]
CLK
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
31. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
32. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05264 Rev. *A
Page 24 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
225
CY7C1366A-225AJC/
GVT71256C36T-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial
Commercial
CY7C1366A-225AC/
GVT71256C36TA-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-225BGC/
GVT71256C36B-4.4
BG119
A101
119-Lead BGA (14 x 22 x 2.4 mm)
200
166
150
225
200
166
150
CY7C1366A-200AJC/
GVT71256C36T-5
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-200AC/
GVT71256C36TA-5
A101
CY7C1366A-200BGC/
GVT71256C36B-5
BG119
A101
CY7C1366A-166AJC/
GVT71256C36T-6
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-166AC/
GVT71256C36TA-6
A101
CY7C1366A-166BGC/
GVT71256C36B-6
BG119
A101
CY7C1366A-150AJC/
GVT71256C36T-6.7
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-150AC/
GVT71256C36TA-6.7
A101
CY7C1366A-150BGC/
GVT71256C36B-6.7
BG119
A101
CY7C1367A-225AJC/
GVT71512C18T-4.4
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-225AC/
GVT71512C18TA-4.4
A101
CY7C1367A-225BGC/
GVT71512C18B-4.4
BG119
A101
CY7C1367A-200AJC/
GVT71512C18T-5
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-200AC/
GVT71512C18TA-5
A101
CY7C1367A-200BGC/
GVT715152C18B-5
BG119
A101
CY7C1367A-166AJC/
GVT715152C18T-6
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-166AC/
GVT71512C18TA-6
A101
CY7C1367A-166BGC/
GVT71512C18B-6
BG119
A101
CY7C1367A-150AJC/
GVT71512C18T-6.7
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-150AC/
GVT71512C18TA-6.7
A101
CY7C1367A-150BGC/
GVT71512C18B-6.7
BG119
Document #: 38-05264 Rev. *A
Page 25 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Ordering Information (continued)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
200
CY7C1366A-200AJCI/
GVT71256C36T-5I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial temp
CY7C1366A-200ACI/
GVT71256C36TA-5I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-200BGCI/
GVT71256C36B-5I
BG119
A101
166
150
200
166
150
CY7C1366A-166AJCI/
GVT71256C36T-6I
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-166ACI/
GVT71256C36TA-6I
A101
CY7C1366A-166BGCI/
GVT71256C36B-6I
BG119
A101
CY7C1366A-150AJCI/
GVT71256C36T-6.7I
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-150ACI/
GVT71256C36TA-6.7I
A101
CY7C1366A-150BGCI/
GVT71256C36B-6.7I
BG119
A101
CY7C1367A-200AJCI/
GVT71512C18T-5I
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-200ACI/
GVT71512C18TA-5I
A101
CY7C1367A-200BGCI/
GVT715152C18B-5I
BG119
A101
CY7C1367A-166AJCI/
GVT715152C18T-6I
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-166ACI/
GVT71512C18TA-6I
A101
CY7C1367A-166BGCI/
GVT71512C18B-6I
BG119
A101
CY7C1367A-150AJC/
GVT71512C18T-6.7I
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-150ACI/
GVT71512C18TA-6.7I
A101
CY7C1367A-150BGCI/
GVT71512C18B-6.7I
BG119
Document #: 38-05264 Rev. *A
Page 26 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05264 Rev. *A
Page 27 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Pentium is a registered trademark, and i486 is a trademark, of Intel Corporation. All product and company names mentioned in
this document are the trademarks of their respective holders.
Document #: 38-05264 Rev. *A
Page 28 of 29
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Document History Page
Document Title: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined
SRAM
Document Number: 38-05264
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
114117
125245
04/26/02
03/19/03
KKV
IXR
New Data Sheet
Changed tKQ, KQX, KQLZ, KHZ, OEQ, OELZ, OEHZ.
**
t
t
t
t
t
t
Document #: 38-05264 Rev. *A
Page 29 of 29
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