IMIC9816ATB [CYPRESS]
Clock Generator, PDSO56;
| 型号： | IMIC9816ATB |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, PDSO56 光电二极管 |
| 文件： | 总15页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Product Features
•
•
Supports Mobile Pentium®III systems.
Designed to support high speed chipset with
Rambus
•
•
1 CPU/2 synchronous DRCG clock.
1 Free Running PCI_F clock for Power
Management Timing
•
•
Supports power management.
Integrates Spread Spectrum Technology for EMI
reduction
One CPU clock
2 Synchronous IOAPIC clocks
•
•
•
•
•
7 Synchronous Low Skew PCI clocks (<500pS)
3 3.3V Synchronous Fixed 66.6MHz clocks
1 48MHz USB clock.
3 REF clocks for peripheral components.
Available in 56 SSOP and TSSOP package
•
•
Frequency Table (in MHz)
Sel133/100#
SEL0 SEL1
CPU
CPU/2
3V66(0:2)
PCI(_F,0:6)
48MHz
REF(0:2) IOAPIC
(0:1)
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Reserved
Hi-Z
Hi-Z
Hi-Z
All outputs in Tri-state
100
100
50
50
66.6
66.6
33.3
33.3
14.318
14.318
Tclk
16.67
16.67
48MHz PLL2 off
Normal mode, 100MHz
Test Mode
48
Tclk/2
Tclk/4
Tclk/4
Tclk/8
Tclk/2
Reserved
Hi-Z
Tclk/16
133.3
133.3
66.6
66.6
66.6
66.6
33.3
14.318
14.318
16.67
16.67
48MHz PLL2 off
33.3
48
Normal mode, 133.3
Table 1
Block Diagram
Pin Configuration
XIN
36pF
36pF
VDDR
X
B
U
F
1
300K
REF0
REF1
VDDR
VSS
REF0
R1OFF#/REF1
R2OFF#/REF2
VDDR
1
56
VDDI
XOUT
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
IOAPIC1
VSS
IOAPIC0
n/c
VDDR
REF2
XIN
XOUT
VDD
VSS
VSS
VDDI
2
CPU/2
VDDC/2
n/c
VSS
n/c
VDDC
CPU
VSS
IOAPIC(0:1)
CPU
R1OFF#
R2OFF#
apic
VDDC
1
cpu
SPREAD#
VDDP
VDDC/2
1
Rin
SEL1
SEL0
SEL133/100#
CPU/2
s1
s0
cpu/2
PCI_F
s133/100#
P6OFF#/PCI6
VSS
PWR_DN#
CPU_STP#
PCI_STP#
VDD3V66
3
PD#
CS#
PS#
3V66(0:2)
66m
pci
VSS
VSS
SPREAD#
sst#
VDDP
5
P50FF#/PCI5
P4OFF#/PCI4
VDDP
3V66-2
VDD3V66
VDD3V66
3V66-1
3V66-0
VSS
P4OFF#
P5OFF#
P6OFF#
PCI(_F,0:3)
PCI6
VDDP
VDDP
VDDP
1
1
1
VDDP
PCI3
PCI2
VSS
VSS
PCI1
PLL1
PCI5
PCI4
SEL0
SEL1
PCI_STP#
CPU_STP#
VDD48
48MHz
VSS
PCI0
VDDP
PWR_DN#
SEL133/100#
VDD48
1
Rin
48MHZ
48
PD#
PLL2
Fig. 1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 1 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Pin Description
PIN No.
Pin Name
PWR
I/O TYPE
Description
2
3
VDD
VDD
O
I/O
Buffered outputs of the signal applied at Xin, typically 14.318MHz
This is a Power-on Bi-directional pin. (see app. note page 4 for strapping). At
power-up this pin is an input R1OFF#.
REF0
R1OFF# /
REF1
PU
If R1OFF# is strapped LOW, then REF1 will be disabled in a low state.
If R1OFF# is strapped HIGH, then REF1 is running (default).
When the supply reaches the rail, this pin becomes REF1, a buffered output of
the signal applied at Xin, typically 14.318MHz
4
VDD
I/O
PU
This is a Power-on Bi-directional pin. (see app. note page 4 for strapping). At
power-up this pin is an input R2OFF#.
R2OFF# /
REF2
If R2OFF# is strapped LOW, then REF2 will be disabled in a low state.
If R2OFF# is strapped HIGH, then REF2 is running (default).
When the supply reaches the rail, this pin becomes REF2, a buffered output of
the signal applied at Xin, typically 14.318MHz
6
7
VDD
VDD
I
Crystal Buffer input pin. Connects to a crystal, or a Can Oscillator. Serves as
input clock TCLK, in Test mode.
Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is
used or in Test mode, this pin is kept unconnected.
XIN
O
XOUT
10
12
13
VDD
VDD
VDD
I
O
I/O
PU
PU
When this pin is low, Spread Spectrum is enabled. See description p.6
This is a free running 3.3 V PCI clock output. Synchronous to CPU clock.
This is a Power-on Bi-directional pin. (see app. note page 4 for strapping). At
power-up this pin is an input P6OFF#.
Spread#
PCI_F
P6OFF# /
PCI6
If P6OFF# is strapped LOW, then PCI6 will be disabled in a low state.
If P6OFF# is strapped HIGH, then PCI6 is running (default).
When the supply reaches the rail, this pin becomes PCI6, a 3.3V PCI clock.
Synchronous to CPU clock.
16
17
VDD
VDD
I/O
I/O
PU
PU
This is a Power-on Bi-directional pin. (see app. note page 4 for strapping). At
power-up this pin is an input P5OFF#.
If P5OFF# is strapped LOW, then PCI5 will be disabled in a low state.
If P5OFF# is strapped HIGH, then PCI5 is running (default).
When the supply reaches the rail, this pin becomes PCI5, a 3.3V PCI clock.
Synchronous to CPU clock.
P5OFF# /
PCI5
This is a Power-on Bi-directional pin. (see app. note page 4 for strapping). At
power-up this pin is an input P4OFF#.
P4OFF# /
PCI4
If P4OFF# is strapped LOW, then PCI4 will be disabled in a low state.
If P4OFF# is strapped HIGH, then PCI4 is running (default).
When the supply reaches the rail, this pin becomes PCI4, a 3.3V PCI clock.
Synchronous to CPU clock.
20,21,24,25
27
VDD
VDD
O
I
3.3 V PCI clock outputs. These signals are synchronous to CPU clocks.
When this pin is asserted low, the device is in Low Power State and all outputs
are low and internal circuitry are shutoff.
Input for frequency selection (see table1, page1).
3.3 V Fixed 48 Mhz USB clock output.
When this pin is asserted low, CPU is synchronously shutdown in a low state.
When this pin is asserted low, only PCI(0:6) are synchronously shutdown in a low
state. PCI_F is not effected by this signal.
PCI(0:3)
PWR_DN#
PU
PU
28
30
32
33
VDD
VDD
VDD
VDD
I
O
I
SEL133/100#
48MHz
CPU_stp#
PCI_stp#
PU
PU
I
34,35
37,38, 41
44
50
53,55
VDD
VDD
VDDC
VDDC/2
VDDI
I
PU
Inputs for function selection (see table1, page1).
SEL(0,1)
3V66 (0:2)
CPU
CPU/2
IOAPIC(0,1)
O
O
O
O
3.3 V Fixed 66.6Mhz Hub-link clock outputs. Synchronous to CPU clocks.
2.5 V Host bus clock output. Programmable per Table1, page1.
2.5 V DRCG clock output. Half CPU frequency and synchronous to CPU clock.
2.5 V IOAPIC clock outputs. Fixed at 16.67MHz and synchronous to CPU clock.
PU = Internal 250K Pull-up
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 2 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Power Plane Distribution
PIN No.
Pin Name
Power to pins
Description
5
2,3,4,6,7
3.3 V Power Supply for reference output clocks and crystal
circuitry.
VDDR
8
3.3V Analog Core Power Supply.
VDD
11,18,19,26
10,12,13,16,17, 3.3V common power supply pin for PCI clocks and input
VDDP
20,21,24,25,27, programming pins (Spread#, PWR_DN#, SEL133/100#)
28
31
30
3.3 V Power Supply for 48MHz output buffer and internal PLL
circuitry.
VDD48
VDD3V66
VDDC
39, 40
45
32,33,34,35,37, 3.3 V Power Supply for 3V66M buffers, digital core circuitry, and
38, 41
44
input programming pins (CPU_STP#, PCI_STP#, SEL(0:1)).
Power Supply pin for CPU output buffer. Typically connected to
2.5V
49
56
50
53,55
Power Supply pin for CPU/2. Typically connected to 2.5V
Power Supply pin for IOAPIC(0:1). Typically connected to 2.5V
Common Ground pins.
VDDC/2
VDDI
VSS
1, 9, 14, 15, 22,
23, 29, 36, 42,
43, 47, 51, 54
46, 48, 52
No Connect
N/C
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins
their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Power on Bi-Directional Pins
Power Up Condition:
Pins 3,4,13,16,and 17 are Power up bi-directional pins and are used for disabling their respective outputs in this device
(see Pin description, Page 2). During power-up, these pins are in input mode (see Fig 2, below), therefore, they are
considered input select pins internal to the IC. After a settling time, the selection data is latched into internal control
registers and these pins become toggling clock outputs.
VDD Rail
Power Supply
Ramp
R1OFF# / REF1
R2OFF# / REF2
P6OFF# / PCI6
P5OFF# / PCI5
-
Hi-Z Input
Toggle Outputs
P4OFF# / PCI4
Select data is latched into register, then pin becomes clock output signal.
Fig. 2
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 3 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Vdd
Strapping Resistor Options:
The power up bidirectional pins have a large value pull-
up each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
3mS settling time), then it is recommended to use an
external Pullup (Rup) in order to insure a high
Rup
50K
IMI C9816
Rd
Load
Bidirectional
selection. In this case, the designer may choose one of
two configurations, see Fig. 3A and Fig. 3B.
JP1
JUMPER
Fig. 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
Fig.3A
Rdn
5K
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.4A. Please note the selection resistors (Rup, and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
JP2
Vdd
3 Way Jumper
Fig. 3B represent a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Rsel
10K
IMI C9816
Rd
Load
Bidirectional
Fig.3B
Power Management Functions
Power Management on this device is controlled by CPU_STP# (pin32), PCI_STP# (pin33) and PWRDN# (pin27).
When CPU_STP# is forced low, only CPU signal is synchronously (no glitch) disabled in a low state. CPU will not
immediately stop, it will toggle one to three complete cycles before stopping on the falling edge, regardless of the
number of cycles it completes, it will stop before the next PCI_F rising edge occurs. This is to ensure synchronous
stopping after a full cycle without any glitches. When CPU_STP# is released to high, CPU is synchronously re-enabled.
The clock will wait the equivalent of one to three cycles after CPU_stp# is asserted high then will start toggling on the
rising edge. Regardless of the number of cycles it completes, it will start before the next PCI_F rising edge occurs. This
also is to ensure a synchronous start of a full clock cycle.
When PCI_STP# is forced low, only PCI(0:6) signals are synchronously disabled in a low state. These signals will
complete one full cycle before stopping one the following falling edge. PCI_F is still running. When PCI_STP# is
released to high, PCI(0:6) are synchronously re-enabled after the equivalent of one full PCI cycle latency.
When PWRDN# is forced low, CPU, PCI(F,0:6), IOAPIC(0:1), 3V66-(0:2), CPU/2, 48MHz, and REF(0:2) signals are
synchronously disabled, all internal circuitry (including the crystal buffer) is shutdown and the device is in Low Power (or
in power down) Mode. After PWRDN# is forced low, all power supplies (3.3V and 2.5V) may be removed. All power
supplies must be re-applied 200mS before releasing PWRDN# (to high), consequently, the device must be allowed 1mS
before the clock outputs settle to their preset frequencies. (see Fig.4, and table 2 below)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 4 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Power Management Timing
Tss
Tss
PCI_F
PCI_STP
PCI(0:6)
CPU_STP
CPU
Fig. 4
Tss is the stop clock setup time. All functionality is referenced to the rising edge of PCI_F. If the tss timing is met, with
respect to the next occurring PCI_F low to high transition, then the CPU or PCI clocks that are controlled are guaranteed
to stay low (stopped) or to rise (run) at the next rising edge of PCI_F. See the AC parameters for tss time.
Power Management Function Table
CPU_stp#
PWRDN#
PCI_stp#
CPU
CPU/2
3V66
(0:2)
PCI(0:6)
PCI_F
48M /
REF(0:2)
IOAPIC
(0:1)
PLL1
PLL2
x
0
0
1
1
0
1
1
1
1
x
0
1
0
1
0
0
0
run
run
0
0
0
0
run
0
0
0
0
off
run
run
run
run
off
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
Table 2
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 5 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Spectrum Spread Clocking
Down Spread Description
Spread Spectrum is a modulation technique for distributing clock period over a certain bandwidth (called Spread
Bandwidth). This technique allows the distribution of the energy (EMI) over a range of frequencies therefore reducing
the radiation generated from clocks. As the spread is a percentage of the rested (non-spread) frequency, it is effective
at the fundamental and all its harmonics.
In this device Spread Spectrum is enabled through pin 10 (Spread#). As the name suggests, spread spectrum is
enabled when Spread# is low. This pin has a 250KΩ internal pull up, therefore, defaults to a high (Spread Spectrum
disabled) unless externally forced to a low.
When Spread# is forced low, the device will be down spread (fig.5B) mode at –0.5%, and the center frequency is shifted
down from its rested (non-spread) value by -0.25%. (ex.: assuming the center frequency is 100MHz in non-spread
mode; when down spread is enabled, the center frequency shifts to 99.75MHz.), see fig.5 below.
Spread off
Spread on
Center
Center
Frequency,
Frequency,
Fig.5
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 6 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +85ºC
2000V
VSS<(Vin or Vout)<VDD
5.5V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters (VDD = VDDR = VDD = VDD48 = VDD3V66 = 3.3V ±5%, VDDC = VDDC/2 = VDDI = 2.5 + 5%, TA = 0ºC to +85ºC)
Characteristic
Symbol Min
Typ
Max
1.0
Units
Vdc
Vdc
Vdc
Vdc
µA
Conditions
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
VIL1
VIH1
VIL2
VIH2
IIL
-
-
-
-
-
Note 1
2.0
-
-
1.0
-
Note 2
2.2
-66
Input Low Current (@VIL =
VSS)
-5
For internal Pull up resistors, Note 1 and
Note 3
Input High Current (@VIL =
VDD)
IIH
5
µA
Tri-State leakage Current
Dynamic Supply Current
Dynamic Supply Current
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin Inductance
Ioz
Idd3.3V
Idd2.5V
Isdd
-
-
-
-
10
160
90
400
5
µA
mA
mA
µA
pF
pF
nH
pF
V
Sel133/100# = 1, Note 4
Sel133/100# = 1, Note 4
Sel133/100# = x, Note 4
-
-
-
-
Cin
-
-
Cout
Lpin
-
-
6
-
-
7
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Cxtal
VBIAS
Txs
27
36
45
Measured from Pin to Ground. Note 5
From Stable 3.3V power supply.
0.3Vdd Vdd/2 0.7Vdd
-
-
40
µS
Note1: Applicable to input signals: Sel133/100#, Sel(0:1), Spread#, PWRDN#, CPU_stp#, PCI_stp#.
Note2: Applicable to Sdata, and Sclk.
Note3: Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.
Note4: All outputs loaded as per table 3.
Note5: Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF
crystal specifications. See Suggested Crystal Parameters Table (Page 11).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 7 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
AC Parameters
133 MHz Host
100 MHz Host
Symbol
Parameter
Units
Notes
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
Min
7.5
1.87
1.67
0.4
-
Max
8.0
-
Min
10.0
3.0
2.8
0.4
-
Max
10.5
-
TPeriod
THIGH
TLOW
Tr / Tf
CPU period
CPU high time
CPU low time
nS
nS
nS
nS
pS
-
-
CPU rise and fall times
CPU Cycle to Cycle Jitter
1.6
250
1.6
250
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TCCJ
CPU/2 period
CPU/2 high time
CPU/2 low time
CPU/2 rise and fall times
CPU/2 Cycle to Cycle Jitter
15.0
5.25
5.05
0.4
-
16.0
-
-
1.6
250
20.0
7.5
7.3
0.4
-
21.0
-
-
1.6
250
nS
nS
nS
nS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
TPeriod
THIGH
TLOW
Tr / Tf
TCCJ
IOAPIC(0:1) period
IOAPIC(0:1) high time
IOAPIC(0:1) low time
IOAPIC(0:1) rise and fall times
IOAPIC(0:1) Cycle to Cycle Jitter
60.0
25.5
25.3
0.4
-
-
-
-
60.0
25.5
25.3
0.4
-
-
-
nS
nS
nS
nS
pS
5, 6, 8
6,10
6, 11
6, 7
N/S
1.6
500
1.6
500
6, 8, 9
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
3V66-(0:2) period
3V66-(0:2) high time
3V66-(0:2) low time
3V66-(0:2) rise and fall times
Any 3V66 clock to any 3V66 clock Skew time
3V66-(0:2) Cycle to Cycle Jitter
15.0
5.25
5.05
0.4
-
16.0
-
-
1.6
250
500
15.0
5.25
5.05
0.4
-
16.0
-
-
1.6
250
500
nS
nS
nS
nS
pS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
-
-
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
PCI(_F,0:6) period
PCI(_F,0:6) period
PCI(_F,0:6) low time
PCI(_F,0:6) rise and fall times
(Any PCI clock) to (Any PCI clock) Skew time
PCI(_F,0:6) Cycle to Cycle Jitter
30.0
12.0
12.0
0.5
-
-
-
-
30.0
12.0
12.0
0.5
-
-
-
-
nS
nS
nS
nS
pS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
2.0
500
500
2.0
500
500
-
-
TPeriod
Tr / Tf
TCCJ
48MHz period ( conforms to +167ppm max)
48MHz rise and fall times
48MHz Cycle to Cycle Jitter
20.8299 20.8333 20.8299 20.8333
nS
nS
pS
5, 6, 8
6, 7
6, 8, 9
1.0
-
4.0
500
1.0
-
4.0
500
TPeriod
Tr / Tf
TCCJ
REF(0:2) period
REF(0:2) rise and fall times
REF(0:2) Cycle to Cycle Jitter
69.8413
1.0
-
71.0
4.0
1000
69.8413
1.0
-
71.0
4.0
1000
nS
nS
pS
5, 6, 8
6, 7
6, 8
tpZL, tpZH
tpLZ, tpZH
tstable
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
Stopclock Set Up Time
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
nS
nS
mS
nS
13
13
12
14
tss
10.0
-
-
-
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 8 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Group Limits and Parameter (applicable to all settings: Sel133/100# = x)
Symbol Parameter
Min Typ
Max
55
Units
%
Notes
TDC
Toff1
Toff2
Toff4
Toff5
Duty Cycle
45
0
50
-
6, 8, 9
6, 8, 9
6, 8, 9
6, 8, 9
6, 8, 9
CPU to 3V66-(0:2) offset, CPU leads
3V66-(0:2) to PCI(_F,0:6) offset, 3V66 leads
CPU to IOAPIC(0:1) offset, CPU leads
CPU to CPU/2 offset, CPU leads
1.5
3.5
4.0
3.5
nS
1.0
1.5
0.5
-
nS
-
nS
-
nS
Note 5: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 6: All outputs loaded as per table 5 below.
Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for
2.5V signals (see Fig.7A and Fig.7B)
Note 8: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V signals. (see Figs.7A & 7B)
Note 9: This measurement is applicable with Spread ON or Spread OFF.
Note 10: Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see Figs. 7A & 7B)
Note 11: Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12: The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable
and operating within the specifications
Note 13: Measured from when both SEL1 And SEL0 are low
Note 14: CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next
PCI_F clock’s rising edge.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 9 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Output name
Max Load (in pF)
CPU, IOAPIC(0:1), CPU/2
PCI(_F,0:6), 3V66(0:2)
48 MHz , REF(0:2)
20
30
20
Table 5.
Test and Measurement Setup
Output under Test
Probe
Load Cap
3.3V signals
2.5V signals
tDC
tDC
-
-
-
-
3.3V
2.5V
2.4V
1.5V
2.0V
1.25V
0.4V
0.4V
0V
0V
Tr
Tf
Tr
Tf
Fig.7A
Fig.7B
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 10 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Output Buffer Characteristics
Buffer Characteristics for CPU, CPU/2
Characteristic
Symbol
IOH1
IOH2
IOL1
IOL2
Z0
Min
-17
-26
12
Typ
-31
- 58
24
Max
-51
Units
mA
mA
mA
mA
Ω
Conditions
Pull-Up Current
Pull-Up Current
Pull-Down Current
Pull-Down Current
Output Impedance
VDD-0.5
1.2V
-101
40
0.4V
27
56
93
1.2V
13.5
45
Buffer Characteristics for IOAPIC(0:1)
Characteristic
Symbol
IOH1
IOH2
IOL1
IOL2
Z0
Min
-22.5
-39
Typ
-45
- 85
36
Max
Units
mA
mA
mA
mA
Ω
Conditions
Conditions
Conditions
Pull-Up Current
Pull-Up Current
Pull-Down Current
Pull-Down Current
Output Impedance
-74
-150
59
VDD-0.5
1.2V
18
0.4V
40
82
138
45
1.2V
13.5
Buffer Characteristics for PCI(F, 0:6), 3V66(0:2)
Characteristic
Symbol
IOH1
IOH2
IOL1
IOL2
Z0
Min
-11
-32
9.4
22.8
12
Typ
-26
-56.5
18
Max
Units
mA
mA
mA
mA
Ω
Pull-Up Current
Pull-Up Current
Pull-Down Current
Pull-Down Current
Output Impedance
-33
-191.5
38
VDD-0.5
1.2V
0.4V
48
118.5
55
1.2V
Buffer Characteristics for 48 MHz and Ref(0:2)
Characteristic
Symbol
IOH1
IOH2
IOL1
IOL2
Z0
Min
-12
-28
9
Typ
-20
-45
13
Max
-50
-96
27
Units
mA
mA
mA
mA
Ω
Pull-Up Current
Pull-Up Current
Pull-Down Current
Pull-Down Current
Output Impedance
VDD-0.5
1.2V
0.4V
22
33
66
1.2V
20
60
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 11 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Min
Typ
Max
Units
MHz
PPM
PPM
PPM
Conditions
Frequency
Fo
12.00
14.31818
16.00
Tolerance
TC
-
-
-
-
-
-
-
-
+/-100
Note 1
TS
+/- 100
Stability (TA -10 to +60C) Note 1
Aging (first year @ 25C) Note 1
Parallel Resonant, Note 1
The crystal’s rated load. Note 1
Note 2
TA
-
5
-
Operating Mode
-
-
Load Capacitance
CXTAL
RESR
20
40
-
pF
Effective Series
-
Ohms
Resistance (ESR)
Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the
chosen crystal meets or exceeds these specifications
Note 2: Larger values may cause this device to exibit oscillator startup problems
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading
capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin
capacitance (CFTG), any circuit traces (CPCB), and any onboard discrete load capacitors (CDISC).
The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a
design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC
)
)
Where:
CXTAL
= the load rating of the crystal
CXOUTFTG = the clock generators XIN pin effective device internal capacitance to ground
CXOUTFTG = the clock generators XOUT pin effective device internal capacitance to ground
CXINPCB = the effective capacitance to ground of the crystal to device PCB trace
CXOUTPCB = the effective capacitance to ground of the crystal to device PCB trace
CXINDISC = any discrete capacitance that is placed between the XIN pin and ground
CXOUTDISC = any discrete capacitance that is placed between the XOUT pin and ground
XIN
CXINPCB
CXINDISC
CXINFTG
CXOUTPCB
CXOUTDISC
CXOUTFTG
XOUT
Clock Generator
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC
)
and each of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as:
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 12 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Suggested Oscillator Crystal Parameters (Cont.)
CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) = 40 X 40
(4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) 40 + 40
= 1600
80
= 20pF
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design
example, you should specify a parallel cut crystal that is designed to work into a load of 20pF.
Package Drawing and Dimensions (56 Pin TSSOP)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 13 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Package Drawing and Dimensions (Cont.)
56 Pin TSSOP Dimensions
INCHES
MILLIMETERS
SYMBOL
MIN
-
NOM
-
MAX
MIN
NOM
MAX
A
A1
A2
000
b
b1
bbb
c
0.043
.0059
-
-
0.10
0.90
0.10
-
0.20
0.08
-
1.10
0.15
0.95
.00197 .00394
0.0335 0.0354 0.0374
0.00394
0.0067
0.0067 0.0079 0.0091
0.0031
0.0035
0.0035 0.0050 0.0063
0°
0.05
0.85
-
0.106
0.17
0.17
0.27
0.23
-
0.0079
0.09
0.09
0°
0.20
0.16
8°
c1
θ
0.127
-
-
8°
e
H
D
E
0.0197 BSC
0.3189 BSC
0.551
0.50 BSC
8.10 BSC
13.90 14.00 14.10
0.547
0.236
0.0197
0.555
0.244
0.240
6.00
0.50
6.10
0.60
6.20
0.75
L
0.236
0.0295
Notes:
1. Die thickness allowable is 0.279 +/- 0.0127 (0.0110 +/-
.005 inches)
2. Dimensions & tolerance per ASME. Y14, 5M-1994.
3. Datum Plane H located at mold parting line and concident
with lead. Where lead exits plastic body at bottom of
parting line.
4. Datums A-B and D to be determined where centerline
between leads exits plastic body at Datum Plane H.
5. “D” and “E” are reference datums and do not include
mode flash or protrusions, and are measured at the
bottom parting line. Mold flash or protrusions shall not
exceed 0.15mm on D and 0.25mm on E per side.
6. Dimension is the length of terminal for soldering to a
substrate.
7. Terminal positions are shown for reference only.
8. Formed leads shall be planar with respect to one another
within 0.076mm at seating plane.
9. The lead width dimension does not include Dambar
protrusion. Allowable Dambar protrusion shall be 0.08mm
total in excess of the lead width dimension located on the
lower radius or the foot. Minimum space between
protrusions and an adjacent lead to be 0.08mm for
0.50mm pitch.
10. Section “C-C” to be determined at 0.10 to 0.25mm from
the lead tip.
11. This part is compliant with JEDEC specification MO-153,
variations DB, DC, DE ED, EE, and FE.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
11/1/1999
Page 14 of 15
+/+…when timing is critical
C9816
133 MHz Clock Generator for Mobile Pentium®III/Rambus Systems
Preliminary
Package Drawing and Dimensions (Cont.)
56 Pin SSOP Outline Dimensions
INCHES
MILLIMETERS
SYMBOL
A
MIN
NOM
MAX
MIN
2.41
NOM
2.59
MAX
2.79
C
0.095
0.102
0.012
0.090
0.010
-
0.110
A1
A2
B
C
D
E
e
0.008
0.088
0.008
0.005
.720
0.016
0.092
0.0135
0.010
.730
0.20
2.24
0.31
2.29
0.41
2.34
L
H
E
0.203 0.254 0.343
0.127 0.254
18.29 18.42 18.54
-
.725
D
0.292
0.296
0.025 BSC
0.406
0.013
0.032
5º
0.299
7.42
7.52
7.59
a
0.635 BSC
A2
A
H
a
0.400
0.10
0.024
0º
0.410
0.016
0.040
8º
10.16 10.31 10.41
A1
0.25
0.61
0º
0.33
0.81
5º
0.41
1.02
8º
e
B
L
a
X
0.085
0.093
0.100
2.16
2.36
2.54
Ordering Information
Part Number
C9816AYB
C9816ATB
Package Type
56 PIN SSOP
56 PIN TSSOP
Production Flow
Commercial, 0ºC to +70ºC
Commercial, 0ºC to +70ºC
Marking: Example: IMI
C9816
Date Code, Lot #
IMIC9816AYB
Flow
B = Commercial, 0ºC to + 70ºC
Package
Y = SSOP
T = TSSOP
Revision
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 1.3
11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Page 15 of 15
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