IMIZ9972BA [CYPRESS]
3.3V, 125-MHz, Multi-Output Zero Delay Buffer; 3.3V ， 125 MHz的，多输出零延迟缓冲器
| 型号： | IMIZ9972BA |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| 文件： | 总9页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z9972
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Table 1. Frequency Table[1]
Features
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0
FVCO
8x
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or crystal reference input
• Spread Spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC972
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12x
16x
20x
16x
24x
32x
40x
4x
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
6x
8x
10x
8x
12x
16x
20x
Note:
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
Block Diagram
Pin Configuration
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
Sync
Frz
D
D
Q
Q
QA0
QA1
QA2
QA3
0
1
Phase
Detector
VCO
TCLK0
0
1
TCLK1
LPF
TCLK_SEL
52 51 50 49 48 47 46 45 44 43 42 41 40
FB_IN
VSS
VSS
MR#/OE
SCLK
1
39
38
37
36
35
34
33
32
31
30
29
28
27
Sync
Frz
QB0
QB0
QB1
2
VDDC
QB1
3
4
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
QB2
QB3
FB_SEL2
VSS
5
QB2
6
VDDC
QB3
7
8
Z9972
MR#/OE
Sync
Frz
D
D
Q
Q
QC0
QC1
Power-On
Reset
FB_IN
VSS
9
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
10
11
12
13
TCLK1
Sync
Frz
2
QC2
SELA(0,1)
FB_OUT
VDDC
FB_SEL0
XIN
XOUT
QC3
2
2
SELB(0,1)
SELC(0,1)
0
1
Sync
Frz
VDD
FB_OUT
D
D
Q
Q
/4, /6, /8, /10
Sync Pulse
/2
14 15 16 17 18 19 20 21 22 23 24 25 26
Sync
Frz
2
SYNC
FB_SEL(0,1)
Data Generator
SCLK
Output Disable
Circuitry
12
SDATA
INV_CLK
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07088 Rev. *D
Revised December 21, 2002
Z9972
Pin Descriptions
Pin
Name
PWR I/O Type
Description
Oscillator Input. Connect to a crystal.
Oscillator Output. Connect to a crystal.
11
XIN
I
12
XOUT
O
9
TCLK0
TCLK1
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
I
PU External Reference/Test Clock Input.
10
I
PU External Reference/Test Clock Input.
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
29
VDDC
VDDC
VDDC
VDDC
O
O
O
O
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
25
SYNC
VDDC
O
Synchronous Pulse Output. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider
ratios selected.
42, 43
40, 41
19, 20
5, 26, 27
52
SELA(1,0)
SELB(1,0)
SELC(1,0)
FB_SEL(2:0)
VCO_SEL
I
I
I
I
I
PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2.
PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2.
PU Frequency Select Inputs. Theseinputsselect the divider ratioatQC(0:3)
outputs. See Table 2.
PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 2.
PU VCO Divider Select Input. When set LOW, the VCO output is divided by
2. When set HIGH, the divider is bypassed. See Table 1.
31
6
FB_IN
I
I
PU Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL_EN
PU PLL Enable Input. When asserted HIGH, PLL is enabled. And when
LOW, the phase-lock loop (PLL) is bypassed.
7
8
2
REF_SEL
TCLK_SEL
MR#/OE
I
I
I
PU Reference Select Input. When HIGH, the crystal oscillator is selected.
And when LOW, TCLK (0,1) is the reference clock.
PU TCLK Select Input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
PU Master Reset/Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
14
INV_CLK
I
PU Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
3
4
SCLK
I
I
PU Serial Clock Input. Clocks data at SDATA into the internal register.
SDATA
PU Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
17, 22, 28,
VDDC[2]
3.3V Power Supply for Output Clock Buffers.
33,37, 45, 49
13
VDD[2]
VSS
3.3V Supply for PLL.
Common Ground.
1, 15, 24, 30,
35, 39, 47, 51
Note:
2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07088 Rev. *D
Page 2 of 9
Z9972
Description
Glitch-Free Output Frequency Transitions
The Z9972 has an integrated PLL that provides low-skew and
low-jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
Customarily when output buffers have their internal counter’s
changed “on the fly’ their output clock periods will:
1. contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the
old or new frequency to which they are being transitioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequency to which they are being transitioned.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select
inputs (see Table 1). The VCO frequency is then divided to
provide the required output frequencies. These dividers are
set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see
Table 2). For situations in which the VCO needs to run at
relatively low frequencies and therefore might not be stable,
assert VCO_SEL LOW to divide the VCO frequency by 2. This
will maintain the desired output relationships, but will provide
an enhanced PLL lock range.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
SYNC Output[3]
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The Z9972 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. The following
timing diagram illustrates various waveforms for the SYNC
output.
The Z9972 is also capable of providing inverted output clocks.
When INV_CLK is asserted HIGH, QC2 and QC3 output
clocks are inverted. These clocks could be used as feedback
outputs to the Z9972 or a second PLL device to generate early
or late clocks for a specific design. This inversion does not
affect the output-to-output skew.
Table 2. Frequency Select Inputs
VCO_SEL
SELA1
SELA0
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/8
VCO/12
VCO/16
VCO/24
VCO/4
VCO/6
VCO/8
VCO/12
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/8
VCO/12
VCO/16
VCO/20
VCO/4
VCO/6
VCO/8
VCO/10
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/4
VCO/8
VCO/12
VCO/16
VCO/2
VCO/4
VCO/6
VCO/8
Note:.
3. The SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be
used as a synchronizing signal.
Document #: 38-07088 Rev. *D
Page 3 of 9
Z9972
VCO
1:1 Mode
2:1 Mode
QA
QC
SYNC
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
4:1 Mode
QA
QC
SYNC
QC
QA
SYNC
4:3 Mode
QA
QC
SYNC
6:1 Mode
QA
QC
SYNC
Figure 1. Sync Output Waveforms
Document #: 38-07088 Rev. *D
Page 4 of 9
Z9972
data. An output is frozen when a logic “0” is programmed and
enabled when a logic “1” is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
Power Management
The individual output enable/freeze control of the Z9972
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
“0” state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
The serial input register is programmed through the SDATA
input by writing a logic “0” start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Figure 2. SDATA Input Register
Document #: 38-07088 Rev. *D
Page 5 of 9
Z9972
Maximum Ratings[4]
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD protection ...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameters
VIL
Description
Input LOW Voltage
Conditions
Min.
VSS
2.0
Typ. Max.
Unit
V
0.8
VDD
–120
10
VIH
IIL
Input HIGH Voltage
Input LOW Current[5]
V
µA
µA
V
IIH
Input HIGH Current
VOL
VOH
IDDQ
IDDA
IDD
Output LOW Voltage[6]
Output HIGH Voltage[6]
Quiescent Supply Current
PLL Supply Current
Dynamic Supply Current
IOL = 20 mA
0.5
IOH = –20 mA
2.4
V
10
15
15
20
mA
mA
mA
VDD only
QA and QB @ 60 MHz
225
QC @ 120 MHz, CL = 30pF
QA and QB @ 25 MHz
QC @ 50 MHz, CL = 30pF
125
4
CIN
Input Pin Capacitance
pF
Notes:
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Inputs have pull-up/pull-down resistors that effect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07088 Rev. *D
Page 6 of 9
Z9972
AC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C[7]
Parameters
Tr/Tf
Description
TCLK Input Rise/Fall
Conditions
Min.
Typ.
Max.
3.0
Unit
ns
Fref
Reference Input Frequency
Crystal Oscillator Frequency
Reference Input Duty Cycle
PLL VCO Lock Range
Note 8
10
Note 8
25
MHz
MHz
%
Fxtal
see Table 3
FrefDC
Fvco
25
75
200
480
10
MHz
ms
Tlock
Tr/Tf
Maximum PLL lock Time
Output Clocks Rise/Fall Time[9]
0.8V to 2.0V
Q (÷2)
0.15
1.2
ns
Fout
Maximum Output Frequency
125
120
80
MHz
Q (÷4)
Q (÷6)
Q (÷8)
60
FoutDC
tpZL, tpZH
tpLZ, tpHZ
TCCJ
Output Duty Cycle[9]
TCYCLE/2 – 750
TCYCLE/2 + 750
ps
ns
ns
ps
ps
ps
Output Enable Time[9](all outputs)
Output Disable Time[9](all outputs)
Cycle to Cycle Jitter[9](peak to peak)
Any Output to Any Output Skew[9, 10]
2
2
10
8
±100
250
130
70
TSKEW
Tpd
350
530
470
Propagation Delay[10, 11]
TCLK0 QFB = (÷8)
–270
–330
TCLK1
Table 3. Crystal Oscillator Frequency
Parameter
Description
Conditions
Note 12
Min.
Typ.
Max.
±100
±100
Units
PPM
TC
TS
Frequency Tolerance
Frequency Temperature
Stability
(TA –10 to +60°C)[12]
PPM
TA
Aging
(first 3 years @ 25°C)[12]
The crystal’s rated load[12]
5
PPM/Yr.
pF
CL
Load Capacitance
20
40
RESR
Effective Series Resistance Note 13
80
Ohms
(ESR)
Notes:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Maximum and minimum input reference is limited by VC0 lock range.
9. Outputs loaded with 30 pF each.
10. 50Ω transmission line terminated into VDD/2
.
11. Tpd is specified for a 50 MHz input reference. Tpd does not include jitter.
12. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these
specifications.
13. Larger values may cause this device to exhibit oscillator startup problems.
Document #: 38-07088 Rev. *D
Page 7 of 9
Z9972
Ordering Information
Part Number
IMIZ9972BA
IMIZ9972BAT
Package Type
52-pin TQFP
52-pin TQFP - Tape and Reel
Production Flow
Industrial, –40°C to +85°C
Industrial, –40°C to +85°C
Package Drawing and Dimensions
52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52
51-85131-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07088 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Z9972
Document Title: Z9972 3.3V, 125 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07088
Orig. of
Rev.
**
ECN No. Issue Date
Change
Description of Change
Convert from IMI to Cypress
107124
108066
111798
06/12/01
07/03/01
02/06/02
IKA
*A
NDP
Changed Commercial to Industrial
*B
BRK
Convert from Word doc to Adobe Framemaker Cypress format
Changed the Timing Diagram and the operating voltage condition
*C
*D
116451
122773
08/16/02
12/21/02
HWT
RBI
Corrected the Ordering Information to match the Dev Master.
Changed Pin Configuration diagram label from CY29972 to IMIZ9972.
Add power up requirements to maximum ratings information.
Document #: 38-07088 Rev. *D
Page 9 of 9
相关型号：
©2020 ICPDF网 联系我们和版权申明