MB3773PF-G-BND-JN-ERE1

MB3773

Power Supply Monitor with

Watch-Dog Timer

Description

MB3773 generates the reset signal to protect an arbitrary system when the power-supply voltage momentarily is intercepted or

decreased. It is IC for the power-supply voltage watch and “Power on reset” is generated at the normal return of the power supply.

MB3773 sends the microprocessor the reset signal when decreasing more than the voltage, which the power supply of the system

specified, and the computer data is protected from an accidental deletion.

In addition, the watch-dog timer for the operation diagnosis of the system is built into, and various microprocessor systems can provide

the fail-safe function. If MB3773 does not receive the clock pulse from the processor for a specified period, MB3773 generates the

reset signal.

Features

■ Precision voltage detection (V_S= 4.2 V 2.5%)

■ Detection threshold voltage has hysteresis function

■ Low voltage output for reset signal (V_CC= 0.8 V Typ)

■ Precision reference voltage output (V_R= 1.245 V 1.5%)

■ With built-in watch-dog timer of edge trigger input.

■ External parts are few.(1 piece in capacity)

■ The reset signal outputs the positive and negative both theories reason.

■ One type of package (SOP-8pin : 1 type)

Application

■ Industrial Equipment

■ Arcade Amusement etc.

Cypress Semiconductor Corporation

Document Number: 002-08513 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 28, 2017

MB3773

Contents

Description ............................................................................. 1

Features .................................................................................. 1

Application ............................................................................. 1

Contents ................................................................................. 2

1. Pin Assignment ................................................................. 3

2. Block Diagram ................................................................... 3

3. Functional Descriptions .................................................... 4

4. Operation Sequence .......................................................... 6

5. Absolute Maximum Ratings ............................................ 7

6. Recommended Operating Conditions ............................. 7

7. Electrical Characteristics .................................................. 8

7.1 DC Characteristics ..................................................... 8

7.2 AC Characteristics ...................................................... 9

8. Typical Characteristic Curves ........................................ 10

9. Application Circuit ........................................................... 13

10. Notes on Use .................................................................. 25

11. Ordering Information ..................................................... 25

12. RoHS Compliance Information of Lead (Pb)

Free version ......................................................................... 25

13. Package Dimension ....................................................... 26

Document History ................................................................ 27

Sales, Solutions, and Legal Information ........................... 28

Document Number: 002-08513 Rev. *C

Page 2 of 28

MB3773

1. Pin Assignment

(TOP VIEW)

C^T

RESET

CK

1

2

3

4

8

7

6

5

RESET

V^S

V^REF

V^CC

GND

(SOE008)

2. Block Diagram

V_C

5

Reference AMP

≈ 1.24 V

COMP.O

Reference Voltage Generator

+

_

V_REF

6

≈ 100

kΩ

≈ 1.2 μA

≈ 10 μA

+

_

+

_

≈ 10 μA

COMP.S

+

_

R

S

Q

V_S

7

≈ 40 kΩ

Inhibit

Watch-

Dog

CK

3

Timer

P.G

4

GND

2

1

8

C_T

RESET

Document Number: 002-08513 Rev. *C

Page 3 of 28

MB3773

3. Functional Descriptions

Comp.S is comparator including hysteresis. it compare the reference voltage and the voltage of Vs, so that when the voltage of Vs

terminal falls below approximately 1.23 V, reset signal outputs.

Instantaneous breaks or drops in the power can be detected as abnormal conditions by the MB3773 within a 2 μs interval.

However because momentary breaks or drops of this duration do not cause problems in actual systems in some cases, a delayed

trigger function can be created by connecting capacitors to the Vs terminal.

Comp.O is comparator for turning on/off the RESET/RESET outputs and, compare the voltage of the C_Tterminal and the threshold

voltage. Because the RESET/RESET outputs have built-in pull-up circuit, there is no need to connect to external pull-up resistor when

connected to a high impedance load such as CMOS logic IC.

(It corresponds to 500 kΩ at Vcc = 5 V.) when the voltage of the CK terminal changes from the “high” level into the “Low” level, pulse

generator is sent to the watch-dog timer by generating the pulse momentarily at the time of drop from the threshold level.

When power-supply voltages fall more than detecting voltages, the watch-dog timer becomes an interdiction.

The Reference amplifier is an op-amp to output the reference voltage.

If the comparator is put up outside, two or more power-supply voltage monitor and overvoltage monitor can be done.

If it uses a comparator of the open-collector output, and the output of the comparator is connected with the Vs terminal of MB3773

without the pull-up resistor, it is possible to voltage monitor with reset-hold time.

Document Number: 002-08513 Rev. *C

Page 4 of 28

MB3773

MB3773 Basic Operation

V_CC

Logic Circuit

TPR (ms) ≈ 1000 · CT (μF)

TWD (ms) ≈ 100 · CT (μF)

RESET

CK

C_T

RESET

CK

TWR (ms) ≈

20 · CT (μF)

Example : C_T= 0.1 μF

T_RR(ms) ≈ 100 (ms)

GND

T_WD(ms) ≈ 10 (ms)

T_WR(ms) ≈ 2 (ms)

V

CC

V

SH

SL

0.8 V

CK

T

CK

CT

T

PR

RESET

T

WD

WR

T

PR

(1) (2)

(3)(4)(5)

(5)

(6)(7)

(8)(9)

(10)

(11) (12)

Document Number: 002-08513 Rev. *C

Page 5 of 28

MB3773

4. Operation Sequence

1. When Vcc rises to about 0.8 V, RESET goes “Low” and RESET goes “High”.

The pull-up current of approximately 1 μA (Vcc = 0.8 V) is output from RESET.

2. When Vcc rises to V_SH(≈ 4.3V), the charge with C_Tstarts.

At this time, the output is being reset.

3. When C_Tbegins charging, RESET goes “High” and RESET goes “Low”.

After T_PRreset of the output is released.

Reset hold time: T_PR(ms) ≈ 1000 × C_T(μF)

After releasing reset, the discharge of C_Tstarts, and watch-dog timer operation starts.

T_PRis not influenced by the CK input.

4. C changes from the discharge into the charge if the clock (Negative edge) is input to the CK terminal while discharging C_T.

5. C changes from the charge into the discharge when the voltage of C_Treaches a constant

threshold (≈ 1.4 V).

4 and 5 are repeated while a normal clock is input by the logic system.

6. When the clock is cut off, gets, and the voltage of C_Tfalls on threshold (≈ 0.4 V) of reset on, RESET goes “Low” and RESET goes

“High”.

Discharge time of C_Tuntil reset is output: T_WDis watch-dog timer monitoring time.

T_WD(ms) ≈ 100 × C_T(μF)

Because the charging time of C_Tis added at accurate time from stop of the clock and getting to the output of reset of the clock,

T_WDbecomes maximum T_WD+ T_WRby minimum T_WD

.

7. Reset time in operating watch-dog timer: T_WRis charging time where the voltage of C_Tgoes up to off

threshold (≈ 1.4 V) for reset.

T_WR(ms) ≈ 20 × C_T(μF)

Reset of the output is released after C_Treaches an off threshold for reset, and C_Tstarts the discharge, after that if the clock is

normally input, operation repeats 4 and 5, when the clock is cut off, operationrepeats 6 and 7.

8. When Vcc falls on V_SL(≈ 4.2 V), reset is output. C_Tis rapidly discharged of at the same time.

9. When Vcc goes up to V_SH, the charge with C_Tis started.

When Vcc is momentarily low,

After falling V_SLor less Vcc, the time to going up is the standard value of the Vcc input pulse width in V_SHor more.

After the charge of C_Tis discharged, the charge is started if it is T_PIor more.

10.Reset of the output is released after T_PR, after Vcc becomes V_SHor more, and the watch-dog timer starts. After that, when Vcc

becomes V_SLor less, 8 to 10 is repeated.

11.While power supply is off, when Vcc becomes V_SLor less, reset is output.

12.The reset output is maintained until Vcc becomes 0.8 V when Vcc falls on 0 V.

Document Number: 002-08513 Rev. *C

Page 6 of 28

MB3773

5. Absolute Maximum Ratings

Rating

Parameter

Supply voltage

Symbol

Unit

Min

- 0.3

—

Max

+ 18

V_CC

V_S

V

V_CC+ 0.3 ( ≤ +18)

+ 18

Input voltage

V_CK

V_OH

P_D

V

RESET, RESET Supply voltage

Power dissipation (Ta ≤ +85°C)

Storage temperature

V_CC+ 0.3 ( ≤ +18)

200

V

mW

°C

T_STG

- 55

+ 125

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in

excess of absolute maximum ratings. Do not exceed these ratings.

6. Recommended Operating Conditions

Value

Parameter

Symbol

Unit

Min

+ 3.5

0

Max

+ 16

20

Supply voltage

V_CC

I_OL

I_OUT

t_WD

_FC, t_RC

C_T

V

RESET, RESET sink current

VREF output current

mA

μA

ms

μs

- 200

0.1

+ 5

Watch clock setting time

CK Rising/falling time

1000

100

10

t

—

Terminal capacitance

0.001

- 40

μF

°C

Operating ambient temperature

Ta

+ 85

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor

device.All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these

ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

Users considering application outside the listed conditions are advised to contact their Cypress representatives

beforehand.

Document Number: 002-08513 Rev. *C

Page 7 of 28

MB3773

7. Electrical Characteristics

7.1 DC Characteristics

(V_CC= 5 V, Ta = + 25°C)

Value

Unit

Parameter

Symbol

I_CC

Condition

Min

—

Typ

Max

Supply current

Watch-dog timer operating

600

900

μA

V_CC

4.10

4.05

4.20

4.15

50

4.20

4.30

100

4.30

4.35

4.40

4.45

150

V_SL

Ta = - 40°C to + 85°C

V_CC

Detection voltage

V

V_SH

V_HYS

V_REF

Ta = - 40°C to + 85°C

V_CC

Hysteresis width

mV

V

—

1.227

1.215

—

1.245

3

1.263

1.275

10

Reference voltage

Ta = - 40°C to + 85°C

V_CC= 3.5 V to 16 V

Reference voltage change rate

∆V_REF1

∆V_REF2

mV

V

Reference voltage output

loading change rate

I_OUT= - 200 μA to + 5 μA

- 5

—

+ 5

CK threshold voltage

V_TH

I_IH

Ta = - 40°C to + 85°C

V_CK= 5.0 V

0.8

—

1.25

0

2.0

1.0

—

CK input current

μA

V

I_IL

V_CK= 0.0 V

- 1.0

- 0.1

Watch-dog timer operating

C_Tdischarge current

I_CTD

7

10

14

V_CT= 1.0 V

V_OH1

V_OH2

V_OL1

V_OL2

V_OL3

V_OL4

I_OL1

V_Sopen, I_RESET= - 5 μA

V_S= 0 V, I_RESET= - 5 μA

V_S= 0 V, I_RESET= 3 mA

V_S= 0 V, I_RESET= 10 mA

V_Sopen, I_RESET= 3 mA

V_Sopen, I_RESET= 10 mA

V_S= 0 V, V_RESET= 1.0 V

V_Sopen, V_RESET= 1.0 V

Power on reset operating

4.5

—

4.9

0.2

0.3

0.2

0.3

60

—

High level output voltage

0.4

0.5

0.4

0.5

—

Output saturation voltage

Output sink current

V

—

20

mA

I_OL2

60

—

C_Tcharge current

I_CTU

0.5

—

1.2

0.8

2.5

1.2

μA

V

V_CT= 1.0 V

V_RESET= 0.4 V,

Min supply voltage for RESET

V_CCL1

I_RESET= 0.2 mA

V_RESET= V_CC- 0.1 V,

R_L(between pin 2 and GND) = 1 MΩ

V_CCL2

—

V

Document Number: 002-08513 Rev. *C

Page 8 of 28

MB3773

7.2 AC Characteristics

Parameter

(V_CC= 5 V, Ta = + 25°C)

Value

Unit

Symbol

T_PI

Condition

Min

Typ

Max

5 V

4 V

V_CCinput pulse width

8.0

—

μs

V_CC

CK

CK input pulse width

T_CKW

3.0

—

or

—

CK input frequency

T_CK

T_WD

T_WR

20

5

—

10

2

—

15

3

μs

ms

Watch-dog timer watching time

Watch-dog timer reset time

C_T= 0.1 μF

1

Rising reset hold time

T_PR

T_PD1

T_PD2

t_R

50

—

100

2

150

10

ms

C_T= 0.1 μF, V_CC

RESET, R_L= 2.2 kΩ,

C_L= 100 pF

Output propagation

delay time from VCC

μs

RESET, R_L= 2.2 kΩ,

C_L= 100 pF

3

10

R_L= 2.2 kΩ,

C_L= 100 pF

Output rising time*

Output falling time*

1.0

0.1

1.5

0.5

μs

R_L= 2.2 kΩ,

C_L= 100 pF

t_F

* : Output rising/falling time are measured at 10 % to 90 % of voltage.

Document Number: 002-08513 Rev. *C

Page 9 of 28

MB3773

8. Typical Characteristic Curves

Supply current vs. Supply voltage

Output voltage vs. Supply voltage

(RESET terminal)

0.75

6.0

5.0

Ta = + 85 °C

Ta = + 25 °C

Pull up 2.2 kΩ

0.65

Ta = − 40 °C, + 25 °C, + 85 °C

Ta = − 40 °C

0.55

0.45

0.35

4.0

3.0

2.0

1.0

C^T= 0.1 μF

Ta = − 40 °C

Ta = + 25 °C

Ta = + 85 °C

0.25

0.15

0

1.0

2.0

3.0

4.0

5.0

6.0 7.0

0

2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0

Supply voltage V_CC(V)

Detection voltage (VSH, VSL) vs.

Output voltage vs. Supply voltage

Operating ambient temperature

(RESET terminal)

(RESET, RESET terminal)

6.0

5.0

4.0

4.50

VSH

VSL

4.44

4.30

4.20

4.10

Pull up 2.2 kΩ

3.0

2.0

1.0

Ta = + 85 °C

Ta = + 25 °C

Ta = − 40 °C

4.00

0

1.0 2.0

3.0 4.0

5.0

6.0

7.0

−40 −20

0

+20 +40 +60 +80 +100

Supply voltage VCC (V)

Operating ambient temperature Ta (°C)

Output saturation voltage

vs. Output sink current

Output saturation voltage

vs. Output sink current

(RESET terminal)

500

CT = 0.1μF

Ta = − 40 °C

CT = 0.1μF

400

300

200

100

Ta = −40 °C

400

Ta = + 25 °C

Ta = + 85 °C

300

200

Ta = +25 °C

Ta = +85 °C

100

0

2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0

0

2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0

Output sink current I_OL2(mA)

Output sink current I_OL8(mA)

(Continued)

Document Number: 002-08513 Rev. *C

Page 10 of 28

MB3773

High level output voltage

vs. High level output current

(RESET terminal)

5.0

4.5

5.0

4.5

CT = 0.1 μF

Ta = +25 °C

Ta = +85 °C

Ta = +25 °C

Ta = +85 °C

Ta = −40 °C

4.0

0

−5

−10

−15

0

−5

−10

−15

High level output current I_OH8(μA)

High level output current I_OH2(μA)

Reference voltage

vs. Reference current

Reference voltage

vs. Supply voltage

1.246

1.244

1.242

1.240

1.238

1.236

1.234

1.255

1.250

Ta = +25 °C

CT = 0.1 μF

Ta = +85 °C

Ta = −40 °C

CT = 0.1 μF

Ta = +25 °C

Ta = +85 °C

1.245

1.240

Ta = −40 °C

0

3.0 5.0 7.0 9.0 11.0 13.0 15.0 17.0 19.0 21.0

0

−40

−80

−120

−160

−200 −240

Supply voltage V_CC(V)

Reference current I_REF(μA)

Reference voltage vs.

Rising reset hold time vs.

Operating ambient temperature

1.27

160

V^CC= 5 V

CT = 0.1 μF

1.26

1.25

140

120

100

80

1.24

1.23

1.22

1.21

60

40

0

−40 −20

0

+20 +40 +60 +80 +100

−40 −20

0

+20 +40 +60 +80 +100

Operating ambient temperature Ta (°C)

(Continued)

Document Number: 002-08513 Rev. *C

Page 11 of 28

MB3773

(Continued)

Reset time vs.

Operating ambient temperature

Watch-dog timer watching time vs.

Operating ambient temperature

(At watch-dog timer)

16

14

VCC = 5 V

V

CC = 5 V

T

3

2

CT = 0.1 μF

C = 0.1 μF

12

10

8

1

0

6

4

0

−40 −20

0

+20 +40 +60 +80 +100

−40 −20

0

+20 +40 +60 +80 +100

Operating ambient temperature Ta (°C)

Watch-dog timer watching time

vs.

Reset time vs.

C_Tterminal capacitance

Rising reset hold time vs.

C_Tterminal capacitance

(at watch-dog timer)

10 ⁶

10 ⁵

10 ⁴

10 ⁶

10 ⁵

10 ⁴

10 ²

10 ¹

10 ⁰

10 ³

Ta = +25 °C,

+85 °C

Ta = −40 °C

10 ²

10 ¹

Ta =

Ta = −40 °C

+25 °C, +85 °C

10 ¹

Ta =

Ta = +25 °C, +85 °C

10 ⁻¹

10 ⁻²

10 ⁻³

−40 °C

10 ⁰

10 ⁻¹

10 ⁻²

10 ⁰

10 ⁻¹

10 ⁻²

10 ⁻³

10 ⁻10 ⁻10 ⁻10 ⁰10 ¹10 ²

3

2

1

10 ⁻³10 ⁻²10 ⁻¹10 ⁰10 ¹10 ²

C_Tterminal capacitance C_T(μF)

Document Number: 002-08513 Rev. *C

Page 12 of 28

MB3773

9. Application Circuit

EXAMPLE 1: Monitoring 5V Supply Voltage and Watch-dog Timer

VCC (5V)

MB3773

Logic circuit

8

7

6

5

1

2

3

4

RESET

CK

C_T

GND

Notes :

• Supply voltage is monitored using V_S.

• Detection voltage are V_SHand V_SL

.

EXAMPLE 2: 5V Supply Voltage Monitoring (external fine-tuning type)

V_CC(5V)

Logic circuit

MB3773

R1

R2

1

2

3

4

8

7

6

5

RESET

CK

CT

GND

Notes :

• Vs detection voltage can be adjusted externally.

• Based on selecting R₁and R₂values that are sufficiently lower than the resistance of the IC’s internal voltage

divider, the detection voltage can be set according to the resistance ratio of R₁and R₂(Refer to the table

below.)

R₁(kΩ)

R₂(kΩ)

Detection voltage: V_SL(V)

Detection voltage: V_SH(V)

10

3.9

4.4

4.1

4.5

4.2

9.1

Document Number: 002-08513 Rev. *C

Page 13 of 28

MB3773

EXAMPLE 3: With Forced Reset (with reset hold)

(a)

V_CC

MB3773

Logic circuit

1

2

3

4

8

7

6

5

RESET

CK

C_T

SW

GND

Note : Grounding pin 7 at the time of SW ON sets RESET (pin 8) to Low and RESET (pin 2) to High.

(b)

V_CC

MB3773

Logic circuit

1

2

3

4

8

7

6

5

RESET

CK

Tr

10 kΩ

Cr

GND

RESIN

Note : Feeding the signal to terminal RESIN and turning on Tr sets the RESET terminal to Low and the

RESET terminal to High.

Document Number: 002-08513 Rev. *C

Page 14 of 28

MB3773

EXAMPLE 4: Monitoring Two Supply Voltages (with hysteresis, reset output and NMI)

V_CC2(12

V_CC_{1 (5}

Logic circuit

RESET

MB3773

1

2

3

4

8

7

6

5

RESET

CK

C_T

30 kΩ

R₃

NMI or port

GND

180 kΩ

10 kΩ

R₆

R₄

+

_

Comp. 1

1.2 kΩ

Comp. 2

R₁

4.7 kΩ

R₅

5.1 kΩ

R₂

Example : Comp. 1, Comp. 2

: MB4204, MB47393

Notes :

• The 5 V supply voltage is monitored by the MB3773.

• The 12 V supply voltage is monitored by the external circuit. Its output is connected to the NMI terminal and, when

voltage drops, Comp. 2 interrupts the logic circuit.

• Use V_CC1( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above.

• The detection voltage of the V_CC2( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has a hysteresis width

of approximately 0.2 V.

V_CC2detection voltage and hysteresis width can be found using the following formulas:

R₃+ (R₄// R₅)

→ Detection voltage

× V_REF

V_2H

=

R₄// R₅

(Approximately 9.4 V in the above illustration)

(Approximately 9.2 V in the above illustration)

R₃+ R₅

V_2L=

→ Hysteresis width V_HYS= V_2H− V_2L

× V_REF

R₅

Document Number: 002-08513 Rev. *C

Page 15 of 28

MB3773

EXAMPLE 5: Monitoring Two Supply Voltages (with hysteresis and reset output)

V

(12

CC2

₁(5 V)

CC

20 kΩ

R₆

Logic circuit

RESET

MB3773

1

2

3

4

8

7

6

5

RESET

CK

30 kΩ

R₃

Diode

C_T

GND

180 kΩ

R₄

+

_

Comp. 1

1.2 kΩ

R₁

Comp. 2

5.1 kΩ

R₂

4.7 kΩ

R₅

Example : Comp. 1, Comp. 2

: MB4204, MB47393

Notes :

• When either 5 V or 12 V supply voltage decreases below its detection voltage (V_SL), the MB3773 RESET terminal

is set to High and the MB3773 RESET terminal is set to Low.

• Use V_CC1( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above.

• The detection voltage of the V_CC2( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has a hysteresis width

of approximately 0.2 V. For the formulas for finding hysteresis width and detection voltage, refer to section 4.

Document Number: 002-08513 Rev. *C

Page 16 of 28

MB3773

EXAMPLE 6: Monitoring Low voltage and Overvoltage Monitoring (with hysteresis)

V

(5

CC

20 kΩ

R₆

MB3773

Logic circuit

1

2

3

4

8

7

6

5

RESET

CK

30 kΩ

R₃

Diode

C_T

GND

180 kΩ

R₄

+

_

+

_

Comp. 1

1.2 kΩ

R₁

Comp. 2

5.6 kΩ

R₆

4.7 kΩ

R₅

Example : Comp. 1, Comp. 2

: MB4204, MB47393

RESET

V_CC

0

V_2LV_2H

V_1LV_1H

Notes :

• Comp. 1 and Comp. 2 are used to monitor for overvoltage while the MB3773 is used to monitor for low voltage.

Detection voltages V_1L/V_1Hat the time of low voltage are approximately 4.2 V/4.3 V. Detection voltages V_2L/V_2Hat

the time of overvoltage are approximately 6.0 V/6.1 V.For the formulas for finding hysteresis width and detection

voltage, see EXAMPLE 4.

• Use V_CC( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above.

Document Number: 002-08513 Rev. *C

Page 17 of 28

MB3773

EXAMPLE 7: Monitoring Supply Voltage Using Delayed Trigger

V_CC

5V

V_CC

4V

MB3773

Logic circuit

1

2

3

4

8

7

6

5

RESET

CK

C_T

C1

GND

Note : Adding voltage such as shown in the figure to V_CCincreases the minimum input pulse

width by 50 μs (C1 = 1000 pF).

Document Number: 002-08513 Rev. *C

Page 18 of 28

MB3773

EXAMPLE 8: Stopping Watch-dog Timer (Monitoring only supply voltage)

These are example application circuits in which the MB3773 monitors supply voltage alone without resetting the micropro-

cessor even if the latter, used in standby mode, stops sending the clock pulse to the MB3773.

• The watch-dog timer is inhibited by clamping the C_Tterminal voltage to V_REF

.

The supply voltage is constantly monitored even while the watch-dog timer is inhibited.

For this reason, a reset signal is output at the occurrence of either instantaneous disruption or a sudden drop to low voltage.

Note that in application examples (a) and (b), the hold signal is inactive when the watch-dog timer is inhibited at the time of

resetting.

If the hold signal is active when tie microprocessor is reset, the solution is to add a gate, as in examples (c) and (d).

(a) Using NPN transistor

V

(5 V)

CC

MB3773

Logic circuit

RESET

1

2

3

4

8

7

6

5

RESET

CK

HALT

GND

R₂=1 kΩ

R₁=1 MΩ

C_T

(b) Using PNP transistor

V

(5 V)

CC

MB3773

Logic circuit

RESET

1

8

7

6

5

2

3

4

RESET

CK

HALT

GND

R₂=1 kΩ

R₁=51

C_T

(Continued)

Document Number: 002-08513 Rev. *C

Page 19 of 28

MB3773

(Continued)

(c) Using NPN transistor

(5 V)

V

CC

MB3773

Logic circuit

1

2

3

4

8

7

6

5

RESET

CK

R₁=1 MΩ

HALT

GND

R₂=1 kΩ

C_T

(d) Using PNP transistor

V

(5 V)

CC

MB3773

Logic circuit

1

2

3

4

8

7

6

5

RESET

CK

R₁=51 kΩ

HALT

GND

R₂=1 kΩ

C_T

Document Number: 002-08513 Rev. *C

Page 20 of 28

MB3773

EXAMPLE 9: Reducing Reset Hold Time

V

( = 5 V)

VCC ( = 5 V)

CC

MB3773

Logic circuit

RESET

Logic circuit

RESET

1

2

3

4

1

2

3

4

8

7

6

5

8

7

6

5

RESET

CK

RESET

CK

C_T

GND

(a) T_PRreduction method

(b) Standard usage

Notes :

• RESET is the only output that can be used.

• Standard T_PR, T_WDand T_WRvalue can be found using the following formulas.

Formulas:T_PR(ms) ≈ 100 × CT (μF)

T

_WD(ms) ≈ 100 × CT (μF)

T_WR(ms) ≈ 16 × CT (μF)

• The above formulas become standard values in determining T_PR, T_WDand T_WR

.

Reset hold time is compared below between the reduction circuit and the standard circuit.

C_T= 0.1 μF

T^PRreduction circuit

10 ms

Standard circuit

100 ms

T_PR

T_WD

T_WR

≈

10 ms

1.6 ms

2.0 ms

Document Number: 002-08513 Rev. *C

Page 21 of 28

MB3773

EXAMPLE 10: Circuit for Monitoring Multiple Microprocessor

V_CC( = 5

FF1

FF2

FF3

S

D₁Q₁

CK Q₁

R

D₂Q₂

CK₂Q₂

R

D₃Q₃

CK Q₃

R

R₂

R₁

*

RESET

CK

RESET

CK

RESET

CK

GND

1

2

8

7

3

4

6

5

C_T

Figure 1

*: Microprocessor

MB3773

Notes :

•

connects from FF1 and FF2 outputs Q₁and Q₂to the NOR input.

• Depending on timing, these connections may not be necessary.

^{• Example : R}₁= R₂= 2.2 kΩ

^C_T= 0.1 μF

CK₁

Q₁

CK₂

Q₂

CK₃

Q₃

NOR

Output

Figure 2

Document Number: 002-08513 Rev. *C

Page 22 of 28

MB3773

Description of Application Circuits

Using one MB3773, this application circuit monitors multiple microprocessor in one system. Signals from each microprocessor are

sent to FF1, FF2 and FF3 clock inputs. Figure 2 shows these timings. Each flip-flop operates using signals sent from microprocessor

as its clock pulse. When even one signal stops, the relevant receiving flip-flop stops operating. As a result, cyclical pulses are not

generated at output Q₃. Since the clock pulse stops arriving at the CK terminal of the MB3773, the MB3773 generates a reset signal.

Note that output Q₃frequency f will be in the following range, where the clock frequencies of CK₁, CK₂and CK₃are f₁, f₂and f₃

respectively.

1

f0

1

f

1

---- --

≤

+

---- ---- ----

f1 f2 f3

where f0 is the lowest frequency among f₁, f₂and f₃.

Document Number: 002-08513 Rev. *C

Page 23 of 28

MB3773

EXAMPLE 11: Circuit for Limiting Upper Clock Input Frequency

V

(5 V)

CC

R₂

RESET

1

2

3

4

8

7

6

5

RESET

C_T

R₁=10 kΩ

T_r1

CK

GND

C₂

Notes :

• This is an example application to limit upper frequency fH of clock pulses sent from the microprocessor.

If the CK cycle sent from the microprocessor exceeds fH, the circuit generates a reset signal.

(The lower frequency has already been set using C_T.)

• When a clock pulse such as shown below is sent to terminal CK, a short T₂prevents C₂voltage from reaching the

CK input threshold level ( := 1.25 V), and will cause a reset signal to be output.

The T₁value can be found using the following formula :

T₁≈ 0.3 C₂R₂

where V_CC= 5 V, T₃≥ 3.0 μs, T₂≥ 20 μs

T₂

CK waveform

T₃

C₂voltage

T

Example : Setting C and R allow the upper T value to be set (Refer to the table below).

1

C

R

T1

0.01 μF

0.1 μF

10 kΩ

30 μs

300 μs

Document Number: 002-08513 Rev. *C

Page 24 of 28

MB3773

10. Notes on Use

■ Take account of common impedance when designing the earth line on a printed wiring board.

■ Take measures against static electricity.

❐ For semiconductors, use antistatic or conductive containers.

❐ When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.

❐ The work table, tools and measuring instruments must be grounded.

❐ The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.

■ Do not apply a negative voltage

❐ Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in

malfunction.

11. Ordering Information

Part number

MB3773PF-❏❏❏E1

Package

Remarks

8-pin plastic SOP

(SOE008)

–

12. RoHS Compliance Information of Lead (Pb) Free version

The LSI products of Cypress with “E1” are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury,

Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) .

The product that conforms to this standard is added “E1” at the end of the part number.

Document Number: 002-08513 Rev. *C

Page 25 of 28

MB3773

13. Package Dimension

Package Code: SOE008

ꢈ

0.25

ꢃ;

H

D

4

D

㻭

5

ꢏ

ꢅ

㻰

ꢅ

ꢏ

ꢈ

4

E1

E

INDEX AREA

ꢇ

0.25

H D

ꢃ;

ꢀ

ꢄ

ꢀ

0.40

C A-B D

㻮

5

BOTTOM VIEW

TOP VIEW

DETAIL A

L2

GAUGE

PLANE

ș

c

A

㻯

SEATING

PLANE

C

A'

b

A1

10

0.10

A-B

e

L

L1

SECTION A-A'

ꢎ

b

0.13

C

D

8

DETAIL A

SIDE VIEW

127(6

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DIMENSION

SYMBOL

MIN. NOM. MAX.

2.25

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A

0.20

0.05

A1

D

ꢂꢂꢂꢂ $ꢂ '$78 ꢂ

ꢁ

6.35 BSC

7.80 BSC

5.30 BSC

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ꢂꢂꢂꢂ (;75( 0(ꢂ 2ꢂ 7+ꢂ 3/$67, ꢂ %2'ꢂ (;&/ 86, 9ꢂ 2ꢂ 02/ ꢂ )/$6 ꢉ

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ꢂꢂꢂꢂ $1ꢂ 0, 6 0$7&ꢂ %(7 :(( ꢂ 7+ꢂ 7 2ꢂ $1ꢂ %277 2 ꢂ 2ꢂ 7+ꢂ 3/$67, ꢂ %2' ꢁ

E

1

ș

0°

0.13

0.39

0.45

8°

ꢁꢂ '$780ꢂ

ꢂ ꢂ ꢂ 7 ꢂ %ꢂ '(7(50, 1( ꢂ $ꢂ '$78 ꢂ ꢁ

0.20

0.55

0.75

c

b

L

e

ꢁꢂ ꢍ ꢂ, ꢂ 7+ꢂ 0$;, 08 ꢂ 180%( ꢂ 2ꢂ 7(50, 1$ꢂ 326, 7, 21ꢂ ) 2ꢂ 7+ꢂ 63(&, ), ('

ꢂꢂꢂꢂꢂ 3$&.$*ꢂ /(1*7 ꢁ

0.47

ꢁꢂ 7+ꢂ ', 0(16, 2ꢂ $33/ ꢂ 7 ꢂ 7+ꢂ )/$ꢂ 6(&7, 2ꢂ 2ꢂ 7+ꢂ /($ ꢂ %(7 :(( ꢂ ꢁ ꢀꢂ PP

0.60

ꢂꢂꢂꢂ 7 ꢂ ꢁ ꢃꢅ Pꢂ )52 ꢂ 7+ꢂ /($ ꢂ 7,

ꢁ

1.25 REF

0.25 BSC

1.27 BSC

1

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ꢂꢂꢂꢂ $ꢂ 0$;, 08 ꢂ 0$7(5, $ꢂ &21', 7, 2 ꢁ

2

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ꢁꢂ 7+, ꢂ &+$ 0)( ꢂ )($785ꢂ, ꢂ 237, 21$ ꢁꢂ / ꢂ, ꢂ, ꢂ 12ꢂ 35(6(1 ꢉꢂ 7+( ꢂ ꢂ 3, ꢂ ꢀ

ꢂꢂꢂꢂ, '(17, ), ( ꢂ 086ꢂ %ꢂ / 2&$7( ꢂ :, 7+, ꢂ 7+ꢂ, 1'(ꢂ $5(ꢂ, 1', &$7('

ꢀ ꢁꢂ ꢍ $ꢀꢂ, ꢂ '(), 1( ꢂ $ꢂ 7+ꢂ 9(57, &$ꢂ ', 67$1&ꢂ )52 ꢂ 7+ꢂ 6($7, 1 ꢂ 3/$1ꢂ 7 2

ꢂꢂꢂꢂꢂꢂꢂ 7+ꢂ / 2 :(6ꢂꢂ 32, 1ꢂ 2ꢂ 7+ꢂ 3$&.$*ꢂ %2'ꢂ (;&/ 8', 1 ꢂ 7+ꢂ /, ꢂ $1ꢂ 25

ꢂꢂꢂꢂꢂꢂꢂ 7+(50$ꢂ (1+$1&( 0(1ꢂ 2ꢂ &$9, 7 ꢂ '2 :ꢂ 3$&.$*ꢂ &21), *85$7, 21 ꢁ

11. JEDEC SPECIFICATION NO. REF : N/A

002-15857 Rev. **

Document Number: 002-08513 Rev. *C

Page 26 of 28

MB3773

Document History

Spansion Publication Number: DS04-27401-8Ea

Document Title: MB3773 Power Supply Monitor with Watch-Dog Timer

Document Number: 002-08513

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

Migrated to Cypress and assigned document number 002-08513.

No change to document contents or format.

**

–

TAOA

05/11/2006

*A

5199075

04/04/2016 Updated to Cypress format.

Updated Pin Assignment: Change the package name from FPT-8P-M01 to SOE008

Updated Ordering Information: Change the package name from FPT-8P-M01 to SOE008

Updated Package Dimension: Updated to Cypress format

Deleted “Marking Format (Lead Free version)”

*B

*C

5592858

5788613

HIXT

01/23/2017

06/28/2017

Deleted “Labeling Sample (Lead free version)”

Deleted “MB3773PF-❏❏❏E1 Recommended Conditions of Moisture Sensitivity Level”

Deleted the part number, “MB3773PF-❏❏❏”, from Ordering Information

Deleted the words in the Remarks, “Lead Free version”, from Ordering Information

MASG

Adapted Cypress new logo.

Document Number: 002-08513 Rev. *C

Page 27 of 28

MB3773

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

| Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/wireless

ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners..

Document Number: 002-08513 Rev. *C

Revised June 28, 2017

Page 28 of 28


型号：	MB3773PF-G-BND-JN-ERE1
厂家：	CYPRESS
描述：	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 6.35 X 5.30 MM, 2.25 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, SOP-8 光电二极管
文件：	总28页 (文件大小：454K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB3773PF-G-BND-JN-ERE1 [CYPRESS]

相关型号：

MB3773PF-XXXE1

MB3773PS

MB3773PS

MB3775

MB3775M

MB3775PF

MB3775PF

MB3775PF-XXX

MB3775PF-XXXE1

MB3775PFE1

MB3775PFE1

MB3775PFV