MB39C503WQN-G-AMERE1

MB39C502/503/504

High Efficiency Step Down

DC/DC Controller Datasheet

Description

MB39C502 is a single output step down DC/DC controller using external FETs. It achieves the high efficiency with

“Enhanced Low Power Mode (LPM) Operation” in light load. In Enhanced LPM, this controller operates that the

quiescent current is reduced only 30μA and the switching frequency is fallen by extending on time. These operations

enable to improve the efficiency in light load. Internal compensation circuit with current mode architecture and internal

boost switch allow reducing the BOM parts and the component area.

Features

 High Efficiency with Enhanced LPM Operation

 Automatic Transition for PFM/PWM

 Enhanced LPM Operation Transferred by SLP_N Assertion

 Over Current Alerting

 Reference Voltage Accuracy: ±1%

 Output Voltage Range

: 0.7V to 2.0V (MB39C502)

: 2.4V to 3.5V (MB39C503)

: fixed 5V

(MB39C504)

 VIN Input Voltage Range

: 4.0V to 25V (MB39C502/C503)

: 5.4V to 25V (MB39C504)

 VDD Input Voltage Range: 4.5V to 5.5V (MB39C502/C503)

 Internal 5V LDO with Switchover (MB39C504)

 Fixed Frequency Emulated On-Time Control: 800kHz

 Current Mode Architecture with Internal Compensation Circuit

 Internal Boost Switch

 Fixed 700μs Soft Start Time without Load Dependence

 Internal Discharge FET

 Power Good Monitor

 Enhanced Protection Functions: OVP, UVP, ILIM

 Thermal Shutdown

 Small 3mm × 3mm × 0.75mm QFN16 Package

Applications

 Point of Load VR for Note PC

 General Purpose Step Down Regulator

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 002-08449 Rev *A

Revised February 12, 2016

MB39C502/503/504

Contents

1. Typical Application ................................................................................................................................ 3

2. Pin Configuration................................................................................................................................... 4

3. Pin Configuration................................................................................................................................... 6

4. Block Diagram........................................................................................................................................ 8

5. Absolute Maximum Rating.................................................................................................................. 10

6. Recommended Operating Conditions.................................................................................................11

7. Electrical Characteristics.................................................................................................................... 13

8. Protections and Power Good function............................................................................................... 22

8.1

8.2

Description......................................................................................................................................... 22

Timing Chart ...................................................................................................................................... 23

9. Enhanced LPM Description ................................................................................................................ 27

9.1

9.2

9.3

Ultra Low Quiescent Current.............................................................................................................. 28

Extended On Time............................................................................................................................. 28

Timing Chart of Enhanced LPM......................................................................................................... 29

10.

Over Current Alerting Description.................................................................................................. 30

11.

Application Note .............................................................................................................................. 31

11.1

11.1.1

Setting Operating Conditions............................................................................................................. 31

Setting Output Voltage................................................................................................................... 31

11.1.2

11.2

Setting Over Current Limitation and Over Current Alerting ............................................................ 31

Selection Parts................................................................................................................................... 32

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.2.7

11.2.8

Selection of Smoothing Inductor .................................................................................................... 32

Selection of Switching FET............................................................................................................ 33

Selection of Fly Back Diode........................................................................................................... 35

Selection of Boost Diode................................................................................................................ 35

Selection of Input Capacitor........................................................................................................... 36

Selection of Output Capacitor........................................................................................................ 37

Selection of Boost Capacitor.......................................................................................................... 38

Selection of VDD Capacitor ........................................................................................................... 39

11.2.9

11.3

Selection of VCC Capacitor and Resistor ...................................................................................... 39

Layout................................................................................................................................................ 40

12.

13.

14.

Ordering Information....................................................................................................................... 43

Package Dimensions....................................................................................................................... 44

Major Changes................................................................................................................................. 45

Document Number: 002-08449 Rev *A

Page 2 of 46

MB39C502/503/504

1. Typical Application

(MB39C502/C503)

VIN

4.0V~25V

V5

C_IND

C_IN

VDD

VCC

VIN

M_H

DRVH

Power Good

OC Alert

PWRGD BST

ALERT_N

LX

L

R_S

VOUT

VOUT Sense

FB

VOUT Sense

M_L

DRVL

C_OUT

LOAD

EN

PGND

SLP#

SLP_N

ILIM

VCC

CSP

CSN

AGND

Document Number: 002-08449 Rev *A

Page 3 of 46

MB39C502/503/504

(MB39C504)

VIN

5.4V~25V

C_IND

C_IN

LDO5 VIN

VCC

M_H

DRVH

Power Good

PWRGD BST

LX

L

R_S

VOUT

VOUT Sense

VOUTS

DRVL

M_L

C_OUT

LOAD

EN

PGND

SLP#

SLP_N

ILIM

VCC

CSP

CSN

AGND

2. Pin Configuration

(MB39C502/C503)

3.0 mm

12

11

10

9

13

14

15

16

8

7

6

5

FB

SLP_N

PWRGD

VCC

DRVH

VIN

(Top View)

LX

EP :AGND

PGND

1

2

3

4

Document Number: 002-08449 Rev *A

Page 4 of 46

MB39C502/503/504

(MB39C504)

3.0 mm

12

11

10

9

13

14

15

16

8

7

6

5

VOUTS

SLP_N

PWRGD

VCC

DRVH

VIN

(Top View)

LX

EP :AGND

PGND

1

2

3

4

Document Number: 002-08449 Rev *A

Page 5 of 46

MB39C502/503/504

3. Pin Configuration

(MB39C502/C503)

Pin Number

Pin Name

ILIM(*1)

I/O

Description

1

2

3

4

5

6

7

8

9

I

Connect to VCC terminal.

Open drain output terminal with over current alerting.

ALERT_N

VDD

O

I

Power supply voltage input terminal of switching FET gate driver.

Low side switching FET gate driver output terminal.

Power ground.

DRVL

PGND

LX

O

-

Inductor and high side switching FET source connection terminal.

Power supply of switching regulator input terminal.

High side switching FET gate driver output terminal.

Boost capacitor connection terminal.

VIN

I

DRVH

BST

O

I

Enable input of PWM controller.

10

EN

I

When turning on, apply greater than 0.65V and less than 5.5V. When turning off, apply less

than 0.25V.

11

12

13

CSP

CSN

FB

I

Current sensing positive input terminal.

Current sensing negative input terminal.

Feedback voltage input of switching regulator.

Low power mode signal input terminal.

Transferred to low power mode by connecting to “L” level

Open drain output terminal with power good.

Power supply voltage input terminal of PWM controller.

Analog ground.

14

SLP_N

I

15

16

EP

PWRGD

VCC

O

I

AGND

-

*1: ILIM terminal should be fixed to connect to VCC terminal.

Document Number: 002-08449 Rev *A

Page 6 of 46

MB39C502/503/504

(MB39C504)

Pin Number

Pin Name

ILIM(*1)

I/O

Description

1

2

3

4

5

6

7

8

9

I

Connect to VCC terminal whenever.

VOUT

LDO5

DRVL

PGND

LX

DCDC output voltage input for switchover.

5V LDO output terminal.

O

-

Low side switching FET gate driver output terminal.

Power ground.

-

Inductor and high side switching FET source connection terminal.

Power supply of switching regulator input terminal.

High side switching FET gate driver output terminal.

Boost capacitor connection terminal.

VIN

I

DRVH

BST

O

I

Enable input of PWM controller.

10

EN

I

When turning on, apply greater than 2.5V and less than 25V. When turning off, apply less

than 0.6V.

11

12

13

CSP

I

Current sensing positive input terminal.

Current sensing negative input terminal.

DCDC output voltage input terminal.

CSN

VOUTS

Low power mode signal input terminal.

Transferred to low power mode by connecting to “L” level

Open drain output terminal with power good.

Power supply voltage input terminal of PWM controller.

Analog ground.

14

SLP_N

I

15

16

EP

PWRGD

VCC

O

I

AGND

-

*1: ILIM terminal should be fixed to connect to VCC terminal.

Document Number: 002-08449 Rev *A

Page 7 of 46

MB39C502/503/504

4. Block Diagram

(MB39C502/C503)

VBIAS

VCC

VIN

SLP_N

EN

REF

EN_SLP

IBIAS

BGR

VREF

EN

SLP

Logic

IBIAS

Control

EN

EN#

DSB_SLP

0.92x

REF

PWRGD Cmp

OV Cmp

PWRGD Logic

(Open Drain)

PWRGD

ALERT_N

VDD

1.15x

REF

ALT

OC Alert

(Open Drain)

REF

VTH

Control

OVP

Logic

0.70x

REF

VIN

UV Cmp

UVP

Logic

BST SW

Control

TON

CSN

FB

TON

Timer

BST

FB Buffer

DISCHG

Logic

High Side

Driver

DH

DRVH

LX

Error Amp

R

Q

Current Cmp

PWM

REF

SS

S

XQ

Drive

Logic

VDD

Low Side

Driver

ILIM

OVP

UVP

ILIM

ALT

AST

DL

ZC

DRVL

PGND

Current Sense Amp

Alert Cmp

CSP

CSN

EN#

UVLO

BSTUV

BST

UVLO

PGND

LX

UVLO

VCC

AGND

Document Number: 002-08449 Rev *A

Page 8 of 46

MB39C502/503/504

(MB39C504)

VBIAS

VCC

SLP_N

EN

VIN

EN

REF

EN_SLP

IBIAS

BGR

VREF

SLP

Logic

IBIAS

Control

EN

EN#

DSB_SLP

0.92x

REF

PWRGD Cmp

OV Cmp

PWRGD Logic

(Open Drain)

PWRGD

VIN

1.15x

REF

VTH

OVP

Control

VOUT

LDO5

Switchover

Logic

0.70x

REF

VIN

UV Cmp

UVP

Logic

BST SW

Control

TON

VOUTS

TON

Timer

BST

FB Buffer

High Side

Driver

DISCHG

Logic

DH

DRVH

LX

Error Amp

R

Q

Current Cmp

PWM

REF

SS

S

XQ

Drive

Logic

VDD

Low Side

Driver

ILIM

OVP

UVP

ILIM

AST

DL

ZC

DRVL

PGND

Current Sense Amp

CSP

CSN

EN#

UVLO

BSTUV

BST

UVLO

PGND1

UVLO

VCC

LX

AGND

Document Number: 002-08449 Rev *A

Page 9 of 46

MB39C502/503/504

5. Absolute Maximum Rating

(MB39C502/C503/C504)

Rating

Parameter

Symbol

V_VIN

Condition

VIN input voltage

Unit

Min

Max

–0.3

–2

+28

V

V_VCC

V_VDD

V_VOUT

V_BST

V_LX

VCC input voltage

+6.5

+34.5

+28

Power supply voltage

VDD input voltage (MB39C502/C503)

VOUT input voltage (MB39C504)

BST bias voltage

LX switching voltage

V_FB

FB input voltage (MB39C502/C503)

VOUTS input voltage

–0.3

V_VCC+0.3

+6.5

V_VOUTS

V_INPUT

V_CS

ILIM input voltage

V_VCC+0.3

+6.5

Terminal voltage

CSP, CSN input voltage

EN input voltage (MB39C502/C503)

EN input voltage (MB39C504)

SLP_N input voltage

+6.5

V_EN

+28

V_SLP

+6.5

V_NOD

V_BST-LX

PWRGD, ALERT_N bias voltage

BST–LX difference voltage

+6.5

BST–VDD difference voltage

(MB39C502/C503)

V_BST-VDD

V_BST-LDO5

-

+28

V

Difference voltage

Output current

BST–VOUT, LDO5 difference voltage

(MB39C504)

V_GND

V_CSP-CSN

I_DRV

AGND–PGND difference voltage

CSP–CSN difference voltage

DRVH, DRVL DC current

PWRGD

–0.3

–60

-

+0.3

+60

V

mA

mW

°C

I_NOD

+2

I_ALERT

P_D

ALERT_N sink current (MB39C502/C503)

Ta ≤ ±25°C

-

+2

Power dissipation

-

2100(*1)

+125

Storage temperature

T_STG

-

–55

*1: When the IC is mounted on 10cm × 10cm four-layer square epoxy board. IC is mounted on a four-layer epoxy

board, which terminal bias, and the IC’s thermal pad is connected to the epoxy board.

WARNING

−

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Document Number: 002-08449 Rev *A

Page 10 of 46

MB39C502/503/504

6. Recommended Operating Conditions

(MB39C502/C503/C504)

Value

Typ

Parameter

Symbol

V_VIN

Condition

Unit

Min

4.0

Max

VIN input voltage (MB39C502/C503)

VIN input voltage (MB39C504)

VCC input voltage

-

25

V

V_VIN

5.4

4.5

4.5(*1)

4.5

0

V_VCC

V_VDD

V_LDO5

V_BST

V_LX

5.5

30.5

25

Power supply voltage

VDD input voltage (MB39C502)

VDD input voltage (MB39C503)

VOUT input voltage (MB39C504)

BST bias voltage

LX switching voltage

–1

FB, ILIM input voltage

(MB39C502/C503)

V_INPUT

0

-

V_VCC

V

V_INPUT

V_CS

ILIM input voltage (MB39C504)

0

-

V_VCC

2.0

V

CSP, CSN input voltage (MB39C502)

CSP, CSN input voltage (MB39C503)

V_CS

3.5

CSP, CSN, VOUTS input voltage

(MB39C504)

Terminal voltage

V_CS

V_EN

0

-

5.5

V

EN, SLP_N input voltage

(MB39C502/C503)

V_EN

EN input voltage (MB39C504)

0

-

25

V

V_SLP

SLP_N input voltage (MB39C504)

5.5

PWRGD, ALERT_N bias voltage

(MB39C502/C503)

V_NOD

0

-

5.5

V

V_NOD

PWRGD bias voltage (MB39C504)

0

-

5.5

V

V_BST-LX

BST–LX difference voltage

BST–VDD difference voltage

(MB39C502/C503)

V_BST-VDD

V_BST-LDO5

-

25

V

Difference voltage

Output current

BST–VOUT, LDO5 difference voltage

(MB39C504)

V

V_GND

V_CSP-CSN

I_DRV

AGND–PGND difference voltage

CSP–CSN difference voltage

DRVH, DRVL DC current

–0.05

-

0.05

35

45

1

0

mV

mA

μF

–45

I_NOD

PWRGD, ALERT_N sink current

Connect BST to LX capacitor

Connect VCC to AGND capacitor

-

BST capacitor

VCC capacitor

C_BST

0.47

1.0

-

C_VCC

-

μF

Connect VDD to PGND capacitor

(MB39C502/C503)

VDD capacitor

LDO5 capacitor

C_VDD

C_LDO5

T_A

-

4.7

-

μF

°C

Connect LDO5 to PGND

capacitor(MB39C504)

-

Operating ambient

temperature

Ambient temperature

–30

85

*1: This VDD minimum input voltage indicates dynamic input range below 1ms. Refer to figure (next page) about the

static VDD minimum input voltage.

Document Number: 002-08449 Rev *A

Page 11 of 46

MB39C502/503/504

VDD Static Input Voltage vs. Ambient Temprature

(BAT54XV2T1G boost diode connected)

5.6

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

4.4

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Ambient Temprature / degC

WARNING

−

The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated

within these ranges.

−

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to use, conditions, or combinations not represented on the data sheet. Users

considering application outside the listed conditions are advised to contact their representatives beforehand.

Document Number: 002-08449 Rev *A

Page 12 of 46

MB39C502/503/504

7. Electrical Characteristics

(MB39C502)

VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

Value

Parameter

Symbol

Condition

Unit

Min

Typ

Max

REFERENCE VOLTAGE

This voltage is compared to feedback

voltage. Ta = 25°C

0.693

0.700

0.707

V

Internal reference voltage

FB input current

V_REF

Ta = –10°C to 85°C

VFB = 1.0V

0.686

-

0.714

0.1

I_FB

–0.1

μA

ENABLE, SLP_N

Enable voltage range

Disable voltage range

V_EN= 5.0V

V_EN

0.65

-

5.5

V

Enable condition

V_DSB

I_EN

0

-

0.25

0.1

V

EN input current

-

0

-

μA

V

V_SLPDSB

V_SLPEN

I_{SLP_N}

LPM disable voltage range

LPM enable voltage range

V_{SLP_N}= 5.0V

0.65

5.5

SLP_N enable condition

SLP_N input current

0

-

0.35

0.1

V

0

μA

SUPPLY CURRENT

VDD, VCC input current at PWM

operating. T_A= 25°C

I_VDDPWM

-

380

180

760

360

μA

VDD, VCC input current at idle state in

PFM operation. Static 0A inductor

current. T_A= 25°C

I_VDDPFM

VDD supply current

VDD, VCC input current at idle state in

LPM operation. Static 0A inductor

current. T_A= 25°C

I_VDDLPM

-

30

60

μA

VDD shutdown current

VIN supply current

I_VDDSDN

I_VIN

VDD, VCC input current at V_EN= 0V

V_VIN= 25V

-

0.1

10

1.0

15

μA

VIN shutdown current

I_VINSDN

VIN input current at V_EN= 0V

UNDER VOLTAGE LOCKOUT

UVLO release voltage

Hysteresis

0.1

1.0

V_UVLO

V_HYS

3.99

4.14

4.29

V

VCC UVLO threshold

0.005

0.070

0.200

SOFT START, DISCHARGE

From enable ON to the switching

initiating.

Period of power on reset

Ramp up time

t_POR

200

598

-

1000

732

μs

From the switching initiating after

enable ON to the output voltage

reaches 95%.

t_SS

665

Discharge resistance

R_DISCHG

V_DISCHG

VOUT = 0.2V, discharge enable.

V_CSNvoltage.

50

100

200

Ω

Discharge ends voltage

0.07

0.10

0.13

V

Document Number: 002-08449 Rev *A

Page 13 of 46

MB39C502/503/504

VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C502)

Value

Parameter

Symbol

Condition

ON TIMER

Unit

Min

Typ

Max

On time

t_ON

V_VIN= 7.4V, V_CSN= 1.2V

V_VIN= 7.4V, V_CSN= 0.2V

193

80

-

210

120

200

227

-

ns

Minimum on time

Minimum off time

t_MINON

t_MINOFF

400

CURRENTLIMITATION

CSP–CSN difference voltage at ILIM

connects to VCC.

Current limitation threshold

V_ILIMIT

19.0

24.0

29.0

mV

ILIM input current

I_ILIM

I_CS

V_ILIM= 5.0V

V_CS= 1.2V

-

0

0.1

-

μA

CSP, CSN input current

–5.0

–2.0

OVER AND UNDER VOLTAGE PROTECTION

For target output voltage. At output

voltage increasing.

Over voltage threshold ratio

Propagation delay of OV

RT_OV

t_OV

110

115

10

125

25

%

-

4

μs

%

Under voltage threshold

ratio

For target output voltage. At output

voltage decreasing.

RT_UV

t_UV

65

40

70

75

Propagation delay of UV

-

100

200

μs

POWER GOOD MONITOR

For target output voltage. At output

voltage increasing.

Power good threshold ratio

Hysteresis Ratio

RT_PG

86

92

98

%

RT_HYS

t_PG

-

3

5

7

%

Power good

Power bad

V_PWRGD= 5.5V

20

4

50

10

0

200

25

1

μs

μA

Propagation delay

t_PB

PWRGD leak current

I_LKPG

-

PWRGD output voltage “L”

level

V_OLPG

I_PWRGD= 1mA sink

-

0.05

0.10

V

THERMAL SHUT DOWN

T_TSDH

T_TSDL

Shut down temperature.

-

150(*1)

125(*1)

-

°C

Shut down temperature

Exited temperature from thermal shut

down state.

OVER CURRENT ALERTING

Over current alerting

threshold ratio

For target current limitation. At output

current increasing.

RT_ALT

78

85

92

%

t_ALTON

t_ALTOFF

I_LKALT

On alerting assertion

On alerting de-assertion

V_{ALERT_N}= 5.5V

20

3

50

10

0

200

25

1

μs

μA

Propagation delay

ALERT_N leak current

-

ALERT_N output voltage “L”

level

V_OLALT

I_{ALERT_N}= 1mA sink

-

0.05

0.10

V

*1: No production tested, ensure by design.

Document Number: 002-08449 Rev *A

Page 14 of 46

MB39C502/503/504

VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C502)

Value

Parameter

Symbol

Condition

Unit

Min

Typ

Max

DRIVER

At 100mA current sourcing

At 100mA current sinking

At 100mA current sourcing

At 100mA current sinking

V_DRVH= 2.5V

R_HOH

-

3(*1)

-

Ω

A

High side on resistance

Low side on resistance

R_HOL

R_LOH

R_LOL

I_SRCH

I_SINKH

I_SRCL

I_SINKL

1(*1)

4(*1)

0.75(*1)

0.7(*1)

1.1(*1)

0.5(*1)

1.7(*1)

High side source current

High side sink current

Low side source current

Low side sink current

V_DRVH= 2.5V

V_DRVL= 2.5V

From DRVH turn off to DRVL turn on.

And reverse it.

Dead time

t_DEAD

10

20

-

ns

BOOST SWITCH

I_BST= 10mA

Boost switch on resistance

BST leak current

R_BST

-

30

50

Ω

I_LKBST

V_BST= 30V

0.1

1.0

μA

*1: No production tested, ensure by design.

Document Number: 002-08449 Rev *A

Page 15 of 46

MB39C502/503/504

VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C503)

Value

Parameter

Symbol

Condition

Unit

Min

Typ

Max

REFERENCE VOLTAGE

This voltage is compared to feedback

voltage. Ta = 25°C

0.99

1.00

1.01

V

Internal reference voltage

FB input current

V_REF

Ta = –10°C to 85°C

VFB = 1.0V

0.98

-

1.02

0.1

I_FB

–0.1

μA

ENABLE, SLP_N

Enable voltage range

Disable voltage range

V_EN= 5.0V

V_EN

0.65

-

5.5

V

Enable condition

V_DSB

I_EN

0

-

0.25

0.1

V

EN input current

-

0

-

μA

V

V_SLPDSB

V_SLPEN

I_{SLP_N}

LPM disable voltage range

LPM enable voltage range

V_{SLP_N}= 5.0V

0.65

5.5

SLP_N enable condition

SLP_N input current

0

-

0.35

0.1

V

0

μA

SUPPLY CURRENT

VDD, VCC input current at PWM

operating. T_A= 25°C

I_VDDPWM

-

380

180

760

360

μA

VDD, VCC input current at idle state in

PFM operation. Static 0A inductor

current. T_A= 25°C

I_VDDPFM

VDD supply current

VDD, VCC input current at idle state in

LPM operation. Static 0A inductor

current. T_A= 25°C

I_VDDLPM

-

30

60

μA

VDD shutdown current

VIN supply current

I_VDDSDN

I_VIN

VDD, VCC input current at V_EN= 0V

V_VIN= 25V

-

0.1

10

1.0

15

μA

VIN shutdown current

I_VINSDN

VIN input current at V_EN= 0V

UNDER VOLTAGE LOCKOUT

UVLO release voltage

Hysteresis

0.1

1.0

V_UVLO

V_HYS

3.99

4.14

4.29

V

VCC UVLO threshold

0.005

0.070

0.200

SOFT START, DISCHARGE

From enable ON to the switching

initiating.

Period of power on reset

Ramp up time

t_POR

200

598

-

1000

732

μs

From the switching initiating after

enable ON to the output voltage

reaches 95%.

t_SS

665

Discharge resistance

R_DISCHG

V_DISCHG

VOUT = 0.2V, discharge enable.

V_CSNvoltage.

50

100

200

Ω

Discharge ends voltage

0.07

0.10

0.13

V

Document Number: 002-08449 Rev *A

Page 16 of 46

MB39C502/503/504

VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C503)

Value

Parameter

ON TIMER

Symbol

Condition

Unit

Min

Typ

Max

621

180

On time

t_ON

V_VIN= 7.4V, V_CSN= 3.3V

529

100

575

200

90

ns

Minimum on time

Minimum off time

t_MINON

V_VIN= 7.4V, V_CSN= 0.2V

-

t_MINOFF

CURRENTLIMITATION

CSP–CSN difference voltage at ILIM

connects to VCC.

Current limitation threshold

V_ILIMIT

21.0

26.0

31.0

mV

ILIM input current

CSP input current

CSN input current

I_ILIM

I_CSP

I_CSN

V_ILIM= 5.0V

V_CSP= 3.3V

-

0

0.1

μA

2.0

8.0

5.0

20.0

OVER AND UNDER VOLTAGE PROTECTION

For target output voltage. At output

voltage increasing.

Over voltage threshold ratio

Propagation delay of OV

RT_OV

t_OV

110

115

10

125

25

%

-

4

μs

%

Under voltage threshold

ratio

For target output voltage. At output

voltage decreasing.

RT_UV

t_UV

65

40

70

75

Propagation delay of UV

-

100

200

μs

POWER GOOD MONITOR

For target output voltage. At output

voltage increasing.

Power good threshold ratio

Hysteresis Ratio

RT_PG

86

92

98

%

RT_HYS

t_PG

-

3

5

7

%

Power good

Power bad

V_PWRGD= 5.5V

20

4

50

10

0

200

25

1

μs

μA

Propagation delay

t_PB

PWRGD leak current

I_LKPG

-

PWRGD output voltage “L”

level

V_OLPG

I_PWRGD= 1mA sink

-

0.05

0.10

V

THERMAL SHUT DOWN

T_TSDH

T_TSDL

Shut down temperature.

-

150(*1)

125(*1)

-

°C

Shut down temperature

Exited temperature from thermal shut

down state.

OVER CURRENT ALERTING

Over current alerting

threshold ratio

For target current limitation. At output

current increasing.

RT_ALT

78

85

92

%

t_ALTON

t_ALTOFF

I_LKALT

On alerting assertion

On alerting de-assertion

V_{ALERT_N}= 5.5V

20

3

50

10

0

200

25

1

μs

μA

Propagation delay

ALERT_N leak current

-

ALERT_N output voltage “L”

level

V_OLALT

I_{ALERT_N}= 1mA sink

-

0.05

0.10

V

*1: No production tested, ensure by design.

Document Number: 002-08449 Rev *A

Page 17 of 46

MB39C502/503/504

VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C503)

Value

Parameter

Symbol

Condition

Unit

Min

Typ

Max

DRIVER

At 100mA current sourcing

At 100mA current sinking

At 100mA current sourcing

At 100mA current sinking

V_DRVH= 2.5V

R_HOH

-

3(*1)

-

Ω

A

High side on resistance

Low side on resistance

R_HOL

R_LOH

R_LOL

I_SRCH

I_SINKH

I_SRCL

I_SINKL

1(*1)

4(*1)

0.75(*1)

0.7(*1)

1.1(*1)

0.5(*1)

1.7(*1)

High side source current

High side sink current

Low side source current

Low side sink current

V_DRVH= 2.5V

V_DRVL= 2.5V

From DRVH turn off to DRVL turn on.

And reverse it.

Dead time

t_DEAD

10

20

-

ns

BOOST SWITCH

I_BST= 10mA

Boost switch on resistance

BST leak current

R_BST

-

30

50

Ω

I_LKBST

V_BST= 30V

0.1

1.0

μA

*1: No production tested, ensure by design.

Document Number: 002-08449 Rev *A

Page 18 of 46

MB39C502/503/504

VIN = 7.4V, VOUT, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C504)

Value

Parameter

Symbol

Condition

Unit

Min

Typ

Max

REFERENCE VOLTAGE

This voltage is compared to feedback

voltage. Ta = 25°C

4.95

5.00

5.05

V

Internal reference voltage

VOUTS input current

V_REF

Ta = –10°C to 85°C

V_VOUTS= 5.0V

4.90

2.5

-

5.10

12.5

I_VOUTS

5.0

μA

ENABLE, SLP_N

Enable voltage range

Disable voltage range

V_EN= 5.0V

V_EN

2.5

-

25

V

Enable condition

V_DSB

I_EN

0

-

0.6

1.2

5.5

0.35

0.1

V

EN input current

-

0.5

μA

V

V_SLPDSB

V_SLPEN

I_{SLP_N}

LPM disable voltage range

LPM enable voltage range

V_{SLP_N}= 5.0V

0.65

-

SLP_N enable condition

SLP_N input current

0

-

V

0

μA

SUPPLY CURRENT

VOUT, VCC input current at PWM

operating. T_A= 25°C

I_VOUTPWM

-

400

200

800

400

μA

VOUT, VCC input current at idle state in

PFM operation. Static 0A inductor

current. T_A= 25°C

I_VOUTPFM

VOUT supply current

VOUT, VCC input current at idle state in

LPM operation. Static 0A inductor

current. T_A= 25°C

I_VOUTLPM

-

50

100

μA

VOUT shutdown current

VIN supply current

I_VOUTSDN

I_VIN

VOUT, VCC input current at V_EN= 0V

V_VIN= 25V

-

0.1

20

1.0

30

μA

VIN shutdown current

UNDER VOLTAGE LOCKOUT

I_VINSDN

VIN input current at V_EN= 0V

0.1

1.0

V_UVLO

V_HYS

UVLO release voltage

Hysteresis

3.99

4.14

4.29

V

VCC UVLO threshold

0.005

0.070

0.200

SOFT START, DISCHARGE

From enable ON to the switching

initiating.

Period of power on reset

Ramp up time

t_POR

300

598

-

1400

732

μs

From the switching initiating after

enable ON to the output voltage

reaches 95%.

t_SS

665

Discharge resistance

R_DISCHG

V_DISCHG

VOUT = 0.2V, discharge enable.

V_CSNvoltage.

50

100

200

Ω

Discharge ends voltage

0.07

0.10

0.13

V

Document Number: 002-08449 Rev *A

Page 19 of 46

MB39C502/503/504

VIN = 7.4V, VOUT, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C504)

Value

Parameter

ON TIMER

Symbol

Condition

Unit

Min

Typ

Max

On time

t_ON

V_VIN= 7.4V, V_VOUT= 5.0V

802

100

-

872

200

120

942

-

ns

Minimum on time

Minimum off time

t_MINON

V_VIN= 7.4V, V_VOUT= 0.2V

-

t_MINOFF

240

CURRENTLIMITATION

CSP–CSN difference voltage at ILIM

connects to VCC.

Current limitation threshold

V_ILIMIT

21.0

26.0

31.0

mV

ILIM input current

CSP input current

CSN input current

I_ILIM

I_CSP

I_CSN

V_ILIM= 5.0V

V_CSP= 5.0V

V_CSN= 5.0V

-

0

0.1

μA

2.0

8.0

5.0

20.0

OVER AND UNDER VOLTAGE PROTECTION

For target output voltage. At output

voltage increasing.

Over voltage threshold ratio

Propagation delay of OV

RT_OV

t_OV

110

115

10

125

25

%

-

4

μs

%

Under voltage threshold

ratio

For target output voltage. At output

voltage decreasing.

RT_UV

t_UV

65

40

70

75

Propagation delay of UV

-

100

200

μs

POWER GOOD MONITOR

For target output voltage. At output

voltage increasing.

Power good threshold ratio

Hysteresis Ratio

RT_PG

86

92

98

%

RT_HYS

t_PG

-

3

5

7

%

Power good

Power bad

V_PWRGD= 5.5V

20

4

50

10

0

200

25

1

μs

μA

Propagation delay

t_PB

PWRGD leak current

I_LKPG

-

PWRGD output voltage “L”

level

V_OLPG

I_PWRGD= 1mA sink

-

0.05

0.10

V

THERMAL SHUT DOWN

Shut down temperature

T_TSDH

T_TSDL

Shut down temperature.

-

150(*1)

125(*1)

-

°C

Exited temperature from thermal shut

down state.

*1: No production tested, ensure by design.

Document Number: 002-08449 Rev *A

Page 20 of 46

MB39C502/503/504

VIN = 7.4V, VOUT, BST and EN connect to 5V power supply, PGND, LX = 0V. T_A= –30°C to +85°C, unless otherwise

noted.

(MB39C504)

Value

Parameter

Symbol

Condition

5V LDO

Unit

Min

Typ

Max

No switchover.

Output voltage

V_LDO5

4.75

25

-

5.00

-

5.25

-

V

VOUT input voltage < 4.4V

No switchover.

Output current

I_LDO5

mA

V_VIN= 5.4V

No switchover.

Output short current

Switchover voltage

Startup time

I_LDO5S

80

125

V_LDO5= 0V

V_SWOVR

V_HYS

VOUT voltage rising.

Hysteresis voltage.

LDO5 voltage reaches to 4.2V.

C_LDO5, C_VCC= 1.0μF

DRIVER

4.35

0.08

4.50

0.10

4.60

0.12

V

t_SLDO5

100

150

400

μs

R_HOH

R_HOL

R_LOH

R_LOL

I_SRCH

I_SINKH

I_SRCL

I_SINKL

At 100mA current sourcing

At 100mA current sinking

At 100mA current sourcing

At 100mA current sinking

V_DRVH= 2.5V

-

3(*1)

-

Ω

A

High side on resistance

Low side on resistance

1(*1)

4(*1)

0.75(*1)

0.7(*1)

1.1(*1)

0.5(*1)

1.7(*1)

High side source current

High side sink current

Low side source current

Low side sink current

V_DRVH= 2.5V

V_DRVL= 2.5V

From DRVH turn off to DRVL turn on.

And reverse it.

Dead time

t_DEAD

10

20

-

ns

BOOST SWITCH

I_BST= 10mA

Boost switch on resistance

BST leak current

R_BST

-

30

50

Ω

I_LKBST

V_BST= 30V

0.1

1.0

μA

*1: No production tested, ensure by design.

Document Number: 002-08449 Rev *A

Page 21 of 46

MB39C502/503/504

8. Protections and Power Good function

8.1 Description

(MB39C502/C503/C504)

This PWM Control IC has some protection functions UVLO, OVP, UVP, ILIM, and TSD for the assumed various power

system failures. Details of these protections are written as follows.

Under Voltage Lockout (UVLO)

The under voltage lockout (UVLO) protects ICs from malfunction and protects the system from

destruction/deterioration, according to the reasons mentioned below.

 Transitional state when the voltage inputs to VCC (5V power supply) terminal.

 Momentary decrease

To prevent such a malfunction, this function detects a voltage drop of the 5V power supply, and stops IC operations.

When the voltage of 5V power supply exceeds the threshold voltage of the under voltage lockout protection circuit, the

system is restored.

Over Voltage Protection (OVP)

This function stops the output voltage when the output voltage has increased, and protects devices connected to the

output. When the over voltage is detected, the controller is fixed that the high side switching FET is turned off and the

low side switching FET is turned on with 10μs propagation delay. When the enable is reentered, this fixed state is

released and beginning soft start.

Under Voltage Protection (UVP)

This function stops the output voltage when the output voltage has lowered, and protects devices connected to the

output. When the under voltage is detected, the controller is fixed that the high side switching FET is turned off and the

low side switching FET is turned off with 100μs propagation delay. When the enable is reentered, this fixed state is

released and beginning soft start.

Over Current Limitation (ILIM)

This function limits the output current when it has increased, and protects devices connected to the output. This

function detects the inductor valley current with current sense resister RSENSE. The differential voltage of the

CSP-CSN terminals is amplified to x20 by internal current sense amplifier, and compared to the limit voltage of 480mV

fixed at internal preset condition. Until the amplified voltage fall the limit voltage, the high side switching FET is held in

the off state. After the voltage has fallen below the limit voltage, the high side switching FET is placed into the ON

state. This limits the lower bound of the inductor current and also restricts the over current. As a result, it becomes

operation that the output voltage droops.

Thermal Shutdown (TSD)

This function prevents the PWM Control IC from a thermal destruction. If the junction temperature reaches +150°C,

the high side and low side switching FET are turned off. Then the discharge operation is carried out to discharge the

output capacitor (The discharge operation continues until the state of the thermal shutdown released). If the junction

temperature drops to +125°C, the soft start is automatically reactivated.

Power Good (PWRGD)

Power good flag is hoisted at PWRGD terminal (Open Drain) to “Hi-Z” level with 50μs propagation delay, when the

output voltage becomes larger than 92% of the output setting voltage. It is related by the OVP protection written

above. When the output voltage becomes lower than power good threshold level, the PWRGD terminal is changed to

“L” level with 10μs propagation delay.

Document Number: 002-08449 Rev *A

Page 22 of 46

MB39C502/503/504

State Table of Protection Function

(MB39C502/C503/C504)

High Side

FET

Low Side

FET

Output

state

Protection Function

Under Voltage Lockout (UVLO)

Over Voltage Protection (OVP)

Remarks

After releasing UVLO, the System is an automatic

restoration with soft start.

OFF

ON

OFF

Latch

OFF

Latch

OFF

−

Latch stall.

OFF

It returns the System by enable reentry.

Latch stall.

Under Voltage Protection (UVP)

OFF

It returns the System by enable reentry.

The output voltage is drooped with current limitation.

Over Current Limitation (ILIM)

Thermal Shutdown (TSD)

Switching

OFF

Switching

OFF

After releasing TSD, the System is an automatic

restoration with soft start.

OFF

8.2 Timing Chart

(MB39C502/C503/C504)

Under Voltage Lockout Protection (UVLO)

Turn On

EN

5V

Power on Reset

200us – 1000us

VCC

Power on Reset

240us

UVLO

DRVH

DRVL

VOUT ≥ 92% of

Setting Voltage

VOUT

Power “Good”

PGOOD

To VCC

50us

Propagation Delay

time

Document Number: 002-08449 Rev *A

Page 23 of 46

MB39C502/503/504

Over Voltage Protection (OVP)

Turn On

EN

Turn Off

5V

VCC

Power on Reset

200us – 1000us

UVLO

DRVH

DRVL

VOUT ≥ 92% of

Setting Voltage

VOUT

OVP

10us

Propagation Delay

Power “Good”

PGOOD

To VCC

50us

Propagation Delay

time

Document Number: 002-08449 Rev *A

Page 24 of 46

MB39C502/503/504

Under Voltage Protection (UVP)

Turn On

EN

Turn Off

5V

VCC

Power on Reset

200us – 1000us

UVLO

DRVH

DRVL

VOUT ≥ 92% of

Setting Voltage

VOUT ≤ 87% of

VOUT

UVP

Setting Voltage

100us

Propagation Delay

10us

Propagation Delay

Power “Good”

PGOOD

To VCC

50us

Propagation Delay

time

Document Number: 002-08449 Rev *A

Page 25 of 46

MB39C502/503/504

Over Current Limitation (ILIM)

ILIM Detection Level

Keep the off state of the high side FET until

the detection value is gained

IL

IOUT

DRVH

DRVL

VOUT

VOUT Setting Voltage

VOUT ≤ 87% of Setting Voltage

Power “Good”

PGOOD

To VCC

10us

Propagation Delay

Power “Bad”

time

Document Number: 002-08449 Rev *A

Page 26 of 46

MB39C502/503/504

Thermal Shutdown (TSD)

Turn On

EN

5V

VCC

Power on Reset

200us – 1000us

Power on Reset

UVLO

DRVH

DRVL

VOUT ≥ 92% of

Setting Voltage

VOUT

TSD

Tj >150degC

Tj <125degC

Power “Good”

PGOOD

To VCC

50us

Propagation Delay

time

9. Enhanced LPM Description

(MB39C502/C503/C504)

This PWM controller has some features for high efficiency technology with “Ultra low quiescent current” and “Extended

on time” on asserting SLP_L signal from the system.

Notes

−

Perform transferring to Enhanced LPM in the static switching state after 2ms from EN turn on. The soft starting

on the enabling Enhanced LPM does not allow this controller.

−

In Enhanced LPM, maximum loading current is less than critical current of “Discontinuous Conductive Mode”, in

other words “pulse skip mode”.

Document Number: 002-08449 Rev *A

Page 27 of 46

MB39C502/503/504

Enhanced LPM Assertion Timming

Maximum Loading Current in Enhanced LPM

Switching

Frequency

EN turn on

Discontinuous

Continuous

Conductive Mode

(Pulse Skip Mode)

Conductive Mode

EN

Brank 2ms from EN turn on

Permission

Prohibition

Load Current

SLP_N

Enhanced LPM Assertion

Critical Current

9.1 Ultra Low Quiescent Current

(MB39C502/C503/C504)

This controller has the feature of “Ultra low quiescent current” 30uA in enhanced LPM. So that the IC power loss is

effectively improved efficiency in DCDC light load.

9.2 Extended On Time

(MB39C502/C503/C504)

This controller uses feed forward on-time architecture with the information of input and output voltage. And this

controller is transferred “Extended on-time” keeping the input and output voltage information in enhanced LPM. BY the

on time is extended, gate drive loss is reduced by decreasing the switching frequency.

In Normal Operation

In Enhanced LPM Operation

On time depended on VIN and VOUT voltage

and x1.41 for normal operation

On time depended on VIN and VOUT voltage

High side

gate

High side

gate

Inductor

current

Inductor

current

0A

Document Number: 002-08449 Rev *A

Page 28 of 46

MB39C502/503/504

9.3 Timing Chart of Enhanced LPM

(MB39C502/C503/C504)

This controller is transferred to enhanced LPM synchronized the zero crossing of inductor current, and transferred to

normal operation with 100ns propagation delay avoid the switching period.

I_LOAD

SLP_N

I_LOAD

SLP_N

< 100ns

normal

0A

VR mode

low power

Inductor

current

Inductor

current

synchronized with zero cross

flag of Inductor Current

anytime for idle period

Idle state

0A

Idle state

I_LOAD

SLP_N

I_LOAD

SLP_N

-1

< 1.25us (< f_{SW_CCM}

normal

)

normal

0A

VR mode

keep the normal mode

low power

Wait the timing

becomes to an idle

mode

Inductor

current

Inductor

current

0A

Idle state

Document Number: 002-08449 Rev *A

Page 29 of 46

MB39C502/503/504

10.Over Current Alerting Description

(MB39C502/C503)

This controller has “Over Current Alerting” function. In near over current limitation range, the ALERT_N with Nch open

drain terminal is change to “L” level. Over current alerting level is set 85% for over current limitation level.

Over Current

Alerting Range

V_OUT

Over current alerting level

is set 85% of over current

limitation level

I_OUT

I_{OUT_MAX}

I_{OUT_OCALERT}

I_{OUT_LIMIT}

Document Number: 002-08449 Rev *A

Page 30 of 46

MB39C502/503/504

11.Application Note

11.1 Setting Operating Conditions

11.1.1

Setting Output Voltage

The output voltage can be set by adjusting the setting output voltage resister ratio. Setting output voltage is calculated

by the following formula.

(MB39C502)

R1 R2

R2

V_OUT



0.7

(MB39C503/C504)

R1 R2

V_OUT



1.0

R2

V_OUT

: output setting voltage (V)

R1, R2

: Feedback resistor (Ω)

The total resistor value (R1+R2) of the setting output resistor should be selected up to 300kΩ.

When the output voltage setting value is higher than 1.2V, select resistance that the current of 300μA or more flows

into feedback resistor.

11.1.2

Setting Over Current Limitation and Over Current Alerting

The over current limitation value can be set by adjusting the current sense resistor. Calculate the resister value by the

following formula.

(MB39C502)



^1





ΔI_LV_OUT30010^9



R_SENSE 0.024 I_LIMIT







2

L



(MB39C503/C504)



^1

I_LV_OUT30010^9





R_SENSE 0.025 I_LIMIT





2

L





R_SENSE

I_LIMIT

ΔI_L

: Over current limitation value setting resister (Ω)

: Over current limitation value (A)

: Inductor ripple current peak to peak value (A)

: Output Voltage (V)

V_OUT

L

: Inductance (H)

Document Number: 002-08449 Rev *A

Page 31 of 46

MB39C502/503/504

The over current limitation value needs to set a sufficient margin against the maximum load current.

The over current alerting value is set with over current limitation value as following formula.

(MB39C503/C504)

V_OUT30010^9

2 L

ΔI_L













0.024

I _ALERT





0.85

R_SENSE

2

R_SENSE

I_ALERT

ΔI_L

: Over current limitation value setting resister (Ω)

: Over current Alerting value (A)

: Inductor ripple current peak to peak value (A)

: Output Voltage (V)

V_OUT

L

: Inductance (H)

11.2 Selection Parts

11.2.1 Selection of Smoothing Inductor

(MB39C502/C503/C504)

As a rough guide, inductance of an inductor should keep the peak to peak value of inductor ripple current below 50%

of the maximum output current. The inductance fulfilling the above condition can be found by the following formula.

V_INV_OUT

LOR I_{OUT _ MAX}V_IN f_SW

V_OUT

L 



L

: Inductance (H)

I_{OUT_MAX}: Maximum load current

LOR

V_IN

: Inductor ripple current peak to peak value – Maximum output current ratio (less than 0.5)

: Power supply voltage (V)

: Output Voltage (V)

V_OUT

f_SW

: Switching frequency (Hz)

The minimum output current (critical current) in the condition that inductor current does not flow in reverse can be

found by the following formula.

V_OUTV_INV_OUT

2 L V_IN f_SW

I_OC





I_OC

L

: Critical current (A)

: Inductance (H)

V_IN

V_OUT

f_SW

: Power supply voltage (V)

: Output voltage (V)

: Switching frequency (Hz)

The maximum value of the current flowing through the inductor needs to be found in order to determine whether the

current flowing through the inductor is within the rated value. The maximum current flowing through the inductor can

be found by the following formula.

Document Number: 002-08449 Rev *A

Page 32 of 46

MB39C502/503/504

ΔI_L

I_{L _ MAX} I_{OUT _ MAX}



2

I_{L_MAX}

: Maximum inductor current (A)

I_{OUT_MAX}: Maximum load current (A)

ΔI_L

: Inductor ripple current peak to peak value (A)

11.2.2

Selection of Switching FET

(MB39C502/C503/C504)

In general, MOSFET should be used with a 30V absolute maximum rating. Obtain the maximum value of the current

flowing through the switching FET in order to determine whether the current flowing through the switching FET is

within the rated value. The maximum current flowing through the switching FET can be found by the following formula.

ΔI_L

I_{D _ MAX} I_{OUT _ MAX}



2

I_{D_MAX}

: Maximum switching FET drain current (A)

I_{OUT_MAX}: Maximum load current (A)

ΔI_L

: Inductor ripple current peak to peak value (A)

In addition, find the loss of the switching FET in order to determine whether the allowable loss of the switching is

within the rated value. The allowable loss of the high side FET can be found by the following formula.

P

 P

 R_{SW _ HS}

FET _ HS

RON _ HS

P_{FET_HS}: Overall Loss of high side FET (W)

P_{RON_HS}: Conduction loss of high side FET (W)

P_{SW_HS}

: Switching loss of high side FET (W)

The conduction loss of high side is followed as.

V_OUT

P_{RON _ HS} I_{OUT _ MAX}²

 R_ON

_ HS

V_IN

P_{RON_HS}: Conduction loss of high side FET (W)

I_{OUT_MAX}: Maximum load current (A)

V_IN

: Power supply voltage (V)

: Output voltage (V)

V_OUT

R_{ON_HS}

: On resistance of high side FET (Ω)

The switching loss of high side is followed as.

P

1.56V_IN f_SW I_{OUT _ MAX}Q_SW

SW _ HS

P_{SW_HS}

V_IN

: Switching loss of high side FET (W)

: Power supply voltage (V)

f_SW

: Switching frequency (Hz)

I_{OUT_MAX}: Maximum load current (A)

Q_SW

: Amount of high side FET gate switch electric charge (C)

Document Number: 002-08449 Rev *A

Page 33 of 46

MB39C502/503/504

MOSFET has a tendency where the gate drive loss increases because lower voltage product has the bigger amount

of gate electric charge (Q_G). Normally, we recommend a 4V drive product, however, the idle period at light load (both

the high side FET and the low side FET is off period) get longer and the gate drive voltage of the high side FET may

decrease, in the automatic PFM/PWM transition. The voltage drops most at no load mode. At the time, confirm that the

boost voltage (voltage between BST-LX pins) is a big enough value for the gate threshold value voltage of the high

side FET.

If it is not enough, consider adding the boost diode, increasing the capacitor value of the capacitor or using a 2.5V (or

1.8V) drive product to the high side FET.

The allowable loss of the low side FET can be found by the following formula.









V_OUT

V_IN

2



P_{FET _ LS} P_{RON _ LS} I_{OUT _ MAX} 1

 R_{ON _ LS}





P_{FET_LS}

: Overall loss of low side FET (W)

P_{RON_LS}: Conduction loss of low side FET (W)

I_{OUT_MAX}: Maximum output current (A)

V_IN

: Switching power supply voltage (V)

: Output voltage (V)

V_OUT

R_{ON_LS}

: On resistance of low side FET (Ω)

In switching of low side FET, the transiting voltage between drain to source is generally small. The switching FET loss

is omitted in this document as it is negligible.

Document Number: 002-08449 Rev *A

Page 34 of 46

MB39C502/503/504

11.2.3

Selection of Fly Back Diode

(MB39C502/C503/C504)

This device is improved by adding the fly back diode when the conversion efficiency improvement or the suppression

of the low side FET fever is desired, although those are unnecessary to execute normally. The effect is achieved in the

condition where the switching frequency is high or output voltage is lower. Select period for the electric current flow

into fly back diode is limited to dead time period because the synchronous rectification system is adopted (as for the

dead time, see “Electrical Characteristics”). Each rating for the fly back diode can be calculated by the following

formula.

I_D I_{OUT _ MAX} f_SW





t_D1 t_D2



I_D

: Forward current rating of SBD (A)

I_{OUT_MAX}: Maximum load current (A)

f_SW

: Switching frequency (Hz)

: Dead times (s)

t_D1, t_D2

I_L

2

I_FSM I_{OUT _ MAX}



I_FSM

: Rated value of fly back diode (V)

I_{OUT_MAX}: Maximum output current (A)

ΔI_L

: Inductor ripple current peak to peak value (A)

V_{R _ FLY}V_IN

V_{R_FLY}

V_IN

: DC reversing voltage of fly back diode (V)

: Switching power supply voltage (V)

11.2.4

Selection of Boost Diode

(MB39C502)

Select a schottky barrier diode (SBD) that has a small forward voltage drop. The current to drive the gate of High-side

FET flows to the SBD of the boost circuit. The average current can be found by the following formula. Select a boost

diode that keep the average current below the current rating.

I_D Q_{G _ HS} f_SW

I_D

: Forward current (A)

Q_{G_HS}

f_SW

: Total gate electric charge of high-side FET (C)

: Switching Frequency (Hz)

The rating of the boost diode can be found by the following formula.

V_{R _ BOOST}V_IN

V_{R_BOOST}: Boost Diode DC reverse voltage (V)

V_IN

: Switching power supply voltage (V)

Document Number: 002-08449 Rev *A

Page 35 of 46

MB39C502/503/504

11.2.5

Selection of Input Capacitor

(MB39C502/C503/C504)

Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the tantalum

capacitor and the polymer capacitor of low ESR when a mass capacitor is needed as the ceramic capacitor cannot

support.

The ripple voltage is generated in the power supply voltage by the switching operation. Calculate the lower bound of

input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of the power supply from the

following formula.

I_{OUT _ MAX}

V_OUT

ΔI_L







ΔV_IN





 ESR I





OUT _ MAX

C_IN

V_IN f_SW

2





ΔV_IN

: Power supply ripple voltage peak to peak value (V)

I_{OUT_MAX}: Maximum load current (A)

C_IN

: Input capacitance (F)

V_IN

: Power supply voltage (V)

V_OUT

f_SW

: Output voltage (V)

: Switching frequency (Hz)

ESR

ΔI_L

: Series resistance component of input capacitor (Ω)

: Ripple current peak to peak value of inductor (A)

Capacitor has frequency characteristics, the temperature characteristics, and the voltage characteristics, etc. The

effective capacitance might become extremely small depending on the use conditions. Note the effective capacitance

in the use conditions.

Calculate ratings of the input capacitor by following formula.

V_CIN V_IN

V_CIN

V_IN

: Withstand voltage of the input capacitor (V)

: Power supply voltage (V)

V_OUT





V_INV_OUT



Irms  I_{OUT _ MAX}



V_IN

Irms

: Allowable ripple current of input capacitor (effective value) (A)

I_{OUT_MAX}: Maximum load current (A)

V_IN

: Power supply voltage (V)

: Output voltage (V)

V_OUT

Document Number: 002-08449 Rev *A

Page 36 of 46

MB39C502/503/504

11.2.6

Selection of Output Capacitor

Since a high ESR causes the output ripple voltage to increase, a low ESR capacitor is needs to be used in order to

reduce the output ripple voltage. Generally, the ceramic capacitor is used as the output capacitor. With the switching

ripple voltage taken consideration, the minimum capacitance required can be found by the following formula.

(MB39C502/C503/C504)

1

C_OUT



2π  f_SW





ΔV_OUTΔI_L ESR



C_OUT

ESR

ΔV_OUT

ΔI_L

: Output capacitance (F)

: Series resistance element of output capacitor (Ω)

: Output ripple voltage (V)

: Inductor ripple current peak to peak value (A)

Also, it is necessary to unite a pole by the output capacitor and the output load with a zero by the internal

compensation circuit, and to limit the crossover frequency. The minimum capacitance required can be found by the

following formula.

(MB39C502)

I_{OUT_ MAX}

C_OUT 42.510^6



V_OUT

(MB39C503)

I_{OUT_MAX}

V_OUT

C_OUT 49.0 10^6

(MB39C504)

C_OUT 21.710^6I_{OUT_ MAX}

(MB39C502)

1

C_OUT 0.5910^6



R_SENSEV_OUT

(MB39C503)

1

C_OUT 0.6710^6

R_SENSE V_OUT

(MB39C504)

1

C_OUT 0.2710^6



R_SENSE

I_{OUT_MAX}: Maximum output load current (A)

V_OUT

: Output voltage (V)

R_SENSE

: Over current limitation value setting resister (Ω)

Document Number: 002-08449 Rev *A

Page 37 of 46

MB39C502/503/504

Moreover, the output capacitance is also derived from the allowable amount of overshoot and under shoot. Adjust the

capacitance so that the overshoot/undershoot voltage should not exceed the target voltage range.

11.2.7

Selection of Boost Capacitor

To drive the gate of high side FET, the boost capacitor must have enough stored charge. 0.47μF is assumed to be

standard; however, it is necessary to adjust it when the high side FET Q_Gis big. Consider the capacitance calculated

by the following formula as the lowest value for the boost capacitance and select a thing anymore.

(MB39C502/C503/C504)

C_BST10Q_{G _ HS}

C_BST

: Boost capacitance (F)

Q_{G_HS}

: Amount of high side FET gate charge (C)

Calculate ratings of the boost capacitor by the following formula.

(MB39C502/C503)

V_CBST V_VDD

(MB39C504)

V_CBSTV_LDO5

V_CBST

V_VDD

: Withstand voltage of the boost capacitor (V)

: Input voltage of VDD terminal (V)

V_LDO5

: Input voltage of LDO5 terminal (V)

Document Number: 002-08449 Rev *A

Page 38 of 46

MB39C502/503/504

11.2.8

Selection of VDD Capacitor

4.7μF is assumed to be a standard, and when Q_Gof switching FET used large, it is necessary to adjust it. To suppress

the ripple voltage by the switching FET gate drive, consider the capacitance calculated by the following formula as the

lowest value for VDD Capacitor and select a thing any more.

Calculate ratings of the VDD terminal capacitor by the following formula.

(MB39C502/C503)

C_VDD 50Q_G

(MB39C504)

C_LDO5 50 Q_G

C_VDD

C_LDO5

Q_G

: VDD pin capacitance (F)

: LDO5 pin capacitance (F)

: Total amount of high and low side FETs gate charge (C)

Calculate ratings of the VDD terminal capacitor by the following formula.

(MB39C502/C503)

V_CVDD V_VDD

(MB39C504)

V_CLDO5V_LDO5

V_CVDD

V_VDD

: Withstand voltage of the VDD terminal capacitor (V)

: Input voltage of VDD terminal (V)

V_CLDO5

V_LDO5

: Withstand voltage of the LDO5 terminal capacitor (V)

: Input voltage of LDO5 terminal (V)

11.2.9

Selection of VCC Capacitor and Resistor

(MB39C502/C503)

Connect 1.0μF between VCC to AGND terminal. Connect 10Ω between VCC to VDD terminal.

(MB39C504)

Connect 1.0μF between VCC to AGND terminal. Connect 10Ω between VCC to LDO5 terminal.

Document Number: 002-08449 Rev *A

Page 39 of 46

MB39C502/503/504

11.3 Layout

(MB39C502/C503)

Consider the points listed below and do the layout design.

 Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor connected with

the VCC and VDD pins, and AGND pin of the switching system parts with switching system GND (PGND). Connect

other GND connection pins with control system GND (AGND), and separate each GND, and try not to pass the

heavy current path through the control system GND (AGND) as much as possible. In that case, connect control

system GND (AGND) and switching system GND (PGND) at the single point of GND (PGND) directly below IC.

Switching system parts are Input capacitor (C_IN), Switching FET, fly back diode (SBD), inductor (L) and Output

capacitor (C_OUT).

 Connect the switching system parts as much as possible on the surface. Avoid the connection through the through

hole as much as possible.

 As for AGND pins of the switching system parts, provide the through hole at the proximal place, and connect it with

GND of internal layer.

 Pay the most attention to the loop composed of input capacitor (C_IN), switching FET, and fly back diode (SBD).

Consider parts are disposed mutually to be near for making the current loop as small as possible.

 Place the bootstrap capacitor (C_BST) proximal to BST and LX pins of IC as much as possible.

 Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current flows momentary

in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.

 Large electric current flows momentary in the net of DRVH and DRVL pins connected with the gate of switching

FET. Wire the line width of about 0.8 mm to be a standard, as short as possible. Take special care about the line of

the DRVL pin, and wire the line as short as possible.

 By-pass capacitor (C_VCC, C_VDD) connected with VCC, and VDD should be placed close to the pin as much as

possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal through-hole.

 Pull the feedback line to be connected to the FB pin of the IC separately from near the output capacitor pin,

whenever possible. Consider the line connected with FB pins to keep away from a switching system parts as much

as possible because it is sensitive to the noise.

Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to the FB pin.

In addition, for the internal layer right under the component mounting place, provide the control system GND

(AGND) of few ripple and few spike noises, or provide the ground plane of the power supply as much as possible.

Consider that the discharge current momentary flows into the CSN pin (about 10mA at 1.0V output voltage) when

the DC/DC operation stops, and then sustain the width for the feedback line.

There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and parts

sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with

inductor).

Document Number: 002-08449 Rev *A

Page 40 of 46

MB39C502/503/504

GND routing example

Layout example of switching components

High Side

Switching FET

Surface Layer

VIN

C_BST

To LX

C_VIN

PGND

Low Side

Switching FET

Output

Capacitor

SBD

(Optional)

C_VCC

C_VIN

(Top View)

EP :AGND

Sense

Resistor

PGND

Inductor

VOUT

Inner Layer :

AGND

Inner Layer :

PGND

C_VDD

To CSP

To CSN

VOUT Sense

Connect the PGND to the AGND at single

point directly under the IC

Document Number: 002-08449 Rev *A

Page 41 of 46

MB39C502/503/504

(MB39C504)

Consider the points listed below and do the layout design.

 Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor connected with

the VCC and LDO5 pins, and AGND pin of the switching system parts with switching system GND (PGND).

Connect other GND connection pins with control system GND (AGND), and separate each GND, and try not to

pass the heavy current path through the control system GND (AGND) as much as possible. In that case, connect

control system GND (AGND) and switching system GND (PGND) at the single point of GND (PGND) directly below

IC. Switching system parts are Input capacitor (C_IN), Switching FET, fly back diode (SBD), inductor (L) and Output

capacitor (C_OUT).

 Connect the switching system parts as much as possible on the surface. Avoid the connection through the through

hole as much as possible.

 As for AGND pins of the switching system parts, provide the through hole at the proximal place, and connect it with

GND of internal layer.

 Pay the most attention to the loop composed of input capacitor (C_IN), switching FET, and fly back diode (SBD).

Consider parts are disposed mutually to be near for making the current loop as small as possible.

 Place the bootstrap capacitor (C_BST) proximal to BST and LX pins of IC as much as possible.

 Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current flows momentary

in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.

 Large electric current flows momentary in the net of DRVH and DRVL pins connected with the gate of switching

FET. Wire the line width of about 0.8 mm to be a standard, as short as possible. Take special care about the line of

the DRVL pin, and wire the line as short as possible.

 By-pass capacitor (C_VCC, C_LDO5) connected with VCC, and LDO5 should be placed close to the pin as much as

possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal through-hole.

 Pull the feedback line to be connected to the FB pin of the IC separately from near the output capacitor pin,

whenever possible. Consider the line connected with FB pins to keep away from a switching system parts as much

as possible because it is sensitive to the noise.

Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to the FB pin.

In addition, for the internal layer right under the component mounting place, provide the control system GND

(AGND) of few ripple and few spike noises, or provide the ground plane of the power supply as much as possible.

Consider that the discharge current momentary flows into the CSN pin (about 10mA at 1.0V output voltage) when

the DC/DC operation stops, and then sustain the width for the feedback line.

There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and parts

sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with

inductor).

Document Number: 002-08449 Rev *A

Page 42 of 46

MB39C502/503/504

GND routing example

Layout example of switching components

High Side

Surface Layer

Switching FET

VIN

C_BST

To LX

C_VIN

PGND

Low Side

Switching FET

Output

Capacitor

SBD

(Optional)

C_VCC

C_VIN

(Top View)

EP :AGND

Sense

Resistor

PGND

Inductor

VOUT

Inner Layer :

AGND

Inner Layer :

PGND

C_LDO5

To CSP

To CSN

VOUT Sense

Connect the PGND to the AGND at single

point directly under the IC

12.Ordering Information

Table 12-1 Ordering information

Part number

Package

Remarks

MB39C502WQN-G-AMERE1

16-pin plastic QFN

(WN2016)

MB39C503WQN-G-AMERE1

MB39C504WQN-G-AMERE1

Document Number: 002-08449 Rev *A

Page 43 of 46

MB39C502/503/504

13.Package Dimensions

Document Number: 002-08449 Rev *A

Page 44 of 46

MB39C502/503/504

14.Major Changes

Spansion Publication Number: MB39C502_DS405-00020-1v0-E

Page

Section

Change Results

Revision 1.0

-

Initial release

NOTE: Please see “Document History” about later revised information.

Document History

Document Title: MB39C502/503/504 High Efficiency Step Down DC/DC Controller Datasheet

Document Number: 002-08449

Orig. of Submission

Revision

ECN

Description of Change

Change

Date

Migrated to Cypress and assigned document number 002-08449.

No change to document contents or format.

**

TAOA

09/09/2014



*A

5127378

TAOA

02/12/2016 Updated to Cypress template

Document Number: 002-08449 Rev *A

Page 45 of 46

MB39C502/503/504

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.

To find the office closest to you, visit us at Cypress Locations.

Products

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Interface

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psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

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Technical Support

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cypress.com/go/memory

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cypress.com/go/support

Spansion Products cypress.com/spansion products

Cypress^®, the Cypress logo, Spansion^®, the Spansion logo, MirrorBit^®, MirrorBit^®Eclipse^TM, ORNAND^TM, Easy DesignSim^TM, Traveo^TMand combinations thereof, are trademarks

and registered trademarks of Cypress Semiconductor Corp. ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or

registered trademarks referenced herein are the property of their respective owners.

responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress

products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement

with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be

expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use

and in doing so indemnifies Cypress against all charges.

This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United

States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to

copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in

support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation,

compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the

materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion

of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 002-08449 Rev *A

Page 46 of 46


型号：	MB39C503WQN-G-AMERE1
厂家：	CYPRESS
描述：	High Efficiency Step Down DC/DC Controller Datasheet
文件：	总46页 (文件大小：1171K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB39C503WQN-G-AMERE1 [CYPRESS]

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SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E