MB89PV490CF [CYPRESS]
Microcontroller, 8-Bit, CMOS, CQFP100, 0.65 MM PITCH, CERAMIC, MQFP-100;
| 型号： | MB89PV490CF |
| 厂家： | 
CYPRESS |
| 描述： | Microcontroller, 8-Bit, CMOS, CQFP100, 0.65 MM PITCH, CERAMIC, MQFP-100 可编程只读存储器 电动程控只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总61页 (文件大小：1678K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12560-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89490 Series
MB89498/F499/PV490
■ DESCRIPTION
The MB89490 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit single-chip microcontrollers.
In addition to a compact instruction set, the general-purpose, single-chip microcontroller contains a variety of
peripheral functions such as 21-bit timebase timer, watch prescaler, PWM timer, 8/16-bit timer/counter, remote
receiver circuit, LCD controller/driver, external interrupt 0 (edge) , external interrupt 1 (level) , 10-bit A/D converter,
UART/SIO, SIO, I2C and watchdog timer reset.
The MB89490 series is designed suitable for compact disc/radio receiver controller as well as in a wide range of
applications for consumer product.
* : F2MC is the abbreviation for Fujitsu Flexible Microcontroller.
■ FEATURES
• Package
QFP, LQFP package for MB89F499, MB89498
MQFP package for MB89PV490
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.9
MB89490 Series
(Continued)
• High speed operating capability at low voltage
• Minimum execution time : 0.32 µs/12.5 MHz
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Branch instructions by test bit
Bit manipulation instructions, etc.
Instruction set optimized for controllers
• PLL circuit for sub-clock
• Embedded for PLL clock multiplication circuit for sub-clock
• Operating clock (PLL for sub-clock) can be selected from no multiplication or 4 times of the sub-clock
oscillation frequency.
• 6 timers
PWM timer × 2
8/16-bit timer/counter × 2
21-bit timebase timer
Watch prescaler
• External interrupt
Edge detection (selectable edge) : 8 channels
Low level interrupt (wake-up function) : 8 channels
• 10-bit A/D converter (8 channels)
10-bit successive approximation type
• UART/SIO
Synchronous/asynchronous data transfer capability
• SIO
Switching of synchronous data transfer capability
• LCD controller/driver
Max 32 segments output × 4 commons
• I2C interface circuit
• Remote receiver circuit
• Low-power consumption mode
Stop mode (oscillation stops so as to minimize the current consumption.)
Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.)
Watch mode (operation except the watch prescaler stops so as to reduce the power comsumption to an
extremely low level.)
Sub-clock mode
• Watchdog timer reset
• I/O ports : Max 66 channels
2
DS07-12560-2E
MB89490 Series
■ PRODUCT LINEUP
Part number
Parameter
MB89498
MB89F499
MB89PV490
Piggy-back
(For evaluation or
development)
Mass production products
(mask ROM product)
Classification
FLASH
48 K × 8-bit
60 K × 8-bit
60 K × 8-bit
ROM size
RAM size
(internal ROM)
(internal FLASH)
(external ROM) *
2 K × 8-bit
2 K × 8-bit
2 K × 8-bit
Number of instructions
Instruction bit length
Instruction length
Data bit length
: 136
: 8-bit
: 1 to 3 bytes
: 1-bit, 8-bit, 16-bit
CPU functions
Minimum instruction execution time : 0.32 µs/12.5 MHz
Minimum interrupt processing time : 2.88 µs/12.5 MHz
General-purpose I/O ports (CMOS) : 56 pins
Input ports (CMOS)
N-channel open drain I/O ports
Total
: 2 pins
: 8 pins
: 66 pins
Ports
21-bit timebase
timer
Interrupt generation cycle (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz
Reset generation cycle (167.8 ms to 335.5 ms) at 12.5 MHz
Watchdog timer
8-bit reload timer operation (supports square wave output and operating clock period :
1 tinst, 8 tinst, 16 tinst, 64 tinst )
PWM timer 0, 1
8-bit accuracy PWM operation
Can be operated either as a 2-channel 8-bit timer/counter (timer 00 and timer 01, each
8/16-bit timer/counter with its own independent operating clock) , or as one 16-bit timer/counter.
00, 01
In timer 00 or 16-bit timer/counter operation, event counter operation by external clock
input and square wave output capability
Can be operated either as a 2-channel 8-bit timer/counter (timer 10 and timer 11, each
8/16-bit timer/counter with its own independent operating clock) , or as one 16-bit timer/counter.
10, 11
In timer 10-bit or 16-bit timer/counter operation, event counter operation by external clock
input and square wave output capability
External interrupt 0
(edge)
8 independent channels (selectable edge, interrupt vector, request flag)
8 channels (low level interrupt)
External interrupt 1
(level)
10-bit accuracy × 8 channels
A/D conversion function (conversion time : 30 tinst )
Supports repeated activation by internal clock
A/D converter
Common output
Segment output
LCD driving power (bias) pins
LCD display RAM size
: 4 (Max)
: 32 (Max)
: 3
LCD controller/driver
: 32 × 4 bits
(Continued)
DS07-12560-2E
3
MB89490 Series
(Continued)
Part number
Parameter
MB89498
MB89F499
MB89PV490
Synchronous/asynchronous data transfer capability
(Max baud rate : 97.656 Kbps at 12.5 MHz)
UART/SIO
(7-bit and 8-bit with parity bit; 8-bit and 9-bit without parity bit)
8-bit serial I/O with LSB first/MSB first selectability
SIO
I2C
1 clock selectable from 4 operation clock (1 external shift clock and 3 internal shift clock :
0.64 µs, 2.56 µs, 10.24 µs at 12.5 MHz)
1 channel
(Use a 2-wire protocol to communicate with other device)
Remote receiver
circuit
Selectable maximum noise width removal
Reversible input polarity
Standby mode
Process
Sleep mode, stop mode, watch mode and sub-clock mode
CMOS
Operating voltage
2.2 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
* : Use MBM27C512 as the external ROM.
4
DS07-12560-2E
MB89490 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Part number
MB89498
MB89F499
MB89PV490
Parameter
FPT-100P-M06
FPT-100P-M20
MQP-100C-P01
O
O
×
O
O
×
×
×
O
O : Availabe
× : Not available
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggy-back product, verify its differences from the product that will be actually used.
Take particular care on the following point : The stack area is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV490, add the current consumed by the EPROM mounted in the piggy-back socket.
• When operating at low speed, the current consumed by the FLASH product is greater than that for the mask
ROM product. However, the current consumption is roughly the same in sleep and stop mode.
• For more information, see “■ ELECTRICAL CHARACTERISTICS”.
3. Oscillation Stabilization Wait Time after Power-on Reset
• For MB89PV490 and MB89F499, the power-on stabilization wait time cannot be selected after power-on reset.
• For MB89498, the power-on stabilization wait time can be selected after power-on reset.
• For more information, please refer to “■ MASK OPTIONS”.
DS07-12560-2E
5
MB89490 Series
■ PIN ASSIGNMENTS
(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
VCC
*P00
1
2
*P01
3
*P02
4
*P03
5
*P04
6
*P05
7
*P06
8
*P07
9
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22EC0
P23
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
VCC
AVCC
(FPT-100P-M06)
* : High current pins
(Continued)
6
DS07-12560-2E
MB89490 Series
(TOP VIEW)
*P02
*P03
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
2
*P04
3
*P05
4
*P06
5
*P07
6
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22/EC0
P23
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
SEG1
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
(FPT-100P-M20)
* : High current pins
(Continued)
DS07-12560-2E
7
MB89490 Series
(Continued)
(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
V
CC
1
*P00
*P01
2
3
*P02
4
*P03
5
*P04
6
*P05
7
*P06
8
*P07
9
121
122
123
124
125
126
127
128
129
113
112
111
110
109
108
107
106
105
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22EC0
P23
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
VCC
AVCC
* : High current pins
(MQP-100C-P01)
Pin assignment on package top (MB89PV490 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pinname Pin no. Pin name
101
102
103
104
105
106
107
N.C.
A15
A12
A7
108
109
110
111
112
113
114
A3
A2
115
116
117
118
119
120
121
O3
VSS
N.C.
O4
122
123
124
125
126
127
128
O8
CE
129
130
131
132
A8
A13
A14
VCC
A1
A10
OE
A0
A6
N.C.
O1
O2
O5
N.C.
A11
A9
A5
O6
A4
O7
N.C. : As connected internally, do not use.
8
DS07-12560-2E
MB89490 Series
■ PIN DESCRIPTION
Pin number
I/O circuit
type
MQFP*1/
QFP*2
Pin name
Function
LQFP*3
99
98
49
48
96
95
46
45
X0
X1
Connection pins for a crystal or other oscillator circuit.
An external clock can be connected to X0. In this case, leave
X1 open.
A
A
X0A
X1A
Connection pins for a crystal or other oscillator circuit.
An external clock can be connected to X0A. In this case, leave
X1A open.
Input pin for setting the memory access mode.
Connect directly to VSS.
97
94
MOD0
B
J
95, 94
92, 91
P84, P83
General-purpose CMOS input port.
Reset I/O pin. The pin is an N-ch open-drain type with pull-up
resistor and hysteresis input. The pin outputs an “L” level when
an internal reset request is present. Inputting an “L” level initial-
izes internal circuits.
96
93
RST
C
2 to 9
99 to 6
P00 to P07
D
E
General-purpose CMOS I/O port.
P10/INT00
to
P17/INT07
General-purpose CMOS I/O port.
The pin is shared with external interrupt 0 input.
10 to 17 7 to 14
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00 and 01 output.
18
19
15
16
P20/TO0
P21/RMC
F
E
General-purpose CMOS I/O port.
The pin is shared with remote receiver input.
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00 and 01 input.
20
21
22
17
18
19
P22/EC0
P23
E
F
F
General-purpose CMOS I/O port.
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10 and 11 output.
P24/TO1
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10 and 11 input.
23
24
25
20
21
22
P25/EC1
P26/PWM0
P27/PWM1
E
F
F
General-purpose CMOS I/O port.
The pin is shared with PWM0 output.
General-purpose CMOS I/O port.
The pin is shared with PWM1 output.
P30/AN0/INT10
to
P37/AN7/INT17
General-purpose CMOS I/O port.
The pin is shared with external interrupt 1 input and A/D
converter input.
32 to 39 29 to 36
40 to 45 37 to 42
G
P40 to P45
H
H
General-purpose N-ch open-drain I/O port.
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C clock I/O.
46
43
P46/SCL
(Continued)
DS07-12560-2E
9
MB89490 Series
(Continued)
Pin number
I/O circuit
type
MQFP*1/
QFP*2
Pin name
Function
LQFP*3
44
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C data I/O.
47
26
27
28
57
58
P47/SDA
P50/SI0
H
E
General-purpose CMOS I/O port.
The pin is shared with SIO data input.
23
General-purpose CMOS I/O port.
The pin is shared with SIO data output.
24
P51/SO0
P52/SCK0
P53/COM2
P54/COM3
F
General-purpose CMOS I/O port.
The pin is shared with SIO clock I/O.
25
E
General-purpose CMOS I/O port.
The pin is shared with the LCD common output.
54
F/I
F/I
General-purpose CMOS I/O port.
The pin is shared with the LCD common output.
55
P60/SEG16
to
P67/SEG23
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
75 to 82 72 to 79
83 to 90 80 to 87
F/I
F/I
P70/SEG24
to
P77/SEG31
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data input.
91
92
93
88
89
90
P80/SI1
P81/SO1
P82/SCK1
E
F
E
I
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data output.
General-purpose CMOS I/O port.
The pin is shared with UART/SIO clock I/O.
SEG0 to
SEG15
59 to 74 56 to 71
55, 56 52, 53
54, 53, 51, 50,
LCD segment output-only pin.
LCD common output-only pin.
LCD driving power supply pin.
COM0,
COM1
I
V1 to V3
⎯
52
49
1, 51
98, 48
VCC
VSS
⎯
⎯
⎯
⎯
Power supply pin.
50, 100 47, 97
Power supply pin (GND) .
30
29
27
26
AVCC
AVR
A/D converter power supply pin.
A/D converter reference voltage input pin.
A/D converter power supply pin.
Use at the same voltage level as VSS.
31
28
AVSS
⎯
*1 : MQP-100C-P01
*2 : FPT-100P-M06
*3 : FPT-100P-M20
10
DS07-12560-2E
MB89490 Series
• External EPROM Socket (MB89PV490 only)
Pin number
Pin name
I/O
Function
MQFP*
102
131
130
103
127
124
128
129
104
105
106
107
108
109
110
111
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
O
Address output pins.
A4
A3
A2
A1
A0
122
121
120
119
118
115
114
113
O8
O7
O6
O5
O4
O3
O2
O1
I
Data input pins.
101
112
117
126
N.C.
⎯
Internally connected pins. Always leave open.
116
123
125
132
VSS
CE
OE
VCC
O
O
O
O
Power supply pin (GND) .
Chip enable pin for the EPROM. Outputs “H” in standby mode.
Output enable pin for the EPROM. Always outputs “L”.
Power supply pin for the EPROM.
* : MQP-100C-P01
DS07-12560-2E
11
MB89490 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Main/Sub-clock circuit
X1 (X1A)
X0 (X0A)
N-ch P-ch
P-ch
N-ch
A
N-ch
Stop mode control signal
• Hysteresis input
(CMOS input in MB89F499)
• The pull-down resistor
(not available in MB89F499)
Approx. 50 kΩ
B
C
R
• The pull-up resistor (P-channel)
Approx. 50 kΩ
• Hysteresis input
R
P-ch
N-ch
• CMOS output
• IOH = − 4 mA, IOL = 12 mA
• CMOS input
pull-up
resistor register
R
P-ch
P-ch
• Selectable pull-up resistor
Approx. 50 kΩ
D
N-ch
port
• CMOS output
• IOH = − 2 mA, IOL = 4 mA
• CMOS port input
pull-up
resistor register
R
P-ch
P-ch
• Hysteresis resource input
• Selectable pull-up resistor
Approx. 50 kΩ
E
N-ch
port
resource
(Continued)
12
DS07-12560-2E
MB89490 Series
(Continued)
Type
Circuit
Remarks
• CMOS output
pull-up
resistor register
• IOH = − 2 mA, IOL = 4 mA
• CMOS input
R
P-ch
N-ch
• Selectable pull-up resistor
Approx. 50 kΩ
P-ch
F
port
• CMOS output
• IOH = − 2 mA, IOL = 4 mA
• CMOS port input
pull-up
resistor register
R
P-ch
N-ch
P-ch
• VIH = 0.85 VCC, VIL = 0.5 VCC resource input
• Analog input
• Selectable pull-up resistor
Approx. 50 kΩ
G
port
resource
analog
• N-ch open-drain output
• IOL = 15 mA
• CMOS port input
• CMOS resource input
• 5 V tolerance
N-ch
H
port/resource
• LCD segment output
P-ch
N-ch
I
P-ch
N-ch
• CMOS input
J
DS07-12560-2E
13
MB89490 Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS IC if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the maximum ratings.
Also, take care to prevent the analog power supply (AVCC andAVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Stabilization
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. As stabilization guidelines, it is recommended
to control voltage fluctuation so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC
value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms
at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up
from stop mode.
7. Treatment of Unused dedicated LCD pins
When dedicated LCD pins are not in use, keep them open.
14
DS07-12560-2E
MB89490 Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F499
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the internal CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
• 60K bytes × 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors)
• Automatic algorithm (Embedded algorithm : Equivalent to MBM29LV200)
• Includes an erase pause and erase restart function
• Data polling and toggle bit for detection of program/erase completion
• Detection of program/erase completion via CPU interrupt
• Compatible with JEDEC-standard commands
• Sector Protection (sectors can be combined in any combination)
• No. of program/erase cycles : 10,000 (Min)
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase data to the flash memory, the program must first be copied from flash memory to RAM so that programming
can be performed without program access from flash memory.
4. Flash Memory Register
• Flash memory control status register (FMCS)
Bit 7
Bit 6
Bit 5
WE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address
007AH
Initial value
000X00-0B
INTE
RDYINT
RDY Reserved Reserved
⎯
Reserved
R/W
R/W
R/W
R
R/W
R/W
⎯
R/W
DS07-12560-2E
15
MB89490 Series
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector during
CPU access and a flash memory programming.
• Sector configuration of flash memory
Flash Memory
16 K bytes
8 K bytes
CPU Address
FFFFH to C000H
BFFFH to A000H
9FFFH to 8000H
7FFFH to 1000H
Programmer Address*
1FFFFH to 1C000H
1BFFFH to 1A000H
19FFFH to 18000H
17FFFH to 11000H
8 K bytes
28 K bytes
* : The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a general-
purpose programmer.
16
DS07-12560-2E
MB89490 Series
■ PROGRAMMING TO THE EPROM WITH PIGGY-BACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Memory Space
Memory space corresponding to EPROM writer is shown in the diagram below.
Address Normal operating mode
Corresponding addresses
on the EPROM programmer
0000H
0080H
I/O
RAM
0880H
Not available
1000H
1000H
PROM
60 KB
EPROM
60 KB
FFFFH
FFFFH
3. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 1000H to FFFFH.
(3) Program to 1000H to FFFFH with the EPROM programmer.
DS07-12560-2E
17
MB89490 Series
■ BLOCK DIAGRAM
X0
X1
Main clock
oscillator circuit
21-bit timebase
timer
AVCC
AVSS
AVR
Clock controller
X0A
X1A
Sub-clock
oscillator circuit
8
8
10-bit
A/D converter
P37/AN7/INT17
to
P30/AN0/INT10
8
Reset circuit
(Watchdog timer)
RST
CMOS I/O port
External interrupt 1
(level)
Watch prescaler
CMOS I/O port
P23
P47/SDA
P46/SCL
I2C
P26/PWM0
P27/PWM1
P21/RMC
8-bit PWM timer 0
8-bit PWM timer 1
Remote receiver circuit
6
P45 to P40
N-ch open-drain I/O port
CMOS I/O port
P84
P83
8/16-bit
timer/counter 00, 01
P82/SCK1
P81/SO1
P80/SI1
P22/EC0
P20/TO0
P25/EC1
P24/TO1
UART/SIO
SIO
8/16-bit
timer/counter 10, 11
P52/SCK0
P51/SO0
P50/SI0
8
8
8
P17/INT07 to
P10/INT00
External interrupt 0
(edge)
CMOS I/O port
2
2
16
2
P54/COM3,
P53/COM2
CMOS I/O port
SEG0
to SEG15
P07 to P00
Port0*
CMOS I/O port
LCD controller/driver
COM0,
COM1
RAM (2 K bytes)
3
32 × 4-bit display
RAM (16 bytes)
V1 to V3
F2MC-8L
CPU
8
8
P67/SEG23
to P60/SEG16
16
P77/SEG31
to P70/SEG24
ROM 48 K bytes/FLASH 60 K bytes
CMOS I/O port
Other pins
VCC × 2, VSS × 2, MOD0
* : High current I/O port.
18
DS07-12560-2E
MB89490 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89490 series offer a memory space of 64K bytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt/reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89490 series is structured as illustrated below.
Memory Space
MB89498
MB89F499
MB89PV490
0000H
0080H
0000H
0080H
0000H
0080H
I/O
I/O
I/O
RAM
RAM
RAM
0100H
0100H
0100H
General-
purpose
registers
General-
purpose
registers
General-
purpose
registers
0200H
0880H
0200H
0880H
0200H
0880H
Vacant
Vacant
1000H
1000H
Vacant
ROM
FLASH
(60 K)
External
ROM
(60 K)
4000H
FFC0H
FFFFH
FFC0H
FFFFH
FFC0H
FFFFH
Vector table (reset, interrupt, vector call instruction)
DS07-12560-2E
19
MB89490 Series
2. Registers
The F2MC-8L family has 2 types of registers; dedicated registers in the CPU and general-purpose registers in
the memory. The following registers are provided :
Program counter (PC)
Accumulator (A)
: A 16-bit register for indicating instruction storage positions.
: A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T) : A 16-bit register for performing arithmetic operations with the accumulator.
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register for index modification.
: A 16-bit pointer for indicating a memory address.
: A 16-bit register for indicating a stack area.
: A 16-bit register for storing a register pointer and condition code.
Initial value
16-bit
PC
A
: Program counter
: Accumulator
FFFDH
Undefined
T
: Temporary accumulator Undefined
IX
: Index register
: Extra pointer
: Stack pointer
: Program status
Undefined
Undefined
Undefined
EP
SP
PS
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8-bit for use as a register bank pointer (RP) and the lower 8-bit for
use as a condition code register (CCR) . (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
Va- Va- Va-
cancy cancy cancy
PS
RP
H
IL1, 0
N
V
C
RP
CCR
20
DS07-12560-2E
MB89490 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Conversion rule for Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for controlling the CPU operations at the time of an interrupt.
H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear
to “0” otherwise. This flag is for decimal adjustment instructions.
I-flag : Interrupt is allowed when this flag is set to “1”. Interrupt is prohibited when the flag is set to “0”. Clear to
“0” at reset.
IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request is higher
than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
Low
1
1
N-flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Clear to “0” otherwise.
Z-flag : Set to “1” when an arithmetic operation results in “0”. Clear to “0” otherwise.
V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Clear to “0” if the
overflow does not occur.
C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to “0”
otherwise. Set to the shift-out value in the case of a shift instruction.
DS07-12560-2E
21
MB89490 Series
The following general-purpose registers are provided :
General-purpose registers : An 8-bit register for storing data
The general-purpose registers are 8-bit and located in the register banks of the memory.
1 bank contains 8 registers. Up to a total of 32 banks can be used on the MB89490 series. The bank currently
in use is indicated by the register bank pointer (RP) .
Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
22
DS07-12560-2E
MB89490 Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
Register name
PDR0
Register description
Port 0 data register
Read/Write
R/W
Initial value
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
00000000B
DDR0
Port 0 direction register
Port 1 data register
W*
PDR1
R/W
DDR1
Port 1 direction register
Port 2 data register
W*
PDR2
R/W
(Reserved)
DDR2
SYCC
STBC
WDTC
TBTC
WPCR
PDR3
DDR3
RSFR
PDR4
PDR5
DDR5
PDR6
DDR6
PDR7
DDR7
PDR8
DDR8
EIC0
Port 2 direction register
R/W
R/W
R/W
W*
00000000B
X-1MM100B
00010XXXB
0---XXXXB
00---000B
System clock control register
Standby control register
Watchdog timer control register
Timebase timer control register
Watch prescaler control register
Port 3 data register
R/W
R/W
R/W
R/W
R
00--0000B
XXXXXXXXB
11111111B
XXXX----B
Port 3 direction register
Reset flag register
Port 4 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
---XXXXXB
---00000B
Port 5 data register
Port 5 direction register
Port 6 data register
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
---XXXXXB
---00000B
Port 6 direction register
Port 7 data register
Port 7 direction register
Port 8 data register
Port 8 direction register
External interrupt 0 control register 0
External interrupt 0 control register 1
External interrupt 0 control register 2
External interrupt 0 control register 3
External interrupt 1 enable register
External interrupt 1 flag register
Serial mode register
00000000B
00000000B
00000000B
00000000B
00000000B
-------0B
EIC1
EIC2
EIC3
EIE1
EIF1
SMR
00000000B
XXXXXXXXB
000000X0B
000000X0B
XXXXXXXXB
SDR
Serial data register
T01CR
T00CR
T01DR
Timer 01 control register
Timer 00 control register
Timer 01 data register
(Continued)
DS07-12560-2E
23
MB89490 Series
Address
23H
Register name
T00DR
T11CR
T10CR
T11DR
T10DR
ADER
Register description
Timer 00 data register
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial value
XXXXXXXXB
000000X0B
000000X0B
XXXXXXXXB
XXXXXXXXB
11111111B
-00000X0B
-0000001B
24H
Timer 11 control register
25H
Timer 10 control register
26H
Timer 11 data register
27H
Timer 10 data register
28H
A/D input enable register
29H
ADC0
A/D control register 0
2AH
2BH
2CH
2DH
2EH
2FH
30H
ADC1
A/D control register 1
ADDH
ADDL
A/D data register (Upper byte)
A/D data register (Lower byte)
PWM 0 timer control register
PWM 0 timer compare register
UART/SIO serial mode control register
UART/SIO serial mode control register
UART/SIO serial status/data register
UART/SIO serial data register
UART/SIO serial rate control register
PWM 1 timer control register
PWM 1 timer compare register
I2C bus status register
------XXB
R
XXXXXXXXB
0-000000B
CNTR0
COMR0
SMC0
R/W
W*
XXXXXXXXB
00000000B
00000000B
00001---B
R/W
R/W
R/W
R/W
R/W
R/W
W*
SMC1
31H
SSD
32H
SIDR/SODR
SRC
XXXXXXXXB
XXXXXXXXB
0-000000B
33H
34H
CNTR1
COMR1
IBSR
35H
XXXXXXXXB
00000000B
00000000B
000XXXXXB
-XXXXXXXB
XXXXXXXXB
----0000B
36H
R
37H
IBCR
I2C bus control register
R/W
R/W
R/W
R/W
R/W
38H
ICCR
I2C clock control register
39H
IADR
I2C address register
3AH
3BH
3CH to 3FH
40H
IDAR
I2C data register
PLLCR
Sub PLL control register
(Reserved)
RMN
RMC
Remote control counter register
Remote control control register
Remote control status register
Remote control FIFO data register
Remote control compare register 0
Remote control compare register 1
Remote control compare register 2
Remote control compare register 3
Remote control compare register 4
R
XXXXXXXXB
00000000B
0X000001B
X----XXXB
41H
R/W
R/W
R
42H
RMS
43H
RMD
44H
RMCD0
RMCD1
RMCD2
RMCD3
RMCD4
R/W
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
11111111B
45H
46H
47H
48H
(Continued)
24
DS07-12560-2E
MB89490 Series
(Continued)
Address
Register name
RMCD5
Register description
Remote control compare register 5
Remote interrupt register
Read/Write
R/W
Initial value
11111111B
0000-000B
49H
4AH
RMCI
R/W
4BH to 5DH
5EH
(Reserved)
LOCR
LCR
LCD controller output control register
LCD controller control register
LCD data RAM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-0000000B
00010000B
XXXXXXXXB
11111111B
11111111B
11111111B
11111111B
---11111B
5FH
60H to 6FH
70H
VRAM
PUCR0
PUCR1
PUCR2
PUCR3
PUCR5
PUCR6
PUCR7
PUCR8
Port 0 pull up resistor control register
Port 1 pull up resistor control register
Port 2 pull up resistor control register
Port 3 pull up resistor control register
Port 5 pull up resistor control register
Port 6 pull up resistor control register
Port 7 pull up resistor control register
Port 8 pull up resistor control register
(Reserved)
71H
72H
73H
74H
75H
11111111B
11111111B
-----111B
76H
77H
78H to 79H
7AH
FMCS
ILR1
ILR2
ILR3
ILR4
Flash memory control status registger
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
(Reserved)
R/W
W*
W*
W*
W*
000X00-0B
11111111B
11111111B
11111111B
11111111B
7BH
7CH
7DH
7EH
7FH
* : Bit manipulation instruction cannot be used.
• Read/write access symbols
R/W: Readable and writable
R :
Read-only
W : Write-only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
- : Unused bit.
M : The initial value of this bit is determined by mask option.
DS07-12560-2E
25
MB89490 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Symbol
Unit
Remarks
Parameter
Min
Max
VCC
AVCC
VSS − 0.3 VSS + 4.0
VSS − 0.3 VSS + 4.0
V
AVCC must be equal to VCC
Power supply voltage*1
AVR
V
V
V
LCD power supply voltage
V1 to V3 VSS − 0.3
VCC
VSS − 0.3 VCC + 0.3
VSS − 0.3 VSS + 6.0
Except P40 to P47
P40 to P47 in MB89PV490 and
MB89498
Input voltage *1
VI
V
VSS − 0.3 VSS + 5.5
VSS − 0.3 VCC + 0.3
V
V
P40 to P47 in MB89F499
Output voltage*1
VO
Maximum clamp current
Total maximum clamp current
ICLAMP
Σ|ICLAMP|
− 2.0
⎯
+ 2.0
20
mA *2
mA *2
mA
“L” level maximum output current IOL
⎯
15
Average value (operating current ×
operating rate)
“L” level average output current
IOLAV
⎯
⎯
4
mA
mA
“L” level total maximum output
current
ΣIOL
100
“L” level total average output
current
Average value (operating current ×
ΣIOLAV
⎯
⎯
⎯
40
− 15
− 4
mA
mA
mA
operating rate)
“H” level maximum output current IOH
Average value (operating current ×
operating rate)
“H” level average output current
IOHAV
“H” level total maximum output
current
ΣIOH
⎯
⎯
− 50
− 20
mA
mA
“H” level total average output
current
Average value (operating current ×
operating rate)
ΣIOHAV
Power consumption
Operating temperature
Storage temperature
PD
⎯
300
+ 85
mW
°C
TA
− 40
− 55
Tstg
+ 150
°C
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P52, P80 to P82
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
(Continued)
26
DS07-12560-2E
MB89490 Series
(Continued)
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
Limiting
P-ch
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-12560-2E
27
MB89490 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min
Max
Normal operation
assurance range
MB89PV490 and
MB89F499
2.7*
3.6
V
V
VCC
AVCC
Normal operation
assurance range
2.2*
3.6
MB89498
Power supply voltage
1.5
2.7
3.6
3.6
V
V
Retains the RAM state in stop mode
AVR
LCD power supply voltage V1 to V3
Operating temperature TA
Vss
−40
Vcc
+85
V
°C
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2 and
“5. A/D Converter Electrical Characteristics”.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Figure1 Operating Voltage vs. Main Clock Operating Frequency (MB89F499/498)
Operating
voltage (V)
3.6
Analog accuracy
assurance range :
VCC = AVCC = 2.7 V to 3.6 V
3.0
2.7
2.2
2.0
Main clock
operating freq. (MHz)
1.0
4.0
2.0
3.0
4.0
1.0
5.0
0.8
6.0
7.0
8.0
9.0 10.0 11.0 12.0 12.5
2.0 1.33
0.66 0.57 0.50 0.44 0.4 0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89F499
28
DS07-12560-2E
MB89490 Series
Figure2 Operating Voltage vs. Main Clock Operating Frequency (MB89PV490)
Operating
voltage (V)
3.6
3.5
Analog accuracy
assurance range :
VCC = AVCC = 2.7 V to 3.6 V
3.0
2.7
Main clock
operating freq. (MHz)
1.0
4.0
2.0
3.0
4.0
1.0
5.0
0.8
6.0
7.0
8.0
9.0 10.0 11.0 12.0 12.5
2.0 1.33
0.66 0.57 0.50 0.44 0.4 0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see figure 1 and 2 if the operating speed
is switched using a gear.
DS07-12560-2E
29
MB89490 Series
3. DC Characteristics
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P84,
SCL, SDA,
⎯
0.7 VCC
⎯
VCC + 0.3
V
VIH
“H” level
input voltage
⎯
⎯
0.7 VCC
0.7 VCC
⎯
⎯
VSS + 6.0
VSS + 5.5
V
V
MB89498
P40 to P47
MB89F499
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 to INT07
VIHS
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VIHA
INT10 to INT17
0.85 VCC
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P84,
SCL, SDA,
VIL
⎯
⎯
VSS −0.3
⎯
⎯
0.3 VCC
V
V
“L” level
input voltage
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 to INT07
VILS
VSS −0.3
0.2 VCC
VILA
INT10 to INT17
⎯
⎯
VSS −0.3
VSS −0.3
⎯
⎯
0.5 VCC
V
V
Open-drain
VSS + 6.0
MB89498
output pin
application
VD
P40 to P47
⎯
VSS −0.3
⎯
VSS + 5.5
V
MB89F499
voltage
(Continued)
30
DS07-12560-2E
MB89490 Series
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
2.2
2.2
⎯
Typ
Max
⎯
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P82
IOH = −2.0 mA
IOH = −4.0 mA
IOL = 4.0 mA
⎯
V
V
V
“H” level
output voltage
VOH
P00 to P07
⎯
⎯
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P82, RST
⎯
0.4
“L” level
output voltage
VOL
P00 to P07
P40 to P47
IOL = 12.0 mA
IOL = 15.0 mA
⎯
⎯
⎯
⎯
0.4
0.4
V
V
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P84
Without
Input leakage
current
ILI
0.45 V < VI < VCC
−5
⎯
+5
µA pull-up
resistor
Open-drain
outputleakage ILOD
current
P40 to P47
0.0 V < VI < VCC
−5
⎯
+5
µA
Pull-down
resistance
Except
MB89F499
RDOWN
MOD0
VI = VCC
25
50
100
kΩ
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P82,
RST
When pull-up
resistor is
selected
Pull-up
resistance
RPULL
VI = 0.0 V
25
50
100
2.5
kΩ
kΩ
(except RST)
Common
output
impedance
RVCOM
COM0 to COM3 V1 to V3 = +3.0 V
⎯
⎯
(Continued)
DS07-12560-2E
31
MB89490 Series
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
Segment
output
impedance
RVSEG
SEG0 to SEG31 V1 to V3 = +3.0 V
⎯
⎯
15
kΩ
kΩ
LCD divided
resistance
Between VCC and
RLCD
⎯
300
500
750
V
SS
LCD
controller/
driver
leakage
current
V1 to V3,
COM0toCOM3,
SEG0 to SEG31
ILCDL
⎯
−1
⎯
+1
µA
FCH = 12.5 MHz
tinst = 0.33 µs
Main clock run mode
⎯
⎯
8.0
7.0
12
mA MB89F499
ICC1
12.0 mA MB89498
FCH = 12.5 MHz
tinst = 5.33 µs
MB89F499
MB89498
ICC2
⎯
⎯
1.0
3.0
3.0
5.0
mA
mA
Main clock run mode
FCH = 12.5 MHz
tinst = 0.33 µs
Main clock sleep
mode
MB89F499
MB89498
ICCS1
FCH = 12.5 MHz
tinst = 5.33 µs
Main clock sleep
mode
MB89F499
MB89498
ICCS2
⎯
⎯
⎯
0.6
2.0
mA
Power supply
current
FCL = 32.768 kHz
Sub-clock mode
TA = +25 °C
VCC
MB89F499
MB89498
ICCL
40.0
60.0
µA
FCL = 32.768 kHz
Sub-clock mode
TA = +25 °C
MB89F499
MB89498
ICCLPLL
180.0 250.0 µA
sub PLL × 4
FCL = 32.768 kHz
Sub-clock sleep
mode
MB89F499
MB89498
ICCLS
⎯
⎯
14.0
1.5
30.0
13.0
µA
µA
TA = +25 °C
FCL = 32.768 kHz
Watch mode
Main clock stop
mode
MB89F499
MB89498
ICCT
TA = +25 °C
(Continued)
32
DS07-12560-2E
MB89490 Series
(Continued)
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
TA = +25 °C
Sub-clock stop mode
MB89F499
MB89498
ICCH
VCC
⎯
0.8
4.0
µA
Power supply
current
AVCC = 3.0 V,
TA = +25 °C
A/D
converting
IA
⎯
⎯
1.2
0.8
4.4
4.0
mA
AVCC
IAH
TA = +25 °C
µA A/D stop
Except
VCC, VSS, AVCC, f = 1 MHz
AVSS, AVR
Input
capacitance
CIN
⎯
10.0
⎯
pF
DS07-12560-2E
33
MB89490 Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min
Max
RST “L” pulse width
tZLZH
⎯
48 tHCYL
⎯
ns
Note : tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
The MCU operation is not guaranteed when the “L” pulse width is shorter than tZLZH.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Min Max
Symbol Condition
Unit
Remarks
Power supply rising time
Power supply cut-off time
tR
tOFF
⎯
50
ms
⎯
1
⎯
ms Due to repeated operations
Note : Make sure that power supply rises within the selected oscillation stabilization time.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be
varied in the course of operation, a smooth voltage rise is recommended.
t
OFF
t
R
1.5 V
0.2 V
0.2 V
0.2 V
VCC
34
DS07-12560-2E
MB89490 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Typ
Symbol
FCH
Pin
Unit
Remarks
Parameter
Min
1
Max
X0, X1
⎯
12.5 MHz
Clock frequency
Clock cycle time
FCL
X0A, X1A
X0, X1
⎯
32.768
⎯
75
1000
⎯
kHz
ns
tHCYL
tLCYL
80
X0A, X1A
13.3
30.5
µs
PWH
PWL
X0
20
⎯
⎯
⎯
15.2
⎯
⎯
⎯
10
ns
Input clock pulse width
PWHL
PWLL
X0A
µs External clock
tCR
tCF
Input clock rising/falling time
X0, X0A
ns
X0 and X1 Timing and Conditions
tHCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
0.2 VCC
X0
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal
or
ceramic resonator is used
When an external clock is used
X0
X1
X0
X1
open
FCH
C2
FCH
C1
DS07-12560-2E
35
MB89490 Series
Sub-clock Timing and Conditions
tLCYL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
tCR
tCF
Sub-clock Conditions
When a crystal
or
ceramic resonator is used
When an external clock is used
When an subclock is not used
X0A
X1A
X0A
X1A
X0A
X1A
FCL
Rd
C1
Open
FCL
Open
C0
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
Remarks
(4/FCH) tinst = 0.32 µs when operating
at FCH = 12.5 MHz
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
µs
Instruction cycle
(minimum execution time)
tinst
(2/FCL) tinst = 61.036 µs when
operating at FCL = 32.768 kHz
2/FCL, 1/2FCL
36
DS07-12560-2E
MB89490 Series
• PLL operation guarantee range (sub PLL × 4)
Relationship between internal operating clock frequency and power supply voltage
Operating
voltage (V)
subPLL operating guarantee range
3.6
3.0
2.7
2.5
2.0
Internal operating clock freq. (kHz)
131.072
15.625
300
6.67
Min execution
time (inst. cycle) (µs)
Not assured for MB89F499 and MB89PV490.
Relationship between sub-clock oscillating frequency and instruction cycle when
sub PLL is enabled
15.625
Multiplied
by 4
6.67
75
32.768
Oscillation clock FCL (kHz)
DS07-12560-2E
37
MB89490 Series
(5) Serial I/O Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin
Condition
Unit
Parameter
Min
2 tinst*
−200
Max
⎯
Serial clock cycle time
SCK ↓ → SO time
Valid SI → SCK ↑
tSCYC
tSLOV
tIVSH
SCK0, SCK1
µs
ns
µs
µs
µs
µs
ns
µs
µs
Internal
shift clock
mode
SCK0, SCK1, SO0, SO1
SI0, SI1, SCK0, SCK1
SCK0, SCK1, SI0, SI1
200
⎯
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time tSHIX
⎯
Serial clock “H” pulse width tSHSL
⎯
SCK0, SCK1
Serial clock “L” pulse width
SCK ↓ → SO time
tSLSH
tSLOV
tIVSH
⎯
External
shift clock
mode
SCK0, SCK1, SO0, SO1
SI0, SI1, SCK0, SCK1
SCK0, SCK1, SI0, SI1
200
⎯
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time tSHIX
⎯
* : For information on tinst, see “ (4) Instruction Cycle”.
Internal Clock Operation
tSCYC
SCK0, SCK1
2.4 V
0.8 V
0.8 V
tSLOV
SO0, SO1
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI0, SI1
External Clock Operation
tSLSH
tSHSL
SCK0, SCK1
SO0, SO1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
tIVSH
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
SI0, SI1
38
DS07-12560-2E
MB89490 Series
(6) I2C Timing
(VCC = 3.0V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin
Unit
Remarks
Parameter
Min
Max
SCL
SDA
1/4 tinst*1 ×
1/4 tinst ×
Start condition output
Stop condition output
Start condition detect
Stop condition detect
tSTA
ns At master mode
M × N − 20
M × N + 20
SCL
SDA
1/4 tinst ×
1/4 tinst ×
tSTO
ns At master mode
(M × N + 8) − 20 (M*2 × N*3 + 8) + 20
SCL
SDA
tSTA
1/4 tinst × 6 + 40
1/4 tinst × 6 + 40
⎯
⎯
ns
SCL
SDA
tSTO
ns
Re-start condition
output
SCL
SDA
1/4 tinst ×
1/4 tinst ×
tSTASU
tSTASU
ns At master mode
ns
(M × N + 8) − 20
(M × N + 8) + 20
Re-start condition
detect
SCL
SDA
1/4 tinst × 4 + 40
⎯
1/4 tinst ×
1/4 tinst ×
SCL output LOW width tLOW
SCL output HIGH width tHIGH
SCL
ns At master mode
M × N − 20
M × N + 20
1/4 tinst ×
(M × N + 8) − 20
1/4 tinst ×
(M × N + 8) + 20
SCL
SDA
SDA
ns At master mode
SDA output delay
tDO
1/4 tinst × 4 − 20
1/4 tinst × 4 + 20
ns
SDA output setup
time after interrupt
tDOSU
1/4 tinst × 4 − 20
⎯
ns *4
SCL input LOW
pulse width
tLOW
tHIGH
SCL
SCL
1/4 tinst × 6 + 40
1/4 tinst × 2 + 40
⎯
⎯
ns
ns
SCL input HIGH
pulse width
SDA input setup time
SDA hold time
tSU
tHO
SDA
SDA
40
0
⎯
⎯
ns
ns
*1 : For information in tinst, see “ (4) Instruction Cycle”.
*2 : M is defined in the I2C clock control register ICCR bit 4 and bit 3 (CS4 and CS3). For details, please refer to
the H/W manual register explanation.
*3 : N is defined in the I2C clock control register ICCR bit 2 to bit 0 (CS2 to CS0).
*4 : When the interrupt period is greater than SCL “L” width, SDA and SCL output (Standard) value is based on
hypothesis when rising time is 0 ns.
DS07-12560-2E
39
MB89490 Series
Data transmit (master/slave)
t
DO
tDO
t
SU
t
HO
tDOSU
SDA
SCL
ACK
9
t
STASU
t
STA
t
LOW
t
HO
1
Data receive (master/slave)
t
SU
t
HO
t
DO
t
DO
tDOSU
SDA
SCL
ACK
9
t
HIGH
tLOW
t
STO
6
7
8
40
DS07-12560-2E
MB89490 Series
(7) Peripheral Input Timing
Parameter
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin
Unit
Remarks
Min
Max
⎯
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
tILIH1
tIHIL1
2 tinst*
2 tinst*
µs
µs
EC0, EC1, INT00 to
INT07, INT10 to INT17
⎯
* : For information on tinst, see “ (4) Instruction Cycle”.
t
IHIL1
tILIH1
EC0, EC1,
INT00 to INT07
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIHIL1
tILIH1
INT10 to INT17
0.85 VCC
0.85 VCC
0.5 VCC
0.5 VCC
DS07-12560-2E
41
MB89490 Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V to 3.6 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Typ
10
Parameter
Resolution
Symbol
Pin
Unit Remarks
Min
⎯
Max
⎯
bit
Total error
⎯
⎯
3.0
2.5
1.9
LSB
LSB
LSB
⎯
Linearity error
⎯
⎯
Differential linearity error
⎯
⎯
⎯
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
Zero transition voltage
VOT
V
V
Full-scale transition
voltage
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR −
0.5 LSB
VFST
A/D mode conversion time
Analog port input current
Analog input voltage
Reference voltage
⎯
IAIN
VAIN
⎯
30 tinst*
⎯
⎯
⎯
⎯
⎯
⎯
10
µs
µA
V
AN0 to
AN7
AVSS
AVR
AVCC
AVSS + 2.7
V
A/D is
µA
IR
⎯
⎯
95.0
170.0
4.0
AVR
activated
Reference voltage supply
current
A/D is
µA
IRH
⎯
stopped
* : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics”.
42
DS07-12560-2E
MB89490 Series
(2) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics.
• Differential linearity error (unit : LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.
• Total error (unit : LSB)
The difference between theoretical and actual conversion values.
Theoretical I/O characteristics
Total error
3FFH
3FEH
3FDH
3FFH
3FEH
3FDH
V
FST
Actual conversion
characteristics
1.5 LSB
{1 LSB × N + VOT
}
004H
003H
002H
001H
004H
003H
002H
001H
V
NT
V
OT
Actual conversion
characteristics
1 LSB
Ideal characteristics
0.5 LSB
AVR
AVR
AVSS
AVSS
Analog input
Analog input
V
FST − VOT
1022
V
NT − {1 LSB × N + 0.5 LSB}
1 LSB
Total error =
1 LSB =
(V)
Zero transition error
Full-scale transition error
Theoretical characteristics
004H
003H
002H
001H
Actual conversion
characteristics
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristics
V
FST
(Actual
measurement
value)
Actual conversion
characteristics
Actual conversion
characteristics
V
OT (Actual measurement
value)
AVR
AVSS
AVR
AVSS
Analog input
Analog input
(Continued)
DS07-12560-2E
43
MB89490 Series
(Continued)
Linearity error
Differential linearity error
Ideal value
3FFH
3FEH
3FDH
Actual conversion
characteristics
N + 1
{1 LSB × N + VOT
}
Actual conversion
characteristics
V
(N + 1)T
V
FST
N
(Actual
V
NT
measurement
value)
004H
003H
002H
001H
N – 1
N – 2
V
NT
Actual conversion
characteristics
Actual conversion
characteristics
Ideal value
VOT (Actual measurement value)
AVSS
AVSS
AVR
AVR
Analog input
Analog input
V(N + 1)T − VNT
1 LSB
VNT − {1 LSB × N + VOT}
− 1
Differential linearity error =
Linearity error =
1 LSB
44
DS07-12560-2E
MB89490 Series
(3) Notes on Using A/D Converter
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
C
MB89498
2.4 kΩ (Max) 44.0 pF (Max)
MB89F499 2.4 kΩ (Max) 28.6 pF (Max)
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB89F499
MB89498
MB89F499
MB89498
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVRH − AVSS| becomes smaller, values of relative errors grow larger.
DS07-12560-2E
45
MB89490 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” level output voltage
VOL vs IOL (MB89F499)
VOL vs IOL (MB89498)
VCC = 2.0 V
VCC = 2.5 V
VCC = 2.7 V
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.25
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
TA = + 25˚C
TA = + 25˚C
0.20
VCC = 2.0 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.15
0.10
0.05
0.00
0
2
4
6
8
10
0
2
4
6
8
10
Port 0
Port 0
IOL [mA]
IOL [mA]
VOL vs IOL (MB89498)
VOL vs IOL (MB89F499)
0.20
0.16
0.12
0.08
0.02
0.00
0.20
0.16
0.12
0.08
0.04
0.00
TA = + 25˚C
TA = + 25˚C
VCC = 2.0 V
VCC = 2.0 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0
2
4
6
8
10
0
2
4
6
8
10
Port 4
Port 4
IOL [mA]
IOL [mA]
(Continued)
DS07-12560-2E
46
MB89490 Series
VOL vs IOL (MB89F499)
VOL vs IOL (MB89498)
VCC = 2.0 V
0.8
0.6
0.4
0.2
0.0
0.8
0.6
0.4
0.2
0.0
TA = + 25˚C
VCC = 2.0 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
TA = + 25˚C
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0
2
4
6
8
10
0
2
4
6
8
10
Other than port 0, port 4
IOL [mA]
Other than port 0, port 4
IOL [mA]
(2) “H” level output voltage
VCC - VOH vs IOH (MB89498)
VCC − VOH vs IOH (MB89F499)
VCC = 2.0 V
1.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.0 V
TA = + 25˚C
TA = + 25˚C
0.8
0.6
0.4
0.2
0.0
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0
−2
−4
−6
−8
−10
0
−2
−4
−6
−8
−10
Port 0
IOH [mA]
IOH [mA]
Port 0
(Continued)
DS07-12560-2E
47
MB89490 Series
VCC - VOH vs IOH (MB89F499)
VCC = 2.0 V VCC = 2.5 V VCC = 2.7 V
VCC - VOH vs IOH (MB89498)
VCC = 2.0 V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
VCC = 3.0 V
TA = + 25˚C
1.2
TA = + 25˚C
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 2.5 V
VCC = 2.7 V
1.0
0.8
0.6
0.4
0.2
0.0
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0
−2
−4
−6
−8
−10
0
−2
−4
−6
−8
−10
Other than port 0
IOH [mA]
Other than port 0
IOH [mA]
(3) Power supply current (External clock)
ICC1 vs VCC (MB89F499)
ICC1 vs VCC (MB89498)
12.0
10.0
8.0
10.0
TA = + 25˚C
TA = + 25˚C
FCH = 12.5 MHz
FCH = 12.5 MHz
8.0
6.0
4.0
2.0
0.0
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
6.0
4.0
FCH = 4.0 MHz
FCH = 4.0 MHz
2.0
FCH = 2.0 MHz
FCH = 1.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
0.0
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
(Continued)
48
DS07-12560-2E
MB89490 Series
ICCS1 vs VCC (MB89498)
ICCS1 vs VCC (MB89F499)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
FCH = 12.5 MHz
TA = + 25˚C
TA = + 25˚C
FCH = 12.5 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 4.0 MHz
FCH = 4.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
ICC2 vs VCC (MB89F499)
ICC2 vs VCC (MB89498)
1.4
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TA = + 25˚C
TA = + 25˚C
FCH = 12.5 MHz
FCH = 12.5 MHz
1.2
1.0
0.8
0.6
0.4
0.2
0.0
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 4.0 MHz
FCH = 4.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
(Continued)
49
DS07-12560-2E
MB89490 Series
ICCS2 vs VCC (MB89F499)
ICCS2 vs VCC (MB89498)
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
TA = + 25˚C
TA = + 25˚C
FCH = 12.5 MHz
FCH = 12.5 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 4.0 MHz
FCH = 4.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
ICCLPLL vs VCC (MB89F499)
ICCLPLL vs VCC (MB89498)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.30
0.25
0.20
0.15
0.10
0.05
0.00
TA = + 25˚C
TA = + 25˚C
FCH = 12.5 MHz
FCH = 12.5 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 4.0 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
FCH = 4.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
(Continued)
DS07-12560-2E
50
MB89490 Series
ICCL vs VCC (MB89F499)
ICCL vs VCC (MB89498)
60.0
50.0
40.0
30.0
20.0
10.0
0.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
TA = + 25˚C
TA = + 25˚C
FCL = 32.768 kHz
FCL = 32.768 kHz
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
ICCLS vs VCC (MB89498)
ICCLS vs VCC (MB89F499)
20.0
16.0
12.0
8.0
20.0
16.0
12.0
8.0
TA = + 25˚C
TA = + 25˚C
FCL = 32.768 kHz
FCL = 32.768 kHz
4.0
4.0
0.0
0.0
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
(Continued)
DS07-12560-2E
51
MB89490 Series
(Continued)
ICCT vs VCC (MB89498)
ICCT vs VCC (MB89F499)
2.0
2.0
1.6
1.2
0.8
0.4
0.0
TA = + 25˚C
TA = + 25˚C
1.6
FCL = 32.768 kHz
1.2
F
CL = 32.768 kHz
0.8
0.4
0.0
1
2
3
4
5
1
2
3
4
5
VCC [V]
VCC [V]
(4) Pull-up resistance
RPULL vs VCC (MB89F499)
RPULL vs VCC (MB89498)
120
200
160
120
80
TA = + 25˚C
TA = + 25˚C
100
80
60
40
20
0
T
T
A
A
= + 110 ˚C
= + 25 ˚C
= - 40 ˚C
T
A
TA = + 110 ˚C
TA = + 25 ˚C
TA = - 40 ˚C
45
0
2.0
2.5
3.0
3.5
4.0
4.5
1.5 2.0
2.5
3.0
3.5
4.0
4.5
VCC [V]
VCC [V]
52
DS07-12560-2E
MB89490 Series
■ MASK OPTIONS
Part number
MB89498
MB89F499
MB89PV490
Specify when
ordering mask
Specifying procedure
Setting not possible
Main clock oscillation stabilizationtime selection
210/FCH
214/FCH
218/FCH
Fixed to oscillation stabilization wait
time of 218/FCH
Selectable
■ ORDERING INFORMATION
Part number
MB89498PF
Package
100-pin Plastic QFP
Remarks
MB89F499PF
(FPT-100P-M06)
MB89498PMC
MB89F499PMC
100-pin Plastic LQFP
(FPT-100P-M20)
100-pin Ceramic MQFP
(MQP-100C-P01)
MB89PV490CF
DS07-12560-2E
53
MB89490 Series
■ PACKAGE DIMENSIONS
100-pin ceramic MQFP
Lead pitch
0.65 mm
Straight
Ceramic
Plastic
Lead shape
Motherboard
material
Mounted package
material
(MQP-100C-P01)
100-pin ceramic MQFP
(MQP-100C-P01)
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.35(.486)TYP
INDEX AREA
0.65±0.15
(.0256±.0060)
1.20 +–00..2400
.047 +–..000186
0.65±0.15
(.0256±.0060)
1.27±0.13
(.050±.005)
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.85(.742)
TYP
10.16(.400)
TYP
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
0.30±0.08
(.012±.003)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.30±0.08
(.012±.003)
1.20 +–00..2400
.047 +–..000186
10.82(.426)
MAX
0.15±0.05
(.006±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
1994-2008 FUJITSU MICROELECTRONICS LIMITED M100001SC-1-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
54
DS07-12560-2E
MB89490 Series
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Gullwing
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8
˚
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-12560-2E
55
MB89490 Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
(Mounting height)
–
0.10 .059 +.008
–.004
INDEX
0.10±
0.10
(.004
±
.004)
(Stand off)
100
26
0°~8
°
"A"
0.50±0.20
(.020±.008
0.25(.010)
)
1
25
0.60
(.024
±
±
0.15
.006)
0.50(.020)
0.20±0.05
(.008 .002)
0.145
±
0.055
.0022)
M
0.08(.003)
±
(.0057
±
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
56
DS07-12560-2E
MB89490 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
The package code is changed.
FPT-100P-M05 → FPT-100P-M20
⎯
⎯
■ PROGRAMMING AND ERASING FLASH Deleted the “6. ROM Programmer Adaptor and Recom-
16
MEMORY ON THE MB89F499
mended ROM Programmers”
■ PROGRAMMING TO THE EPROM WITH
PIGGY-BACK/EVALUATION DEVICE
Deleted the “2. Programming Socket Adapter”
17
■ ICE PROBE POD ADAPTOR OF PIGGY- Deleted the “■ ICE PROBE POD ADAPTOR OF PIG-
BACK/EVA CHIP
GY-BACK/EVA CHIP”
Changed the items of “Zero transition voltage” and
■ ELECTRICAL CHARACTERISTICS
5. A/D Converter Electrical Characteristics
“Full-scale transition voltage”.
mV → V
AVCC → AVR
42
Order informations are changed.
MB89498PFV → MB89498PMC
MB89F499PFV→ MB89F499PMC
53
56
■ ORDERING INFORMATION
■ PACKAGE DIMENSIONS
The package code is changed.
FPT-100P-M05→ FPT-100P-M20
The vertical lines marked in the left side of the page show the changes.
DS07-12560-2E
57
MB89490 Series
MEMO
58
DS07-12560-2E
MB89490 Series
MEMO
DS07-12560-2E
59
MB89490 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Business & Media Promotion Dept.
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