MB90349ESPMC [CYPRESS]
F2MC-16LX 16-bit Microcontroller;
| 型号： | MB90349ESPMC |
| 厂家： | 
CYPRESS |
| 描述： | F2MC-16LX 16-bit Microcontroller 微控制器 |
| 文件： | 总93页 (文件大小：16745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
1. Go to www.cypress.com/pcn.
2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB90340E Series
F2MC-16LX 16-bit Microcontroller
Datasheet
The MB90340E series with up to 2 FULL-CAN interfaces is especially designed for automotive and other industrial applications. Its
main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message
buffer scheme and so offering more functions than a normal full CAN approach.
The power to the MCU core (3 V) is supplied by a built-in regulator circuit, giving these microcontrollers superior performance in
terms of power consumption and tolerance to EMI.
Features
Resolution is selectable between 8-bit and 10-bit.
CPU
Instruction system best suited to controller
Activation by external trigger input is allowed.
- Wide choice of data types (bit, byte, word, and long word)
- Wide choice of addressing modes (23 types)
- Enhanced functionality with signed multiply and divide
Conversion time : 3 s (at 24 MHz machine clock, including
sampling time)
instructions and the RETI instruction
- Enhanced high-precision computing with 32-bit accumulator
Address match detection (program patch) func-
tion
Instruction system compatible with high-level language (C
language) and multitask
- Employing system stack pointer
- Various enhanced pointer indirect instructions
- Barrel shift instructions
Detects address matches against 6 address pointers
Timer
Time-base timer, watch timer, watchdog timer : 1 channel
8/16-bit PPG timer : 8-bit 16 channels, or 16-bit 8
channels
Increased processing speed
- 4-byte instruction queue
16-bit reload timer : 4 channels
Serial interface
16-bit input/output timer
LIN-UART : 4 channels
- 16-bit free-run timer : 2 channels
(FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/
5/6/7)
- 16-bit input capture: (ICU): 8 channels
- 16-bit output compare: (OCU): 8 channels
- Equipped with full-duplex double buffer
- Clock-asynchronous or clock-synchronous serial transmission
is available
I2C interface : 2 channels (only for devices with a C suffix in
the part number)
- Up to 400 kbps transfer rate
Full-CAN controller
Up to 2 channels
Interrupt controller
Powerful 8-level, 34-condition interrupt feature
Compliant with Ver2.0A and Ver2.0B CAN specifications
16 built-in message buffers
Up to 16 external interrupts are supported
CAN wake-up function
Automatic data transfer function independent of CPU
- Expanded intelligent I/O service function (EI2OS) : up to 16
channels
Low power consumption (standby) mode
Sleep mode (a mode that halts CPU operating clock)
Timebase timer mode (a mode where only the oscillation
clock, sub clock, timebase timer and watch timer operate)
I/O ports
General-purpose input/output port (CMOS output)
- 80 ports (for devices without an S suffix in the part number -
i.e. devices that support the sub clock)
Watch mode (a mode that operates sub clock and watch
timer only)
- 82 ports (for devices with an S suffix in the part number - i.e.
devices that do not support the sub clock)
Stop mode (a mode that stops oscillation clock and sub
clock)
8/10-bit A/D converter
CPU intermittent operation mode
16 channels (only for devices without a C suffix in the part
Clock modulation circuit
number)
Technology
CMOS technology
24 channels (only for devices with a C suffix in the part
number)
Cypress Semiconductor Corporation
Document Number: 002-04498 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2016
MB90340E Series
Contents
Product Lineup ................................................................3
Pin Assignments ..............................................................6
Pin Description ...............................................................12
I/O Circuit Type ...............................................................19
Handling Devices ............................................................23
Block Diagrams ..............................................................26
Memory Map ....................................................................28
I/O Map ............................................................................30
CAN Controllers ..............................................................41
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register ..............................................48
Electrical Characteristics ...............................................50
Absolute Maximum Ratings .......................................50
Recommended Operating Conditions .......................52
DC Characteristics ....................................................53
AC Characteristics .....................................................55
Clock Timing ..............................................................55
Reset Standby Input ..................................................58
Power On Reset ........................................................59
Clock Output Timing ..................................................59
Bus Timing (Read) ....................................................60
Bus Timing (Write) .....................................................61
Ready Input Timing ...................................................62
Hold Timing ...............................................................63
LIN-UART0/1/2/3 .......................................................64
Trigger Input Timing ..................................................69
Timer Related Resource Input Timing .......................70
Timer Related Resource Output Timing ....................70
I2C Timing .................................................................71
A/D Converter ............................................................72
Definition of A/D Converter Terms ...........................73
Notes on A/D Converter Section ...............................74
Flash Memory Program/Erase Characteristics .........76
Example Characteristics ................................................77
Ordering Information ......................................................86
Package Dimensions ......................................................89
Major Changes ................................................................91
Document Number: 002-04498 Rev. *A
Page 2 of 92
MB90340E Series
1. Product Lineup
Part Number
MB90341E(S), MB90341CE(S),
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
MB90V340E-101,
MB90V340E-102
Parameter
Type
CPU
Evaluation products
F2MC-16LX CPU
Flash memory products
MASK ROM products
On-chip PLL clock multiplier (1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL 6)
System clock
512 Kbytes :
256 Kbytes :
MB90F345E(S), MB90F345CE(S)
256 Kbytes :
MB90F342E(S), MB90F342CE(S),
MB90342E(S), MB90342CE(S),
MB90349E(S), MB90349CE(S)
128 Kbytes :
ROM
External
MB90F349E(S), MB90F349CE(S)
128 Kbytes :
MB90F347E(S), MB90F347CE(S)
64 Kbytes :
MB90341E(S), MB90341CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S)
64 Kbytes :
MB90F346E(S), MB90F346CE(S)
MB90346E(S), MB90346CE(S)
20 Kbytes :
16 Kbytes :
MB90F345E(S), MB90F345CE(S)
16 Kbytes :
MB90F342E(S), MB90F342CE(S),
MB90F349E(S), MB90F349CE(S)
6 Kbytes :
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
6 Kbytes :
RAM
30 Kbytes
MB90F347E(S), MB90F347CE(S)
2 Kbytes :
MB90347E(S), MB90347CE(S)
2 Kbytes :
MB90F346E(S), MB90F346CE(S)
MB90346E(S), MB90346CE(S)
Emulator-specific power
supply*
Yes
0.35 m CMOS with
regulator for built-in
power supply
0.35 m CMOS with built-in power supply regulator
Technology
Flash memory with Charge pump for programming voltage
3.5 V to 5.5 V : When normal operating (not using A/D converter)
4.0 V to 5.5 V : When using the A/D converter/Flash programming
Operating
5 V 10
voltage range
4.5 V to 5.5 V : When using the external bus
Temperature range
Package
PGA-299
40°C to 105°C
QFP-100, LQFP-100
5 channels
4 channels
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
LIN-UART
Devices with a C suffix in the part number : 2 channels
2 channels
I2C (400 kbps)
Devices without a C suffix in the part number :
(Continued)
Document Number: 002-04498 Rev. *A
Page 3 of 92
MB90340E Series
Part Number
MB90341E(S), MB90341CE(S),
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
MB90V340E-101,
MB90V340E-102
Parameter
Devices with a C suffix in the part number
Devices without a C suffix in the part number
: 24 channels
: 16 channels
24 input channels
A/D Converter
10-bit or 8-bit resolution
Conversion time : Min 3 s include sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function
Generates an interrupt signal on overflow
Supports Timer Clear when the output compare finds a match
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock freq.)
16-bit Free-run
Timer (2 channels)
Free-run Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
Free-run Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
Generates an interrupt signal when one of the 16-bit free-run timer matches the output compare register
A pair of compare registers can be used to generate an output signal.
(8 channels)
16-bit Input Capture
(8 channels)
Captures the value of the 16-bit free-run timer and generates an interrupt when triggered by a pin input (rising
edge, falling edge, or both rising and falling edges).
8 channels (16-bit) /16 channels (8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
8/16-bit
Programmable Pulse
Generator
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
2 channels :
2 channels :
MB90341E(S), MB90341CE(S),
MB90F342E(S), MB90F342CE(S),
MB90342E(S), MB90342CE(S)
MB90F345E(S), MB90F345CE(S)
1 channel :
3 channels
1 channel :
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
CAN Interface
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
Document Number: 002-04498 Rev. *A
Page 4 of 92
MB90340E Series
(Continued)
Part Number
MB90341E(S), MB90341CE(S),
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
MB90V340E-101,
MB90V340E-102
Parameter
External Interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A Converter
2 channels
Devices with sub clock : devices without an S suffix in the part number
Sub clock
Only for
(maximum 100 kHz)
MB90V340E-102
Devices without sub clock : devices with an S suffix in the part number
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
I/O Ports
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 cycles
Data retention time : 20 years
Flash Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (except for
MB90F346E(S) and MB90F346CE (S) )
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01-E) is used.
Please refer to the Emulator operation manual for details.
Document Number: 002-04498 Rev. *A
Page 5 of 92
MB90340E Series
2. Pin Assignments
MB90341E(S), MB90342E(S), MB90F342E(S), MB90F345E(S), MB90346E(S), MB90F346E(S),
MB90347E(S), MB90F347E(S), MB90348E(S), MB90349E(S), MB90F349E(S)
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
P75/INT5
P74/INT4
P73/INT3
P72/INT2
P71/INT1
P70/INT0
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
QFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRL
AVRH
AVcc
P57/AN15
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
(Continued)
Document Number: 002-04498 Rev. *A
Page 6 of 92
MB90340E Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
MD1
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD2
P75/INT5
P74/INT4
P73/INT3
P72/INT2
P71/INT1
P70/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
LQFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M20)
* : X0A, X1A : devices without an S suffix in the part number
P40, P4 : devices with an S suffix in the part number
Document Number: 002-04498 Rev. *A
Page 7 of 92
MB90340E Series
MB90341CE(S), MB90342CE(S), MB90F342CE(S), MB90F345CE(S), MB90346CE(S), MB90F346CE(S), MB90347CE(S),
MB90F347CE(S), MB90348CE(S), MB90349CE(S), MB90F349CE(S)
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
QFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVss
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRH
AVcc
P57/AN15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
(Continued)
Document Number: 002-04498 Rev. *A
Page 8 of 92
MB90340E Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD1
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
LQFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M20)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
Document Number: 002-04498 Rev. *A
Page 9 of 92
MB90340E Series
MB90V340E-101/MB90V340E-102
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
QFP - 100
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRL
AVRH
AVcc
P57/AN15/DA01
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
This pin assignment is for using MB90V340E-101/102 via probecable as MB90340E.
(Continued)
Document Number: 002-04498 Rev. *A
Page 10 of 92
MB90340E Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
MD1
49
MD2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
LQFP - 100
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
AVRL
AVRH
AVcc
P57/AN15/DA01
P56/AN14/DA00
P55/AN13
P54/AN12/TOT3
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M20)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
This pin assignment is for using MB90V340E-101/102 via probecable as MB90340E.
Document Number: 002-04498 Rev. *A
Page 11 of 92
MB90340E Series
3. Pin Description
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
General purpose I/O pins. The register can be set to select whether to use a
pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O
port when the corresponding bit in the external address output control register
(HACR) is 1.
P24 to P27
1 to 4
99 to 2
G
Output pins of the external address bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pins are enabled as
high address output pins (A20 to A23).
A20 to A23
IN0 to IN3
P30
Trigger input pins for input captures.
General purpose I/O pin.The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
5
6
3
4
G
G
Address latch enable output pin. This function is enabled when the external bus
is enabled.
ALE
IN4
Trigger input pin for input capture.
General purpose I/O pin.The register can be set to select whether to use a
pull-up resistor.
P31
This function is enabled in single-chip mode.
External read strobe output pin. This function is enabled when the external bus is
enabled.
RD
IN5
Trigger input pin for input capture.
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
WR/WRL pin output is disabled.
P32
Write strobe output pin for the external data bus. This function is enabled when
both the external bus and the WR/WRL pin output are enabled. WRL is used to
write-strobe 8 lower bits of the data bus in 16-bit access while WR is used to
write-strobe 8 bits of the data bus in 8-bit access.
7
8
5
6
G
G
WR / WRL
INT10R
P33
External interrupt request input pin.
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.This function is enabled either in single-chip mode or when the
WRH pin output is disabled.
Write strobe output pin for the upper 8 bits of the external data bus. This function
is enabled when the external bus is enabled, when the external bus 16-bit mode
is selected, and when the WRH output pin is enabled.
WRH
(Continued)
Document Number: 002-04498 Rev. *A
Page 12 of 92
MB90340E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
hold function is disabled.
P34
9
7
G
Hold request input pin. This function is enabled when both the external bus
and the hold function are enabled.
HRQ
OUT4
Waveform output pin for output compare.
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
hold function is disabled.
P35
10
11
8
9
G
G
G
Hold acknowledge output pin. This function is enabled when both the external
bus and the hold function are enabled.
HAK
OUT5
Waveform output pin for output compare.
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
external ready function is disabled.
P36
External ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
RDY
OUT6
Waveform output pin for output compare.
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
clock output is disabled.
P37
12
10
Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
CLK
OUT7
P40, P41
Waveform output pin for output compare
General purpose I/O pins.
F
B
(devices with an S suffix in the part number and or MB90V340E-101)
13, 14
11, 12
Oscillation pins for sub clock
X0A, X1A
(devices without an S suffix in the part number and or MB90V340E-102)
15
16
13
14
VCC
VSS
Power (3.5 V to 5.5 V) input pin
GND pin
This is the power supply stabilization capacitor This pin should be connected
17
15
C
K
to a ceramic capacitor with a capacitance greater than or equal to 0.1 F.
General purpose I/O pin.
P42
IN6
Trigger input pin for input capture.
18
16
F
RX input pin for CAN1 Interface
(MB90341E/342E/F342E/F345E only)
RX1
INT9R
External interrupt request input pin
(Continued)
Document Number: 002-04498 Rev. *A
Page 13 of 92
MB90340E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
P43
General purpose I/O pin.
IN7
Trigger input pin for input capture.
19
17
F
TX Output pin for CAN1
(MB90341E/342E/F342E/F345E only)
TX1
P44
General purpose I/O pin.
20
21
18
19
SDA0
FRCK0
P45
H
H
Serial data I/O pin for I2C (devices with a C suffix in the part number)
Input pin for the 16-bit Free-run Timer 0
General purpose I/O pin.
Serial clock I/O pin for I2C (devices with a C suffix in the part number)
Input pin for the 16-bit Free-run Timer
General purpose I/O pin.
SCL0
FRCK1
P46
22
23
20
21
H
H
SDA1
P47
Serial data I/O pin for I2C (devices with a C suffix in the part number)
General purpose I/O pin.
SCL1
P50
Serial clock I/O pin for I2C (devices with a C suffix in the part number)
General purpose I/O pin.
24
25
26
27
22
23
24
25
AN8
O
I
Analog input pin for the A/D converter
Serial data input pin for UART2
SIN2
P51
General purpose I/O pin.
AN9
Analog input pin for the A/D converter
Serial data output pin for UART2
SOT2
P52
General purpose I/O pin.
AN10
SCK2
P53
I
Analog input pin for the A/D converter
Clock I/O pin for UART2
General purpose I/O pin.
AN11
TIN3
I
Analog input pin for the A/D converter
Event input pin for the reload timer
General purpose I/O pin.
P54
28
29
26
27
AN12
TOT3
P55
I
I
Analog input pin for the A/D converter
Output pin for the reload timer
General purpose I/O pin.
AN13
P56, P57
AN14, AN15
AVCC
Analog input pin for the A/D converter
General purpose I/O pins.
30, 31
32
28, 29
30
J
Analog input pins for the A/D converter
Analog power input pin for the A/D Converter
K
(Continued)
Document Number: 002-04498 Rev. *A
Page 14 of 92
MB90340E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
Reference voltage input pin for the A/D Converter. This power
33
31
AVRH
L
supply must be turned on or off while a voltage higher than or equal to AVRH
is applied to AVCC
.
34
35
32
33
AVRL
K
K
Lower reference voltage input pin for the A/D Converter
Analog GND pin for the A/D Converter
General purpose I/O pins.
AVSS
P60 to P67
AN0 to AN7
Analog input pins for the A/D converter
36 to 43
44
34 to 41
42
I
PPG0, 2, 4, 6, 8,
A, C, E
Output pins for PPGs
VSS
GND pin
P70 to P75
General purpose I/O pins.
Analog input pins for the A/D converter (devices with a C suffix in the part
number)
45 to 50
43 to 48
AN16 to AN21
I
INT0 to INT5
MD2
External interrupt request input pins
Input pin for specifying the operating mode.
Input pins for specifying the operating mode.
Reset input pin
51
49
D
C
E
52, 53
54
50, 51
52
MD1, MD0
RST
P76, P77
General purpose I/O pins.
Analog input pins for the A/D converter (devices with a C suffix in the part
number)
55, 56
53, 54
AN22, AN23
I
INT6, INT7
P80
External interrupt request input pins
General purpose I/O pin.
TIN0
Event input pin for the reload timer
Trigger input pin for the A/D converter
External interrupt request input pin
General purpose I/O pin.
57
55
F
ADTG
INT12R
P81
TOT0
CKOT
INT13R
P82
Output pin for the reload timer
Output pin for the clock monitor
External interrupt request input pin
General purpose I/O pin.
58
56
F
SIN0
Serial data input pin for UART0
Event input pin for the reload timer
External interrupt request input pin
General purpose I/O pin.
59
60
57
58
M
F
TIN2
INT14R
P83
SOT0
TOT2
Serial data output pin for UART0
Output pin for the reload timer
(Continued)
Document Number: 002-04498 Rev. *A
Page 15 of 92
MB90340E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
P84
General purpose I/O pin.
Clock I/O pin for UART0
61
59
SCK0
F
INT15R
P85
External interrupt request input pin
General purpose I/O pin.
Serial data input pin for UART1
General purpose I/O pin.
Serial data output pin for UART1
General purpose I/O pin.
Clock I/O pin for UART1
Power (3.5 V to 5.5 V) input pin
GND pin
62
63
64
60
61
62
M
F
SIN1
P86
SOT1
P87
F
SCK1
65
66
63
64
VCC
VSS
P90 to P93
PPG1, 3, 5, 7
P94 to P97
General purpose I/O pins
Output pins for PPGs
67 to 70
71 to 74
65 to 68
69 to 72
F
General purpose I/O pins
F
Waveform output pins for output compares. This function is enabled when
the OCU enables waveform output.
OUT0 to OUT3
PA0
General purpose I/O pin.
75
76
73
74
RX0
INT8R
PA1
F
F
RX input pin for CAN0 Interface
External interrupt request input pin
General purpose I/O pin.
TX0
TX Output pin for CAN0
General purpose I/O pins. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P00 to P07
77 to 84
75 to 82
G
G
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
AD00 to AD07
INT8 to INT15
External interrupt request input pins.
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
P10
This function is enabled in single-chip mode.
85
83
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD08
TIN1
Event input pin for the reload timer
(Continued)
Document Number: 002-04498 Rev. *A
Page 16 of 92
MB90340E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled in single-chip mode.
P11
86
84
85
G
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
AD09
TOT1
Output pin for the reload timer
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
P12
This function is enabled in single-chip mode.
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
87
N
AD10
SIN3
Serial data input pin for UART3
INT11R
External interrupt request input pin
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
P13
This function is enabled in single-chip mode.
88
89
86
87
G
G
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
AD11
SOT3
Serial data output pin for UART3
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
P14
This function is enabled in single-chip mode.
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
AD12
SCK3
VCC
VSS
X1
Clock I/O pin for UART3
Power (3.5 V to 5.5 V) input pin
GND pin
90
91
92
93
88
89
90
91
Main clock output pin
Main clock input pin
A
X0
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
P15
This function is enabled in single-chip mode.
94
95
92
93
G
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
AD13
P16
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
G
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
AD14
(Continued)
Document Number: 002-04498 Rev. *A
Page 17 of 92
MB90340E Series
(Continued)
Pin No.
QFP100*1 LQFP100*2
I/O
Pin name
Circuit
Function
type*3
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
P17
This function is enabled in single-chip mode.
96
94
G
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
AD15
General purpose I/O pins. The register can be set to select whether to use a
pull-up resistor.In external bus mode, the pin is enabled as a
general-purpose I/O port when the corresponding bit in the external address
output control register (HACR) is 1.
P20 to P23
97 to 100
95 to 98
G
Output pins of the external address bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pins are enabled as
high address output pins (A16 to A19).
A16 to A19
PPG9,PPGB,PP
GD,PPGF
Output pins for PPGs
1 : FPT-100P-M06
2 : FPT-100P-M20
3 : For I/O circuit type, refer to “I/O Circuit Type”.
Document Number: 002-04498 Rev. *A
Page 18 of 92
MB90340E Series
4. I/O Circuit Type
Type
Circuit
Remarks
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 M
X1
Xout
A
X0
Standby control signal
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 M
X1A
Xout
B
X0A
Standby control signal
MASK ROM and evaluation products:
CMOS hysteresis input pin
R
R
CMOS hysteresis
C
Flash memory products:
CMOS input pin
inputs
MASK ROM and evaluation products:
CMOS hysteresis input pin
Pull-down resistor value: approx. 50 k
CMOS hysteresis
inputs
Flash memory products:
D
CMOS input pin
Pull-down
Resistor
No pull-down
CMOS hysteresis input pin
Pull-up resistor value: approx. 50 k
Pull-up
E
Resistor
R
CMOS hysteresis
inputs
(Continued)
Document Number: 002-04498 Rev. *A
Page 19 of 92
MB90340E Series
Type
Circuit
Remarks
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
N-ch
Pout
Nout
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
F
R
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
CMOS level output
Pull-up control
(IOL = 4 mA, IOH 4 mA)
CMOS hysteresis input (with function to disconnect
input during standby)
P-ch
P-ch
Pout
Nout
Automotive input (with function to
disconnect input during standby)
TTL input (with function to disconnect
N-ch
input during standby)
R
Programmable pull-up resistor: 50 k
G
approx.
CMOS hysteresis
input
Automotive input
TTL input
Standby control for
input shutdown
CMOS level output
(IOL = 3 mA, IOH 3 mA)
P-ch
Pout
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
N-ch
Nout
disconnect input during standby)
H
R
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
(Continued)
Document Number: 002-04498 Rev. *A
Page 20 of 92
MB90340E Series
Type
Circuit
Remarks
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
N-ch
Pout
Nout
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
A/D converter analog input
R
I
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
Analog input
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
N-ch
Pout
D/A analog output
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
A/D converter analog input
Nout
R
CMOS hysteresis
input
J
Automotive input
Standby control for
input shutdown
Analog input
Analog output
Power supply input protection circuit
P-ch
K
N-ch
A/D converter reference voltage power supply input
pin, with the protection
circuit
ANE
AVR
P-ch
N-ch
Flash memory devices do not have a protection
L
circuit against VCC for pin AVRH
ANE
Document Number: 002-04498 Rev. *A
Page 21 of 92
MB90340E Series
(Continued)
Type
Circuit
Remarks
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
N-ch
Pout
Nout
CMOS input (with function to disconnect input
during standby)
Automotive input (with function to
disconnect input during standby)
M
R
CMOS input
Automotive input
Standby control for
input shutdown
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS input (with function to disconnect input
during standby)
Pull-up control
Pout
P-ch
P-ch
Automotive input (with function to
disconnect input during standby)
N-ch
Nout
TTL input (with function to disconnect
input during standby)
R
N
Programmable pull-up resistor: 50 k
approx
CMOS input
Automotive input
TTL input
Standby control for
input shutdown
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
N-ch
Pout
Nout
CMOS input (with function to disconnect input
during standby)
Automotive input (with function to
disconnect input during standby)
A/D converter analog input
R
O
CMOS input
Automotive input
Standby control for
input shutdown
Analog input
Document Number: 002-04498 Rev. *A
Page 22 of 92
MB90340E Series
5. Handling Devices
1.Preventing latch-up
CMOS IC may suffer latch-up under the following conditions:
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
A voltage higher than the rated voltage is applied between VCC and VSS pins.
The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply
voltage.
2.Handling unused pins
Leaving unused input terminals open may lead to permanent damage due to malfunction and latch-up; pull up or pull down the
terminals through the resistors of 2 k or more.
3.Power supply pins (V /V
)
CC SS
If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected
inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the
standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Connect VCC and VSS pins to the device from the current supply source at a possibly low impedance.
As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 F as a bypass capacitor
between VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90340E
Series
Vcc
Vss
Vcc
Vss
4.Mode Pins (MD0 to MD2)
Connect the mode pins directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the
printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance
connection.
Document Number: 002-04498 Rev. *A
Page 23 of 92
MB90340E Series
5. Sequence for Turning On the Power Supply to the A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23) after turning-on the
digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does
not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
6.Connection of Unused A/D Converter Pins when the A/D Converter is Used
Connect unused pins of A/D converter to AVCC VCC, AVSS AVRH AVRL VSS
.
7.Crystal Oscillator Circuit
The X0, X1 pins and X0A, X1A pins may be possible causes of abnormal operation. Make sure to provide bypass capacitors via the
shortest distance from X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to
the utmost effort, that the oscillation circuit lines do not cross the lines of other circuits. It is highly recommended to provide a printed
circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation.
For each of the mass-production products, request an oscillator evaluation from the manufacturer of the oscillator you are using.
8. Pull-up/down resistors
The MB90340E Series does not support internal pull-up/down resistors (except for the pull-up resistors built into ports 0 to 3). Use
external components where needed.
9.Using external clock
To use an external clock, drive the X0 pin and leave the X1 pin open.
MB90340E Series
X0
Open
X1
10.Precautions when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
11.Notes on operation in PLL clock mode
If PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external
oscillator or the external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
12.Notes on Power-On
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power-on to 50 s or more (0.2 V to 2.7
V)
Document Number: 002-04498 Rev. *A
Page 24 of 92
MB90340E Series
13.Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range.
Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple
variations (peak- to-peak values) at commercial frequencies (50 MHz/60 MHz) fall below 10 of the standard VCC supply voltage
and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
14.Port 0 to Port 3 Output During Power-on (External-bus Mode)
As shown below, when the power is turned on in External-Bus mode, there is a possibility that output signal of Port 0 to Port 3 might
be unstable irrespective of the reset input.
1/2VCC
VCC
Port0 to Port3
Port0 to Port3 outputs
might be unstable
Port0 to Port3 outputs = Hi-Z
15.Notes on Using the CAN Function
To use the CAN function, please set the DIRECT bit of the CAN Direct Mode Register (CDMR) to 1.
16.Flash Security Function (except for MB90F346E)
A security bit is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Refer to following table for the address of the security bit.
Flash memory size
Address of the security bit
MB90F347E
Embedded 1 Mbit Flash Memory
FE0001H
FC0001H
F80001H
MB90F342E
MB90F349E
Embedded 2 Mbits Flash Memory
Embedded 4 Mbits Flash Memory
MB90F345E
17.Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data
due to the noise.
Document Number: 002-04498 Rev. *A
Page 25 of 92
MB90340E Series
6. Block Diagrams
MB90V340E-101/102
X0,X1
X0A,X1A*
RST
Clock
16LX
CPU
Controller
Free-run
Timer 0
FRCK0
RAM
30 Kbytes
Input
Capture
IN7 to IN0
8 channels
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
5 channels
Free-run
Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 channels
LIN-UART
5 channels
RX2 to RX0
TX2 to TX0
16-bit Reload
Timer
4 channels
AVCC
TIN3 to TIN0
AVSS
AN23 to AN0
AVRH
TOT3 to TOT0
8/10-bit
A/D converter
24 channels
AD15 to AD00
A23 to A16
ALE
AVRL
ADTG
RD
10-bit
D/A converter
2 channels
External
Bus
Interface
WR/WRL
WRH
DA01, DA00
HRQ
HAK
8/16-bit
PPG
16/8 channels
PPGF to PPG0
RDY
CLK
I2C
Interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
External
Interrupt
16 channels
INT7 to INT0
DMAC
Clock
CKOT
Monitor
* : Only for MB90V340E-102
Document Number: 002-04498 Rev. *A
Page 26 of 92
MB90340E Series
MB90341E(S), MB90341CE(S), MB90342E(S), MB90342CE(S), MB90F342E(S), MB90F342CE(S), MB90F345E(S),
MB90F345CE(S), MB90346E(S), MB90346CE(S), MB90F346E(S), MB90F346CE(S), MB90347E(S), MB90347CE(S),
MB90F347E(S), MB90F347CE(S), MB90348E(S), MB90348CE(S), MB90349E(S), MB90349CE(S), MB90F349E(S), MB90F349CE(S)
X0,X1
Clock
1
16LX
CPU
X0A,X1A*
RST
Controller
Free-run
Timer 0
RAM
2 K/6 K/16 K/
20 Kbytes
FRCK0
Input
Capture
IN7 to IN0
8 channels
ROM/Flash
64 K/128 K
256 K/384 K/
512 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
4 channels
Free-run
Timer 1
SOT3 to SOT0
SCK3 to SCK0
SIN3 to SIN0
CAN
Controller
1/2 channels*
3
LIN-UART
4 channels
RX0, RX1*
3
3
TX0, TX1*
16-bit Reload
Timer
4 channels
AV
AV
CC
SS
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
A/D Converter
16/24
AN15 to AN0
AN23 to AN16*
AVRH
2
AD15 to AD00
A23 to A16
ALE
channels
AVRL
ADTG
RD
External
Bus
Interface
WR/WRL
WRH
8/16-bit
PPG
16/8 channels
HRQ
PPGF to PPG0
HAK
RDY
CLK
2
2
I C
SDA1, SDA0*
Interface
2 channels
2
SCL1, SCL0*
INT15 to INT8
(INT15R to INT8R)
External
Interrupt
INT7 to INT0
16 channels
DMAC
Clock
Monitor
CKOT
*1 : Only for devices with an S suffix in the part number
*2 : Only for devices with a C suffix in the part number
*3 : Only the MB90341E(S)/ 341CE(S)/ 342E(S)/ 342CE(S)/ F342E(S)/F342CE(S)/F345E(S)/ F345CE(S)
are equipped with 2 CAN channels
Document Number: 002-04498 Rev. *A
Page 27 of 92
MB90340E Series
7. Memory Map
MB90V340E-101/102
MB90F345E(S)/F345CE(S)
000000
0000EF
H
H
000000
0000EF
H
H
Peripheral
Peripheral
External access area
External access area
000100
H
000100
H
RAM 20 Kbytes
RAM 30 Kbytes
0050FF
007900
H
H
0078FF
007900
H
H
Peripheral
Peripheral
007FFF
008000
H
H
007FFF
H
H
008000
ROM
ROM
(image of FF bank)
(image of FF bank)
00FFFF
F80000
H
H
00FFFF
H
H
External access area
External access area
ROM (F8 bank)
F80000
ROM (F8 bank)
F8FFFF
F90000
H
H
F8FFFF
H
H
F90000
ROM (F9 bank)
ROM (FA bank)
ROM (FB bank)
ROM (FC bank)
ROM (FD bank)
ROM (FE bank)
ROM (FF bank)
ROM (F9 bank)
ROM (FA bank)
ROM (FB bank)
ROM (FC bank)
ROM (FD bank)
ROM (FE bank)
ROM (FF bank)
F9FFFF
FA0000
H
H
F9FFFF
H
H
FA0000
FAFFFF
FB0000
H
H
FAFFFF
FB0000
H
H
FBFFFF
FC0000
H
H
FBFFFF
FC0000
H
H
FCFFFF
H
H
FCFFFF
FD0000
H
H
FD0000
FDFFFF
FE0000
H
H
FDFFFF
FE0000
H
H
FEFFFF
FF0000
H
H
FEFFFF
FF0000
H
H
FFFFFF
H
FFFFFF
H
: Not accessible
Document Number: 002-04498 Rev. *A
Page 28 of 92
MB90340E Series
MB90342E(S)/342CE(S)
MB90F342E(S)/F342CE(S)
MB90349E(S)/349CE(S)
MB90F349E(S)/F349CE(S)
MB90341E(S)/341CE(S)
MB90348E(S)/348CE(S) MB90F347E(S)/F347CE(S)
MB90347E(S)/347CE(S)
MB90346E(S)/346CE(S)
MB90F346E(S)/F346CE(S)
000000H
000000H
0000EFH
000000H
0000EFH
000000H
0000EFH
Peripheral
0000EFH
Peripheral
Peripheral
Peripheral
External access area
RAM 2 Kbytes
External access area
000100H
External access area
External access area
000100H
0008FFH
000100H
000100H
0018FFH
RAM 6 Kbytes
RAM 16 Kbytes
RAM 16 Kbytes
003FFFH
003FFFH
007900H
007900H
007900H
007900H
Peripheral
Peripheral
Peripheral
Peripheral
007FFFH
008000H
007FFFH
008000H
007FFFH
008000H
007FFFH
008000H
ROM (image
of FF bank)
ROM (image
of FF bank)
ROM (image
of FF bank)
ROM (image
of FF bank)
00FFFFH
00FFFFH
00FFFFH
00FFFFH
External
External
External
External
access area
access area
access area
access area
FC0000H
ROM (FC bank)
FCFFFFH
FD0000H
ROM (FD bank)
FDFFFFH
FE0000H
FE0000H
FE0000H
FE0000H
ROM (FE bank)
FEFFFFH
ROM (FE bank)
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
FEFFFFH
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FF0000H
FF0000H
ROM (FF bank)
FFFFFFH
ROM (FF bank)
FFFFFFH
FFFFFFH
FFFFFFH
: Not accessible
Note: :An image of the data in the FF bank of ROM is visible in the upper part of bank 00, which makes it possible for the C
compiler to use the small memory model. The lower 16 bits of addresses in the FF bank are the same as the lower 16 bits
of addresses in the 00 bank so that tables stored in the ROM can be accessed without using the far specifier in the pointer
declaration.
For example, when the address 00C000H is accessed, the data at FFC000H in ROM is actually accessed.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
As a result, the image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
Document Number: 002-04498 Rev. *A
Page 29 of 92
MB90340E Series
8. I/O Map
Address
Register
Abbreviation
PDR0
Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
00000DH
00000EH
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
000019H
00001AH
00001BH
00001CH
00001DH
00001EH
00001FH
Port 0 Data Register
Port 1 Data Register
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 5, A/D
Port 6, A/D
Port 7, A/D
Ports
PDR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 Data Register
PDR2
Port 3 Data Register
PDR3
Port 4 Data Register
PDR4
Port 5 Data Register
PDR5
Port 6 Data Register
PDR6
Port 7 Data Register
PDR7
Port 8 Data Register
PDR8
Port 9 Data Register
PDR9
Port A Data Register
PDRA
ADER5
ADER6
ADER7
ILSR0
ILSR1
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
Port 5 Analog Input Enable Register
Port 6 Analog Input Enable Register
Port 7 Analog Input Enable Register
Input Level Select Register 0
Input Level Select Register 1
Port 0 Direction Register
Port 1 Direction Register
Port 2 Direction Register
Port 3 Direction Register
Port 4 Direction Register
Port 5 Direction Register
Port 6 Direction Register
Port 7 Direction Register
Port 8 Direction Register
Port 9 Direction Register
Port A Direction Register
Reserved
11111111B
11111111B
XXXXXXXXB
XXXX0XXXB
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000100B
Ports
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 0 Pull-up Control Register
Port 1 Pull-up Control Register
Port 2 Pull-up Control Register
Port 3 Pull-up Control Register
PUCR0
PUCR1
PUCR2
PUCR3
R/W
Port 0
Port 1
Port 2
Port 3
00000000B
00000000B
00000000B
00000000B
R/W
R/W
W, R/W
(Continued)
Document Number: 002-04498 Rev. *A
Page 30 of 92
MB90340E Series
Address
000020H
000021H
000022H
000023H
Register
Abbreviation
Access Resource name Initial value
Serial Mode Register 0
SMR0
W,R/W
W,R/W
R/W
00000000B
00000000B
00000000B
00001000B
Serial Control Register 0
SCR0
Reception/Transmission Data Register 0
Serial Status Register 0
RDR0/TDR0
SSR0
R,R/W
UART0
Extended Communication Control
Register 0
R,W,
R/W
000024H
ECCR0
000000XXB
000025H
000026H
000027H
000028H
000029H
00002AH
00002BH
Extended Status/Control Register 0
Baud Rate Generator Register 00
Baud Rate Generator Register 01
Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
00000000B
00001000B
R/W
R/W
W,R/W
W,R/W
R/W
Serial Control Register 1
SCR1
Reception/Transmission Data Register 1
Serial Status Register 1
RDR1/TDR1
SSR1
R,R/W
UART1
Extended Communication Control
Register 1
R,W,
R/W
00002CH
ECCR1
000000XXB
00002DH
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
000036H
000037H
000038H
000039H
00003AH
Extended Status/Control Register 1
Baud Rate Generator Register 10
Baud Rate Generator Register 11
PPG 0 Operation Mode Control Register
PPG 1 Operation Mode Control Register
PPG 0/PPG 1 Count Clock Select Register
Reserved
ESCR1
BGR10
BGR11
PPGC0
PPGC1
PPG01
R/W
00000100B
00000000B
00000000B
0X000XX1B
0X000001B
000000X0B
R/W
R/W
W,R/W
W,R/W
R/W
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
PPG 2 Operation Mode Control Register
PPG 3 Operation Mode Control Register
PPG 2/PPG 3 Count Clock Select Register
Reserved
PPGC2
PPGC3
PPG23
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
PPG 4 Operation Mode Control Register
PPG 5 Operation Mode Control Register
PPG 4/PPG 5 Clock Select Register
PPGC4
PPGC5
PPG45
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
Address Match
Detection 1
00003BH
Address Detect Control Register 1
PACSR1
R/W
00000000B
00003CH
00003DH
00003EH
00003FH
PPG 6 Operation Mode Control Register
PPG 7 Operation Mode Control Register
PPG 6/PPG 7 Count Clock Control Register
Reserved
PPGC6
PPGC7
PPG67
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit PPG 6/7
(Continued)
Document Number: 002-04498 Rev. *A
Page 31 of 92
MB90340E Series
Address
000040H
000041H
Register
Abbreviation Access
Resource name
Initial value
0X000XX1B
0X000001B
PPG 8 Operation Mode Control Register
PPG 9 Operation Mode Control Register
PPGC8
PPGC9
W,R/W
W,R/W
16-bit PPG 8/9
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
PPG 8/PPG 9 Count Clock Control
Register
000042H
PPG89
R/W
000000X0B
000043H
000044H
000045H
Reserved
PPG A Operation Mode Control Register
PPG B Operation Mode Control Register
PPGCA
PPGCB
W,R/W
W,R/W
0X000XX1B
0X000001B
PPG A/PPG B Count Clock Select
Register
000046H
PPGAB
R/W
000000X0B
000047H
000048H
000049H
Reserved
PPG C Operation Mode Control Register
PPG D Operation Mode Control Register
PPGCC
PPGCD
W,R/W
W,R/W
0X000XX1B
0X000001B
PPG C/PPG D Count Clock Select
Register
00004AH
PPGCD
R/W
000000X0B
00004BH
00004CH
00004DH
Reserved
PPG E Operation Mode Control Register
PPG F Operation Mode Control Register
PPGCE
PPGCF
W,R/W
W,R/W
0X000XX1B
0X000001B
PPG E/PPG F Count Clock Select
Register
00004EH
PPGEF
R/W
000000X0B
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
000059H
00005AH
00005BH
00005CH
00005DH
00005EH
00005FH
Reserved
Input Capture Control Status 0/1
Input Capture Edge 0/1
ICS01
ICE01
ICS23
ICE23
ICS45
ICE45
ICS67
ICE67
OCS0
OCS1
OCS2
OCS3
OCS4
OCS5
OCS6
OCS7
R/W
R/W, R
R/W
R
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXX000XXB
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
Input Capture Control Status 2/3
Input Capture Edge 2/3
Input Capture Control Status 4/5
Input Capture Edge 4/5
R/W
R
Input Capture Control Status 6/7
Input Capture Edge 6/7
R/W
R/W, R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare Control Status 0
Output Compare Control Status 1
Output Compare Control Status 2
Output Compare Control Status 3
Output Compare Control Status 4
Output Compare Control Status 5
Output Compare Control Status 6
Output Compare Control Status 7
(Continued)
Document Number: 002-04498 Rev. *A
Page 32 of 92
MB90340E Series
Address
000060H
000061H
000062H
000063H
000064H
000065H
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
00006DH
00006EH
00006FH
Register
Abbreviation
TMCSR0
TMCSR0
TMCSR1
TMCSR1
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
Access
Resource name
Initial value
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
Timer Control Status 0
R/W
16-bit Reload
Timer 0
Timer Control Status 0
Timer Control Status 1
Timer Control Status 1
Timer Control Status 2
Timer Control Status 2
Timer Control Status 3
Timer Control Status 3
A/D Control Status 0
A/D Control Status 1
A/D Data 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
16-bit Reload
Timer 1
16-bit Reload
Timer 2
16-bit Reload
Timer 3
ADCS1
ADCR0
A/D Converter
ROM Mirror
A/D Data 1
ADCR1
R
ADC Setting 0
ADSR0
R/W
R/W
ADC Setting 1
ADSR1
Reserved
ROM Mirror Function Select
ROMM
W
XXXXXXX1B
000070H
to
Reserved for CAN Controller 0/1. Refer to “CAN Controllers”
Reserved
00008FH
000090H
to
00009AH
DMA Descriptor Channel Specified
Register
00009BH
DCSR
R/W
00000000B
DMA
00009CH
00009DH
DMA Status L Register
DMA Status H Register
DSRL
DSRH
R/W
R/W
00000000B
00000000B
Address Match
Detection 0
00009EH
00009FH
0000A0H
0000A1H
Address Detect Control Register 0
PACSR0
DIRR
R/W
00000000B
XXXXXXX0B
00011000B
11111100B
Delayed Interrupt Trigger/Release
Register
R/W
Delayed Interrupt
Low Power
Control Circuit
Low-power Mode Control Register
Clock Selection Register
LPMCR
CKSCR
W,R/W
R,R/W
Low Power
Control Circuit
0000A2H,
0000A3H
Reserved
0000A4H
DMA Stop Status Register
DSSR
R/W
DMA
00000000B
(Continued)
Document Number: 002-04498 Rev. *A
Page 33 of 92
MB90340E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
Automatic Ready Function Select
Register
0000A5H
ARSR
W
0011XX00B
External Memory
Access
External Address Output Control
Register
0000A6H
HACR
W
00000000B
0000A7H
0000A8H
0000A9H
0000AAH
0000ABH
0000ACH
0000ADH
Bus Control Signal Selection Register
Watchdog Control Register
Time Base Timer Control Register
Watch Timer Control Register
Reserved
ECSR
WDTC
TBTC
WTC
W
0000000XB
XXXXX111B
1XX00100B
1X001000B
R,W
Watchdog Timer
Time Base Timer
Watch Timer
W,R/W
R,R/W
DMA Enable L Register
DERL
DERH
R/W
R/W
00000000B
00000000B
DMA
DMA Enable H Register
Flash Control Status Register
0000AEH
FMCS
R,R/W
Flash Memory
000X0000B
(Flash memory devices only.
Otherwise reserved)
0000AFH
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
0000C0H
0000C1H
0000C2H
0000C3H
Reserved
Interrupt Control Register 00
Interrupt Control Register 01
Interrupt Control Register 02
Interrupt Control Register 03
Interrupt Control Register 04
Interrupt Control Register 05
Interrupt Control Register 06
Interrupt Control Register 07
Interrupt Control Register 08
Interrupt Control Register 09
Interrupt Control Register 10
Interrupt Control Register 11
Interrupt Control Register 12
Interrupt Control Register 13
Interrupt Control Register 14
Interrupt Control Register 15
D/A Converter Data 0
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
DAT0
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
XXXXXXXXB
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
Interrupt Control
D/A Converter Data 1
DAT1
R/W
D/A Converter
D/A Control 0
DACR0
DACR1
R/W
D/A Control 1
R/W
(Continued)
Document Number: 002-04498 Rev. *A
Page 34 of 92
MB90340E Series
Address
Register
Abbreviation Access
Resource name
Initial value
0000C4H,
0000C5H
Reserved
0000C6H
0000C7H
0000C8H
0000C9H
0000CAH
0000CBH
0000CCH
0000CDH
0000CEH
0000CFH
0000D0H
0000D1H
0000D2H
0000D3H
External Interrupt Enable 0
ENIR0
EIRR0
ELVR0
ELVR0
ENIR1
EIRR1
ELVR1
ELVR1
EISSR
PSCCR
BAPL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
XXXX0000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
External Interrupt Source 0
External Interrupt 0
External Interrupt Level Setting 0
External Interrupt Level Setting 0
External Interrupt Enable 1
External Interrupt Source 1
External Interrupt Level Setting 1
External Interrupt Level Setting 1
External Interrupt Source Select
PLL/Sub clock Control Register
DMA Buffer Address Pointer L Register
DMA Buffer Address Pointer M Register
DMA Buffer Address Pointer H Register
DMA Control Register
External Interrupt 1
PLL
R/W
R/W
R/W
R/W
BAPM
BAPH
DMACS
I/O Register Address Pointer L
Register
DMA
0000D4H
0000D5H
IOAL
IOAH
R/W
R/W
XXXXXXXXB
XXXXXXXXB
I/O Register Address Pointer H
Register
0000D6H
0000D7H
0000D8H
0000D9H
Data Counter L Register
Data Counter H Register
Serial Mode Register 2
Serial Control Register 2
DCTL
DCTH
SMR2
SCR2
R/W
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
R/W
W,R/W
W,R/W
Reception/Transmission Data
Register 2
0000DAH
0000DBH
0000DCH
RDR2/TDR2
SSR2
R/W
00000000B
00001000B
000000XXB
Serial Status Register 2
R,R/W
UART2
Extended Communication Control
Register 2
R,W,
R/W
ECCR2
0000DDH
0000DEH
0000DFH
Extended Status Control Register 2
Baud Rate Generator Register 20
Baud Rate Generator Register 21
ESCR2
BGR20
BGR21
R/W
R/W
R/W
00000100B
00000000B
00000000B
0000E0H
to
Reserved for CAN Controller 2. Refer to “CAN Controllers”
External
0000EFH
0000F0H
to
0000FFH
(Continued)
Document Number: 002-04498 Rev. *A
Page 35 of 92
MB90340E Series
Address
007900H
007901H
007902H
007903H
007904H
007905H
007906H
007907H
007908H
007909H
00790AH
00790BH
00790CH
00790DH
00790EH
00790FH
007910H
007911H
007912H
007913H
007914H
007915H
007916H
007917H
007918H
007919H
00791AH
00791BH
00791CH
00791DH
00791EH
00791FH
007920H
007921H
007922H
007923H
Register
Abbreviation
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reload Register L0
R/W
Reload Register H0
Reload Register L1
Reload Register H1
Reload Register L2
Reload Register H2
Reload Register L3
Reload Register H3
Reload Register L4
Reload Register H4
Reload Register L5
Reload Register H5
Reload Register L6
Reload Register H6
Reload Register L7
Reload Register H7
Reload Register L8
Reload Register H8
Reload Register L9
Reload Register H9
Reload Register LA
Reload Register HA
Reload Register LB
Reload Register HB
Reload Register LC
Reload Register HC
Reload Register LD
Reload Register HD
Reload Register LE
Reload Register HE
Reload Register LF
Reload Register HF
Input Capture 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
16-bit PPG 6/7
16-bit PPG 8/9
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 0
IPCP0
R
Input Capture 1
IPCP1
R
Input Capture 1
IPCP1
R
(Continued)
Document Number: 002-04498 Rev. *A
Page 36 of 92
MB90340E Series
Address
007924H
007925H
007926H
007927H
007928H
007929H
00792AH
00792BH
00792CH
00792DH
00792EH
00792FH
007930H
007931H
007932H
007933H
007934H
007935H
007936H
007937H
007938H
007939H
00793AH
00793BH
00793CH
00793DH
00793EH
00793FH
007940H
007941H
007942H
007943H
007944H
007945H
007946H
007947H
Register
Abbreviation
IPCP2
Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
Input Capture 2
Input Capture 2
Input Capture 3
Input Capture 3
Input Capture 4
Input Capture 4
Input Capture 5
Input Capture 5
Input Capture 6
Input Capture 6
Input Capture 7
Input Capture 7
R
IPCP2
R
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
Free-run Timer 0
IPCP3
R
IPCP3
R
IPCP4
R
IPCP4
R
IPCP5
R
IPCP5
R
IPCP6
R
IPCP6
R
IPCP7
R
IPCP7
R
Output Compare 0
Output Compare 0
Output Compare 1
Output Compare 1
Output Compare 2
Output Compare 2
Output Compare 3
Output Compare 3
Output Compare 4
Output Compare 4
Output Compare 5
Output Compare 5
Output Compare 6
Output Compare 6
Output Compare 7
Output Compare 7
Timer Data 0
OCCP0
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
OCCP4
OCCP4
OCCP5
OCCP5
OCCP6
OCCP6
OCCP7
OCCP7
TCDT0
TCDT0
TCCSL0
TCCSH0
TCDT1
TCDT1
TCCSL1
TCCSH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer Data 0
00000000B
Timer Control Status 0
Timer Control Status 0
Timer Data 1
00000000B
0XXXXXXXB
00000000B
Timer Data 1
00000000B
Free-run Timer 1
Timer Control Status 1
Timer Control Status 1
00000000B
0XXXXXXXB
(Continued)
Document Number: 002-04498 Rev. *A
Page 37 of 92
MB90340E Series
Address
007948H
007949H
00794AH
00794BH
00794CH
00794DH
00794EH
00794FH
007950H
007951H
Register
Abbreviation
Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
R/W
16-bit Reload
Timer 0
Timer 0/Reload 0
Timer 1/Reload 1
Timer 2/Reload 2
Timer 3/Reload 3
TMR0/TMRLR0
R/W
R/W
16-bit Reload
Timer 1
TMR1/TMRLR1
TMR2/TMRLR2
TMR3/TMRLR3
R/W
R/W
16-bit Reload
Timer 2
R/W
R/W
16-bit Reload
Timer 3
R/W
Serial Mode Register 3
Serial Control Register 3
SMR3
SCR3
W,R/W
W,R/W
00000000B
Reception/Transmission Data
Register 3
007952H
007953H
007954H
RDR3/TDR3
SSR3
R/W
00000000B
00001000B
000000XXB
Serial Status Register 3
R,R/W
UART3
Extended Communication Control
Register 3
R,W,
R/W
ECCR3
007955H
007956H
007957H
007958H
007959H
Extended Status Control Register
Baud Rate Generator Register 30
Baud Rate Generator Register 31
Serial Mode Register 4
ESCR3
BGR30
BGR31
SMR4
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W
R/W
W,R/W
W,R/W
Serial Control Register 4
SCR4
Reception/Transmission Data
Register 4
00795AH
00795BH
00795CH
RDR4/TDR4
SSR4
R/W
00000000B
00001000B
000000XXB
Serial Status Register 4
R,R/W
UART4
Extended Communication Control
Register 4
R,W,
R/W
ECCR4
00795DH
00795EH
00795FH
Extended Status Control Register
Baud Rate Generator Register 40
Baud Rate Generator Register 41
ESCR4
BGR40
BGR41
R/W
R/W
R/W
00000100B
00000000B
00000000B
007960H
to
00796BH
Reserved
00796CH
00796DH
00796EH
00796FH
Clock Output Enable Register
Reserved
CLKR
R/W
Clock Monitor
XXXX0000B
CAN Direct Mode Register
CAN Switch Register
CDMR
R/W
R/W
CAN Clock sync
CAN 0/1
XXXXXXX0B
XXXXXX00B
CANSWR
(Continued)
Document Number: 002-04498 Rev. *A
Page 38 of 92
MB90340E Series
Address
007970H
007971H
007972H
007973H
007974H
007975H
007976H
007977H
007978H
Register
I2C Bus Status Register 0
I2C Bus Control Register 0
Abbreviation
IBSR0
Access
Resource name
Initial value
00000000B
00000000B
00000000B
00000000B
11111111B
R
IBCR0
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
I2C 10-bit Slave Address Register 0
I2C Interface 0
I2C 10-bit Slave Address Mask
Register 0
00111111B
00000000B
01111111B
I2C 7-bit Slave Address Register 0
I2C 7-bit Slave Address Mask Register 0
I2C Data Register 0
ISMK0
IDAR0
00000000B
007979H,
00797AH
Reserved
00797BH
I2C Clock Control Register 0
ICCR0
R/W
I2C Interface 0
00011111B
00797CH
to
00797FH
Reserved
007980H
007981H
007982H
007983H
007984H
007985H
007986H
007987H
007988H
I2C Bus Status Register 1
I2C Bus Control Register 1
IBSR1
IBCR1
ITBAL1
ITBAH1
ITMKL1
ITMKH1
ISBA1
R
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2C 10-bit Slave Address Register 1
I2C Interface 1
I2C 10-bit Slave Address Mask
Register 1
I2C 7-bit Slave Address Register 1
I2C 7-bit Slave Address Mask Register 1
I2C Data Register 1
ISMK1
IDAR1
007989H,
00798AH
Reserved
00798BH
I2C Clock Control Register 1
ICCR1
CMCR
R/W
I2C Interface 1
Clock Modulator
00011111B
0001X000B
00798CH
to
0079C1H
Reserved
0079C2H
Clock Modulator Control Register
Reserved
R, R/W
0079C3H
to
0079DFH
(Continued)
Document Number: 002-04498 Rev. *A
Page 39 of 92
MB90340E Series
(Continued)
Address
0079E0H
0079E1H
0079E2H
0079E3H
0079E4H
0079E5H
0079E6H
0079E7H
0079E8H
Register
Abbreviation
PADR0
Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Detect Address Setting 0
R/W
Detect Address Setting 0
Detect Address Setting 0
Detect Address Setting 1
Detect Address Setting 1
Detect Address Setting 1
Detect Address Setting 2
Detect Address Setting 2
Detect Address Setting 2
PADR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PADR0
PADR1
Address Match
Detection 0
PADR1
PADR1
PADR2
PADR2
PADR2
0079E9H
to
0079EFH
Reserved
0079F0H
0079F1H
0079F2H
0079F3H
0079F4H
0079F5H
0079F6H
0079F7H
0079F8H
Detect Address Setting 3
Detect Address Setting 3
Detect Address Setting 3
Detect Address Setting 4
Detect Address Setting 4
Detect Address Setting 4
Detect Address Setting 5
Detect Address Setting 5
Detect Address Setting 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
0079FFH
Reserved
007A00H
to
Reserved for CAN Controller 0. Refer to “CAN Controllers
Reserved for CAN Controller 0. Refer to “CAN Controllers”
Reserved for CAN Controller 1. Refer to “CAN Controllers”
Reserved for CAN Controller 1. Refer to “CAN Controllers”
Reserved
007AFFH
007B00H
to
007BFFH
007C00H
to
007CFFH
007D00H
to
007DFFH
007E00H
to
007FFFH
Note: Initial value of “X” represents unknown value.
Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
Document Number: 002-04498 Rev. *A
Page 40 of 92
MB90340E Series
9. CAN Controllers
The CAN controller has the following features:
Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
Supports transmission of data frames by receiving remote frames
16 transmission/reception message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID
acceptance mask
Two acceptance mask registers in either standard frame format or extended frame formats
Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers (1)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
000070H
000080H
Message Buffer
Valid Register
00000000B
00000000B
BVALR
R/W
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
Transmit Request
Register
00000000B
00000000B
TREQR
TCANR
TCR
R/W
W
Transmit Cancel
Register
00000000B
00000000B
Transmission
Complete Register
00000000B
00000000B
R/W
R/W
R/W
R/W
R/W
Receive Complete
Register
00000000B
00000000B
RCR
Remote Request
Receiving Register
00000000B
00000000B
RRTRR
ROVRR
RIER
Receive Overrun
Register
00000000B
00000000B
Reception Interrupt
Enable Register
00000000B
00000000B
Document Number: 002-04498 Rev. *A
Page 41 of 92
MB90340E Series
List of Control Registers (2)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
007B00H
007D00H
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
Control Status
Register
CSR
007B01H
007B02H
007B03H
007B04H
007B05H
007B06H
007B07H
007B08H
007B09H
007B0AH
007B0BH
007B0CH
007B0DH
007B0EH
007B0FH
007B10H
007B11H
007B12H
007B13H
007B14H
007B15H
007B16H
007B17H
007B18H
007B19H
007B1AH
007B1BH
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007D0DH
007D0EH
007D0FH
007D10H
007D11H
007D12H
007D13H
007D14H
007D15H
007D16H
007D17H
007D18H
007D19H
007D1AH
007D1BH
Last Event
000X0000B
LEIR
R/W
Indicator Register
XXXXXXXXB
Receive And Transmit
Error Counter
00000000B
00000000B
RTEC
BTR
R
Bit Timing
Register
11111111B
X1111111B
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
IDE Register
IDER
TRTRR
RFWTR
TIER
Transmit RTR
Register
00000000B
00000000B
Remote Frame
Receive Waiting
Register
XXXXXXXXB
XXXXXXXXB
Transmit Interrupt
Enable Register
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
Acceptance Mask
Select Register
AMSR
AMR0
AMR1
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance Mask
Register 0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance Mask
Register 1
XXXXXXXXB
XXXXXXXXB
Document Number: 002-04498 Rev. *A
Page 42 of 92
MB90340E Series
List of Message Buffers (ID Registers) (1)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
007A00H
to
007A1FH
007C00H
to
XXXXXXXXB
to
XXXXXXXXB
General-
Purpose RAM
R/W
007C1FH
007C20H
007C21H
007C22H
007C23H
007C24H
007C25H
007C26H
007C27H
007C28H
007C29H
007C2AH
007C2BH
007C2CH
007C2DH
007C2EH
007C2FH
007C30H
007C31H
007C32H
007C33H
007C34H
007C35H
007C36H
007C37H
007C38H
007C39H
007C3AH
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
007A20H
007A21H
007A22H
007A23H
007A24H
007A25H
007A26H
007A27H
007A28H
007A29H
007A2AH
007A2BH
007A2CH
007A2DH
007A2EH
007A2FH
007A30H
007A31H
007A32H
007A33H
007A34H
007A35H
007A36H
007A37H
007A38H
007A39H
007A3AH
007A3BH
007A3CH
007A3DH
007A3EH
007A3FH
XXXXXXXXB
XXXXXXXXB
ID Register 0
IDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 1
ID Register 2
ID Register 3
ID Register 4
ID Register 5
ID Register 6
ID Register 7
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Document Number: 002-04498 Rev. *A
Page 43 of 92
MB90340E Series
List of Message Buffers (ID Registers) (2)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
007A40H
007C40H
XXXXXXXXB
XXXXXXXXB
007A41H
007A42H
007A43H
007A44H
007A45H
007A46H
007A47H
007A48H
007A49H
007A4AH
007A4BH
007A4CH
007A4DH
007A4EH
007A4FH
007A50H
007A51H
007A52H
007A53H
007A54H
007A55H
007A56H
007A57H
007A58H
007A59H
007A5AH
007A5BH
007A5CH
007A5DH
007A5EH
007A5FH
007C41H
007C42H
007C43H
007C44H
007C45H
007C46H
007C47H
007C48H
007C49H
007C4AH
007C4BH
007C4CH
007C4DH
007C4EH
007C4FH
007C50H
007C51H
007C52H
007C53H
007C54H
007C55H
007C56H
007C57H
007C58H
007C59H
007C5AH
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
ID Register 8
IDR8
IDR9
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 9
ID Register 10
ID Register 11
ID Register 12
ID Register 13
ID Register 14
ID Register 15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Document Number: 002-04498 Rev. *A
Page 44 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
Register
Abbreviation
Access
Initial Value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
CAN0
CAN1
007A60H
007C60H
DLC Register 0
DLCR0
R/W
007A61H
007A62H
007A63H
007A64H
007A65H
007A66H
007A67H
007A68H
007A69H
007A6AH
007A6BH
007A6CH
007A6DH
007A6EH
007A6FH
007A70H
007A71H
007A72H
007A73H
007A74H
007A75H
007A76H
007A77H
007A78H
007A79H
007A7AH
007A7BH
007A7CH
007A7DH
007A7EH
007A7FH
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
DLC Register 1
DLC Register 2
DLC Register 3
DLC Register 4
DLC Register 5
DLC Register 6
DLC Register 7
DLC Register 8
DLC Register 9
DLC Register 10
DLC Register 11
DLC Register 12
DLC Register 13
DLC Register 14
DLC Register 15
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Document Number: 002-04498 Rev. *A
Page 45 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
007A80H
to
007A87H
007C80H
to
007C87H
XXXXXXXXB
to
XXXXXXXXB
Data Register 0
(8 bytes)
DTR0
R/W
007A88H
to
007A8FH
007C88H
to
007C8FH
XXXXXXXXB
to
XXXXXXXXB
Data Register 1
(8 bytes)
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
007A90H
to
007A97H
007C90H
to
007C97H
XXXXXXXXB
to
XXXXXXXXB
Data Register 2
(8 bytes)
007A98H
to
007A9FH
007C98H
to
007C9FH
XXXXXXXXB
to
XXXXXXXXB
Data Register 3
(8 bytes)
007AA0H
to
007AA7H
007CA0H
to
007CA7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 4
(8 bytes)
007AA8H
to
007AAFH
007CA8H
to
007CAFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 5
(8 bytes)
007AB0H
to
007AB7H
007CB0H
to
007CB7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 6
(8 bytes)
007AB8H
to
007ABFH
007CB8H
to
007CBFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 7
(8 bytes)
007AC0H
to
007AC7H
007CC0H
to
007CC7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 8
(8 bytes)
007AC8H
to
007ACFH
007CC8H
to
007CCFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 9
(8 bytes)
007AD0H
to
007AD7H
007CD0H
to
007CD7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 10
(8 bytes)
007AD8H
to
007ADFH
007CD8H
to
007CDFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 11
(8 bytes)
007AE0H
to
007AE7H
007CE0H
to
007CE7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 12
(8 bytes)
007AE8H
to
007AEFH
007CE8H
to
007CEFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 13
(8 bytes)
Document Number: 002-04498 Rev. *A
Page 46 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
007AF0H
to
007AF7H
007CF0H
to
007CF7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 14
(8 bytes)
DTR14
R/W
007AF8H
to
007AFFH
007CF8H
to
007CFFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 15
(8 bytes)
DTR15
R/W
Document Number: 002-04498 Rev. *A
Page 47 of 92
MB90340E Series
10. Interrupt Factors, Interrupt Vectors, Interrupt Control Register
Interrupt control
register
DMA
channel
number
EI2OS
Support
Interrupt vector
Number Address
Interrupt cause
Number
Address
Reset
N
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
INT9 instruction
N
0
Exception
N
CAN 0 RX
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
CAN 0 TX/NS
N
CAN 1 RX / Input Capture 6
CAN 1 TX/NS / Input Capture 7
CAN 2 RX / I2C0
Y1
Y1
N
CAN 2 TX/NS
N
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
PPG 0/1/4/5
Y1
Y1
Y1
Y1
N
1
2
3
PPG 2/3/6/7
N
PPG 8/9/C/D
N
PPG A/B/E/F
N
Time Base Timer
N
External Interrupt 0 to 3, 8 to 11
Watch Timer
Y1
N
4
External Interrupt 4 to 7, 12 to 15
A/D Converter
Y1
Y1
N
5
Free-run Timer 0 / Free-run Timer 1
Input Capture 4/5 / I2C1
Output Compare 0/1/4/5
Input Capture 0 to 3
Output Compare 2/3/6/7
UART 0 RX
6
Y1
Y1
Y1
Y1
Y2
Y1
Y2
Y1
7
8
9
10
11
12
13
UART 0 TX
UART 1 RX / UART 3 RX
UART 1 TX / UART 3 TX
(Continued)
Document Number: 002-04498 Rev. *A
Page 48 of 92
MB90340E Series
(Continued)
Interrupt control
register
DMA
channel
number
EI2OS
Support
Interrupt vector
Number Address
Interrupt cause
Number
Address
UART 2 RX / UART 4 RX
UART 2 TX / UART 4 TX
Flash Memory
Y2
14
#39
#40
#41
#42
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR14
ICR15
0000BEH
Y1
N
15
0000BFH
Delayed Interrupt
N
Y1
Y2
N
: Usable
: Usable, with EI2OS stop function
: Unusable
Note:
The peripheral resources sharing the ICR register have the same interrupt level.
When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
Document Number: 002-04498 Rev. *A
Page 49 of 92
MB90340E Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
VSS 0.3
VSS 0.3
VSS 6.0
VSS 6.0
V
2
AVCC
V
V
VCC AVCC
*
Power supply voltage*1
AVCC AVRH, AVCC AVRL, AVRH
AVRH,
AVRL
VSS 0.3
VSS 6.0
AVRL
Input voltage*1
Output voltage*1
VI
VSS 0.3
VSS 0.3
4.0
VSS 6.0
VSS 6.0
4.0
40
V
*3
VO
V
*3
Maximum Clamp Current
ICLAMP
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*5
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
Power consumption
|ICLAMP|
IOL
*5
40
55
15
*4, *6
*4, *7
*4
IOLAV
IOL
IOLAV
IOH
4
100
50
*4, *8
*4, *6
*4, *7
*4
15
4
100
50
450
IOHAV
IOH
IOHAV
PD
*4, *8
Operating temperature
TA
105
150
Storage temperature
TSTG
°C
*1: This parameter is based on VSS AVSS 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does
not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an
input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87,
P90 to P97, PA0, PA1
*5: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P57 (Evaluation device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
Use within recommended operating conditions.
Use with DC voltage (current)
The B signal should always be applied by using a limiting resistance placed between the B signal and the microcontroller.
The value of the limiting resistance should be set so that when the B signal is applied, the input current to
the microcontroller pin does not exceed the rated value, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
(Continued)
Document Number: 002-04498 Rev. *A
Page 50 of 92
MB90340E Series
(Continued)
Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
sNuoptpelythiastpifrothveideBd firnopmuttihseappipnlsie,dsoduthriantginpcoowmepr-leotne, othpeerpaotiwoenrmsuapyprleysiusltp. rovided from the pins and the
rCeasureltimngusstubpepltyakveonltangoet mtoalyeanvoet btheesuBffiicniepnutt tpoinooppeerant.e the power-on reset.
Sample recommended circuits:
Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
B input (0 V to 16 V)
N-ch
R
*6: The maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*7: The average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins.
*8: The average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04498 Rev. *A
Page 51 of 92
MB90340E Series
11.2 Recommended Operating Conditions
(VSS AVSS 0 V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
4.0
5.0
5.5
V
V
Under normal operation
Under normal operation, when not using the A/D
converter and not Flash
3.5
5.0
5.5
VCC
AVCC
,
Power supply voltage
programming.
4.5
3.0
5.0
5.5
5.5
V
V
When External bus is used.
Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of better AC
characteristics. Capacitor at the VCC should be
greater than this
Smoothing capacitor
CS
TA
0.1
1.0
F
capacitor.
Operating temperature
40
105
°C
C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Document Number: 002-04498 Rev. *A
Page 52 of 92
MB90340E Series
11.3 DC Characteristics
Symb
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS AVSS 0 V)
A
CP
Value
Typ
Parameter
Pin
Condition
Unit
Remarks
ol
Min
Max
Port inputs if CMOS
hysteresis input levels are selected
(except P12, P44, P45, P46, P47,
P50, P82, P85)
VIHS
0.8 VCC
VCC 0.3
V
Port inputs if
Automotive input levels are selected
VIHA
VIHT
0.8 VCC
2.0
VCC 0.3
VCC 0.3
V
V
Port inputs if TTL input levels are
selected
Input H
voltage
(At VCC
5 V 10)
P12, P50, P82, P85
inputs if CMOS input levels are
selected
VIHS
0.7 VCC
VCC 0.3
VCC 0.3
V
V
P44, P45, P46, P47
inputs if CMOS hysteresis
input levels are selected
VIHI
0.7 VCC
0.8 VCC
RST input pin
(CMOS hysteresis)
VIHR
VIHM
VCC 0.3
VCC 0.3
V
V
VCC 0.3
MD input pin
Port inputs if CMOS
hysteresis input levels are selected
(except P12, P44, P45, P46, P47,
P50, P82, P85)
VILS
VSS 0.3
0.2 VCC
V
Port inputs if
Automotive input levels are selected
VILA
VILT
VSS 0.3
VSS 0.3
0.5 VCC
0.8
V
V
Port inputs if TTL
input levels are selected
Input L
voltage
P12, P50, P82, P85
inputs if CMOS input levels are
selected
(At VCC
5 V 10)
VILS
VSS 0.3
VSS 0.3
0.3 VCC
0.3 VCC
V
V
P44, P45, P46, P47
inputs if CMOS hysteresis
input levels are selected
VILI
RST input pin
(CMOS hysteresis)
VILR
VILM
VOH
VSS 0.3
VSS 0.3
VCC 0.5
0.2 VCC
VSS 0.3
V
V
V
MD input pin
VCC 4.5 V,
Output H
voltage
Normal
outputs
IOH 4.0 mA
VCC 4.5 V,
Output H
voltage
I2C current
outputs
VOHI
VOL
VCC 0.5
0.4
0.4
V
V
V
IOH 3.0 mA
VCC 4.5 V,
IOL 4.0 mA
Output L
voltage
Normal
outputs
VCC 4.5 V,
IOL 3.0 mA
Output L
voltage
I2C current
outputs
VOLI
(Continued)
Document Number: 002-04498 Rev. *A
Page 53 of 92
MB90340E Series
(Continued)
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS AVSS 0 V)
A
CP
Value
Typ
Symbo
l
Parameter
Pin
Condition
Unit Remarks
Min
1
Max
1
Input leak current
IIL
VCC 5.5 V, VSS VI VCC
A
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-up
resistance
RUP
25
50
100
k
Except Flash
Pull-down
resistance
RDOWN MD2
25
50
55
100
70
k
memory
devices
VCC 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
VCC 5.0 V,
mA
Flash
ICC
Internal frequency : 24 MHz,
At writing Flash memory.
VCC 5.0 V,
70
75
25
0.3
85
90
35
0.8
mA
mA
mA
mA
memory
devices
Flash
memory
devices
Internal frequency : 24 MHz,
At erasing Flash memory.
VCC 5.0 V,
ICCS
Internal frequency : 24 MHz,
In Sleep mode.
VCC 5.0 V,
ICTS
Internal frequency : 2 MHz,
In Main Timer mode
VCC 5.0 V,
Power supply
current*
Internal frequency : 24 MHz,
VCC
ICTSPLL6
4
7
mA
A
A
A
In PLL Timer mode,
external frequency 4 MHz
VCC = 5.0 V
Internal frequency : 8 kHz,
In sub operation
TA = 25C
ICCL
70
20
10
140
50
35
VCC = 5.0 V
Internal frequency : 8 kHz,
In sub sleep
ICCLS
TA = 25C
VCC = 5.0 V
Internal frequency : 8 kHz,
In watch mode
TA = 25C
ICCT
VCC 5.0 V,
ICCH
7
5
25
15
A
In Stop mode,
TA 25C
Other than C,
AVCC, AVSS
AVRH, AVRL,
CC, VSS
,
Input capacitance
CIN
pF
V
* : The power supply current is measured with an external clock.
Document Number: 002-04498 Rev. *A
Page 54 of 92
MB90340E Series
11.4 AC Characteristics
11.4.1 Clock Timing
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS AVSS 0 V)
A
CP
Value
Typ
Parameter
Symbol
Pin
Unit
Remarks
Min
Max
3
4
16
MHz
When using an oscillation circuit
PLL multiplied by 1
16
12
8
MHz
MHz
MHz
MHz
When using an oscillation circuit
PLL multiplied by 2
4
4
4
When using an oscillation circuit
PLL multiplied by 3
fC
X0, X1
When using an oscillation circuit
Clock frequency
PLL multiplied by 4
6
When using an oscillation circuit
PLL multiplied by 6
4
MHz
MHz
When using an oscillation circuit
3
24
When using an external clock*
X0A, X1A
—
32.768
100
kHz
fCL
X0, X1
X0, X1
X0A, X1A
X0
62.5
41.67
10
333
333
ns
ns
When using an oscillation circuit
When using an external clock
tCYL
Clock cycle time
tCYLL
30.5
—
s
PWH, PWL
10
15.2
5
ns
s
ns
Input clock pulse width
Duty ratio is about 30 to 70.
PWHL, PWLL X0A
5
Input clock rise and fall time
tCR, tCF
fCP
fCPL
tCP
X0
1.5
When using external clock
When using main clock
When using sub clock
When using main clock
When using sub clock
24
MHz
kHz
ns
Internal operating clock
frequency (machine clock)
41.67
20
8.192
50
122.1
666
Internal operating clock
cycle time (machine clock)
tCPL
s
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within the range as
mentioned in “Relation between the external clock frequency and machine clock frequency”.
Document Number: 002-04498 Rev. *A
Page 55 of 92
MB90340E Series
Clock Timing
t
CYL
0.8 VCC
0.2 VCC
X0
P
WH
PWL
t
CF
tCR
t
CYLL
0.8 VCC
X0A
0.2 VCC
P
WHL
PWLL
t
CF
tCR
Document Number: 002-04498 Rev. *A
Page 56 of 92
MB90340E Series
Guaranteed PLL operation range
Guaranteed operation range
5.5
4.0
Guaranteed A/D Converter
operation range
3.5
Guaranteed PLL operation range
1.5
24
4
Machine clock fCP (MHz)
Guaranteed operation range of MB90340E series
Guaranteed oscillation frequency range
x 2
x 1
x 6 x 4
x 3
24
16
12
x 1/2
(PLL off)
8
4.0
1.5
12
16
3
8
4
24
External clock fC (MHz) *
* : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
Document Number: 002-04498 Rev. *A
Page 57 of 92
MB90340E Series
11.4.2 Reset Standby Input
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS AVSS 0.0 V)
A
CP
Value
Min
Parameter
Symbol
Pin
Unit
Remarks
Max
500
ns
Under normal operation
In Stop mode, Sub Clock mode,
Sub Sleep mode and Watch
mode
Oscillation time of oscillator*
Reset input time
tRSTL
RST
s
s
100 s
100
In Time Timer mode
* : The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred s and several ms, and for an external clock, the time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
Document Number: 002-04498 Rev. *A
Page 58 of 92
MB90340E Series
11.4.3 Power On Reset
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS AVSS 0.0 V)
A
CP
Value
Min Max
Parameter
Symbol
Pin
Condition
Unit
Remarks
Power on rise time
Power off time
tR
tOFF
VCC
VCC
0.05
1
30
ms
ms
Waiting time until power-on
tR
2.7 V
V
CC
0.2 V
0.2 V
0.2 V
tOFF
Note:
: If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup
smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below.
Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL
clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3 V
Holds RAM data
VSS
11.4.4 Clock Output Timing
(T 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, f 24 MHz)
A
CP
Value
Min Max
Parameter
Symbol
Pin
Condition
Unit
Remarks
62.5
ns
fCP 16 MHz
fCP 24 MHz
fCP 16 MHz
fCP 24 MHz
Cycle time
tCYC
CLK
41.67
20
ns
ns
ns
CLK CLK
tCHCL
CLK
13
Document Number: 002-04498 Rev. *A
Page 59 of 92
MB90340E Series
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
Document Number: 002-04498 Rev. *A
Page 60 of 92
MB90340E Series
11.4.5 Bus Timing (Read)
(T 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, f 24 MHz)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
ALE pulse width
tLHLL
tAVLL
ALE
tCP/2 10
ns
Valid address
ALE, A23 to A16, AD15 to
AD00
t
CP/2 20
ns
ns
ns
ns
ALE time
ALE
tLLAX
tAVRL
tAVDV
ALE, AD15 to AD00
tCP/2 15
tCP 15
Address valid time
Valid address
A23 to A16,
AD15 to AD00, RD
RD time
Valid address
A23 to A16,
AD15 to AD00
5 tCP/2 60
Valid data input
RD pulse width
tRLRH
tRLDV
tRHDX
tRHLH
tRHAX
RD
3 tCP/2 20
3 tCP/2 50
ns
ns
ns
ns
ns
RD Valid data input
RD Data hold time
RD ALE time
RD Address valid time
RD, AD15 to AD00
RD, AD15 to AD00
RD, ALE
0
tCP/2 15
tCP/2 10
RD, A23 to A16
Valid address
A23 to A16,
AD15 to AD00, CLK
tAVCH
tCP/2 16
ns
CLK time
RD CLK time
ALE RD time
tRLCH
tLLRL
RD, CLK
ALE, RD
tCP/2 15
tCP/2 15
ns
ns
tRLCH
tAVCH
2.4 V
2.4 V
CLK
ALE
RD
0.8 V
tLLAX
tAVLL
tRHLH
2.4 V
2.4 V
2.4 V
0.8 V
tLHLL
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
VIH
2.4 V
0.8 V
VIH
VIL
AD15 to AD00
Address
Read data
VIL
Document Number: 002-04498 Rev. *A
Page 61 of 92
MB90340E Series
11.4.6 Bus Timing (Write)
(T 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, f 24 MHz)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
tCP15
Max
A23 to A16, AD15
to AD00, WR
Valid address WR time
tAVWL
ns
WR pulse width
tWLWH
tDVWH
tWHDX
tWHAX
tWHLH
tWLCH
WR
3 tCP/2 20
3 tCP/2 20
15
ns
ns
ns
ns
ns
ns
Valid data output WR time
WR Data hold time
WR Address valid time
WR ALE time
AD15 to AD00, WR
AD15 to AD00, WR
A23 to A16, WR
WR, ALE
tCP/2 10
tCP/2 15
tCP/2 15
WR CLK time
WR, CLK
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
WR (WRL, WRH)
2.4 V
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
Document Number: 002-04498 Rev. *A
Page 62 of 92
MB90340E Series
11.4.7 Ready Input Timing
(T 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, f 24 MHz)
A
CP
Rated Value
Min Max
Test
Condition
Parameter
Symbol
Pin
Unit
Remarks
45
32
0
ns
fCP 16 MHz
fCP 24 MHz
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
ns
ns
Note:
: If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
Document Number: 002-04498 Rev. *A
Page 63 of 92
MB90340E Series
11.4.8 Hold Timing
(T 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, f 24 MHz)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Pin floating HAK time
HAK time Pin valid time
tXHAL
tHAHV
HAK
HAK
30
tCP
ns
tCP
2 tCP
ns
Note:
: There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Hi-Z
2.4 V
2.4 V
0.8 V
Each pin
0.8 V
Document Number: 002-04498 Rev. *A
Page 64 of 92
MB90340E Series
11.4.9 LIN-UART0/1/2/3
Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
tIVSHI
tSHIXI
SCK0 to SCK3
5 tCP
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK SOT delay time
Valid SIN SCK
50
50
ns
ns
ns
Internal shift clock
CmLode8o0uptpFutp1insTTaLre.
SCK0 to SCK3,
SIN0 to SIN3
t
CP + 80
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
0
Serial clock “L” pulse width
Serial clock “H” pulse width
tSHSL
tSLSH
SCK0 to SCK3
SCK0 to SCK3
3 tCP - tR
tCP + 10
ns
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK SOT delay time
Valid SIN SCK
tSLOVE
tIVSHE
tSHIXE
2 tCP + 60
ns
ns
ns
External shift clock
SCK0 to SCK3,
SIN0 to SIN3
30
CmLode8o0uptpFutp1insTTaLre.
SCK0, SCK1,
SIN0 to SIN3
SCK Valid SIN hold time
t
CP + 30
SCK fall time
SCK rise time
tF
SCK0 to SCK3
SCK0 to SCK3
10
10
ns
ns
tR
Note:
AC characteristic in CLK synchronized mode.
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
Internal Shift Clock Mode
t
SCYC
2.4 V
SCK0 to SCK3
SOT0 to SOT3
0.8 V
0.8 V
t
SLOVI
2.4 V
0.8 V
t
IVSHI
t
SHIXI
V
V
IH
IL
V
V
IH
IL
SIN0 to SIN3
Document Number: 002-04498 Rev. *A
Page 65 of 92
MB90340E Series
External Shift Clock Mode
t
SLSH
t
SHSL
V
IH
VIH
SCK0 to SCK3
V
IL
VIL
t
SLOVE
t
F
t
R
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
t
IVSHE
t
SHIXE
V
V
IH
IL
V
V
IH
IL
Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK SOT delay time
Valid SIN SCK
tSHOVI
50
50
ns
ns
ns
Internal shift clock
CmLode8o0uptpFutp1insTTaLre.
SCK0 to SCK3,
SIN0 to SIN3
tIVSLI
tSLIXI
tCP + 80
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
0
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0 to SCK3
SCK0 to SCK3
3 tCP - tR
tCP + 10
ns
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK SOT delay time
Valid SIN SCK
tSHOVE
tIVSLE
tSLIXE
2 tCP + 60
ns
ns
ns
External shift clock
SCK0 to SCK3,
SIN0 to SIN3
30
CmLode8o0uptpFutp1insTTaLre.
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
t
CP + 30
SCK fall time
SCK rise time
tF
SCK0 to SCK3
SCK0 to SCK3
10
10
ns
ns
tR
Note:
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Document Number: 002-04498 Rev. *A
Page 66 of 92
MB90340E Series
Internal Shift Clock Mode
t
SCYC
2.4 V
SCK0 to SCK3
0.8 V
t
SHOVI
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
t
IVSLI
t
SLIXI
V
V
IH
IL
V
V
IH
IL
External Shift Clock Mode
t
SHSL
t
SLSH
V
IH
V
IH
SCK0 to SCK3
V
IL
V
IL
t
SHOVE
t
R
t
F
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
t
IVSLE
t
SLIXE
V
IH
IL
V
V
IH
IL
V
Document Number: 002-04498 Rev. *A
Page 67 of 92
MB90340E Series
Bit setting: ESCR:SCES 0, ECCR:SCDE 1
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK SOT delay time
tSHOVI
50
50
ns
ns
ns
ns
Internal clock operation output
pins are
CL 80 pF 1 TTL.
SCK0 to SCK3,
SIN0 to SIN3
Valid SIN SCK
tIVSLI
tSLIXI
tSOVLI
tCP 80
0
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
SOT SCK delay time
SCK0 to SCK3,
SOT0 to SOT3
3 tCP 70
Note:
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
t
SCYC
2.4 V
SCK0 to SCK3
SOT0 to SOT3
0.8 V
0.8 V
t
SHOVI
t
SOVLI
2.4 V
0.8 V
2.4 V
0.8 V
t
IVSLI
tSLIXI
V
V
IH
IL
V
V
IH
IL
SIN0 to SIN3
Document Number: 002-04498 Rev. *A
Page 68 of 92
MB90340E Series
Bit setting: ESCR:SCES 1, ECCR:SCDE 1
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0 to SCK3
5 tCP
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK SOT delay time
50
50
ns
ns
ns
ns
Internal clock operation
SCK0 to SCK3,
SIN0 to SIN3
Valid SIN SCK
tIVSHI
tSHIXI
tSOVHI
tCP 80
0
CouLtpu8t 0pipnsFare1 TTL.
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
SOT SCK delay time
SCK0 to SCK3,
SOT0 to SOT3
3 tCP 70
Note:
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
tSCYC
2.4 V
2.4 V
SCK0 to SCK3
0.8 V
tSLOVI
tSOVHI
2.4 V
0.8 V
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
Document Number: 002-04498 Rev. *A
Page 69 of 92
MB90340E Series
11.4.10 Trigger Input Timing
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS 0.0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
INT0 to INT15,
INT0R to INT15R,
ADTG
tTRGH
tTRGL
Input pulse width
5 tCP
ns
VIH
VIH
INT0 to INT15,
VIL
VIL
INT0R to INT15R,
ADTG
tTRGH
tTRGL
Document Number: 002-04498 Rev. *A
Page 70 of 92
MB90340E Series
11.4.11 Timer Related Resource Input Timing
(T 40°C to 105°C, VCC 5.0 V 10, f 24 MHz, VSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
tTIWL
TIN0 to TIN3,
IN0 to IN7
Input pulse width
4 tCP
ns
VIH
VIH
VIL
VIL
TIN0 to TIN3,
IN0 to IN7
tTIWH
tTIWL
11.4.12 Timer Related Resource Output Timing
(T = –40C to +105C, VCC 5.0 V 10, f 24 MHz, V = 0.0 V)
A
CP
SS
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
TOT0 to TOT3,
PPG0 to PPGF
CLK TOUT change time
tTO
30
ns
2.4 V
CLK
2.4 V
0.8 V
TOT0 to TOT3,
PPG0 to PPGF
tTO
Document Number: 002-04498 Rev. *A
Page 71 of 92
MB90340E Series
11.4.13 I2C Timing
(T –40C to +105C, VCC 5.0 V 10, VSS 0.0 V)
A
Standard-mode
Min Max
Fast-mode*1
Min Max
Parameter
Symbol
Condition
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA SCL
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
1.3
0.6
s
s
Set-up time (repeated) START condition
SCL SDA
tSUSTA
tHDDAT
tSUDAT
tSUSTO
4.7
0
0.6
0
s
s
ns
R 1.7 k,
C 50 pF*2
Data hold time
SCL SDA
3.45*3
0.9*4
Data set-up time
SDA SCL
250
100
Set-up time for STOP condition
SCL SDA
4.0
4.7
0.6
1.3
s
s
Bus free time between a STOP and START condition tBUS
*1:For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2:R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.
*3:The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.
*4:A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be
met.
V
IH
IL
V
IH
V
IH
VIH
SDA
SCL
V
V
IL
VIL
VIL
tBUS
t
SUDAT
t
HDSTA
IH
t
LOW
V
IH
V
IH
V
IH
V
IH
V
VIH
VIL
VIL
VIL
tHIGH
t
HDSTA
t
HDDAT
t
SUSTA
tSUSTO
Document Number: 002-04498 Rev. *A
Page 72 of 92
MB90340E Series
11.5 A/D Converter
(TA
40°C to 105°C, 3.0 V AVRH AVRL, VCC AVCC 5.0 V 10, f 24 MHz, VSS AVSS 0 V)
CP
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
Resolution
10
bit
Total error
3.0
2.5
LSB
LSB
Nonlinearity error
Differential
nonlinearity error
1.9
LSB
V
Zero reading
voltage
AVRL
1.5 LSB
AVRL
0.5 LSB
AVRL
2.5 LSB
VOT
AN0 to AN23
Full scale reading
voltage
AVRH
3.5 LSB
AVRH
1.5 LSB
AVRH
0.5 LSB
VFST
AN0 to AN23
V
1.0
2.0
0.5
1.2
4.5 V AVCC 5.5 V
4.0 V AVCC < 4.5 V
4.5 V AVCC 5.5 V
4.0 V AVCC < 4.5 V
Compare time
Sampling time
16500
s
s
Analog port input
current
IAIN
AN0 to AN23
AN0 to AN23
0.3
0.3
A
Analog input
voltage range
VAIN
AVRL
AVRH
V
IA
AVRH
AVRL
AVCC
AVCC
AVRH
AVRH
AVRL 2.7
3.5
600
AVCC
V
Reference
voltage range
0
AVRH 2.7
7.5
V
mA
A
A
A
Power supply
current
IAH
IR
5
*
*
900
5
Reference
voltage current
IRH
Offset between
input channels
AN0 to AN23
4
LSB
*: If the A/D convertor is not operating, a current when CPU is stopped is applicable (VCC AVCC AVRH 5.0 V) .
Note: : The accuracy gets worse as |AVRH AVRL| becomes smaller.
Document Number: 002-04498 Rev. *A
Page 73 of 92
MB90340E Series
11.6 Definition of A/D Converter Terms
Resolution
Non linearity
error
: Analog variation that is recognized by the A/D converter.
:
The deviation between the actual conversion characteristics and a line that joins the
zero-transition line ( “00 0000 0000” “00 0000 0001” ) to the full-scale transition line
( “11 1111 1110” “11 1111 1111” ) .
Differential
linearity error
Total error
:
:
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Difference between the actual value and the ideal value. The total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
V
NT {1 LSB (N 1) 0.5 LSB}
[LSB]
Total error of digital output “N”
1 LSB (Ideal value)
1 LSB
AVRH AVRL
[V]
1024
N : Value of the digital output from the A/D converter
V
V
V
(Ideal value) AVRL 0.5 LSB [V]
(Ideal value) AVRH 1.5 LSB [V]
: A voltage at which the digital output transitions from (N 1) to N .
OT
FST
NT
H
H
(Continued)
Document Number: 002-04498 Rev. *A
Page 74 of 92
MB90340E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
3FEH
3FDH
Actual conversion
characteristics
(N + 1)H
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
VFST (actual
measurement
value)
NH
VNT (actual
measurement value)
004H
003H
002H
001H
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
(N − 1)H
(N − 2)H
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
V
NT {1 LSB (N 1) V
}
OT
[LSB]
Non linearity error of digital output N
1 LSB
V ( ) V
N+1 T
1 LSB
NT
Differential linearity error of digital output N
1 LSB
1 LSB [LSB]
V
FST V
OT
[V]
1022
N
: Value of the digital output from the A/D converter
: Voltage at which digital output transits from “000 ” to “001 .”
V
V
OT
H
H
: Voltage at which digital output transits from “3FE ” to “3FF .”
FST
H
H
11.7 Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 k or lower (4.0 V AVCC 5.5 V,
sampling period 0.5 s)
If an external capacitor is used, in consideration of the capacitive voltage dividing effect between the external capacitor and the
internal on-chip capacitor, it is recommended that the capacitance of the external capacitor be several thousand times greater than
the capacitance of the internal capacitor.
Document Number: 002-04498 Rev. *A
Page 75 of 92
MB90340E Series
If the output impedance of the external circuit is too high, a sampling period for an analog voltage may be insufficient.
A Analog input circuit model
R
Analog input
Comparator
C
4.5 V AVCC 5.5 V : R=: 2.52 k, C=: 10.7 pF
4.0 V AV < 4.5 V : R=: 13.6 k, C=: 10.7 pF
CC
Note:
: Use the values in the figure only as a guideline.
Document Number: 002-04498 Rev. *A
Page 76 of 92
MB90340E Series
11.8 Flash Memory Program/Erase Characteristics
Value
Typ
Parameter
Conditions
Unit
Remarks
Min
Max
Excludes programming prior to
erasure
Sector erase time
1
15
s
s
TA 25°C
VCC 5.0 V
Excludes programming prior to
erasure
Chip erase time
9
Word (16-bit width)
programming time
Except for the over head time of
the system
16
3600
s
Program/Erase cycle
10000
cycle
Average
Flash Data Retention Time
20
year
*
TA 85°C
* : This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to translate high
temperature measurements into normalized value at 85°C) .
Document Number: 002-04498 Rev. *A
Page 77 of 92
MB90340E Series
12. Example Characteristics
MB90F346E, MB90F346ES, MB90F346CE, MB90F346CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 8 kHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
CC (V)
5.5
6.5
V
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation, f Internal operation frequencyTA 25°C, external clock operation, f Internal operation frequency
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICTS VCC
ICCT VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
400
350
300
250
200
150
100
50
20
18
16
14
12
10
8
6
4
2
0
f = 2 MHz
f = 8 kHz
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
V
5.5
6.5
CC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, stopped
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
6.5
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
V
CC (V)
Document Number: 002-04498 Rev. *A
Page 78 of 92
MB90340E Series
MB90F347E, MB90F347ES, MB90F347CE, MB90F347CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequencyTA 25°C, external clock operation f Internal operation frequency
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 8 kHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
CC (V)
5.5
6.5
V
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICTS VCC
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
400
350
300
250
200
150
100
50
20
18
16
14
12
10
8
6
4
2
0
f = 2 MHz
f = 8 kHz
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
V
5.5
6.5
CC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, stopped
10
9
10
9
8
8
7
7
6
6
5
5
4
3
4
3
f = 24 MHz
2
1
0
2
1
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
5.5
6.5
V
CC (V)
Document Number: 002-04498 Rev. *A
Page 79 of 92
MB90340E Series
MB90F349E, MB90F349ES, MB90F349CE, MB90F349CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
f = 24 MHz
f = 8 kHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICTS VCC
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
400
350
300
250
200
150
100
50
20
18
16
14
12
10
8
6
4
2
f = 2 MHz
f = 8 kHz
0
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, stopped
10
9
10
9
8
8
7
7
6
6
5
5
4
3
4
3
f = 24 MHz
2
1
0
2
1
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
Document Number: 002-04498 Rev. *A
Page 80 of 92
MB90340E Series
MB90F342E, MB90F342ES, MB90F342CE, MB90F342CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
f = 24 MHz
f = 8 kHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
6.5
ICTS VCC
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
400
350
300
250
200
150
100
50
20
18
16
14
12
10
8
6
4
2
f = 2 MHz
f = 8 kHz
0
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, stopped
10
9
10
9
8
8
7
7
6
6
5
5
4
3
4
3
f = 24 MHz
2
1
0
2
1
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
Document Number: 002-04498 Rev. *A
Page 81 of 92
MB90340E Series
MB90F345E, MB90F345ES, MB90F345CE, MB90F345CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, external clock operation f Internal operation frequency
100
90
80
70
60
f = 24 MHz
f = 8 kHz
50
70
f = 20 MHz
60
50
40
30
20
10
0
f = 16 MHz
40
30
20
10
0
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
V
5.5
6.5
2.5
3.5
4.5
5.5
6.5
CC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency
35
TA 25°C, external clock operation f Internal operation frequency
50
45
40
35
30
25
20
15
10
5
30
f = 24 MHz
25
f = 20 MHz
20
15
10
5
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
CC (V)
5.5
6.5
2.5
3.5
4.5
5.5
6.5
V
ICTS VCC
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, external clock operation f Internal operation frequency
400
350
300
20
18
16
14
12
10
8
6
4
2
0
f = 2 MHz
250
200
150
100
50
f = 8 kHz
0
2.5
3.5
4.5
CC (V)
5.5
6.5
2.5
3.5
4.5
5.5
6.5
V
VCC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, stopped
10
9
10
9
8
8
7
7
6
6
5
5
4
3
4
3
f = 24 MHz
2
1
0
2
1
0
2.5
3.5
4.5
CC (V)
5.5
6.5
2.5
3.5
4.5
5.5
6.5
V
VCC (V)
Document Number: 002-04498 Rev. *A
Page 82 of 92
MB90340E Series
MB90346E, MB90346ES, MB90346CE, MB90346CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, external clock operation f Internal operation frequency
70
100
90
80
70
60
60
f = 24 MHz
50
f = 20 MHz
f = 16 MHz
40
30
20
10
0
f = 8 kHz
50
f = 12 MHz
f = 10 MHz
f = 8 MHz
40
30
20
10
0
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency
35
TA 25°C, external clock operation f Internal operation frequency
50
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
CC (V)
5.5
6.5
2.5
3.5
4.5
CC (V)
5.5
6.5
V
V
ICTS VCC
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, external clock operation f Internal operation frequency
20
18
16
14
12
10
8
6
4
2
0
400
350
300
f = 2 MHz
250
200
150
100
50
f = 8 kHz
0
2.5
3.5
4.5
CC (V)
5.5
6.5
3.5
2.5
4.5
5.5
6.5
V
VCC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, stopped
10
9
10
9
8
8
7
7
6
6
5
5
4
3
4
3
f = 24 MHz
2
1
0
2
1
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
Document Number: 002-04498 Rev. *A
Page 83 of 92
MB90340E Series
MB90347E, MB90347ES, MB90347CE, MB90347CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, external clock operation f Internal operation frequency
70
100
90
80
70
60
60
f = 24 MHz
50
f = 20 MHz
f = 16 MHz
40
30
20
10
0
f = 8 kHz
50
f = 12 MHz
f = 10 MHz
f = 8 MHz
40
30
20
10
0
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency
35
TA 25°C, external clock operation f Internal operation frequency
50
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
CC (V)
5.5
6.5
2.5
3.5
4.5
CC (V)
5.5
6.5
V
V
ICTS VCC
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, external clock operation f Internal operation frequency
20
18
16
14
12
10
8
6
4
2
0
400
350
300
f = 2 MHz
250
200
150
100
50
f = 8 kHz
0
2.5
3.5
4.5
CC (V)
5.5
6.5
3.5
2.5
4.5
5.5
6.5
V
VCC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation f Internal operation frequency
TA 25°C, stopped
10
9
10
9
8
8
7
7
6
6
5
5
4
3
4
3
f = 24 MHz
2
1
0
2
1
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
Document Number: 002-04498 Rev. *A
Page 84 of 92
MB90340E Series
I/O characteristics
(VCCVOH) IOH
VOL IOL
TA 25°C, VCC 4.5 V
TA 25°C, VCC 4.5 V
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
I
OL (mA)
IOH (mA)
Automotive VIN VCC
TA 25°C
CMOS VIN VCC
Other than UART-SIN pin and I2C pin
TA 25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
VIHA
VILA
VIHS
VILS
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
VCC (V)
TTL VIN VCC
CMOS VIN VCC
UART-SIN pin, I2C pin
TA 25°C
TA 25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.3
2.0
1.8
1.5
1.3
1.0
0.8
0.5
0.3
0.0
V
V
IHS
ILS
VIHT
VILT
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
CC (V)
VCC (V)
V
Document Number: 002-04498 Rev. *A
Page 85 of 92
MB90340E Series
13. Ordering Information
Part number
MB90F342EPF
Package
Remarks
MB90F342ESPF
MB90F342CEPF
MB90F342CESPF
MB90F342EPMC
MB90F342ESPMC
MB90F342CEPMC
MB90F342CESPMC
MB90F345EPF
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
MB90F345ESPF
MB90F345CEPF
MB90F345CESPF
MB90F345EPMC
MB90F345ESPMC
MB90F345CEPMC
MB90F345CESPMC
MB90F346EPF
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
MB90F346ESPF
MB90F346CEPF
MB90F346CESPF
MB90F346EPMC
MB90F346ESPMC
MB90F346CEPMC
MB90F346CESPMC
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
(Continued)
Document Number: 002-04498 Rev. *A
Page 86 of 92
MB90340E Series
Part number
Package
Remarks
MB90F347EPF
MB90F347ESPF
MB90F347CEPF
MB90F347CESPF
MB90F347EPMC
MB90F347ESPMC
MB90F347CEPMC
MB90F347CESPMC
MB90F349EPF
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
MB90F349ESPF
MB90F349CEPF
MB90F349CESPF
MB90F349EPMC
MB90F349ESPMC
MB90F349CEPMC
MB90F349CESPMC
MB90341EPF
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
MB90341ESPF
100-pin plastic QFP
(FPT-100P-M06)
MB90341CEPF
MB90341CESPF
MB90341EPMC
MB90341ESPMC
MB90341CEPMC
MB90341CESPMC
MB90342EPF
100-pin plastic LQFP
(FPT-100P-M20)
MB90342ESPF
100-pin plastic QFP
(FPT-100P-M06)
MB90342CEPF
MB90342CESPF
MB90342EPMC
MB90342ESPMC
MB90342CEPMC
MB90342CESPMC
100-pin plastic LQFP
(FPT-100P-M20)
(Continued)
Document Number: 002-04498 Rev. *A
Page 87 of 92
MB90340E Series
(Continued)
Part number
Package
Remarks
MB90346EPF
MB90346ESPF
MB90346CEPF
MB90346CESPF
MB90346EPMC
MB90346ESPMC
MB90346CEPMC
MB90346CESPMC
MB90347EPF
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
MB90347ESPF
MB90347CEPF
MB90347CESPF
MB90347EPMC
MB90347ESPMC
MB90347CEPMC
MB90347CESPMC
MB90348EPF
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
MB90348ESPF
MB90348CEPF
MB90348CESPF
MB90348EPMC
MB90348ESPMC
MB90348CEPMC
MB90348CESPMC
MB90349EPF
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
MB90349ESPF
MB90349CEPF
MB90349CESPF
MB90349EPMC
MB90349ESPMC
MB90349CEPMC
MB90349CESPMC
MB90V340E-101CR
MB90V340E-102CR
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
299-pin ceramic PGA
(PGA-299C-A01)
For evaluation
Document Number: 002-04498 Rev. *A
Page 88 of 92
MB90340E Series
14. Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*
14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
–
0.10 .059 +.008
–.004
INDEX
(Mounting height)
0.10 0.10
(.004 .004)
(Stand off)
100
26
0°~8
°
"A"
0.50 0.20
(.020 .008
0.25(.010)
)
1
25
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
(.008 .002)
0.145 0.055
(.006 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5
Document Number: 002-04498 Rev. *A
Page 89 of 92
MB90340E Series
(Continued)
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90 0.40(.941 .016)
*
20.00 0.20(.787 .008)
80
51
81
50
0.10(.004)
17.90 0.40
(.705 .016)
*14.00 0.20
(.551 .008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8
°
1
30
0.65(.026)
0.32 0.05
(.013 .002)
0.17 0.06
(.007 .002)
M
0.13(.005)
0.25 0.20
(.010 .008)
(Stand off)
0.80 0.20
(.031 .008)
"A"
0.88 0.15
(.035 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7
Document Number: 002-04498 Rev. *A
Page 90 of 92
MB90340E Series
15. Major Changes
Spansiion Publication Number: DS07-13747-4E
Page
Section
Change Results
Deleted the part numbers;
MB90F343E(S), MB90F343CE(S)
Electrical
Characteristics
Added “*6” in remark for “L" level maximum output current and “H” level maximum
output current.
Absolute Maximum Ratings
Added “*7” in remark for “L" level average output current and “H” level average
output current.
51
52
Added “*8” in remark for “L"level average overall output current and “H” level
average overall output current.
Added as follows.
“*6:The maximum output current is defined as the peak value of the current of any
one of the corresponding pins.”
“*7:The average output current is defined as the value of the average current
flowing over 100 ms at any one of the corresponding pins.”
“*8:The average total output current is defined as the value of the average current
flowing over 100 ms at all of the corresponding pins.”
NOTE: Please see “Document History” about later revised information.
Document History
Document Title: MB90340E Series F2MC-16LX 16-bit Microcontroller Datasheet
Document Number: 002-04498
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
AKIH
08/23/2010 Migrated to Cypress and assigned document number 002-04498.
No change to document contents or format.
*A
5221535
AKIH
05/04/2016 Updated to Cypress template
Document Number: 002-04498 Rev. *A
Page 91 of 92
MB90340E Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 002-04498 Rev. *A
Revised May 4,2016
Page 92 of 92
相关型号：
MB90349PFV
Microcontroller, 16-Bit, MROM, F2MC-16LX CPU, 24MHz, CMOS, PQFP100, PLASTIC, LQFP-100
FUJITSU
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