MB90548GPF [CYPRESS]
CMOS F2MC-16LX MB90540G/545GSeries 16-bit Proprietary Microcontroller;型号: | MB90548GPF |
厂家: | CYPRESS |
描述: | CMOS F2MC-16LX MB90540G/545GSeries 16-bit Proprietary Microcontroller 时钟 微控制器 外围集成电路 |
文件: | 总70页 (文件大小:5564K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MB90F543G(S)/546G(S)/548G(S)/549G(S)/549G(S)/
V540GM/B90543G(S)/547G(S)/548G(S)/F548GL(S)
CMOS F2MC-16LX MB90540G/545G
Series 16-bit Proprietary Microcontroller
The MB90540G/545G series with FULL-CAN and Flash ROM is specially designed for automotive and industrial applications. Its
main features are on-board CAN Interfaces (MB90540G series: 2 channels, MB90545G series: 1 channel) , which conform to CAN
V2.0A and V2.0B specifications, supporting very flexible message buffer scheme and so offering more functions than a normal full
CAN approach. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MCfamily with additional instruction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipula-
tion instructions.The micro controller has a 32-bit accumulator for processing long word data.The MB90540G/545G series has
peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture
(ICU) , output compare (OCU) ) .
Erase can be performed on each block
Block protection with external programming voltage
Features
Clock
Low-power consumption (stand-by) mode
Embedded PLL clock multiplication circuit
Sleep mode (mode in which CPU operating clock is
Operating clock (PLL clock) can be selected from : divided-
stopped)
by-2 of oscillation or one to four times the oscillation
Stop mode (mode in which oscillation is stopped)
Minimum instruction execution time : 62.5 ns (operation at
CPU intermittent operation mode
oscillation of 4 MHz, PLL four times multiplied :
Watch mode
machine clock 16 MHz and at operating VCC = 5.0 V)
Hardware stand-by mode
Subsystem Clock : 32 kHz
Process
Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
0.5 m CMOS technology
I/O port
General-purpose I/O ports : 81 ports
Timer
Enhanced signed multiplication/division instruction and
RETI instruction functions
Enhanced precision calculation realized by the 32-bit
accumulator
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit 4 channels
16-bit reload timer : 2 channels
Instruction set designed for high level language (C
language) and multi-task operations
Adoption of system stack pointer
16-bit I/O timer
16-bit free-run timer : 1 channel
Input capture : 8 channels
Output compare : 4 channels
Enhanced pointer indirect instructions
Barrel shift instructions
Program patch function (for two address pointers)
Enhanced execution speed : 4-byte Instruction queue
Enhanced interrupt function : 8 levels, 34 factors
Extended I/O serial interface : 1 channel
UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop
bit) transmission can be selectively used.
Automatic data transmission function independent of CPU
operation
UART 1 (SCI)
Extended intelligent I/O service function (EI2OS)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial (extended
I/O serial) can be used.
Embedded ROM size and types
MASK ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes
Flash ROM : 128 Kbytes/256 Kbytes
Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes
(evaluation chip)
External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service
(EI2OS) and generating an external interrupt which is
triggered by an external input.
Flash ROM
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed
boot sector in Flash Memory
Delayed interrupt generation module
Generates an interrupt request for switching tasks.
8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Cypress Semiconductor Corporation
Document Number: 002- 07696 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised 2016 November 30
MB90540G/545G Series
Starting by an external trigger input.
Conversion time : 26.3 s
Flexible message buffering (mailbox and FIFO buffering can
be mixed)
FULL-CAN interfaces
External bus interface : Maximum address space 16 Mbytes
Package: QFP-100, LQFP-100
MB90540G series : 2 channels
MB90545G series : 1 channel
Conforming to Version 2.0 Part A and Part B
Document Number: 002- 07696 Rev. *A
Page 2 of 70
MB90540G/545G Series
Contents
Features..............................................................................1
Product Lineup ..................................................................4
Pin Assignment .................................................................7
Pin Description ..................................................................9
I/O Circuit Type................................................................14
Handling Devices.............................................................17
Block Diagram .................................................................21
Memory Map.....................................................................22
I/O Map..............................................................................23
CAN Controller.................................................................29
Interrupt Map....................................................................35
Electrical Characteristics................................................37
Example Characteristics.................................................61
Ordering Information.......................................................66
Package Dimensions.......................................................67
Major Changes.................................................................69
Document History............................................................69
Sales, Solutions, and Legal Information .......................70
Document Number: 002- 07696 Rev. *A
Page 3 of 70
MB90540G/545G Series
1. Product Lineup
MB90543G (S)
MB90547G (S)
MB90548G (S)
MB90549G (S)
MB90F543G (S) /F548G (S)
MB90F549G (S) /F546G (S)
MB90F548GL(S)
Features
MB90V540G
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier (1, 2, 3, 4, 1/2 when PLL stop)
Minimum instruction exection time : 62.5 ns (machine clock 16MHz, 4MHz osc. four times multiplied by PLL)
System clock
Flash memory
MASK ROM :
MB90547G(S): 64 Kbytes
MB90F543G(S)/F548G(S) / F548GL(S)
: 128 Kbytes
ROM
RAM
MB90543G(S)/548G(S): 128
Kbytes
External
8 Kbytes
MB90F549G(S)/F546G(S) :
256 Kbytes
MB90549G(S): 256 Kbytes
MB90F548G(S)/F548GL(S):
4 Kbytes
MB90547G(S): 2 Kbytes
MB90548G(S): 4 Kbytes
MB90F543G (S) /F549G(S) :
6 Kbytes
MB90543G(S)/549G(S):
6 Kbytes
MB90F546G(S) : 8 Kbytes
MB90F543G/F548G/F549G/F546G/
F548GL :
MB90543G/547G/548G/549G :
Two clocks system
Two clocks system
Clocks
MB90543GS/547GS/548GS/
549GS :
Two clocks system*1
MB90F543GS/F548GS/F549GS/
F546GS/F548GLS :
One clock system
One clock system
*3
Operating voltage range
Temperature range
Package
40 C to 105 C
QFP100, LQFP100
PGA-256
None
Emulator-specify
power supply*2
Full duplex double buffer
Support asynchronous/synchronous (with start/stop bit) transfer
UART0
Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock 16 MHz
Full duplex double buffer
UART1
(SCI)
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous)
62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and nagative-edge clock synchronization
Serial I/O
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock 16 MHz
10-bit or 8-bit resolution
A/D Converter
8 input channels
Conversion time : 26.3 s (per one channel)
(Continued)
Document Number: 002- 07696 Rev. *A
Page 4 of 70
MB90540G/545G Series
MB90543G (S)
MB90547G (S)
MB90548G (S)
MB90549G (S)
MB90F543G (S) /F548G (S)
MB90F549G (S) /F546G (S)
MB90F548GL(S)
Features
MB90V540G
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys System clock frequency)
Supports External Event Count function
16-bit Reload Timer
(2 channels)
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys System clock freq.)
Signals an interrupt when a match with 16-bit Free-run Timer
Four 16-bit compare registers
16-bit Free-run Timer
16-bit Output Compare
(4 channels)
A pair of compare registers can be used to generate an output signal
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
16-bit Input Capture
(8 channels)
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
8/16-bit
Eight 8-bit reload registers for H pulse width
Programmable
Pulse Generator
(4 channels)
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit
reload counter
4 output pins
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys System clock frequency, fosc Oscillation clock frequency)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
CAN Interface
MB90540G series
: 2 channels
Automatic transmission responding to Remote Frame
Prioritized 16 massage buffers for data and ID’s supports multipe massages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
MB90545G series
: 1 channel
32 kHz Sub-clock
Sub-clock for low power operation
External Interrupt
(8 channels)
Can be programmed edge sensitive or level sensitive
External bus
interface
External access using the selectable 8-bit or 16-bit bus is enabled
(external bus mode.)
Virtually all external pins can be used as general purpose I/O
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
Sub-clock for 32 kHz Sub clock low power operation
Supports automatic programming, Embeded Algorithm
Write/Erase/Erase-Suspend/Erase-Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
I/O Ports
Flash Memory
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
*1 : If the one clock system is used, equip X0A and X1A with clocks from the tool side.
Document Number: 002- 07696 Rev. *A
Page 5 of 70
MB90540G/545G Series
*2 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.Please refer to the MB2145-507 hardware manual (2.7
Emulator-specific Power Pin) about details.
*3 : Operating Voltage Range
Products
Operation guarantee range
MB90F543G(S)/F546G(S)/F548G(S)/
MB90549G(S)/F549G(S)/V540/V540G
4.5 V to 5.5 V
3.5 V to 5.5 V
MB90F548GL(S)/543G(S)/547G(S)/548G(S)
Document Number: 002- 07696 Rev. *A
Page 6 of 70
MB90540G/545G Series
2. Pin Assignment
(TOP VIEW)
P20/A16
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
X0A
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
2
X1A
3
PA0
4
RST
5
P97/RX1
P96/TX1
P95/RX0
P94/TX0
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
HST
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
VCC
P45/SOT1
P46/SOT2
P47/SCK2
C
P50/SIN2
P51/INT4
P52/INT5
MD2
(FPT-100P-M06)
Document Number: 002- 07696 Rev. *A
Page 7 of 70
MB90540G/545G Series
(TOP VIEW)
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
1
2
3
4
5
75
RST
74 P97/RX1
73
72
71
70
P96/TX1
P95/RX0
P94/TX0
P93/INT3
6
7
8
9
69 P92/INT2
P30/ALE
P31/RD
68
67
P91/INT1
P90/INT0
VSS
P32/WRL/WR
10
66 P87/TOT1
65
P33/WRH 11
P34/HRQ 12
P86/TIN1
64 P85/OUT1
P35/HAK
P36/RDY
P37/CLK
P40/SOT0 16
P41/SCK0
13
14
15
63
62
61
60
59
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
17
P42/SIN0 18
P43/SIN1 19
58 P77/OUT3/IN7
57
P76/OUT2/IN6
P44/SCK1
VCC
P45/SOT1
20
21
22
56 P75/IN5
55 P74/IN4
54 P73/IN3
53 P72/IN2
52 P71/IN1
P46/SOT2 23
P47/SCK2 24
25
51
C
P70/IN0
(FPT-100P-M20)
Document Number: 002- 07696 Rev. *A
Page 8 of 70
MB90540G/545G Series
3. Pin Description
Pin No.
Pin name
Circuit type
Function
LQFP*2
QFP*1
80
82
83
X0
X1
A
High speed crystal oscillator input pins
81
78
(Oscillation)
Low speed crystal oscillator input pins. For the one clock system parts,
perfom external pull-down processing.
80
79
X0A
X1A
A
(Oscillation)
Low speed crystal oscillator input pins. For the one clock system parts, leave
it open.
77
75
50
77
52
RST
HST
B
External reset request input pin
Hardware standby input pin
C
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
P00 to P07
83 to 90
91 to 98
85 to 92
I
I/O pins for 8 lower bits of the external address/data bus. This function is
enabled when the external bus is enabled.
AD00 to AD07
P10 to P17
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
93 to 100
I
I
I/O pins for 8 higher bits of the external address/data bus. This function is
enabled when the external bus is enabled.
AD08 to AD15
General I/O port with programmable pullup. In external bus mode, this
function is valid when the corresponding bits in the external address output
control resister (HACR) are set to “1”.
P20 to P27
A16 to A23
99 to 6
1 to 8
8-bit I/O pins for A16 to A23 at the external address/data bus. In external bus
mode, this function is valid when the corresponding bits in the external
address output control resister (HACR) are set to “0”.
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
P30
ALE
P31
RD
7
8
9
I
I
Address latch enable output pin. This function is enabled when the external
bus is enabled.
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
10
Read strobe output pin for the data bus. This function is enabled when the
external bus is enabled.
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the WR/WRL pin output is disabled.
P32
WRL
Write strobe output pin for the data bus. This function is enabled when both
the external bus and the WR/WRL pin output are enabled. WRL is write-
strobe output pin for the lower 8 bits of the data bus in 16-bit access. WR is
write-strobe output pin for the 8 bits of the data bus in 8-bit access.
10
12
I
WR
(Continued)
Document Number: 002- 07696 Rev. *A
Page 9 of 70
MB90540G/545G Series
Pin No.
LQFP*2 QFP*1
Pin name
Circuit type
Function
General I/O port with programmable pullup. This function is enabled in the
single-chip mode, external bus 8-bit mode or when WRH pin output is disabled.
P33
11
13
I
Write strobe output pin for the 8 higher bits of the data bus. This function is
enabled when the external bus is enabled, when the external bus 16-bit mode
is selected, and when the WRH output pin is enabled.
WRH
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the hold function is disabled.
P34
12
13
14
15
16
17
14
15
16
17
18
19
I
I
I
Hold request input pin. This function is enabled when both the external bus
and the hold functions are enabled.
HRQ
P35
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the hold function is disabled.
Hold acknowledge output pin. This function is enabled when both the external
bus and the hold functions are enabled.
HAK
P36
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the external ready function is disabled.
Ready input pin. This function is enabled when both the external bus and the
external ready functions are enabled.
RDY
P37
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the CLK output is disabled.
H
G
G
CLK output pin. This function is enabled when both the external bus and CLK
outputs are enabled.
CLK
P40
General I/O port. This function is enabled when UART0 disables the serial
data output.
Serial data output pin for UART0. This function is enabled when UART0
enables the serial data output.
SOT0
P41
General I/O port. This function is enabled when UART0 disables serial clock
output.
Serial clock I/O pin for UART0. This function is enabled when UART0 enables
the serial clock output.
SCK0
P42
General I/O port. This function is always enabled.
18
19
20
21
G
G
Serial data input pin for UART0. Set the corresponding Port
Direction Register to input if this function is used.
SIN0
P43
General I/O port. This function is always enabled.
Serial data input pin for UART1. Set the corresponding Port
Direction Register to input if this function is used.
SIN1
(Continued)
Document Number: 002- 07696 Rev. *A
Page 10 of 70
MB90540G/545G Series
Pin No.
LQFP*2 QFP*1
Pin name
Circuit type
Function
General I/O port. This function is enabled when UART1 disables the clock
output.
P44
20
22
23
22
24
25
G
Serial clock pulse I/O pin for UART1. This function is enabled when UART1
enables the serial clock output.
SCK1
P45
General I/O port. This function is enabled when UART1 disables the serial
data output.
G
G
Serial data output pin for UART1. This function is enabled when UART1
enables the serial data output.
SOT1
P46
General I/O port. This function is enabled when the Extended I/O serial
interface disables the serial data output.
Serial data output pin for the Extended I/O serial interface. This function is
enabled when the Extended I/O serial interface enables the serial data output.
SOT2
P47
General I/O port. This function is enabled when the Extended I/O serial
interface disables the clock output.
24
26
28
G
Serial clock pulse I/O pin for the Extended I/O serial interface . This function is
enabled when the Extended I/O serial interface enables the Serial clock
output.
SCK2
P50
General I/O port. This function is always enabled.
26
D
D
D
Serial data input pin for the Extended I/O serial interface . Set the
corresponding Port Direction Register to input if this function is used.
SIN2
P51 to P54
INT4 to INT7
P55
General I/O port. This function is always enabled.
27 to 30
31
29 to 32
33
External interrupt request input pins for INT4 to INT7. Set the corresponding
Port Direction Register to input if this function is used.
General I/O port. This function is always enabled.
Trigger input pin for the A/D converter. Set the corresponding Port Direction
Register to input if this function is used.
ADTG
General I/O port. This function is enabled when the analog input enable
register specifies a port.
P60 to P63
AN0 to AN3
P64 to P67
36 to 39
38 to 41
E
Analog input pins for the 8/10-bit A/D converter. This function is enabled when
the analog input enable register specifies A/D.
General I/O port. The function is enabled when the analog input enable
register specifies a port.
41 to 44
43 to 46
E
D
Analog input pins for the 8/10-bit A/D converter. This function is enabled when
the analog input enable register specifies A/D.
AN4 to AN7
P56
General I/O port. This function is always enabled.
45
47
Event input pin for the 16-bit reload timers 0. Set the corresponding Port
Direction Register to input if this function is used.
TIN0
(Continued)
Document Number: 002- 07696 Rev. *A
Page 11 of 70
MB90540G/545G Series
Pin No.
LQFP*2 QFP*1
Pin name
Circuit type
Function
General I/O port. This function is enabled when the 16-bit reload timers 0
disables the output.
P57
46
48
D
Output pin for the 16-bit reload timers 0. This function is enabled when the
16-bit reload timers 0 enables the output.
TOT0
P70 to P75
General I/O ports. This function is always enabled.
Trigger input pins for input captures ICU0 to ICU5. Set the corresponding
Port Direction Register to input if this
function is used.
51 to 56
53 to 58
D
D
D
IN0 to IN5
General I/O ports. This function is enabled when the OCU disables the
waveform output.
P76 , P77
Event output pins for output compares OCU2 and OCU3. This function is
enabled when the OCU enables the waveform output.
OUT2 , OUT3
57 , 58
59 , 60
Trigger input pins for input captures ICU6 and ICU7. Set the corresponding
Port Direction Register to input and disable the OCU waveform output if this
function is used.
IN6 , IN7
General I/O ports. This function is enabled when 8/16-bit PPG disables the
waveform output.
P80 to P83
PPG0 to PPG3
P84 , P85
59 to 62
61 to 64
Output pins for 8/16-bit PPGs. This function is enabled when 8/16-bit PPG
enables the waveform output.
General I/O ports. This function is enabled when the OCU disables the
waveform output.
63 , 64
65
65 , 66
67
D
D
D
Waveform output pins for output compares OCU0 and OCU1. This function is
enabled when the OCU enables the waveform output.
OUT0 , OUT1
P86
General I/O port. This function is always enabled.
Input pin for the 16-bit reload timers 1. Set the corresponding Port Direction
Register to input if this function is used.
TIN1
General I/O port. This function is enabled when the 16-bit reload timers 1
disables the output.
P87
66
68
Output pin for the 16-bit reload timers 1.This function is enabled when the 16-
bit reload timers 1 enables the output.
TOT1
P90 to P93
INT0 to INT3
P94
General I/O port. This function is always enabled.
67 to 70
71
69 to 72
73
D
D
External interrupt request input pins for INT0 to INT3. Set the corresponding
Port Direction Register to input if this function is used.
General I/O port. This function is enabled when CAN0 disables the output.
TX output pin for CAN0. This function is enabled when CAN0 enables the
output.
TX0
(Continued)
Document Number: 002- 07696 Rev. *A
Page 12 of 70
MB90540G/545G Series
(Continued)
Pin No.
LQFP*2 QFP*1
Pin name
P95
Circuit type
Function
General I/O port. This function is always enabled.
72
74
75
76
D
RX input pin for CAN0 Interface. When the CAN function is used, output from
the other functions must be stopped.
RX0
P96
TX1
P97
RX1
PA0
AVCC
General I/O port. This function is enabled when CAN1 disables the output.
73
74
D
TX output pin for CAN1. This function is enabled when CAN1 enables the
output (only MB90540G series) .
General I/O port. This function is always enabled.
D
D
RX input pin for CAN1 Interface. When the CAN function is used, output from
the other functions must be stopped (only MB90540G series) .
76
32
78
34
General I/O port. This function is always enabled.
Power
supply
Power supply pin for the A/D Converter. This power supply must be turned on
or off while a voltage higher than or equal to AVCC is applied to VCC.
Power
supply
35
33
37
35
36
AVSS
Power supply pin for the A/D Converter.
External reference voltage input pin for the A/D Converter. This power supply
must be turned on or off while a voltage higher than or equal to AVRH is
applied to AVCC.
Power
supply
AVRH
Power
supply
34
AVRL
MD0, MD1
MD2
C
External reference voltage input pin for the A/D Converter.
Input pins for specifying the operating mode. The pins must be directly
connected to VCC or VSS.
47, 48
49
49, 50
51
C
F
Input pin for specifying the operating mode. The pin must be directly
connected to VCC or VSS.
Power supply stabilization capacitor pin. It should be connected externally to
an 0.1 F ceramic capacitor.
25
27
Power
supply
21, 82
9, 40, 79
23, 84
11, 42, 81
VCC
Input pin for power supply (5.0 V) .
Input pin for power supply (0.0 V) .
Power
supply
VSS
*1 : FPT-100P-M06
*2 : FPT-100P-M20
Document Number: 002- 07696 Rev. *A
Page 13 of 70
MB90540G/545G Series
4. I/O Circuit Type
Circuit type
Diagram
Remarks
High-speed oscillation feedback resistor :
1 M approx.
X1, X1A
Low-speed oscillation feedback resistor:
10 M approx.
X0, X0A
A
Standby control signal
CMOS Hysteresis input
Pull-up resistor : 50 k approx.
R (Pull-up)
B
CMOS
Hysteresis input
R
CMOS Hysteresis input
CMOS
Hysteresis input
R
C
CMOS level output
V
CC
CMOS Hysteresis input
P-ch
N-ch
D
CMOS
Hysteresis input
R
(Continued)
Document Number: 002- 07696 Rev. *A
Page 14 of 70
MB90540G/545G Series
Circuit type
Diagram
Remarks
CMOS level output
CMOS Hysteresis input
Analog input
VCC
P-ch
N-ch
E
P-ch
Analog input
N-ch
CMOS
Hysteresis input
R
CMOS Hysteresis input
CMOS
Hysteresis input
Pull-down Resistor : 50 k approx.
(except Flash devices)
R
F
R (Pull-down)
CMOS level output
CMOS Hysteresis input
V
CC
TTL level input (Flash devices in
P-ch
N-ch
Flash writer mode only)
G
CMOS
Hysteresis input
R
R
TTL level input
T
(Continued)
Document Number: 002- 07696 Rev. *A
Page 15 of 70
MB90540G/545G Series
(Continued)
Circuit type
Diagram
Remarks
CMOS level output
CMOS Hysteresis input
Programmable pull-up resistor :
50 k approx.
VCC
CNTL
P-ch
VCC
P-ch
H
N-ch
CMOS
Hysteresis input
R
CMOS level output
CMOS Hysteresis input
TTL level input (Flash devices in
VCC
CNTL
Flash writer mode only)
VCC
Programmable pullup resistor :
50 k approx.
P-ch
N-ch
P-ch
I
CMOS
Hysteresis input
R
R
TTL level input
T
Document Number: 002- 07696 Rev. *A
Page 16 of 70
MB90540G/545G Series
5. Handling Devices
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
A voltage higher than the rated voltage is applied between VCC and VSS.
The AVcc power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, care must also be taken in not allowing the analog power-supply voltage (AVCC, AVRH) to exceed the digital
power-supply voltage.
(2) Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they
must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k.
Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described
connection.
(3) Using external clock
To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.
MB90540G/545G Series
X0
Open
X1
(4) Use of the sub-clock
Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When
using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins.
(5) Power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal
operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-
magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total current rating.
Make sure to connect VCC and VSS pins via the lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90540G/545G
Series
VCC
VSS
VCC
VSS
Document Number: 002- 07696 Rev. *A
Page 17 of 70
MB90540G/545G Series
(6) Pull-up/down resistors
The MB90540G/545G Series does not support internal pull-up/down resistors (except Port0 Port3 : pull-up resistors) . Use
external components where needed.
(7) Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via the
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort,
that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the
operation.
(8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the
digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does
not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) .
C(9o)nCneocntnuencutsioend opifnUsnouf sAe/Dd PcoinnsveorfteAr/tDo CAVonCCvertVeCrC, AVSS AVRH VSS.
(10) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(11) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to
2.7 V) .
Document Number: 002- 07696 Rev. *A
Page 18 of 70
MB90540G/545G Series
(12) Indeterminate outputs from ports 0 and 1 (MB90V540G only)
During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0
and 1 become following state.
If RST pin is “H”, the outputs become indeterminate.
If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow.
RST pin is “H”
Oscillation setting time*2
Power-on reset*1
VCC (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
Period of indeterminated
*1 : Power-on reset time : “Period of clock frequency” 217 (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : “Period of clock frequency” 218 (Clock frequency of 16 MHz : 16.38 ms)
Document Number: 002- 07696 Rev. *A
Page 19 of 70
MB90540G/545G Series
RST pin is “L”
Oscillation setting time*2
Power-on reset*1
VCC (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
High-impedance
*1 : Power-on reset time : “Period of clock frequency” 217 (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : “Period of clock frequency” 218 (Clock frequency of 16 MHz : 16.38 ms)
(13) Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on
the power again.
(14) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the corresponding bank register
(DTB, ADB, USB, SSB) is set in “00H”.
If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder by the execution
result of the instruction is not stored in the register of the instruction operand.
(15) Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
(16) Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no
external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
Document Number: 002- 07696 Rev. *A
Page 20 of 70
MB90540G/545G Series
6. Block Diagram
X0, X1
X0A, X1A
F2MC 16LX
CPU
Clock
Controller
RST
HST
16-bit
Free-run
Timer
RAM
2 K/4 K/6 K/8 K
16-bit Input
Capture
8 ch.
IN0 to IN5
ROM/Flash
128 K/256 K/
64K(ROM only)
IN6/OUT2,
IN7/OUT3
16-bit Output
Compare
4 ch.
OUT0, OUT1
Prescaler
UART0
8/16-bit
PPG
4 ch.
SOT0
PPG0 to PPG3
SCK0
SIN0
RX0, RX1 *
TX0, TX1 *
CAN
Controller
Prescaler
SOT1
UART1
(SCI)
SCK1
SIN1
TIN0, TIN1
16-bit Reload
Timer 2 ch.
TOT0, TOT1
Prescaler
Serial I/O
AD00 to AD15
A16 to A23
ALE
SOT2
SCK2
SIN2
RD
External
Bus
Interface
WRL
AVCC
WRH
AVSS
HRQ
HAK
RDY
AN0 to AN7
AVRH
10-bit A/D
Converter
8 ch.
AVRL
ADTG
CLK
External
Interrupt
8 ch.
INT0 to INT7
* : Only the MB90540G series has two channels
Document Number: 002- 07696 Rev. *A
Page 21 of 70
MB90540G/545G Series
7. Memory Map
The memory space of the MB90540G/545G Series is shown below.
MB90548G(S)
MB90F548GL(S)
MB90F548G (S)
MB90549G (S) /
F549G (S)
MB90V540G/
F546G (S)
MB90543G(S)
F543G(S)
MB90547G (S)
FFFFFF
H
H
FFFFFF
H
FFFFFF
H
FFFFFF
H
FFFFFFH
ROM
(FF bank)
ROM
(FF bank)
ROM
(FF bank)
ROM
(FF bank)
ROM
(FF bank)
FF0000
FF0000
H
FF0000
H
FF0000
H
FF0000
H
FEFFFF
H
FEFFFF
H
FEFFFF
H
FEFFFFH
ROM
ROM
ROM
ROM
(FE bank)
(FE bank)
(FE bank)
(FE bank)
FE0000
H
FE0000
H
FE0000
H
FE0000
H
FDFFFF
H
FDFFFF
H
ROM
ROM
(FD bank)
(FD bank)
External
FD0000
H
FD0000
H
FCFFFF
H
FCFFFF
H
ROM
External
External
ROM
(FC bank)
(FC bank)
FC0000
H
FC0000
00FFFF
H
External
External
00FFFF
H
00FFFF
H
00FFFF
H
00FFFF
H
H
ROM
ROM
ROM
ROM
ROM
(Image of
FF bank)
(Image of
FF bank)
(Image of
FF bank)
(Image of
FF bank)
(Image of
FF bank)
004000
H
004000
H
004000
H
004000
H
004000
003FFF
H
H
003FFF
H
003FFF
H
003FFF
H
003FFFH
Peripheral
External
Peripheral
External
Peripheral
External
Peripheral
External
Peripheral
External
003900
H
003900
002000
0018FF
H
003900
002000
H
003900H
003900
H
H
H
H
002100
H
002000
0020FF
H
001FF5
001FF0
H
H
H
0018FF
H
ROM correction
RAM 8 K
0010FF
H
RAM 6 K
RAM 6 K
0008FF
H
RAM 4 K
RAM 2 K
External
000100
H
000100
H
000100
H
000100H
000100
H
External
External
External
External
0000BF
H
0000BF
000000
H
0000BF
000000
H
0000BF
000000
H
0000BF
H
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
H
H
H
000000H
000000
H
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.
Since the low-order 16 bits address are the same, the table in ROM can be referenced without using the “far” specification in
the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM area in bank FF exceeds 48
Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH is visible in bank 00,
while the image between FF0000H and FF3FFFH is visible only in bank FF.
Document Number: 002- 07696 Rev. *A
Page 22 of 70
MB90540G/545G Series
8. I/O Map
Address
00H
Register
Port 0 data register
Abbreviation
PDR0
Access
R/W
Resource name
Port 0
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
_ _ _ _ _ _ _XB
01H
Port 1 data register
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
02H
Port 2 data register
03H
Port 3 data register
04H
Port 4 data register
05H
Port 5 data register
06H
Port 6 data register
07H
Port 7 data register
08H
Port 8 data register
09H
Port 9 data register
0AH
0BH to 0FH
10H
Port A data register
Reserved
Port 0 direction register
Port 1 direction register
Port 2 direction register
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Port A direction register
Analog Input Enable register
Port 0 Pullup control register
Port 1 Pullup control register
Port 2 Pullup control register
Port 3 Pullup control register
Serial Mode Control Register 0
Serial Status Register 0
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
ADER
PUCR0
PUCR1
PUCR2
PUCR3
UMC0
USR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 6, A/D
Port 0
Port 1
Port 2
Port 3
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
_ _ _ _ _ _ _0B
1 1 1 1 1 1 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
0 0 0 1 0 0 0 0B
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
UART0
Serial input data register 0/
Serial output data register 0
22H
23H
UIDR0/UODR0
URD0
R/W
R/W
XXXXXXXXB
Rate and data register 0
0 0 0 0 0 0 0XB
(Continued)
Document Number: 002- 07696 Rev. *A
Page 23 of 70
MB90540G/545G Series
Address
24H
Register
Serial mode register 1
Access
R/W
R/W
Resource name
Initial value
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
Abbreviation
SMR1
25H
26H
Serial control register 1
SCR1
Serial input data register 1/
Serial output data register 1
SIDR1/SODR1 R/W
XXXXXXXXB
UART1
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
Serial status register 1
SSR1
CDCR
SES1
R/W
R/W
R/W
0 0 0 0 1_0 0B
0_ _ _1 1 1 1B
_ _ _ _ _ _ _0B
UART1 prescaler control register
Serial Edge select register
Prohibited
Serial I/O prescaler
SCDCR
SMCS
SMCS
SDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0_ _ _1 1 1 1B
_ _ _ _0 0 0 0B
0 0 0 0 0 0 1 0B
XXXXXXXXB
Serial mode control register
Serial mode control register
Serial data register
Extended I/O
Serial Interface
Serial Edge select register
External interrupt enable register
External interrupt request register
External interrupt level register
External interrupt level register
A/D control status register 0
A/D control status register 1
A/D data register 0
SES2
_ _ _ _ _ _ _0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
ENIR
EIRR
External Interrupt
A/D Converter
ELVR
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
ELVR
ADCS0
ADCS1
ADCR0
ADCR1
PPGC0
PPGC1
PPG01
A/D data register 1
R/W
R/W
R/W
R/W
0 0 0 0 1 _ XXB
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
PPG0 operation mode control register
PPG1 operation mode control register
PPG0/1 clock selection register
Prohibited
16-bit Programmable
Pulse
Generator 0/1
PPG2 operation mode control register
PPG3 operation mode control register
PPG2/3 Clock Selection Register
Prohibited
PPGC2
PPGC3
PPG23
R/W
R/W
R/W
0 _ 0 0 0 _ _1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
16-bit Programmable
Pulse
Generator 2/3
PPG4 operation mode control register
PPG5 operation mode control register
PPG4/5 clock selection register
Prohibited
PPGC4
PPGC5
PPG45
R/W
R/W
R/W
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
16-bit Programmable
Pulse
Generator 4/5
PPG6 operation mode control register
PPG7 operation mode control register
PPG6/7 clock selection register
PPGC6
PPGC7
PPG67
R/W
R/W
R/W
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
16-bit Programmable
Pulse
Generator 6/7
(Continued)
Document Number: 002- 07696 Rev. *A
Page 24 of 70
MB90540G/545G Series
Address
47H to 4BH
4CH
Register
Abbreviation
Access
Resource name
Initial value
Prohibited
ICS01
R/W
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
_ _ _ _ 0 0 0 0B
XXXXXXXXB
Input capture control status register 0/1
Input capture control status register 2/3
Input capture control status register 4/5
Input capture control status register 6/7
Timer control status register 0
4DH
ICS23
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4EH
ICS45
4FH
ICS67
50H
TMCSR0
51H
Timer control status register 0
TMCSR0
16-bit Reload Timer 0
16-bit Reload Timer 1
52H
Timer register 0/reload register 0
TMR0/TMRLR0
TMR0/TMRLR0
TMCSR1
53H
Timer register 0/reload register 0
XXXXXXXXB
54H
Timer control status register 1
0 0 0 0 0 0 0 0B
_ _ _ _ 0 0 0 0B
XXXXXXXXB
55H
Timer control status register 1
TMCSR1
56H
Timer register 1/reload register 1
TMR1/TMRLR1
TMR1/TMRLR1
OCS0
57H
Timer register 1/reload register 1
XXXXXXXXB
58H
0 0 0 0 _ _ 0 0B
_ _ _0 0 0 0 0B
0 0 0 0 _ _ 0 0B
_ _ _ 0 0 0 0 0B
Output compare control status register 0
Output Compare 0/1
Output Compare 2/3
59H
Output compare control status register 1 OCS1
5AH
OCS2
OCS3
Output compare control status register 2
Output compare control status register 3
Prohibited
5BH
5CH to 6BH
6CH
Timer Data register
TCDT
TCDT
TCCS
R/W
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
6DH
Timer Data register
I/O Timer
6EH
Timer Control register
ROM mirror function
selection register
6FH
ROMM
R/W
ROM Mirror
_ _ _ _ _ _ _ 1B
70H to 7FH
80H to 8FH
90H to 9DH
Reserved for CAN 0 Interface.
Reserved for CAN 1 Interface.
Prohibited
Address Match
Detection
Function
Program address detection
control status register
9EH
PACSR
R/W
0 0 0 0 0 0 0 0B
9FH
A0H
Delayed interrupt/release register
Low-power mode control register
DIRR
R/W
R/W
Delayed Interrupt
_ _ _ _ _ _ _ 0B
0 0 0 1 1 0 0 0B
Low Power
Controller
LPMCR
Low Power
Controller
A1H
Clock selection register
CKSCR
R/W
1 1 1 1 1 1 0 0B
(Continued)
Document Number: 002- 07696 Rev. *A
Page 25 of 70
MB90540G/545G Series
Address
A2H to A4H
A5H
Register
Abbreviation
Access
Resource name
Initial value
Prohibited
ARSR
W
0 0 1 1 _ _ 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 _B
XXXXX 1 1 1B
1 - - 0 0 1 0 0B
1 X 0 0 0 0 0 0B
Automatic ready function select register
External address output control register
Bus control signal selection register
Watchdog Timer control register
Time Base Timer Control register
Watch timer control register
External Memory
Access
A6H
HACR
ECSR
WDTC
TBTC
WTC
W
A7H
W
A8H
R/W
R/W
R/W
Watchdog Timer
Time Base Timer
Watch Timer
A9H
AAH
ABH to ADH
Prohibited
Flash memory control status register
(Flash only, otherwise reserved)
AEH
FMCS
R/W
Flash Memory
0 0 0 X 0 0 0 0B
AFH
B0H
Prohibited
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
External
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
B1H
B2H
B3H
B4H
B5H
B6H
B7H
Interrupt
controller
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H to FFH
Address
1FF0H
Register
Abbreviation
Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Program address detection register 0
Program address detection register 0
Program address detection register 0
Program address detection register 1
Program address detection register 1
Program address detection register 1
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
R/W
R/W
R/W
R/W
R/W
R/W
1FF1H
1FF2H
Address Match
Detection Function
1FF3H
1FF4H
1FF5H
(Continued)
Document Number: 002- 07696 Rev. *A
Page 26 of 70
MB90540G/545G Series
Address
3900H
Register
Access
R/W
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Abbreviation
PRLL0
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reserved
3901H
3902H
3903H
3904H
3905H
3906H
3907H
3908H
3909H
390AH
390BH
390CH
390DH
390EH
390FH
3910H to 3917H
3918H
3919H
391AH
391BH
391CH
391DH
391EH
391FH
3920H
3921H
3922H
3923H
3924H
3925H
3926H
3927H
PRLH0
PRLL1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16-bit Programmable Pulse
Generator 0/1
PRLH1
PRLL2
PRLH2
PRLL3
16-bit Programmable Pulse
Generator 2/3
PRLH3
PRLL4
PRLH4
PRLL5
16-bit Programmable Pulse
Generator 4/5
PRLH5
PRLL6
PRLH6
PRLL7
16-bit Programmable Pulse
Generator 6/7
PRLH7
Input Capture Register 0
Input Capture Register 0
Input Capture Register 1
Input Capture Register 1
Input Capture Register 2
Input Capture Register 2
Input Capture Register 3
Input Capture Register 3
Input Capture Register 4
Input Capture Register 4
Input Capture Register 5
Input Capture Register 5
Input Capture Register 6
Input Capture Register 6
Input Capture Register 7
Input Capture Register 7
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
IPCP4
IPCP4
IPCP5
IPCP5
IPCP6
IPCP6
IPCP7
IPCP7
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
(Continued)
Document Number: 002- 07696 Rev. *A
Page 27 of 70
MB90540G/545G Series
(Continued)
Address
3928H
Register
Abbreviation
OCCP0
Access
R/W
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Output Compare Register 0
Output Compare Register 0
Output Compare Register 1
Output Compare Register 1
Output Compare Register 2
Output Compare Register 2
Output Compare Register 3
Output Compare Register 3
3929H
392AH
392BH
392CH
392DH
392EH
392FH
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare 0/1
Output Compare 2/3
3930H to 39FFH Reserved
3A00H to 3AFFH Reserved for CAN 0 Interface.
3B00H to 3BFFH Reserved for CAN 0 Interface.
3C00H to 3CFFH Reserved for CAN 1 Interface.
3D00H to 3DFFH Reserved for CAN 1 Interface.
3E00H to 3FFFH Reserved
Read/write notation
R/W
: Reading and writing permitted
R
: Read-only
W
: Write-only
Initial value notation
0
1
X
_
: Initial value is “0”.
: Initial value is “1”.
: Initial value is undefined.
: Initial value is unused.
Note:
Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results
in reading “X”.
Document Number: 002- 07696 Rev. *A
Page 28 of 70
MB90540G/545G Series
9. CAN Controller
The MB90540G series contains two CAN controllers (CAN0 and CAN1) , the MB90545G series contains only one (CAN0) . The Evaluation Chip
MB90V540G also has two CAN controllers.
The CAN controller has the following features :
Conforms to CAN Specification Version 2.0 Part A and B
❐ Supports transmission/reception in standard frame and extended frame formats
Supports transmission of data frames by receiving remote frames
16 transmitting/receiving message buffers
❐ 29-bit ID and 8-byte data
❐ Multi-level message buffer configuration
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID
acceptance mask
❐ Two acceptance mask registers in either standard frame format or extended frame formats
Bit rate programmable from 10 Kbps to 1 Mbps (when input clock is at 16 MHz)
List of Control Registers
Address
Register
Message buffer valid register
Transmit request register
Transmit cancel register
Abbreviation
Access
Initial Value
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
CAN0
000070H
CAN1
000080H
BVALR
R/W
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
TREQR
TCANR
TCR
R/W
W
Transmit complete register
Receive complete register
Remote request receiving register
Receive overrun register
R/W
R/W
R/W
R/W
R/W
RCR
RRTRR
ROVRR
RIER
Receive interrupt enable register
(Continued)
Document Number: 002- 07696 Rev. *A
Page 29 of 70
MB90540G/545G Series
(Continued)
Address
Register
Control status register
Abbreviation
Access
R/W, R
R/W
Initial Value
00---000 0----0-1B
CAN0
003B00H
003B01H
003B02H
003B03H
003B04H
003B05H
003B06H
003B07H
003B08H
003B09H
003B0AH
003B0BH
003B0CH
003B0DH
003B0EH
003B0FH
003B10H
003B11H
003B12H
003B13H
003B14H
003B15H
003B16H
003B17H
003B18H
003B19H
003B1AH
003B1BH
CAN1
003D00H
003D01H
003D02H
003D03H
003D04H
003D05H
003D06H
003D07H
003D08H
003D09H
003D0AH
003D0BH
003D0CH
003D0DH
003D0EH
003D0FH
003D10H
003D11H
003D12H
003D13H
003D14H
003D15H
003D16H
003D17H
003D18H
003D19H
003D1AH
003D1BH
CSR
Last event indicator register
LEIR
-------- 000-0000B
Receive/transmit error counter register RTEC
R
00000000 00000000B
-1111111 11111111B
Bit timing register
IDE register
BTR
R/W
IDER
TRTRR
R/W
XXXXXXXX XXXXXXXXB
00000000 00000000B
XXXXXXXX XXXXXXXXB
00000000 00000000B
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
Transmit RTR register
R/W
Remote frame receive waiting register RFWTR
R/W
Transmit request enable register
Acceptance mask select register
TIER
R/W
AMSR
R/W
R/W
R/W
Acceptance mask register 0
Acceptance mask register 1
AMR0
AMR1
List of Message Buffers (ID Registers)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
003A00H
to
003A1FH
003C00H
to
003C1FH
XXXXXXXXB
to
XXXXXXXXB
General-purpose RAM
R/W
003A20H
003A21H
003A22H
003A23H
003C20H
003C21H
003C22H
003C23H
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
ID register 0
IDR0
R/W
Document Number: 002- 07696 Rev. *A
Page 30 of 70
MB90540G/545G Series
Address
Register
Abbreviation
Access
Initial Value
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
CAN0
003A24H
003A25H
003A26H
003A27H
003A28H
003A29H
003A2AH
003A2BH
003A2CH
003A2DH
003A2EH
003A2FH
003A30H
003A31H
003A32H
003A33H
003A34H
003A35H
003A36H
003A37H
003A38H
003A39H
003A3AH
003A3BH
CAN1
003C24H
003C25H
003C26H
003C27H
003C28H
003C29H
003C2AH
003C2BH
003C2CH
003C2DH
003C2EH
003C2FH
003C30H
003C31H
003C32H
003C33H
003C34H
003C35H
003C36H
003C37H
003C38H
003C39H
003C3AH
003C3BH
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
IDR1
R/W
IDR2
IDR3
IDR4
IDR5
IDR6
R/W
R/W
R/W
R/W
R/W
XXXXX--- XXXXXXXXB
(Continued)
Document Number: 002- 07696 Rev. *A
Page 31 of 70
MB90540G/545G Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
CAN0
003A3CH
003A3DH
003A3EH
003A3FH
003A40H
003A41H
003A42H
003A43H
003A44H
003A45H
003A46H
003A47H
003A48H
003A49H
003A4AH
003A4BH
003A4CH
003A4DH
003A4EH
003A4FH
003A50H
003A51H
003A52H
003A53H
003A54H
003A55H
003A56H
003A57H
003A58H
003A59H
003A5AH
003A5BH
003A5CH
003A5DH
003A5EH
003A5FH
CAN1
003C3CH
003C3DH
003C3EH
003C3FH
003C40H
003C41H
003C42H
003C43H
003C44H
003C45H
003C46H
003C47H
003C48H
003C49H
003C4AH
003C4BH
003C4CH
003C4DH
003C4EH
003C4FH
003C50H
003C51H
003C52H
003C53H
003C54H
003C55H
003C56H
003C57H
003C58H
003C59H
003C5AH
003C5BH
003C5CH
003C5DH
003C5EH
003C5FH
ID register 7
ID register 8
ID register 9
ID register 10
ID register 11
ID register 12
ID register 13
ID register 14
ID register 15
IDR7
R/W
IDR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
Document Number: 002- 07696 Rev. *A
Page 32 of 70
MB90540G/545G Series
List of Message Buffers (DLC Registers and Data Registers)
Address
Register
Abbreviation
Access
Initial Value
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXX
CAN0
003A60H
003A61H
003A62H
003A63H
003A64H
003A65H
003A66H
003A67H
003A68H
003A69H
003A6AH
003A6BH
003A6CH
003A6DH
003A6EH
003A6FH
003A70H
003A71H
003A72H
003A73H
003A74H
003A75H
003A76H
003A77H
003A78H
003A79H
003A7AH
003A7BH
003A7CH
003A7DH
003A7EH
003A7FH
CAN1
003C60H
003C61H
003C62H
003C63H
003C64H
003C65H
003C66H
003C67H
003C68H
003C69H
003C6AH
003C6BH
003C6CH
003C6DH
003C6EH
003C6FH
003C70H
003C71H
003C72H
003C73H
003C74H
003C75H
003C76H
003C77H
003C78H
003C79H
003C7AH
003C7BH
003C7CH
003C7DH
003C7EH
003C7FH
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
DLCR0
R/W
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
003A80H
to
003C80H
to
XXXXXXXXB
to
Data register 0 (8 bytes)
DTR0
R/W
003A87H
003C87H
XXXXXXXXB
(Continued)
Document Number: 002- 07696 Rev. *A
Page 33 of 70
MB90540G/545G Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
003A88H
to
003C88H
to
XXXXXXXXB
to
Data register 1 (8 bytes)
DTR1
R/W
003A8FH
003C8FH
XXXXXXXXB
003A90H
to
003A97H
003C90H
to
003C97H
XXXXXXXXB
to
XXXXXXXXB
Data register 2 (8 bytes)
Data register 3 (8 bytes)
Data register 4 (8 bytes)
Data register 5 (8 bytes)
Data register 6 (8 bytes)
Data register 7 (8 bytes)
Data register 8 (8 bytes)
Data register 9 (8 bytes)
Data register 10 (8 bytes)
Data register 11 (8 bytes)
Data register 12 (8 bytes)
Data register 13 (8 bytes)
Data register 14 (8 bytes)
Data register 15 (8 bytes)
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
DTR14
DTR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
003A98H
to
003A9FH
003C98H
to
003C9FH
XXXXXXXXB
to
XXXXXXXXB
003AA0H
to
003AA7H
003CA0H
to
003CA7H
XXXXXXXXB
to
XXXXXXXXB
003AA8H
to
003AAFH
003CA8H
to
003CAFH
XXXXXXXXB
to
XXXXXXXXB
003AB0H
to
003AB7H
003CB0H
to
003CB7H
XXXXXXXXB
to
XXXXXXXXB
003AB8H
to
003ABFH
003CB8H
to
003CBFH
XXXXXXXXB
to
XXXXXXXXB
003AC0H
to
003AC7H
003CC0H
to
003CC7H
XXXXXXXXB
to
XXXXXXXXB
003AC8H
to
003ACFH
003CC8H
to
003CCFH
XXXXXXXXB
to
XXXXXXXXB
003AD0H
to
003AD7H
003CD0H
to
003CD7H
XXXXXXXXB
to
XXXXXXXXB
003AD8H
to
003ADFH
003CD8H
to
003CDFH
XXXXXXXXB
to
XXXXXXXXB
003AE0H
to
003AE7H
003CE0H
to
003CE7H
XXXXXXXXB
to
XXXXXXXXB
003AE8H
to
003AEFH
003CE8H
to
003CEFH
XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
003AF7H
003CF0H
to
003CF7H
XXXXXXXXB
to
XXXXXXXXB
003AF8H
to
003CF8H
to
XXXXXXXXB
to
003AFFH
003CFFH
XXXXXXXXB
Document Number: 002- 07696 Rev. *A
Page 34 of 70
MB90540G/545G Series
10. Interrupt Map
Interrupt vector
Number Address
Interrupt control register
EI2OS
clear
Interrupt cause
Number
Address
Reset
N/A
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
INT9 instruction
Exception
N/A
N/A
N/A
N/A
N/A
N/A
*1
CAN 0 RX
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
CAN 0 TX/NS
CAN 1 RX
CAN 1 TX/NS
External Interrupt INT0/INT1
Time Base Timer
16-bit Reload Timer 0
8/10-bit A/D Converter
16-bit Free-run Timer
External Interrupt INT2/INT3
Serial I/O
N/A
*1
*1
N/A
*1
*1
8/16-bit PPG 0/1
Input Capture 0
N/A
*1
External Interrupt INT4/INT5
Input Capture 1
*1
*1
8/16-bit PPG 2/3
External Interrupt INT6/INT7
Watch Timer
N/A
*1
N/A
N/A
*1
8/16-bit PPG 4/5
Input Capture 2/3
8/16-bit PPG 6/7
Output Compare 0
Output Compare 1
Input Capture 4/5
Output Compare 2/3 - Input Capture 6/7
16-bit Reload Timer 1
UART 0 RX
N/A
*1
*1
*1
*1
*1
*2
UART 0 TX
*1
UART 1 RX
*2
UART 1 TX
*1
Flash Memory
N/A
N/A
Delayed interrupt
(Continued)
Document Number: 002- 07696 Rev. *A
Page 35 of 70
MB90540G/545G Series
(Continued)
*1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal.
*2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
Notes :
N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the
EI2OS interrupt clear signal.
At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If
one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost
because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for
this interrupt number.
If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is
asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt
source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled.
Document Number: 002- 07696 Rev. *A
Page 36 of 70
MB90540G/545G Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
(VSS AVSS 0.0 V)
Value
Parameter
Symbol
Units
Remarks
Min
Max
VCC
AVCC
VSS 0.3
VSS 0.3
VSS 6.0
VSS 6.0
V
V
VCC AVCC
*1
Power supply voltage
AVCC AVRH/AVRL, AVRH
AVRH, AVRL VSS 0.3
VSS 6.0
V
AVRL
*1
Input voltage
VI
VSS 0.3
VSS 6.0
VSS 6.0
2.0
20
V
*2
*2
*6
*6
*3
*4
Output voltage
VO
VSS 0.3
V
Maximum clamp current
ICLAMP
| ICLAMP |
IOL
2.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
C
Total maximum clamp current
“L” level max output current
“L” level avg. output current
“L” level max overall output current
“L” level avg. overall output current
“H” level max output current
“H” level avg. output current
“H” level max overall output current
“H” level avg. overall output current
15
IOLAV
IOL
4
100
IOLAV
IOH
50
*5
*3
*4
15
4
IOHAV
IOH
IOHAV
100
50
500
*5
Flash device
MASK ROM
Power consumption
PD
400
Operating temperature
Storage temperature
TA
40
55
105
150
TSTG
C
*1 : AVCC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not exceed AVRH.
*2 : VI and VO should not exceed VCC 0.3 V. However if the maximum current to/from an input is limited by some means with
external components, the ICLAMP rating supercedes the VI rating.
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
*6 :
❐ Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80
to P87, P90 to P97, PA0
❐ Use within recommended operating conditions.
❐ Use at DC voltage (current) .
❐ The B signal should always be applied with a limiting resistance placed between the B signal and the microcontroller.
❐ The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller
pin does not exceed rated values, either instantaneously or for prolonged periods.
❐ Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
❐ Note that if a B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the
pins, so that incomplete operation may result.
❐ Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting supply volt-
age may not be sufficient to operate the power-on result.
❐ Care must be taken not to leave the B input pin open.
Document Number: 002- 07696 Rev. *A
Page 37 of 70
MB90540G/545G Series
❐ Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot
accept B signal input.
❐ Sample recommended circuits :
Input/Output Equivalent circuits
Protective diode
VCC
P-ch
N-ch
Limiting
resistance
B input (0 V to 16 V)
R
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002- 07696 Rev. *A
Page 38 of 70
MB90540G/545G Series
11.2 Recommended Conditions
(VSS AVSS 0.0 V)
Value
Typ
Parameter
Symbol
Units
Remarks
Min
Max
Under normal operation : Other than
MB90F548GL(S)/543G(S)/547G(S)/548G(S)
4.5
5.0
5.5
5.5
V
Under normal operation when A/D conveter is
used :
MB90F548GL(S)/543G(S)/547G(S)/548G(S)
Power supply voltage
VCC, AVCC
Under normal operation when A/D conveter is
not used :
MB90F548GL(S)/543G(S)/547G(S)/548G(S)
3.5
3.0
5.0
V
0.1
5.5
1.0
V
Maintain RAM data in stop mode
*
Smooth capacitor
CS
TA
0.022
F
C
Operating temperature
40
105
*: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The bypass capacitor should be greater than this
capacitor.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
C Pin Connection Diagram
C
CS
Document Number: 002- 07696 Rev. *A
Page 39 of 70
MB90540G/545G Series
11.3 DC Characteristics
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10%, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
CMOS
Condition
Units
Remarks
Min
Typ
Max
VIHS
hysteresis
input pin
0.8 VCC
VCC 0.3
V
Input H
voltage
VIH
TTL input pin
MD input pin
V
V
VIHM
V2.C0C 0.3
VCC 0.3
VCC 0.3
CMOS
hysteresis
input pin
VILS
0.2 VCC
V
Input L
voltage
VIL
TTL input pin
MD input pin
V
V
VILM
VSS 0.3
V0.S8S 0.3
VCC 4.5 V,
IOH 4.0 mA
VCC 4.5 V,
IOL 4.0 mA
VCC 5.5 V,
VSS VI VCC
Output H
voltage
VOH
VOL
IIL
All output pins
All output pins
VCC 0.5
V
Output L
voltage
0.4
V
Input leak
current
5
5
A
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-up
resistance
RUP
25
25
50
50
100
100
k
k
Except
Flash
devices
Pull-down
resistance
RDOWN
MD2
(Continued)
Document Number: 002- 07696 Rev. *A
Page 40 of 70
MB90540G/545G Series
(Continued)
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Typ
Sym-
bol
Parameter
Pin name
Condition
Units
mA
Remarks
Min
Max
55
Internal frequency : 16 MHz, At
normal operating
40
ICC
Internal frequency : 16 MHz, At
Flash programming/erasing
50
12
70
20
mA
Flash device
Internal frequency : 16 MHz, At
sleep mode
ICCS
mA
300
600
600
A
A
VCC 5.0 V 10,
1100
MB90F548GL (S) only
ICTS
Internal frequency : 2 MHz,
At pseudo timer mode
MB90543G(S)/547G(S)/
548(S) only
200
400
A
Power
supply
current*
VCC
400
50
750
100
300
A
A
A
MB90F548GL only
MASK ROM
Internal frequency : 8 kHz,
ICCL
At sub operation, TA 25 C
150
Flash device
Internal frequency : 8 kHz,
At sub sleep, TA 25 C
Internal frequency : 8 kHz,
25 C
ICCLS
15
40
A
ICCT
7
25
A
A
A
ICCH1
ICCH2
AAtt stitmoepr, TmAode2,5TAC
5
20
ATtAhard2w5arCe standby mode,
50
100
Other than
AVCC, AVSS,
AVRH,
AVRL, C,
VCC, VSS
Input
capacity
CIN
5
15
pF
* : The power supply current testing conditions are when using the external clock.
Document Number: 002- 07696 Rev. *A
Page 41 of 70
MB90540G/545G Series
11.4 AC Characteristics
11.4.1 Clock Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Units
Remarks
Min
Typ
Max
16
No multiplier
3
8
4
3
3
3
MHz
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 1
16
8
MHz
MHz
MHz
MHz
MHz
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 2
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 3
5.33
4
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 4
When using an oscillator circuit
VCC 5.0 V 10%
When using an oscillator circuit
VCC < 4.5 V(MB90F548GL(S)/543G(S)/
547G(S)/548G(S))
fC
X0, X1
Oscillation frequency
5
No multiplier
When using an external clock
3
8
4
3
16
16
8
MHz
MHz
MHz
MHz
PLL multiplied by 1
When using an external clock
PLL multiplied by 2
When using an external clock
PLL multiplied by 3
When using an external clock
5.33
PLL multiplied by 4
When using an external clock
3
4
MHz
kHz
fCL
X0A, X1A
32.768
(Continued)
Document Number: 002- 07696 Rev. *A
Page 42 of 70
MB90540G/545G Series
(Continued)
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Units
Remarks
Min
62.5
Typ
Max
333
No multiplier
ns
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 1
62.5
125
125
250
333
333
333
ns
ns
ns
ns
ns
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 2
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 3
187.5
250
When using an oscillator circuit
VCC 5.0 V 10%
PLL multiplied by 4
When using an oscillator circuit
VCC 5.0 V 10%
When using an oscillator circuit
VCC < 4.5 V(MB90F548GL(S)/543G(S)/
547G(S)/548G(S))
tCYL
X0, X1
Clock cycle time
200
No multiplier
When using an external clock
62.5
62.5
125
333
125
250
333
333
ns
ns
ns
ns
ns
PLL multiplied by 1
When using an external clock
PLL multiplied by 2
When using an external clock
PLL multiplied by 3
When using an external clock
187.5
250
PLL multiplied by 4
When using an external clock
tLCYL
X0A, X1A
X0
10
30.5
s
ns
s
PWH, PWL
PWLH, PWLL
15.2
Input clock pulse width
Duty ratio is about 30 to 70.
X0A
Input clock rise and fall
time
tCR, tCF
X0
5
ns
When using an external clock
fCP
1.5
16
MHz
kHz
ns
When using main clock
When using sub-clock
When using main clock
When using sub-clock
Machine clock frequency
Machine clock cycle time
fLCP
tCP
62.5
8.192
122.1
666
tLCP
s
Document Number: 002- 07696 Rev. *A
Page 43 of 70
MB90540G/545G Series
Clock Timing
tCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tCF
tCR
tLCYL
0.8 VCC
0.2 VCC
X0A
PWLH
PWLL
tCF
tCR
Guaranteed PLL operation range
Guaranteed operation range
(Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S))
Guaranteed operation range
(MB90F548GL(S)/543G(S)/547G(S)/548G(S))
5.5
Guaranteed A/D Converter
operation range
Power supply voltage
4.5
VCC (V)
3.5
Guaranteed PLL operation range
(MB90F548GL(S)/543G(S)/547G(S)/548G(S))
Guaranteed PLL operation range
( Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S))
1.5
8
16
Machine clock fCP (MHz)
Document Number: 002- 07696 Rev. *A
Page 44 of 70
MB90540G/545G Series
External clock frequency and Machine clock frequency
×4
×3
×2
×1
16
12
Machine clock
fCP (MHz)
9
8
×1/2
(PLL off)
4
3
4
8
16
External clock fC (MHz)
AC characteristics are set to the measured reference voltage values below.
Output signal waveform
Input signal waveform
Output Pin
Hysteresis Input Pin
0.8 VCC
0.2 VCC
2.4 V
0.8 V
TTL Input Pin
2.0 V
0.8 V
Document Number: 002- 07696 Rev. *A
Page 45 of 70
MB90540G/545G Series
11.4.2 Clock Output Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
62.5
Max
Cycle time
CLK CLK
tCYC
tCHCL
ns
ns
CLK
VCC 5 V 10
20
t
CYC
t
CHCL
2.4 V
2.4 V
CLK
0.8 V
11.4.3 Reset and Hardware Standby Input Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Pin
Parameter
Symbol
Units
ns
Remarks
Under normal operation
In stop mode
name
Min
Max
4 tCP
Oscillation time of
ms
oscillator 4 tCP
In pseudo timer mode (MB90543G
(S) /547G (S) /548G (S) )
100
s
Reset input time
tRSTL
RST
In pseudo timer mode
(Other than MB90543G (S) /547G
(S) /548G (S) )
4 tCP
ns
In sub-clock mode,
sub-sleep mode,
timer mode
2 tLCP
s
Hardware standby input time
tHSTL
HST
4 tCP
ns
Under normal operation
Note : “tcp” represents one cycle time of the machine clock.
Oscillation time of oscillator is time that amplitude reached the 90. In the crystal oscillator, the oscillation time is between
several ms to tens of ms. In ceramic oscillator, the oscillation time is between handreds of s to several ms. In the external
clock, the oscillation time is 0 ns.
Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
Document Number: 002- 07696 Rev. *A
Page 46 of 70
MB90540G/545G Series
In under normal operation, pseudo timer mode, sub-clock mode, sub-sleep mode, timer mode
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
In stop mode
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation clock
4 tCP
Oscillation time of
oscillator
Oscillation setting time
Instruction execution
Internal reset
Document Number: 002- 07696 Rev. *A
Page 47 of 70
MB90540G/545G Series
11.4.4 Power On Reset
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
0.05
50
Max
30
Power on rise time
Power off time
tR
tOFF
VCC
VCC
ms
ms
*
Waiting time until power-on
* : VCC must be kept lower than 0.2 V before power-on.
Notes : The above values are used for creating a power-on reset.
Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power
supply using the above values.
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is
1 V or fewer per second, however, you can use the PLL clock.
VCC
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
3.0 V
RAM data being held
VSS
Document Number: 002- 07696 Rev. *A
Page 48 of 70
MB90540G/545G Series
11.4.5 Bus Timing (Read)
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
ALE pulse width
Symbol
tLHLL
Pin name
ALE
Condition
Units
ns
Remarks
Min
Max
tCP/2 20
ALE,
A16 to A23,
AD00 to AD15
Valid address ALE time
ALE Address valid time
Valid address RD time
tAVLL
tLLAX
tAVRL
tCP/2 20
tCP/2 15
tCP 15
ns
ns
ns
ALE, AD00 to
AD15
A16 toA23,
AD00 to AD15,
RD
Valid address Valid data
input
A16 to A23,
AD00 to AD15
tAVDV
tRLRH
tRLDV
5 tCP/2 60
ns
ns
ns
RD pulse width
RD
3 tCP/2 20
RD, AD00 to
AD15
RD Valid data input
3 tCP/2 60
RD, AD00 to
AD15
RD Data hold time
tRHDX
0
ns
RD ALE time
tRHLH
tRHAX
RD, ALE
tCP/2 15
tCP/2 10
ns
ns
RD Address valid time
RD, A16 to A23
A16 to A23,
AD00 to AD15,
CLK
Valid address CLK time
tAVCH
tCP/2 20
ns
RD CLK time
ALE RD time
tRLCH
tLLRL
RD, CLK
ALE, RD
tCP/2 20
tCP/2 15
ns
ns
Document Number: 002- 07696 Rev. *A
Page 49 of 70
MB90540G/545G Series
Bus Timing (Read)
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
ALE
RD
tLHLL
tAVLL
tRLRH
2.4 V
tLLAX
tLLRL
0.8 V
tAVRL
tRLDV
tRHAX
2.4 V
0.8 V
2.4 V
A16 to A23
0.8 V
tAVDV
tRHDX
2.4 V
2.4 V
0.8 V
0.8 VCC
0.8 VCC
AD00 to AD15
Address
Read data
0.8 V
0.2 VCC
0.2 VCC
Document Number: 002- 07696 Rev. *A
Page 50 of 70
MB90540G/545G Series
11.4.6 Bus Timing (Write)
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
Max
A16 to A23 AD00
to AD15, WR
Valid address WR time
WR pulse width
tAVWL
tWLWH
tDVWH
tCP 15
ns
WR
3 tCP/2 20
3 tCP/2 20
ns
ns
AD00 to AD15,
WR
Valid data output WR time
AD00 to AD15,
WR
WR Data hold time
tWHDX
20
ns
WR Address valid time
WR ALE time
tWHAX
tWHLH
tWLCH
A16 to A23, WR
WR, ALE
tCP/2 10
tCP/2 15
tCP/2 20
ns
ns
ns
WR CLK time
WR, CLK
Bus Timing (Write)
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A16 to A23
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD00 to AD15
Address
Write data
Document Number: 002- 07696 Rev. *A
Page 51 of 70
MB90540G/545G Series
11.4.7 Ready Input Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
Max
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
45
0
ns
ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
Ready Input Timing
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
0.8 VCC
0.8 VCC
RDY
no WAIT is used.
RDY
When WAIT is used
(1 cycle).
0.2 VCC
Document Number: 002- 07696 Rev. *A
Page 52 of 70
MB90540G/545G Series
11.4.8 Hold Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
Max
Pin floating HAK time
HAK time Pin valid time
tXHAL
tHAHV
HAK
HAK
30
tCP
2 tCP
ns
ns
tCP
Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.
Hold Timing
HAK
2.4 V
0.8 V
tXHAL
tHAHV
High impedance
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
11.4.9 UART0/1, Serial I/O Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
tSCYC
Pin name
Condition
Units
ns
Remarks
Min
8 tCP
Max
Serial clock cycle time
SCK0 to SCK2
SCK0 to SCK2,
SOT0 to SOT2
SCK SOT delay time
tSLOV
tIVSH
tSHIX
80
100
60
80
ns
ns
ns
Internal clock operation
output pins are CL 80
pF 1 TTL.
SCK0 to SCK2,
SIN0 to SIN2
Valid SIN SCK
SCK0 to SCK2,
SIN0 to SIN2
SCK Valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0 to SCK2
SCK0 to SCK2
4 tCP
ns
ns
4 tCP
SCK0 to SCK2,
SOT0 to SOT2
SCK SOT delay time
Valid SIN SCK
SCK Valid SIN hold time
Notes :
tSLOV
tIVSH
tSHIX
External clock operation
output pins are CL 80
pF 1 TTL.
150
ns
ns
ns
SCK0 to SCK2,
SIN0 to SIN2
60
60
SCK0 to SCK2,
SIN0 to SIN2
■ AC characteristic in CLK synchronized mode.
■ CL is load capacity value of pins when testing.
■ For tCP (Machine clock cycle time) , refer to “ (1) Clock Timing”.
Document Number: 002- 07696 Rev. *A
Page 53 of 70
MB90540G/545G Series
Internal Shift Clock Mode
SCK
t
SCYC
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOT
SIN
0.8 V
t
IVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Shift Clock Mode
SCK
tSLSH
t
SHSL
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
Document Number: 002- 07696 Rev. *A
Page 54 of 70
MB90540G/545G Series
11.4.10 Timer Input Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
Max
tTIWH
tTIWL
TIN0, TIN1
IN0 to IN7
Input pulse width
4 tCP
ns
Timer Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTIWH
tTIWL
11.4.11 Timer Output Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
Max
TOT0 , TOT1,
PPG0 to PPG3
CLK TOUT change time
tTO
30
ns
Timer Output Timing
2.4 V
CLK
2.4 V
0.8 V
TOUT
t
TO
Document Number: 002- 07696 Rev. *A
Page 55 of 70
MB90540G/545G Series
11.4.12 Trigger Input Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Condition
Units
Remarks
Min
Max
5 tCP
ns
s
Under nomal operation
In stop mode
tTRGH
tTRGL
INT0 to INT7,
ADTG
Input pulse width
1
Trigger Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL
Document Number: 002- 07696 Rev. *A
Page 56 of 70
MB90540G/545G Series
11.5 A/D Converter
11.5.1 Electrical Characteristics
(VCC AVCC 5.0 V10, VSS AVSS 0.0 V, 3.0 V AVRH AVRL, TA 40 C to 105 C)
Value
Parameter
Symbol
Pin name
Units
bit
Remarks
Min
Typ
Max
Resolution
10
Conversion error
Nonlinearity error
5.0
2.5
LSB
LSB
Differential nonlinearity
error
1.9
LSB
V
AVRL 3.5
AVRL 0.5
AVRL 4.5
Zero transition voltage
VOT
AN0 to AN7
AN0 to AN7
LSB
LSB
LSB
AVRH 6.5
AVRH 1.5
AVRH 1.5
Full scale transition voltage
VFST
V
LSB
LSB
LSB
Internal
Compare time
Sampling time
352 tCP
ns
frequency :
16 MHz
Internal
frequency :
16 MHz
64 tCP
ns
VCC AVCC
Analog port input current
Analog input voltage range
IAIN
AN0 to AN7
1
1
A
5.0 V 1
VAIN
IA
AN0 to AN7
AVRH
AVRL
AVRL
5
AVRH
V
AVRL 2.7
0
AVCC
V
Reference voltage range
Power supply current
AVRH 2.7
5
V
AVCC
mA
A
A
A
A
IAH
AVCC
*
400
140
600
260
5
Flash device
MASK ROM
*
IR
AVRH
Reference voltage supply current
IRH
AVRH
Offset between input
channels
AN0 to AN7
4
LSB
* : When not using an A/D converter, this is the current (VCC AVCC AVRH 5.0 V) when the CPU is stopped.
Note: The functionality of the A/D converter is only guaranteed for VCC 5.0 V 10 (also for MB90543G(S)/547G(S)/548G(S)/
F548G(S)/F548GL(S)).
Document Number: 002- 07696 Rev. *A
Page 57 of 70
MB90540G/545G Series
11.5.2 A/D Converter Glossary
Resolution :
Analog changes that are identifiable with the A/D converter
Linearity error :
The deviation of the straight line connecting the zero transition point (“00 0000 0000” “00 0000
0001”) with the full-scale transition point (“11 1111 1110” “11 1111 1111”) from actual conversion
characteristics
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
Total error :
The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
0.5 LSB
Actual conversion
Value
3FE
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
V
NT
(measured value)
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
AVRL
AVRH
Analog input
AVRH AVRL
1 LSB (Theoretical value)
[V]
1024
VOT (Theoretical value) AVRL 0.5 LSB [V]
VFST (Theoretical value) AVRH 1.5 LSB [V]
VNT {1 LSB (N 1) 0.5 LSB}
Total error for digital output N
[LSB]
1 LSB
VNT : Voltage at a transition of digital output from (N 1) to N
(Continued)
Document Number: 002- 07696 Rev. *A
Page 58 of 70
MB90540G/545G Series
(Continued)
Linearity error
Differential linearity error
Theorential characteristics
3FF
3FE
3FD
Actual conversion
value
N + 1
{1 LSB × (N − 1) + VOT }
Actual conversion value
VFST
(measured value)
N
VNT
004
003
002
001
V (N + 1) T
Actual conversion
characteristics
(measured value)
N − 1
N − 2
VNT (measured value)
Theoretical
characteristics
Acturel conversion
value
(measured value)
VOT
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
Linearity error of
digital output N
VNT {1 LSB (N 1) VOT}
[LSB]
1 LSB
Differential linearity error
of digital N
V (N
1) T VNT
1 LSB [LSB]
1 LSB
VFST VOT
1 LSB
[V]
1022
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
11.5.3 Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions, :
Output impedance values of the external circuit of 15 k or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is
recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor.
Note : When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient
(sampling period 4.00 s @machine clock of 16 MHz) .
Equipment of analog input circuit model
Comparator
3.2 kΩ Max
Analog input
30 pF Max
11.5.4 Error
The smaller the | AVRH AVRL |, the greater the error would become relatively.
Document Number: 002- 07696 Rev. *A
Page 59 of 70
MB90540G/545G Series
11.6 Flash Memory Program/Erase Characteristics
Value
Parameter
Condition
Units
Remarks
Min
Typ
Max
Sector erase time
1
5
7
15
s
Excludes 00H programming prior erasure
MB90F543G (S) /F548G (S)
/F548GL (S)
Excludes 00H
programming
prior erasure
s
Chip erase time
TA 25 C
VCC 5.0 V
s
MB90F549G (S) /F546G (S)
Word (16 bit width)
programming time
16
3,600
s
Excludes system-level overhead
Erase/Program cycle
10,000
cycle
Document Number: 002- 07696 Rev. *A
Page 60 of 70
MB90540G/545G Series
12. Example Characteristics
“H” level output voltage
“L” level output voltage
VOL – IOL
(VCC = 4.5 V,Ta = +25˚C)
VOH – IOH
(VCC = 4.5 V, Ta = +25˚C)
5
4.5
4
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5
3
2.5
2
1.5
1
0.5
0
0
-2
-4
-6
-8
-10
2
4
6
8
10
0
IOL [mA]
IOH [mA]
“H” level input voltage/ “L” level input voltage
(Hysterisis inpiut)
Vin – Vcc
(Ta = +25˚C)
5
4
3
2
1
0
VIH
VIL
3
3.5
4
4.5
5
5.5
6
6.5
Document Number: 002- 07696 Rev. *A
Page 61 of 70
MB90540G/545G Series
Power supply current (MB90549G)
Icc – Vcc
Iccs – Vcc
(Ta = +25˚C)
(Ta = +25˚C)
fcp = 16 MHz
12
10
8
40
35
30
25
20
15
10
5
fcp = 16 MHz
fcp = 12 MHz
fcp = 12 MHz
fcp = 10 MHz
fcp = 8 MHz
fcp = 10 MHz
fcp = 8 MHz
6
4
fcp = 4 MHz
fcp = 2 MHz
fcp = 4 MHz
fcp = 2 MHz
2
0
0
2
3
4
5
6
7
2
3
4
5
6
7
Vcc [V]
Vcc [V]
ICTS – VCC
ICCL – VCC
(Ta = +25˚C)
(Ta = +25˚C)
600
500
400
300
200
100
0
100
90
80
70
60
50
40
30
20
10
0
fcp = 2 MHz
fcp = 8 kHz
2
3
4
5
6
7
2
3
4
5
6
7
Vcc [V]
Vcc [V]
Document Number: 002- 07696 Rev. *A
Page 62 of 70
MB90540G/545G Series
ICCLS – VCC
ICCT – VCC
(Ta = +25˚C)
(Ta = +25˚C)
40
35
30
25
20
15
10
5
25
20
15
10
5
fcp = 8 kHz
fcp = 8 kHz
0
0
7
7
2
3
4
5
6
2
3
4
5
6
Vcc [V]
Vcc [V]
ICCH2 – VCC
(hardware standby, Ta = +25 ˚C)
ICCH1 – VCC
(STOP, Ta = +25 ˚C)
100
90
85
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
2
3
4
5
6
7
2
3
4
5
6
7
VCC [V]
VCC [V]
Document Number: 002- 07696 Rev. *A
Page 63 of 70
MB90540G/545G Series
Power supply current (MB90F549G)
Iccs – Vcc
Icc – Vcc
(Ta = +25 ˚C)
(Ta = +25 ˚C)
fcp = 16 MHz
14
12
10
8
45
fcp = 16 MHz
40
35
30
25
20
15
10
5
fcp = 12 MHz
fcp = 12 MHz
fcp = 10 MHz
fcp = 8 MHz
fcp = 10 MHz
fcp = 8 MHz
6
fcp = 4 MHz
fcp = 2 MHz
fcp = 4 MHz
fcp = 2 MHz
4
2
0
0
7
2
3
4
5
6
2
3
4
5
6
7
VCC [V]
VCC [V]
ICTS – VCC
ICCL – VCC
(Ta = +25 ˚C)
(Ta = +25 ˚C)
300
600
250
200
150
100
50
500
400
300
200
100
0
fcp = 2 MHz
fcp = 8 kHz
0
2
3
4
5
6
7
2
3
4
5
6
7
VCC [V]
VCC [V]
Document Number: 002- 07696 Rev. *A
Page 64 of 70
MB90540G/545G Series
ICCLS – VCC
ICCT – VCC
(Ta = +25 ˚C)
(Ta = +25 ˚C)
25
20
15
10
5
45
40
35
30
25
20
15
10
5
fcp = 8 MHz
fcp = 8 MHz
0
0
2
3
4
5
6
7
2
3
4
5
6
7
VCC [V]
VCC [V]
ICCH1 – VCC
(STOP, Ta = +25 ˚C)
ICCH2 – VCC
(hardware standby, Ta = +25 ˚C)
20
100
90
85
70
60
50
40
30
20
10
0
18
16
14
12
10
8
6
4
2
0
2
3
4
5
6
7
2
3
4
5
6
7
VCC [V]
VCC [V]
Document Number: 002- 07696 Rev. *A
Page 65 of 70
MB90540G/545G Series
13. Ordering Information
Part number
Package
Remarks
MB90F543GPF
MB90F543GSPF
MB90F546GPF
MB90F546GSPF
MB90F548GPF
MB90F548GSPF
MB90F548GLPF
MB90F548GLSPF
MB90F549GPF
100-pinPlastic QFP
(FPT-100P-M06)
MB90F549GSPF
MB90543GPF
MB90543GSPF
MB90547GPF
MB90547GSPF
MB90548GPF
MB90548GSPF
MB90549GPF
MB90549GSPF
MB90F543GPMC
MB90F543GSPMC
MB90F546GPMC
MB90F546GSPMC
MB90F548GPMC
MB90F548GSPMC
MB90F548GLPMC
MB90F548GLSPMC
MB90F549GPMC
MB90F549GSPMC
MB90543GPMC
100-pinPlastic LQFP
(FPT-100P-M20)
MB90543GSPMC
MB90547GPMC
MB90547GSPMC
MB90548GPMC
MB90548GSPMC
MB90549GPMC
MB90549GSPMC
Document Number: 002- 07696 Rev. *A
Page 66 of 70
MB90540G/545G Series
14. Package Dimensions
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90 0.40(.941 .016)
*
20.00 0.20(.787 .008)
80
51
81
50
0.10(.004)
17.90 0.40
(.705 .016)
*
14.00 0.20
(.551 .008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 –+00..2305
.118 +–..000184
(Mounting height)
0~8
˚
1
30
0.65(.026)
0.32 0.05
(.013 .002)
0.17 0.06
(.007 .002)
M
0.13(.005)
0.25 0.20
(.010 .008)
(Stand off)
0.80 0.20
(.031 .008)
"A"
0.88 0.15
(.035 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
2002 FUJITSU LIMITED F100008S-c-5-5
(Continued)
Document Number: 002- 07696 Rev. *A
Page 67 of 70
MB90540G/545G Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*
14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
–
0.10 .059 +.008
–.004
INDEX
(Mounting height)
0.10 0.10
(.004 .004)
(Stand off)
100
26
0˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60 0.15
(.024 .006)
1
25
0.50(.020)
0.20 0.05
(.008 .002)
0.145 0.055
(.0057 .0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2
2005 FUJITSU LIMITED F100031S-c-2-1
Document Number: 002- 07696 Rev. *A
Page 68 of 70
MB90540G/545G Series
15. Major Changes
Spansion Publication Number: DS07-13703-7E
Section
Change Results
Changed the name in peripheral resource.
■ PRODUCT LINEUP
16-bit I/O Timer 16-bit Free-run Timer
■ I/O CIRCUIT TYPE
■ BLOCK DIAGRAM
Changed the name of input typ.
Hysteresis CMOS Hysteresis
HYS CMOS Hysteresis
Changed the arrow direction of SOT1 signal at UART1(SCI).
“ ” (input/output) “” (output)
■ I/O MAP
Changed the text of “Note”.
■ INTERRUPT MAP
Changed the name of peripheral resource of the pin number: #19.
I/O Timer 16-bit Free-run Timer
■ ELECTRICAL CHARACTERISTICS
Changed the remarks of “parameter: Power supply voltage”.
2. Recommended Conditions
3. DC Characteristics
Changed the maximum value of symbol : VILM of parameter: Input voltage.
VCC + 0.3 VSS + 0.3
Added the following remarks for parameter : Pull-down resistance.
Except Flash device
4. AC Characteristics
(1) Clock Timing
Added the value when using an external clock in Oscillation frequency and
Clock cycle time on (1) Clock Timing for parameter.
Added the item of A/D converter operation range in figure of “ Guaranteed
PLL operation range”
(3) Reset and Hardware Standby Input Timing
Changed the following item.
(3) Reset and Hardware Standby Input Timing Remarks:
In sub-clock mode, sub-sleep mode, timer mode
2tCP 2tLCP
(4) Power On Reset
Changed as follows;
Due to repetitive operation Waiting time until power-on
5. A/D Converter
Changed the unit of Zero transition voltage and Full scale transition voltage.
mV V
■ ORDERING INFORMATION
Added the MB90F548GLPMC in Part Numbers.
NOTE: Please see “Document History” about later revised information.
Document History
Document Title: MB90F543G(S)/546G(S)/548G(S)/549G(S)/549G(S)/V540G/MB90543G(S)/547G(S)/548G(S)/F548GL(S)
CMOS F2MC-16LX MB90540G/545G Series 16-bit Proprietary Microcontroller
Document Number: 002-07696
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
AKIH
11/13/2008 Migrated to Cypress and assigned document number 002-07696.
No change to document contents or format.
*A
5537115
AKIH
11/30/2016 Updated to Cypress template
Document Number: 002- 07696 Rev. *A
Page 69 of 70
MB90540G/545G Series
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
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Document Number: 002-07696 Rev. *A
Revised November 30, 2016
Page 70 of 70
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