MB95F478KPMC2-G-SNE2 [CYPRESS]
Microcontroller, 8-Bit, FLASH, F2MC-8 CPU, 16.25MHz, CMOS, PQFP64,;
| 型号： | MB95F478KPMC2-G-SNE2 |
| 厂家： | 
CYPRESS |
| 描述： | Microcontroller, 8-Bit, FLASH, F2MC-8 CPU, 16.25MHz, CMOS, PQFP64, 微控制器 外围集成电路 |
| 文件： | 总85页 (文件大小：3006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB95410H/470H Series
New 8FX 8-bit Microcontrollers
MB95410H/470H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of this series contain a variety of peripheral resources.
Features
2
F MC-8FX CPU core
8/10-bit A/D converter
Instruction set optimized for controllers
■ 8-bit or 10-bit resolution can be selected
■ Multiplication and division instructions
■ 16-bit arithmetic operations
LCD controller (LCDC)
■ On MB95F414H/F414K/F416H/F416K/F418H/F418K, LCD
output can be selected from 40 SEG 4 COM to 36 SEG
8 COM.
■ Bit test branch instructions
■ Bit manipulation instructions, etc.
■ On MB95F474H/F474K/F476H/F476K/F478H/F478K, LCD
output can be selected from 32 SEG 4 COM to 28 SEG
8 COM.
Clock
■ Selectable main clock source
■ Internal divider resistor whose resistancevalue canbeselected
from 10 k or 100 k through software
❐ Main OSC clock (up to 16.25 MHz, maximum machine clock
frequency: 8.125 MHz)
❐ External clock (up to 32.5 MHz, maximum machine clock
■ Interrupt in sync with the LCD module frame frequency
■ Blinking function
frequency: 16.25 MHz)
❐ Main CR clock (1/8/10/12.5 MHz 2%, maximum machine
clock frequency: 12.5 MHz)
❐ Main PLL clock (up to 16.25 MHz, maximum machine clock
frequency: 16.25 MHz)
■ Inverted display function
Low power consumption (standby) modes
■ Stop mode
■ Selectable subclock source
❐ Sub-OSC clock (32.768 kHz)
❐ External clock (32.768 kHz)
■ Sleep mode
❐ Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
■ Watch mode
Timer
■ Time-base timer mode
■ 8/16-bit composite timer 2 channels
■ 8/16-bit PPG 2 channels
■ 16-bit reload timer 1 channel
■ Event counter 1 channel
■ Time-base timer 1 channel
■ Watch prescaler 1 channel
I/O port
■ MB95F414H/F416H/F418H (maximum no. of I/O ports: 74)
❐ General-purpose I/O ports (N-ch open drain)
❐ General-purpose I/O ports (CMOS I/O)
: 3
: 71
■ MB95F414K/F416K/F418K (maximum no. of I/O ports: 75)
❐ General-purpose I/O ports (N-ch open drain)
❐ General-purpose I/O ports (CMOS I/O)
: 4
: 71
■ MB95F474H/F476H/F478H (maximum no. of I/O ports: 58)
UART-SIO
❐ General-purpose I/O ports (N-ch open drain)
❐ General-purpose I/O ports (CMOS I/O)
: 3
: 55
■ Capable of clock-asynchronous (UART) serial data transfer
and clock-synchronous (SIO) serial data transfer
■ MB95F474K/F476K/F478K (maximum no. of I/O ports: 59)
■ Full duplex double buffer
❐ General-purpose I/O ports (N-ch open drain)
❐ General-purpose I/O ports (CMOS I/O)
: 4
: 55
2
I C
Built-in wake-up function
On-chip debug
External interrupt
■ 1-wire serial control
■ Interrupt by edge detection (rising edge, falling edge, and both
■ Serial writing supported (asynchronous mode)
edges can be selected)
Hardware/software watchdog timer
■ Built-in hardware watchdog timer
■ Built-in software watchdog timer
■ Can be used to wake up the device from different low power
consumption (standby) modes
Cypress Semiconductor Corporation
Document Number: 002-07475 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 4, 2016
MB95410H/470H Series
Low-voltage detection reset circuit
Dual operation Flash memory
Built-in low-voltage detector
The program/erase operation and the read operation can be
executed in different banks (upper bank/lower bank) simultane-
ously.
Clock supervisor counter
Built-in clock supervisor counter function
Flash memory security function
Programmable port input voltage level
Protects the content of the Flash memory
CMOS input level / hysteresis input level
Document Number: 002-07475 Rev. *A
Page 2 of 85
MB95410H/470H Series
Contents
Product Line-up ................................................................4
Oscillation Stabilization Wait Time .................................8
Packages And Corresponding Products ........................8
Differences among Products and Notes
I/O Map (MB95470H Series) ...........................................39
Interrupt Source Table ...................................................45
Electrical Characteristics ...............................................46
Absolute Maximum Ratings .......................................46
Recommended Operating Conditions .......................48
DC Characteristics ....................................................49
AC Characteristics .....................................................53
A/D Converter ............................................................67
Flash Memory Program/Erase Characteristics ..........71
Sample Characteristics ..................................................72
Mask Options ..................................................................78
Ordering Information ......................................................79
Package Dimension ........................................................80
Major Changes ................................................................83
Document History ...........................................................84
on Product Selection ........................................................9
Pin Assignment ..............................................................10
Pin Description (MB95410H Series) ..............................12
Pin Description (MB95470H Series) ..............................18
I/O Circuit Type ...............................................................23
Notes on Device Handling .............................................28
Pin Connection ...............................................................28
Block Diagram (MB95410H Series) ...............................30
Block Diagram (MB95470H Series) ...............................31
CPU Core .........................................................................32
I/O Map (MB95410H Series) ...........................................33
Document Number: 002-07475 Rev. *A
Page 3 of 85
MB95410H/470H Series
1. Product Line-up
MB95410H Series
Part number
MB95F414H
MB95F416H
MB95F418H
MB95F414K
MB95F416K
MB95F418K
Package
Type
Flash memory product
Clock supervisor
counter
It supervises the main clock oscillation.
Program ROM
capacity
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
No
60 Kbyte
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
Yes
60 Kbyte
RAM capacity
2032 bytes
2032 bytes
Low-voltage
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time
• Interrupt processing time
: 61.5 ns (machine clock frequency = 16.25 MHz)
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max)
• CMOS I/O
• N-ch open drain : 3
: 74
: 71
• I/O ports (Max)
• CMOS I/O
• N-ch open drain
: 75
: 71
: 4
General-purpose
I/O
Time-base timer
Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
• The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Hardware/software
watchdog timer
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
I2C
• Bus error function and arbitration function
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
3 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error
detection function.
UART/SIO
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer is enabled.
8 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
(Continued)
Document Number: 002-07475 Rev. *A
Page 4 of 85
MB95410H/470H Series
(Continued)
Part number
MB95F414H
MB95F416H
MB95F418H
MB95F414K
MB95F416K
MB95F418K
Package
2 channels
• Each timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit composite
timer
• COM output: 4 or 8 (selectable)
• SEG output: 36 or 40 (selectable)
- If the number of COM outputs is 4, the maximum number of SEG outputs is 40, and the maximum number
of pixels that can be displayed 160 (440).
- If the number of COM outputs is 8, the maximum number of SEG outputs is 36, and the maximum number
of pixels that can be displayed 288 (836).
LCD controller
(LCDC)
• LCD drive power supply (bias) pins: 5 (Max)
• Duty LCD mode
• LCD standby mode
• Blinking function
• Internal divider resistor whose resistance value can be selected from 10 k or 100 k through software
• Interrupt in sync with the LCD module frame frequency
• Inverted display function
1 channel
• Two clock modes and two counter operating modes can be selected
• Square waveform output
16-bit reload timer
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter function can be
implemented. When the event counter function is used, the 16-bit reload timer and the 8/16-bit composite timer
ch. 1 are unavailable.
Event counter
8/16-bit PPG
2 channels
• Each channel of the PPG can be used as “8-bit PPG 2 channels” or “16-bit PPG 1 channel”
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
• Counter value can be set from 0 to 63. (Capable of counting for 1 minute when the clock source is 1 second
and the counter value is to 60)
Watch counter
External interrupt
8 channels
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
• It supports serial writing. (asynchronous mode)
On-chip debug
Watch prescaler
Eight different time intervals can be selected.
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/erase-resume
commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Number of program/erase cycles: 100000
Flash memory
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode
Package
Sleep mode, stop mode, watch mode, time-base timer mode
FPT-80P-M37
Document Number: 002-07475 Rev. *A
Page 5 of 85
MB95410H/470H Series
MB95470H Series
Part number
MB95F474H
MB95F476H
MB95F478H
MB95F474K
MB95F476K
MB95F478K
Package
Type
Flash memory product
Clock supervisor
counter
It supervises the main clock oscillation.
Program ROM
capacity
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
No
60 Kbyte
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
Yes
60 Kbyte
RAM capacity
2032 bytes
2032 bytes
Low-voltage
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time
• Interrupt processing time
: 61.5 ns (machine clock frequency = 16.25 MHz)
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max)
• CMOS I/O
• N-ch open drain
: 58
: 55
: 3
• I/O ports (Max)
• CMOS I/O
• N-ch open drain : 4
: 59
: 55
General-purpose
I/O
Time-base timer
Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
• The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Hardware/software
watchdog timer
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
I2C
• Bus error function and arbitration function
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
3 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error
detection function.
UART/SIO
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer is enabled.
8 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
2 channels
• Each timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit composite
timer
(Continued)
Document Number: 002-07475 Rev. *A
Page 6 of 85
MB95410H/470H Series
(Continued)
Part number
MB95F474H
MB95F476H
MB95F478H
MB95F474K
MB95F476K
MB95F478K
Package
• COM output: 4 or 8 (selectable)
• SEG output: 28 or 32 (selectable)
- If the number of COM outputs is 4, the maximum number of SEG outputs is 32, and the maximum number
of pixels that can be displayed 128 (432).
- If the number of COM outputs is 8, the maximum number of SEG outputs is 28, and the maximum number
of pixels that can be displayed 224 (828).
• LCD drive power supply (bias) pins: 4 (Max)
LCD controller
(LCDC)
• Duty LCD mode
• LCD standby mode
• Blinking function
• Internal divider resistor whose resistance value can be selected from 10 k or 100 k through software
• Inverted display function
1 channel
• Two clock modes and two counter operating modes can be selected
• Square waveform output
16-bit reload timer
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter function can be
implemented. When the event counter function is used, the 16-bit reload timer and the 8/16-bit composite timer
ch. 1 are unavailable.
Event counter
8/16-bit PPG
2 channels
• Each channel of the PPG can be used as “8-bit PPG 2 channels” or “16-bit PPG 1 channel“
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
• Counter value can be set from 0 to 63. (Capable of counting for 1 minute when the clock source is 1 second
and the counter value is to 60)
Watch counter
External interrupt
8 channels
Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
It can be used to wake up the device from the standby mode.
• 1-wire serial control
• It supports serial writing. (asynchronous mode)
On-chip debug
Watch prescaler
Eight different time intervals can be selected.
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/erase-resume
commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Number of program/erase cycles: 100000
Flash memory
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode
Package
Sleep mode, stop mode, watch mode, time-base timer mode
FPT-64P-M38
FPT-64P-M39
Document Number: 002-07475 Rev. *A
Page 7 of 85
MB95410H/470H Series
2. Oscillation Stabilization Wait Time
The main CR clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum value.
Oscillation stabilization wait time
Remarks
(210 2) / FCRH
Approx. 128 µs (when the main CR clock is 8 MHz)
The main PLL clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum value.
Oscillation stabilization wait time
Remarks
(214 2) / FCH
Approx. 14.1 ms (when the main PLL clock is 4 MHz)
3. Packages And Corresponding Products
Part number
MB95F414H
MB95F474H
MB95F416H
MB95F418H
MB95F414K
MB95F474K
MB95F416K
MB95F476K
MB95F418K
MB95F478K
Package
FPT-80P-M37
O
Part number
MB95F476H
MB95F478H
Package
FPT-64P-M38
FPT-64P-M39
O
O
O: Available
Document Number: 002-07475 Rev. *A
Page 8 of 85
MB95410H/470H Series
4. Differences among Products and Notes on Product Selection
Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “17. Electrical Characteristics”.
Package
For details of information on each package, see “3. Packages And Corresponding Products” and “21. Package Dimension”.
Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “17. Electrical Characteristics”.
On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For details of the connection
method, refer to “Chapter 31 Example Of Serial Programming Connection” in the hardware manual of the MB95410H/470H Series.
Document Number: 002-07475 Rev. *A
Page 9 of 85
MB95410H/470H Series
5. Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVcc
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P60/SEG10
PC7/SEG09
PC6/SEG08
PC5/SEG07
PC4/SEG06
PC3/SEG05
PC2/SEG04
PC1/SEG03
PC0/SEG02
PB1/SEG01
PB0/SEG00
P17/CMPO
PF2/RST
Vcc
P07/INT07/AN07/SEG30
P06/INT06/AN06/SEG31
P05/INT05/AN05/SEG32/UCK1
P04/INT04/AN04/SEG33/UI1
P03/INT03/AN03/SEG34/UO1
P02/INT02/AN02/SEG35/UCK2
P01/INT01/AN01/SEG36/UI2
P00/INT00/AN00/UO2
P16/PPG10
3
4
5
6
7
8
(TOP VIEW)
MB95410H Series
9
10
11
12
13
14
15
16
17
18
19
20
P15/PPG11
(FPT-80P-M37)
P14/UCK0
P13/ADTG
P12/DBG
P11/UO0
PG1/X0A
PG2/X1A
C
P10/UI0
P53/TO0
P52/TI0/TO00
PF0/X0
P51/EC0
PF1/X1
P50/TO01
Vss
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(Continued)
Document Number: 002-07475 Rev. *A
Page 10 of 85
MB95410H/470H Series
(Continued)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc
P07/INT07/AN07/SEG22
P06/INT06/AN06/SEG23
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P60/SEG06
PC3/SEG05
PC2/SEG04
PC1/SEG03
PC0/SEG02
PB1/SEG01
PB0/SEG00
P17/CMPO
PF2/RST
Vcc
3
P05/INT05/AN05/SEG24/UCK1
P04/INT04/AN04/SEG25/UI1
P03/INT03/AN03/SEG26/UO1
P02/INT02/AN02/SEG27/UCK2
P01/INT01/AN01/SEG28/TO00/UI2
P00/INT00/AN00/SEG29/UO2
P16/SEG30/PPG10
4
5
6
(TOP VIEW)
MB95470H Series
7
8
9
(FPT-64P-M38)
(FPT-64P-M39)
10
11
12
13
14
15
16
P15/SEG31/PPG11
PG1/X0A
PG2/X1A
C
P14/UCK0/EC0/TI0
P13/ADTG/TO01
P12/DBG
PF0/X0
P11/UO0
PF1/X1
P10/UI0/TO0
Vss
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Document Number: 002-07475 Rev. *A
Page 11 of 85
MB95410H/470H Series
6. Pin Description (MB95410H Series)
Pin no.
Pin name
AVCC
P07
I/O circuit type*
Function
1
—
A/D converter power supply pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT07
AN07
SEG30
P06
2
3
S
S
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT06
AN06
SEG31
P05
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT05
AN05
SEG32
UCK1
P04
4
5
6
7
8
S
V
S
S
V
LCDC SEG output pin
UART/SIO ch. 1 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT04
AN04
SEG33
UI1
LCDC SEG output pin
UART/SIO ch. 1 data input pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P03
INT03
AN03
SEG34
UO1
LCDC SEG output pin
UART/SIO ch. 1 data output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P02
INT02
AN02
SEG35
UCK2
P01
LCDC SEG output pin
UART/SIO ch. 2 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT01
AN01
SEG36
UI2
LCDC SEG output pin
UART/SIO ch. 2 data input pin
(Continued)
Document Number: 002-07475 Rev. *A
Page 12 of 85
MB95410H/470H Series
Pin no.
Pin name
P00
I/O circuit type*
Function
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT00
AN00
UO2
P16
9
W
UART/SIO ch. 2 data output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
General-purpose I/O port
A/D trigger input (ADTG) pin
General-purpose I/O port
DBG input pin
10
11
12
13
14
15
16
17
Y
Y
H
H
D
H
G
H
PPG10
P15
PPG11
P14
UCK0
P13
ADTG
P12
DBG
P11
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
16-bit reload timer output pin
General-purpose I/O port
16-bit reload timer input pin
UO0
P10
UI0
P53
TO0
P52
18
TI0
H
TO00
P51
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
19
20
21
22
H
H
I
EC0
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
I2C data I/O pin
P50
TO01
P23
SDA
P22
General-purpose I/O port
I2C clock I/O pin
I
SCL
P21
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
23
24
PPG01
CMPP
P20
T
T
PPG00
CMPN
(Continued)
Document Number: 002-07475 Rev. *A
Page 13 of 85
MB95410H/470H Series
Pin no.
Pin name
P90
I/O circuit type*
Function
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC SEG output pin
25
R
V4
P91
26
27
28
29
30
31
32
33
34
35
36
37
38
39
R
R
V3
P92
V2
P93
R
V1
P94
R
V0
PB2
M
M
M
M
M
M
M
M
M
M
SEG37
PB3
General-purpose I/O port
LCDC SEG output pin
SEG38
PB4
General-purpose I/O port
LCDC SEG output pin
SEG39
PA0
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
Power supply pin (GND)
General-purpose I/O port
Main clock oscillation pin
General-purpose I/O port
Main clock oscillation pin
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PA4
COM4
PA5
COM5
PA6
COM6
PA7
40
41
42
M
—
B
COM7
VSS
PF1
X1
PF0
43
B
X0
(Continued)
Document Number: 002-07475 Rev. *A
Page 14 of 85
MB95410H/470H Series
Pin no.
Pin name
C
I/O circuit type*
Function
44
—
Capacitor connection pin
General-purpose I/O port
Subclock oscillation pin (32 kHz)
General-purpose I/O port
Subclock oscillation pin (32 kHz)
Power supply pin
PG2
X1A
PG1
X0A
VCC
45
C
46
47
C
—
PF2
General-purpose I/O port
48
A
Reset pin
RST
Dedicate reset pin for MB95F414H/F416H/F418H
General-purpose I/O port
Voltage comparator output pin
General-purpose I/O port
LCDC SEG output pin
P17
CMPO
PB0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
H
M
M
M
M
M
M
M
M
M
M
M
M
M
SEG00
PB1
General-purpose I/O port
LCDC SEG output pin
SEG01
PC0
General-purpose I/O port
LCDC SEG output pin
SEG02
PC1
General-purpose I/O port
LCDC SEG output pin
SEG03
PC2
General-purpose I/O port
LCDC SEG output pin
SEG04
PC3
General-purpose I/O port
LCDC SEG output pin
SEG05
PC4
General-purpose I/O port
LCDC SEG output pin
SEG06
PC5
General-purpose I/O port
LCDC SEG output pin
SEG07
PC6
General-purpose I/O port
LCDC SEG output pin
SEG08
PC7
General-purpose I/O port
LCDC SEG output pin
SEG09
P60
General-purpose I/O port
LCDC SEG output pin
SEG10
P61
General-purpose I/O port
LCDC SEG output pin
SEG11
P62
General-purpose I/O port
LCDC SEG output pin
SEG12
(Continued)
Document Number: 002-07475 Rev. *A
Page 15 of 85
MB95410H/470H Series
Pin no.
Pin name
P63
I/O circuit type*
Function
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
63
M
SEG13
P64
64
65
66
67
68
69
70
71
72
73
74
75
76
M
M
M
M
M
M
M
M
M
M
M
M
M
SEG14
P65
SEG15
P66
SEG16
P67
SEG17
P43
SEG18
P42
SEG19
P41
SEG20
P40
SEG21
PE0
SEG22
PE1
SEG23
PE2
SEG24
PE3
SEG25
PE4
SEG26
PE5
77
78
SEG27
TO11
PE6
M
M
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
SEG28
TO10
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
(Continued)
Document Number: 002-07475 Rev. *A
Page 16 of 85
MB95410H/470H Series
(Continued)
Pin no.
Pin name
PE7
I/O circuit type*
Function
General-purpose I/O port
LCDC SEG output pin
79
80
SEG29
EC1
M
8/16-bit composite timer ch. 1 clock input pin
A/D converter power supply pin (GND)
AVSS
—
*: For the I/O circuit types, see “8. I/O Circuit Type”.
Document Number: 002-07475 Rev. *A
Page 17 of 85
MB95410H/470H Series
7. Pin Description (MB95470H Series)
Pin no.
Pin name
AVCC
P07
I/O circuit type*
Function
1
—
A/D converter power supply pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT07
AN07
SEG22
P06
2
3
S
S
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT06
AN06
SEG23
P05
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT05
AN05
SEG24
UCK1
P04
4
5
6
7
S
V
S
S
LCDC SEG output pin
UART/SIO ch. 1 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT04
AN04
SEG25
UI1
LCDC SEG output pin
UART/SIO ch. 1 data input pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P03
INT03
AN03
SEG26
UO1
LCDC SEG output pin
UART/SIO ch. 1 data output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P02
INT02
AN02
SEG27
UCK2
P01
LCDC SEG output pin
UART/SIO ch. 2 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT01
AN01
SEG28
TO00
UI2
8
V
LCDC SEG output pin
8/16-bit composite timer ch. 0 output pin
UART/SIO ch. 2 data input pin
(Continued)
Document Number: 002-07475 Rev. *A
Page 18 of 85
MB95410H/470H Series
Pin no.
Pin name
P00
I/O circuit type*
Function
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT00
AN00
SEG29
UO2
9
S
LCDC SEG output pin
UART/SIO ch. 2 data output pin
General-purpose I/O port
LCDC SEG output pin
P16
10
11
SEG30
PPG10
P15
M
M
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
LCDC SEG output pin
SEG31
PPG11
P14
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
UCK0
EC0
12
13
H
H
8/16-bit composite timer ch. 0 clock input pin
16-bit reload timer input pin
General-purpose I/O port
A/D trigger input (ADTG) pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
DBG input pin
TI0
P13
ADTG
TO01
P12
14
15
D
H
DBG
P11
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
16-bit reload timer output pin
General-purpose I/O port
I2C data I/O pin
UO0
P10
16
UI0
G
TO0
P23
17
18
I
I
SDA
P22
General-purpose I/O port
I2C clock I/O pin
SCL
P21
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
19
20
PPG01
CMPP
P20
T
T
PPG00
CMPN
(Continued)
Document Number: 002-07475 Rev. *A
Page 19 of 85
MB95410H/470H Series
Pin no.
Pin name
P90
I/O circuit type*
Function
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
Power supply pin (GND)
General-purpose I/O port
Main clock oscillation pin
General-purpose I/O port
Main clock oscillation pin
Capacitor connection pin
General-purpose I/O port
Subclock oscillation pin (32 kHz)
General-purpose I/O port
Subclock oscillation pin (32 kHz)
Power supply pin
21
R
V4
P91
22
23
24
25
26
27
28
29
30
31
R
R
V3
P92
V2
P93
R
V1
PA0
M
M
M
M
M
M
M
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PA4
COM4
PA5
COM5
PA6
COM6
PA7
32
33
34
M
—
B
COM7
VSS
PF1
X1
PF0
X0
35
36
37
B
—
C
C
PG2
X1A
PG1
X0A
VCC
PF2
38
39
C
—
General-purpose I/O port
40
A
Reset pin
RST
Dedicated reset pin for MB95F474H/F476H/F478H
(Continued)
Document Number: 002-07475 Rev. *A
Page 20 of 85
MB95410H/470H Series
Pin no.
Pin name
P17
I/O circuit type*
Function
General-purpose I/O port
Voltage comparator output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
41
H
CMPO
PB0
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
SEG00
PB1
SEG01
PC0
SEG02
PC1
SEG03
PC2
SEG04
PC3
SEG05
P60
SEG06
P61
SEG07
P62
SEG08
P63
SEG09
P64
SEG10
P65
SEG11
P66
SEG12
P67
SEG13
PE0
SEG14
PE1
SEG15
(Continued)
Document Number: 002-07475 Rev. *A
Page 21 of 85
MB95410H/470H Series
(Continued)
Pin no.
Pin name
PE2
I/O circuit type*
Function
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
58
59
60
M
SEG16
PE3
M
M
SEG17
PE4
SEG18
PE5
61
62
SEG19
TO11
PE6
M
M
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
SEG20
TO10
PE7
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
63
64
SEG21
EC1
M
LCDC SEG output pin
8/16-bit composite timer ch. 1 clock input pin
A/D converter power supply pin (GND)
AVSS
—
*: For the I/O circuit types, see “8. I/O Circuit Type”.
Document Number: 002-07475 Rev. *A
Page 22 of 85
MB95410H/470H Series
8. I/O Circuit Type
Type
Circuit
Remarks
• N-ch open drain output
• Hysteresis input
• Reset output
Reset input / Hysteresis input
Reset output / Digital output
A
N-ch
Port select
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
Clock input
X1
B
X0
• CMOS output
• Hysteresis input
Standby control / Port select
P-ch
Port select
Digital output
Digital output
N-ch
Standby control
Hysteresis input
Port select
R
Pull-up control
P-ch
N-ch
P-ch
Digital output
Digital output
Standby control
Hysteresis input
• Oscillation circuit
Clock input
• Low-speed side
Feedback resistance: approx. 10 MΩ
X1A
X0A
C
• CMOS output
• Hysteresis input
• Pull-up control available
Standby control / Port select
Port select
R
Pull-up control
Digital output
N-ch
P-ch
Digital output
Digital output
Standby control
Hysteresis input
(Continued)
Document Number: 002-07475 Rev. *A
Page 23 of 85
MB95410H/470H Series
Type
Circuit
Remarks
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
D
Digital output
N-ch
Pull-up control
R
P-ch
Digital output
Digital output
• CMOS output
P-ch
• Hysteresis input
• CMOS input
G
N-ch
• Pull-up control available
Standby control
Hysteresis input
CMOS input
Pull-up control
R
P-ch
N-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
Digital output
P-ch
H
Standby control
Hysteresis input
Standby control
CMOS input
• N-ch open drain output
• CMOS input
I
Hysteresis input
• Hysteresis input
Digital output
N-ch
Pull-up control
R
P-ch
N-ch
Digital output
Digital output
P-ch
• CMOS output
• Hysteresis input
• Analog input
J
• Pull-up control available
Analog input
A/D control
Standby control
Hysteresis input
(Continued)
Document Number: 002-07475 Rev. *A
Page 24 of 85
MB95410H/470H Series
Type
Circuit
Remarks
P-ch
N-ch
Digital output
Digital output
• CMOS output
M
• LCD output
• Hysteresis input
LCD output
LCD control
Standby control
Hysteresis input
P-ch
N-ch
Digital output
Digital output
• CMOS output
• LCD output
N
LCD output
• Hysteresis input
• CMOS input
LCD control
Standby control
Hysteresis input
CMOS input
P-ch
N-ch
Digital output
Digital output
• CMOS output
• LCD output
• Hysteresis input
Q
LCD output
LCD control
Standby control
External interrupt
control
Hysteresis input
P-ch
Digital output
Digital output
• CMOS output
N-ch
R
• LCD power supply
• Hysteresis input
LCD internal divider
resistor I/O
LCD control
Standby control
Hysteresis input
(Continued)
Document Number: 002-07475 Rev. *A
Page 25 of 85
MB95410H/470H Series
Type
Circuit
Remarks
P-ch
N-ch
Digital output
Digital output
• CMOS output
• LCD output
Analog input
S
• Hysteresis input
• Analog input
LCD output
LCD control
A/D control
Standby control
Hysteresis input
Pull-up control
R
P-ch
N-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• Analog input
T
• Pull-up control available
Analog input
Analog input control
Standby control
Hysteresis input
P-ch
N-ch
Digital output
Digital output
• CMOS output
• LCD output
Analog input
V
• Hysteresis input
• Analog input
• CMOS input
LCD output
LCD control
A/D control
Standby control
Hysteresis input
CMOS input
(Continued)
Document Number: 002-07475 Rev. *A
Page 26 of 85
MB95410H/470H Series
(Continued)
Type
Circuit
Remarks
P-ch
N-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• Analog input
W
Analog input
Analog input control
Standby control
Hysteresis input
P-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
Y
N-ch
Standby control
Hysteresis input
Document Number: 002-07475 Rev. *A
Page 27 of 85
MB95410H/470H Series
9. Notes on Device Handling
Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a
medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned
in "17.1 Absolute Maximum Ratings" of “17. Electrical Characteristics” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed.
Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating
range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial
frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms
at a momentary fluctuation such as switching the power supply.
Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop
mode.
10. Pin Connection
Treatment of unused input pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull
up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave
it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it
unconnected.
Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and
conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the
device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS
pin at a location close to this device.
DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and
the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RST pin and the
VCC or VSS pin when designing the layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output function of the PF2/RST pin can
be enabled by the RSTOE bit in the SYSC register, and the reset input function or the general purpose I/O function can be selected
by the RSTEN bit in the SYSC register.
Analog power supply
Always set the same potential to AVCC and VCC pins. When VCC is larger than AVCC, the current may flow through the AN00 to AN07
pins.
Document Number: 002-07475 Rev. *A
Page 28 of 85
MB95410H/470H Series
Treatment of power supply pins on the A/D converter
Ensure that AVCC is equal to VCC and AVSS equal to VSS even when the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. Therefore, connect a ceramic capacitor of 0.1 µF (approx.) as a bypass
capacitor between the AVCC pin and the AVSS pin in the vicinity of this device.
C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a
capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from
unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between
CS and the VSS pin when designing the layout of a printed circuit board.
DBG/RST/C pins connection diagram
DBG
C
RST
Cs
Document Number: 002-07475 Rev. *A
Page 29 of 85
MB95410H/470H Series
11. Block Diagram (MB95410H Series)
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Flash with security function
(60/36/20 Kbyte)
PF1/X1*2
PF0/X0*2
PG2/X1A*2
PG1/X0A*2
RAM (2032/1008/496 bytes)
Interrupt controller
Oscillator
circuit
CR
oscillator
Clock control
P52/TO00
C
8/16-bit composite timer ch. 0
8/10-bit A/D converter
P50/TO01
P51/EC0
Watch counter
On-chip debug
Wild register
P12*1/DBG
P00/AN00 to P07/AN07
P13/ADTG
4 COM:
8 COM:
P00/INT00 to P07/INT07
External interrupt
P90/V4 to P94/V0
P90/V4 to P94/V0
PA0/COM0 to PA3/COM3
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC7/SEG09
P60/SEG10 to P67/SEG17
P43/SEG18 to P40/SEG21
PE0/SEG22 to PE7/SEG29
P07/SEG30 to P01/SEG36
PB2/SEG37 to PB4/SEG39
PA0/COM0 to PA7/COM7
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC7/SEG09
P60/SEG10 to P67/SEG17
P43/SEG18 to P40/SEG21
PE0/SEG22 to PE7/SEG29
P07/SEG30 to P02/SEG35
P14/UCK0
P11/UO0
P10/UI0
UART/SIO ch. 0
UART/SIO ch. 1
UART/SIO ch. 2
LCDC
(4 COM or 8 COM)
P05/UCK1
P03/UO1
P04/UI1
*3
P02/UCK2
P00/UO2
P01/UI2
P52/TI0
16-bit reload timer
P53/TO0
P20/PPG00
P21/PPG01
PE5/TO11
PE6/TO10
PE7/EC1
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
P16/PPG10
P15/PPG11
P20/CMPN
P21/CMPP
P17/CMPO
P22/SCL*1
P23/SDA*1
Voltage comparator
Port
I2C
Port
Vcc
Vss
*1: PF2, P12, P22 and P23 are N-ch open drain pins.
*2: Software option
*3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter
when the event counter operating mode is enabled.
Document Number: 002-07475 Rev. *A
Page 30 of 85
MB95410H/470H Series
12. Block Diagram (MB95470H Series)
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Flash with security function
(60/36/20 Kbyte)
PF1/X1*2
PF0/X0*2
PG2/X1A*2
PG1/X0A*2
RAM (2032/1008/496 bytes)
Interrupt controller
Oscillator
circuit
CR
oscillator
Clock control
P01/TO00
C
8/16-bit composite timer ch. 0
8/10-bit A/D converter
P13/TO01
P14/EC0
Watch counter
On-chip debug
Wild register
P12*1/DBG
P00/AN00 to P07/AN07
P13/ADTG
4 COM:
8 COM:
P00/INT00 to P07/INT07
External interrupt
P90/V4 to P93/V1
P90/V4 to P93/V1
PA0/COM0 to PA3/COM3
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC3/SEG05
P60/SEG06 to P67/SEG13
PE0/SEG14 to PE7/SEG21
P07/SEG22 to P00/SEG29
P16/SEG30, P15/SEG31
PA0/COM0 to PA7/COM7
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC3/SEG05
P60/SEG06 to P67/SEG13
PE0/SEG14 to PE7/SEG21
P07/SEG22 to P02/SEG27
P14/UCK0
P11/UO0
P10/UI0
UART/SIO ch. 0
UART/SIO ch. 1
UART/SIO ch. 2
LCDC
(4 COM or 8 COM)
P05/UCK1
P03/UO1
P04/UI1
*3
P02/UCK2
P00/UO2
P01/UI2
P14/TI0
16-bit reload timer
P10/TO0
P20/PPG00
P21/PPG01
PE5/TO11
PE6/TO10
PE7/EC1
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
P16/PPG10
P15/PPG11
P20/CMPN
P21/CMPP
P17/CMPO
P22*1/SCL
P23*1/SDA
Voltage comparator
Port
I2C
Port
Vcc
Vss
*1: PF2, P12, P22 and P23 are N-ch open drain pins.
*2: Software option
*3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter
when the event counter operating mode is enabled.
Document Number: 002-07475 Rev. *A
Page 31 of 85
MB95410H/470H Series
13. CPU Core
Memory Space
The memory space of the MB95410H/470H Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area.
The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory
maps of the MB95410H/470H Series are shown below.
Memory Maps
MB95F414H/F414K
MB95F474H/F474K
MB95F416H/F416K
MB95F476H/F476K
MB95F418H/F418K
MB95F478H/F478K
0000
H
0000
H
0000
H
I/O area
I/O area
I/O area
0080
0090
0100
H
H
0080
0090
0100
H
0080
0090
0100
H
Access prohibited
RAM 496 bytes
Access prohibited
RAM 1008 bytes
Access prohibited
RAM 2032 bytes
H
H
H
H
H
Registers
Registers
Registers
0200
0280
H
H
0200
0480
H
0200
H
H
Access prohibited
Access prohibited
0880
H
H
Access prohibited
Extended I/O area
0F80
H
0F80
H
0F80
Extended I/O area
Flash 4 Kbyte
Extended I/O area
Flash 4 Kbyte
1000
2000
H
H
1000
2000
H
H
1000
H
Vacant
Vacant
7FFF
H
Flash 60 Kbyte
BFFF
H
H
Flash 32 Kbyte
Flash 16 Kbyte
FFFF
FFFF
H
FFFF
H
Document Number: 002-07475 Rev. *A
Page 32 of 85
MB95410H/470H Series
14. I/O Map (MB95410H Series)
Register
Address
Register name
R/W
Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
PDR0
DDR0
PDR1
DDR1
—
Port 0 data register
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
R/W
R/W
R/W
R/W
—
00000000B
00000000B
00000000B
00000000B
—
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
SYCC2
PDR2
DDR2
Oscillation stabilization wait time setting register
PLL control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
00000000B
XXXXXX11B
00000XXXB
000XXXXXB
00000000B
00000000B
00000000B
XX100011B
00000000B
00000000B
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Port 2 data register
Port 2 direction register
0010H,
0011H
—
(Disabled)
—
—
0012H
0013H
0014H
0015H
0016H
0017H
PDR4
DDR4
PDR5
DDR5
PDR6
DDR6
Port 4 data register
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port 4 direction register
Port 5 data register
Port 5 direction register
Port 6 data register
Port 6 direction register
0018H to
001BH
—
(Disabled)
—
—
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port 9 direction register
Port A data register
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
0024H,
0025H
—
(Disabled)
—
—
(Continued)
Document Number: 002-07475 Rev. *A
Page 33 of 85
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W
Initial value
0026H
0027H
0028H
0029H
002AH
002BH
002CH
002DH
002EH
PDRE
DDRE
PDRF
DDRF
PDRG
DDRG
—
Port E data register
R/W
R/W
R/W
R/W
R/W
R/W
—
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
—
Port E direction register
Port F data register
Port F direction register
Port G data register
Port G direction register
(Disabled)
PUL1
PUL2
Port 1 pull-up register
Port 2 pull-up register
R/W
R/W
00000000B
00000000B
002FH,
0030H
—
PUL5
—
(Disabled)
(Disabled)
—
R/W
—
—
00000000B
—
0031H
Port 5 pull-up register
Port G pull-up register
0032H to
0034H
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
8/16-bit composite timer 01 status control register 1
8/16-bit composite timer 00 status control register 1
8/16-bit composite timer 11 status control register 1
8/16-bit composite timer 10 status control register 1
8/16-bit PPG01 control register
PC00
8/16-bit PPG00 control register
PC11
8/16-bit PPG11 control register
PC10
8/16-bit PPG10 control register
TMCSRH0
TMCSRL0
16-bit reload timer control status register upper
16-bit reload timer control status register lower
0040H to
0047H
—
(Disabled)
—
—
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch. 0/ch. 1
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
004CH to
004EH
—
(Disabled)
—
—
004FH
0050H
LCDCC2
CMR0
LCDC control register 2
R/W
R/W
00010100B
000X0001B
Voltage comparator control register
0051H to
0055H
—
(Disabled)
—
—
(Continued)
Document Number: 002-07475 Rev. *A
Page 34 of 85
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W
Initial value
0056H
0057H
0058H
0059H
005AH
005BH
005CH
005DH
005EH
005FH
0060H
0061H
0062H
0063H
0064H
0065H
0066H
0067H
0068H
0069H
006AH
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
0078H
SMC10
SMC20
SSR0
TDR0
RDR0
SMC11
SMC21
SSR1
TDR1
RDR1
IBCR00
IBCR10
IBCR0
IDDR0
IAAR0
ICCR0
SMC12
SMC22
SSR2
TDR2
RDR2
—
UART/SIO serial mode control register 1 ch. 0
UART/SIO serial mode control register 2 ch. 0
UART/SIO serial status register ch. 0
UART/SIO serial output data register ch. 0
UART/SIO serial input data register ch. 0
UART/SIO serial mode control register 1 ch. 1
UART/SIO serial mode control register 2 ch. 1
UART/SIO serial status register ch. 1
UART/SIO serial output data register ch. 1
UART/SIO serial input data register ch. 1
I2C bus control register 0
R/W
R/W
R/W
R/W
R
00000000B
00100000B
00000001B
00000000B
00000000B
00000000B
00100000B
00000001B
00000000B
00000000B
00000001B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00100000B
00000001B
00000000B
00000000B
—
R/W
R/W
R/W
R/W
R
R/W
R/W
R
I2C bus control register 1
I2C bus status register
I2C data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
I2C address register
I2C clock control register
UART/SIO serial mode control register 1 ch. 2
UART/SIO serial mode control register 2 ch. 2
UART/SIO serial status register ch. 2
UART/SIO serial output data register ch. 2
UART/SIO serial input data register ch. 2
(Disabled)
—
ADC1
ADC2
ADDH
ADDL
WCSR
FSR2
FSR
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
Watch counter status register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
000X0000B
00000000B
00000000B
—
Flash memory status register 2
Flash memory status register
SWRE0
FSR3
—
Flash memory sector write control register 0
Flash memory status register 3
(Disabled)
—
WREN
WROR
—
Wild register address compare enable register
Wild register data test setting register
Mirror of register bank pointer (RP) and direct bank pointer (DP)
R/W
R/W
—
00000000B
00000000B
—
(Continued)
Document Number: 002-07475 Rev. *A
Page 35 of 85
MB95410H/470H Series
Register
Address
Register name
Interrupt level setting register 0
R/W
Initial value
abbreviation
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
R/W
R/W
R/W
R/W
R/W
R/W
—
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
—
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
ILR2
ILR3
ILR4
ILR5
—
(Disabled)
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register address setting register (upper) ch. 0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Wild register address setting register (upper) ch. 1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
Wild register address setting register (upper) ch. 2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
0F89H to
0F91H
—
(Disabled)
—
—
0F92H
0F93H
0F94H
0F95H
0F96H
0F97H
0F98H
0F99H
0F9AH
0F9BH
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
T01CR0
T00CR0
T01DR
T00DR
TMCR0
T11CR0
T10CR0
T11DR
T10DR
TMCR1
PPS01
PPS00
PDS01
PDS00
PPS11
PPS10
PDS11
PDS10
8/16-bit composite timer 01 status control register 0
8/16-bit composite timer 00 status control register 0
8/16-bit composite timer 01 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
8/16-bit composite timer 00 data register
8/16-bit composite timer 00/01 timer mode control register
8/16-bit composite timer 11 status control register 0
8/16-bit composite timer 10 status control register 0
8/16-bit composite timer 11 data register
8/16-bit composite timer 10 data register
8/16-bit composite timer 10/11 timer mode control register
8/16-bit PPG01 cycle setting buffer register
8/16-bit PPG00 cycle setting buffer register
8/16-bit PPG01 duty setting buffer register
8/16-bit PPG00 duty setting buffer register
8/16-bit PPG11 cycle setting buffer register
8/16-bit PPG10 cycle setting buffer register
8/16-bit PPG11 duty setting buffer register
8/16-bit PPG10 duty setting buffer register
(Continued)
Document Number: 002-07475 Rev. *A
Page 36 of 85
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W
Initial value
0FA4H
0FA5H
PPGS
REVC
8/16-bit PPG start register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
—
8/16-bit PPG output inversion register
TMRH0
TMRLRH0
TMRL0
TMRLRL0
PSSR0
BRSR0
PSSR1
BRSR1
PSSR2
BRSR2
—
16-bit reload timer timer register upper
0FA6H
0FA7H
16-bit reload timer reload register upper
16-bit reload timer timer register lower
16-bit reload timer reload register lower
0FA8H
0FA9H
0FAAH
0FABH
0FACH
0FADH
0FAEH
0FAFH
0FB0H
0FB1H
0FB2H
0FB3H
0FB4H
0FB5H
0FB6H
0FB7H
0FB8H
0FB9H
0FBAH
UART/SIO dedicated baud rate generator prescaler select register ch. 0
UART/SIO dedicated baud rate generator baud rate setting register ch. 0 R/W
UART/SIO dedicated baud rate generator prescaler select register ch. 1 R/W
UART/SIO dedicated baud rate generator baud rate setting register ch. 1 R/W
UART/SIO dedicated baud rate generator prescaler select register ch. 2 R/W
UART/SIO dedicated baud rate generator baud rate setting register ch. 2 R/W
(Disabled)
A/D input disable register (lower)
—
AIDRL
R/W
R/W
—
00000000B
00000000B
—
LCDCC1
—
LCDC control register 1
(Disabled)
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
LCDCE6
LCDCE7
LCDCB1
LCDCB2
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
LCDC enable register 6
LCDC enable register 7
LCDC blinking setting register 1
LCDC blinking setting register 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00111110B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0FBBH,
0FBCH
—
(Disabled)
—
—
0FBDH to
0FE0H
LCDRAM
LCDC display RAM (36 bytes)
R/W
00000000B
0FE1H
0FE2H
0FE3H
—
(Disabled)
—
—
EVCR
WCDR
Event counter control register
Watch counter data register
R/W
R/W
00000000B
00111111B
(Continued)
Document Number: 002-07475 Rev. *A
Page 37 of 85
MB95410H/470H Series
(Continued)
Register
Address
Register name
Main CR clock trimming register (upper)
R/W
Initial value
abbreviation
0FE4H
0FE5H
CRTH
CRTL
R/W
R/W
0XXXXXXXB
00XXXXXXB
Main CR clock trimming register (lower)
0FE6H,
0FE7H
—
(Disabled)
—
—
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
0FEDH
0FEEH
0FEFH
SYSC
CMCR
CMDR
WDTH
WDTL
—
System configuration register
Clock monitoring control register
Clock monitoring data register
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
(Disabled)
R/W
R/W
R
11000011B
XX000000B
00000000B
XXXXXXXXB
XXXXXXXXB
—
R
R
—
ILSR
Input level select register
R/W
R/W
00000000B
01000000B
WICR
Interrupt pin control register
0FF0H to
0FFFH
—
(Disabled)
—
—
R/W access symbols
R/W : Readable / Writable
: Read only
R
Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
Document Number: 002-07475 Rev. *A
Page 38 of 85
MB95410H/470H Series
15. I/O Map (MB95470H Series)
Register
Address
Register name
R/W
Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
PDR0
DDR0
PDR1
DDR1
—
Port 0 data register
R/W
R/W
R/W
R/W
—
00000000B
00000000B
00000000B
00000000B
—
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
SYCC2
PDR2
DDR2
Oscillation stabilization wait time setting register
PLL control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
00000000B
XXXXXX11B
00000XXXB
000XXXXXB
00000000B
00000000B
00000000B
XX100011B
00000000B
00000000B
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Port 2 data register
Port 2 direction register
0010H to
0015H
—
(Disabled)
—
—
0016H
0017H
PDR6
DDR6
Port 6 data register
R/W
R/W
00000000B
00000000B
Port 6 direction register
0018H to
001BH
—
(Disabled)
—
—
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port 9 direction register
Port A data register
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
0024H,
0025H
—
(Disabled)
—
—
0026H
0027H
0028H
0029H
002AH
002BH
002CH
PDRE
DDRE
PDRF
DDRF
PDRG
DDRG
—
Port E data register
Port E direction register
Port F data register
Port F direction register
Port G data register
Port G direction register
(Disabled)
R/W
R/W
R/W
R/W
R/W
R/W
—
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
—
(Continued)
Document Number: 002-07475 Rev. *A
Page 39 of 85
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W
Initial value
002DH
002EH
PUL1
PUL2
Port 1 pull-up register
Port 2 pull-up register
R/W
R/W
00000000B
00000000B
002FH to
0034H
—
(Disabled)
—
—
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
Port G pull-up register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
8/16-bit composite timer 01 status control register 1
8/16-bit composite timer 00 status control register 1
8/16-bit composite timer 11 status control register 1
8/16-bit composite timer 10 status control register 1
8/16-bit PPG01 control register
PC00
8/16-bit PPG00 control register
PC11
8/16-bit PPG11 control register
PC10
8/16-bit PPG10 control register
TMCSRH0
TMCSRL0
16-bit reload timer control status register upper
16-bit reload timer control status register lower
0040H to
0047H
—
(Disabled)
—
—
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch. 0/ch. 1
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
004CH to
004EH
—
(Disabled)
—
—
004FH
0050H
LCDCC2
CMR0
LCDC control register 2
R/W
R/W
00010100B
000X0001B
Voltage comparator control register
0051H to
0055H
—
(Disabled)
—
—
0056H
0057H
0058H
0059H
005AH
005BH
005CH
005DH
005EH
SMC10
SMC20
SSR0
UART/SIO serial mode control register 1 ch. 0
UART/SIO serial mode control register 2 ch. 0
UART/SIO serial status register ch. 0
R/W
R/W
R/W
R/W
R
00000000B
00100000B
00000001B
00000000B
00000000B
00000000B
00100000B
00000001B
00000000B
(Continued)
TDR0
UART/SIO serial output data register ch. 0
UART/SIO serial input data register ch. 0
UART/SIO serial mode control register 1 ch. 1
UART/SIO serial mode control register 2 ch. 1
UART/SIO serial status register ch. 1
RDR0
SMC11
SMC21
SSR1
R/W
R/W
R/W
R/W
TDR1
UART/SIO serial output data register ch. 1
Document Number: 002-07475 Rev. *A
Page 40 of 85
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W
Initial value
005FH
0060H
0061H
0062H
0063H
0064H
0065H
0066H
0067H
0068H
0069H
006AH
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
0078H
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
RDR1
IBCR00
IBCR10
IBCR0
IDDR0
IAAR0
ICCR0
SMC12
SMC22
SSR2
TDR2
RDR2
—
UART/SIO serial input data register ch. 1
I2C bus control register 0
R
00000000B
00000001B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00100000B
00000001B
00000000B
00000000B
—
R/W
R/W
R
I2C bus control register 1
I2C bus status register
I2C data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
I2C address register
I2C clock control register
UART/SIO serial mode control register 1 ch. 2
UART/SIO serial mode control register 2 ch. 2
UART/SIO serial status register ch. 2
UART/SIO serial output data register ch. 2
UART/SIO serial input data register ch. 2
(Disabled)
—
ADC1
ADC2
ADDH
ADDL
WCSR
FSR2
FSR
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
Watch counter status register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
000X0000B
00000000B
00000000B
—
Flash memory status register 2
Flash memory status register
SWRE0
FSR3
—
Flash memory sector write control register 0
Flash memory status register 3
(Disabled)
—
WREN
WROR
—
Wild register address compare enable register
Wild register data test setting register
Mirror of register bank pointer (RP) and direct bank pointer (DP)
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
(Disabled)
R/W
R/W
—
00000000B
00000000B
—
ILR0
R/W
R/W
R/W
R/W
R/W
R/W
—
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
—
ILR1
ILR2
ILR3
ILR4
ILR5
—
WRARH0
WRARL0
WRDR0
Wild register address setting register (upper) ch. 0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
R/W
R/W
R/W
00000000B
00000000B
00000000B
(Continued)
Document Number: 002-07475 Rev. *A
Page 41 of 85
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W
Initial value
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
WRARH1
WRARL1
WRDR1
Wild register address setting register (upper) ch. 1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
WRARH2
WRARL2
WRDR2
Wild register address setting register (upper) ch. 2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
0F89H to
0F91H
—
(Disabled)
—
—
0F92H
0F93H
0F94H
0F95H
0F96H
0F97H
0F98H
0F99H
0F9AH
0F9BH
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
0FA4H
0FA5H
T01CR0
T00CR0
T01DR
T00DR
TMCR0
T11CR0
T10CR0
T11DR
T10DR
TMCR1
PPS01
PPS00
PDS01
PDS00
PPS11
8/16-bit composite timer 01 status control register 0
8/16-bit composite timer 00 status control register 0
8/16-bit composite timer 01 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
8/16-bit composite timer 00 data register
8/16-bit composite timer 00/01 timer mode control register
8/16-bit composite timer 11 status control register 0
8/16-bit composite timer 10 status control register 0
8/16-bit composite timer 11 data register
8/16-bit composite timer 10 data register
8/16-bit composite timer 10/11 timer mode control register
8/16-bit PPG01 cycle setting buffer register
8/16-bit PPG00 cycle setting buffer register
8/16-bit PPG01 duty setting buffer register
8/16-bit PPG00 duty setting buffer register
8/16-bit PPG11 cycle setting buffer register
PPS10
PDS11
PDS10
PPGS
8/16-bit PPG10 cycle setting buffer register
8/16-bit PPG11 duty setting buffer register
8/16-bit PPG10 duty setting buffer register
8/16-bit PPG start register
REVC
8/16-bit PPG output inversion register
TMRH0
TMRLRH0
TMRL0
TMRLRL0
PSSR0
BRSR0
PSSR1
BRSR1
16-bit reload timer timer register upper
0FA6H
0FA7H
16-bit reload timer reload register upper
16-bit reload timer timer register lower
16-bit reload timer reload register lower
0FA8H
0FA9H
0FAAH
0FABH
UART/SIO dedicated baud rate generator prescaler select register ch. 0
UART/SIO dedicated baud rate generator baud rate setting register ch. 0
UART/SIO dedicated baud rate generator prescaler select register ch. 1
UART/SIO dedicated baud rate generator baud rate setting register ch. 1
(Continued)
Document Number: 002-07475 Rev. *A
Page 42 of 85
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W
Initial value
0FACH
0FADH
0FAEH
0FAFH
0FB0H
0FB1H
0FB2H
0FB3H
0FB4H
0FB5H
0FB6H
0FB7H
0FB8H
0FB9H
0FBAH
PSSR2
BRSR2
—
UART/SIO dedicated baud rate generator prescaler select register ch. 2
R/W
00000000B
00000000B
—
UART/SIO dedicated baud rate generator baud rate setting register ch. 2 R/W
(Disabled)
A/D input disable register (lower)
—
AIDRL
LCDCC1
—
R/W
R/W
—
00000000B
00000000B
—
LCDC control register 1
(Disabled)
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
LCDCE6
—
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
LCDC enable register 6
R/W
R/W
R/W
R/W
R/W
R/W
—
00111100B
00000000B
00000000B
00000000B
00000000B
00000000B
—
(Disabled)
(Disabled)
(Disabled)
LCDCB1
LCDCB2
LCDC blinking setting register 1
LCDC blinking setting register 2
R/W
R/W
00000000B
00000000B
0FBBH,
0FBCH
—
LCDRAM
—
—
R/W
—
—
00000000B
—
0FBDH to
0FD8H
LCDC display RAM (28 bytes)
0FD9H to
0FE1H
0FE2H
0FE3H
0FE4H
0FE5H
EVCR
WCDR
CRTH
CRTL
Event counter control register
Watch counter data register
R/W
R/W
R/W
R/W
00000000B
00111111B
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
0XXXXXXXB
00XXXXXXB
0FE6H,
0FE7H
—
(Disabled)
—
—
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
SYSC
CMCR
CMDR
WDTH
WDTL
System configuration register
R/W
R/W
R
11000011B
XX000000B
00000000B
XXXXXXXXB
XXXXXXXXB
Clock monitoring control register
Clock monitoring data register
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
R
R
(Continued)
Document Number: 002-07475 Rev. *A
Page 43 of 85
MB95410H/470H Series
(Continued)
Register
abbreviation
Address
Register name
R/W
Initial value
0FEDH
0FEEH
0FEFH
—
(Disabled)
—
—
ILSR
WICR
Input level select register
R/W
R/W
00000000B
01000000B
Interrupt pin control register
0FF0H to
0FFFH
—
(Disabled)
—
—
R/W access symbols
R/W : Readable / Writable
: Read only
R
Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
Document Number: 002-07475 Rev. *A
Page 44 of 85
MB95410H/470H Series
16. Interrupt Source Table
Vector table address
Priority order of in-
Interrupt
request
number
Bit name of
interrupt level
setting register
terrupt sources of
the same level
(occurring
Interrupt source
Upper
Lower
simultaneously)
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
UART/SIO ch. 0
High
IRQ00
IRQ01
IRQ02
IRQ03
FFFAH
FFF8H
FFF6H
FFF4H
FFFBH
FFF9H
FFF7H
FFF5H
L00 [1:0]
L01 [1:0]
L02 [1:0]
L03 [1:0]
IRQ04
IRQ05
IRQ06
IRQ07
IRQ08
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFF3H
FFF1H
FFEFH
FFEDH
FFEBH
L04 [1:0]
L05 [1:0]
L06 [1:0]
L07 [1:0]
L08 [1:0]
8/16-bit composite timer ch. 0 (lower)
8/16-bit composite timer ch. 0 (upper)
UART/SIO ch. 2
LCD controller
8/16-bit PPG ch. 1 (lower)
UART/SIO ch. 1
IRQ09
FFE8H
FFE9H
L09 [1:0]
8/16-bit PPG ch. 1 (upper)
16-bit reload timer ch. 0
8/16-bit PPG ch. 0 (upper)
8/16-bit PPG ch. 0 (lower)
8/16-bit composite timer ch. 1 (upper)
Voltage comparator
I2C
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
L14 [1:0]
L15 [1:0]
L16 [1:0]
L17 [1:0]
L18 [1:0]
L19 [1:0]
—
8/10-bit A/D converter
Time-base timer
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
Watch counter
—
IRQ21
IRQ22
FFD0H
FFCEH
FFD1H
FFCFH
L21 [1:0]
L22 [1:0]
8/16-bit composite timer ch. 1 (lower)
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Low
Document Number: 002-07475 Rev. *A
Page 45 of 85
MB95410H/470H Series
17. Electrical Characteristics
17.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VSS 6
VSS 6
VSS 6
2
Power supply voltage*1
Input voltage*1
VCC
VI
VSS 0.3
VSS 0.3
VSS 0.3
2
V
V
*2
*2
Output voltage*1
VO
V
Maximum clamp current
Total maximum clamp current
ICLAMP
|ICLAMP
mA
mA
Applicable to specific pins*3
Applicable to specific pins*3
|
—
20
“L” level maximum output
current
ICL
—
—
—
15
4
mA
mA
mA
Average output current =
operating current operating ratio (1 pin)
“L” level average current
ICLAV
IOL
“L” level total maximum
output current
100
Total average output current =
operating current operating ratio
(Total number of pins)
“L” level total average output
current
IOLAV
—
50
mA
“H” level maximum output
current
ICH
—
—
—
15
4
mA
mA
mA
Average output current =
operating current operating ratio (1 pin)
“H” level average current
ICHAV
IOH
“H” level total maximum
output current
100
Total average output current =
operating current operating ratio
(Total number of pins)
“H” level total average output
current
IOHAV
—
50
mA
Power consumption
Operating temperature
Storage temperature
Pd
TA
—
320
85
mW
C
40
55
Tstg
150
C
*1: These parameters are based on the condition that VSS = 0.0 V.
*2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/from an input
is limited by means of an external component, the ICLAMP rating is used instead of the VI rating.
(Continued)
Document Number: 002-07475 Rev. *A
Page 46 of 85
MB95410H/470H Series
(Continued)
*3: Applicable to the following pins: P00 to P07, P10, P11, P13 to P16, P20 to P22, P40 to P43, P50 to P53, P60 to P67, P90 to P94,
PA0 to PA7, PB0 to PB4, PC0 to PC7, PE0 to PE7, PF0, PF1, PG1 and PG2 (P40 to P43, P50 to P53, P94, PB2 to PB4 and PC4
to PC7 are only available on the MB95410H Series.)
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV
(High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistance should be set so that when the HV (High Voltage) signal is applied the input current to the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential
may pass through the protective diode to increase the potential of the VCC pin, and thus affects other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied
from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may
not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit
Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-07475 Rev. *A
Page 47 of 85
MB95410H/470H Series
17.2 Recommended Operating Conditions
Value
(VSS = 0.0 V)
Parameter
Symbol
Unit
Remarks
Min
2.4*1*2
2.3
Max
5.5*1
5.5
In normal operation
Other than on-chip debug mode
Hold condition in stop mode
In normal operation
Power supply
voltage
VCC,
AVCC
V
2.9
5.5
On-chip debug mode
*3
2.3
5.5
Hold condition in stop mode
Smoothing
capacitor
CS
TA
0.022
1
µF
40
85
35
Other than on-chip debug mode
On-chip debug mode
Operating
temperature
C
+5
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is initially 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have
a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from
unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between
CS and the VSS pin when designing the layout of a printed circuit board.
DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device.
All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-07475 Rev. *A
Page 48 of 85
MB95410H/470H Series
17.3 DC Characteristics
(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
When CMOS input
level (hysteresis
input) is selected
P01, P04, P10,
P22, P23
VIHI
*1
0.7 VCC
—
VCC 0.3
V
P00 to P07, P10 to
P17,
P20 to P23, P40 to
P43*2,
P50 to P53*2, P60
to P67,
"H" level input
voltage
P90 to P93, P94*2,
PA0 to PA7,
PB0, PB1,
VIHS
*1
0.8 VCC
—
VCC 0.3
V
Hysteresis input
Hysteresis input
PB2 to PB4*2,
PC0 to PC3,
PC4 to PC7*2,
PE0 to PE7,
PF0, PF1, PG1,
PG2
VIHM
VIL
PF2
—
*1
0.7 VCC
—
—
VCC 0.3
V
V
When CMOS input
level (hysteresis
input) is selected
P01, P04, P10,
P22, P23
VSS 0.3
0.3 VCC
P00 to P07, P10 to
P17,
P20 to P23, P40 to
P43*2,
P50 to P53*2, P60
to P67,
“L” level input
voltage
P90 to P93, P94*2,
PA0 to PA7,
PB0, PB1,
VILS
*1
VSS 0.3
—
0.2 VCC
V
Hysteresis input
Hysteresis input
PB2 to PB4*2,
PC0 to PC3,
PC4 to PC7*2,
PE0 to PE7,
PF0, PF1, PG1,
PG2
VILM
PF2
—
—
VSS 0.3
VSS 0.3
—
—
0.3 VCC
V
V
Open-drain
output
application
P12, P22, P23,
PF2
VD
VSS 5.5
voltage
Output pins other
than P12, P22,
P23, PF2
“H” level
output voltage
VOH1
I
OH = 4 mA
VCC 0.5
—
—
V
(Continued)
Document Number: 002-07475 Rev. *A
Page 49 of 85
MB95410H/470H Series
(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Typ*4
Parameter
Symbol
Pin name
Condition
IOL = 4 mA
Unit
Remarks
Min
Max
“L” level output
voltage
VOL1
All output pins
—
—
0.4
V
Input leak current
(Hi-Z output leak
current)
When pull-up
µA resistance is
disabled
ILI
All input pins
0.0 V < VI < VCC
5
—
5
P10, P11, P13,
P14, P17, P20,
P21,
When pull-up
k resistance is
enabled
Pull-up resistance
Input capacitance
RPULL
VI = 0 V
25
50
100
P50 to P53*2,
PG1, PG2
Other than VCC
and VSS
CIN
f = 1 MHz
—
—
5
15
17
pF
Except during
Flash memory
programmingand
14.1
mA
V
CC = 5.5 V
FCH = 32 MHz
erasing
ICC
FMP = 16 MHz
During Flash
Main clock mode
(divided by 2)
memory
programmingand
—
—
20
39.5
9
mA
erasing
VCC = 5.5 V
FCH = 32 MHz
ICCS
FMP = 16 MHz
6.6
mA
Main sleep mode
(divided by 2)
VCC = 5.5 V
VCC
(External clock
operation)
Power supply
current*3
F
CL = 32 kHz
FMPL = 16 kHz
ICCL
—
60
153
µA
µA
Subclock mode
(divided by 2)
TA = 25C
VCC = 5.5 V
FCL = 32 kHz
F
MPL = 16 kHz
ICCLS
—
—
9
84
30
Subsleep mode
(divided by 2)
TA = 25C
VCC = 5.5 V
F
CL = 32 kHz
ICCT
Watch mode
Main stop mode
TA = 25C
4.3
µA
(Continued)
Document Number: 002-07475 Rev. *A
Page 50 of 85
MB95410H/470H Series
(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Typ*4
Max
VCC = 5.5 V
FCH = 4 MHz
MP = 10 MHz
Main PLL mode
(multiplied by 2.5)
TA = 25C
F
—
9.7
12.5
mA
VCC
ICCMPLL (External clock
operation)
VCC = 5.5 V
FCH = 6.44 MHz
F
MP = 16 MHz
—
13.9
20
mA
Main PLL mode
(multiplied by 2.5)
TA = 25C
VCC = 5.5 V
FCRH = 12.5 MHz
ICCMCR
—
—
11
13.2
410
mA
µA
FMP = 12.5 MHz
Main CR clock mode
VCC
VCC = 5.5 V
Sub-CR clock mode
(multiplied by 2.5)
TA = 25C
ICCSCR
112
Power supply
current*3
VCC = 5.5 V
F
CH = 32 MHz
ICCTS
—
—
—
1
3
mA
Time-base timer mode
TA = 25C
VCC
(External clock
operation)
VCC = 5.5 V
Substop mode
TA = 25C
Main stop mode
ICCH
3.1
1.5
22.5
4.7
µA with one clock
selected
Current consumption
for
A/D conversion at
16 MHz
IA
mA
Current consumption
for stopping
A/D conversion at
16 MHz
AVCC
IAH
—
—
1
5
µA
µA
Current consumption of
voltage comparator at
16 MHz
IV
113
350
(Continued)
Document Number: 002-07475 Rev. *A
Page 51 of 85
MB95410H/470H Series
(Continued)
(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Typ*4
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Max
Current consumption of
the low-voltage
detection circuit
ILVD
ICRH
ICRL
—
31
54
µA
mA
µA
Power supply
current*3
Current consumption of
the main CR oscillator
VCC
—
—
0.5
20
0.6
72
Current consumption of
the sub-CR oscillator
oscillating at 100 kHz
LCD internal
division resis-
tance
—
—
400
40
—
—
k
k
RLCD
—
Between V4 and VSS
V1 to V4 = 4.1 V
—
COM0 to COM7
output
impedance
RVCOM COM0 to COM7
RVSEG SEG00 to SEG39
—
—
1
—
—
—
5
7
k
k
µA
SEG00 to
SEG39 output
impedance
V0 to V4, COM0 to
ILCDL COM7,
LCD leakage
current
1
SEG00 to SEG39
*1: The input levels of P01, P04, P10, P22 and P23 can be switched between “CMOS input level” and “hysteresis input level”. The
input level selection register (ILSR) is used to switch between the two input levels.
*2: P40 to P43, P50 to P53, P94, PB2 to PB4 and PC4 to PC7 are only available on the MB95410H Series.
*3: • Thepowersupplycurrentisdeterminedbytheexternalclock. Whenthelow-voltagedetectionoptionisselected, thepower-supply
current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC
to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will
bethe sum of addingupthe current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators
(ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are
always enabled, and current consumption therefore increases accordingly.
• See “17.4. AC Characteristics: 17.4.1. Clock Timing” for FCH and FCL
.
• See “17.4. AC Characteristics: 17.4.2. Source Clock/Machine Clock” for FMP and FMPL
.
*4: VCC = 5.0 V, TA = +25°C
Document Number: 002-07475 Rev. *A
Page 52 of 85
MB95410H/470H Series
17.4 AC Characteristics
17.4.1 Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Typ
Parameter
Symbol Pin name
Condition
Unit
Remarks
Min
Max
When the main oscillation circuit is
used
X0, X1
X0
—
1
—
16.25
MHz
X1: open
1
1
—
—
—
—
—
12.5
10
8
12
32.5
8.13
6.5
MHz
MHz
When the main external clock is
used
*
FCH
—
—
—
3
MHz Main PLL multiplied by 2
MHz Main PLL multiplied by 2.5
MHz Main PLL multiplied by 4
MHz
X0, X1
—
3
3
4.06
12.75
10.2
8.16
1.02
12.25
9.8
Operating conditions:
• The main CR clock is used.
• TA = 10C to 85C
MHz
—
Clock
7.84
0.98
12.1875
9.75
7.8
MHz
frequency
1
MHz
FCRH
12.5
10
8
12.8125 MHz
Operating conditions:
• The main CR clock is used.
• TA = 40C to 1C
10.25
8.2
MHz
MHz
MHz
—
—
—
0.975
1
1.025
When the sub-oscillation circuit is
used
—
32.768
—
kHz
kHz
FCL
X0A, X1A
When the sub-external clock is
used
—
50
32.768
100
—
FCRL
—
—
—
200
1000
kHz When the sub-CR clock is used
When the main oscillation circuit is
used
X0, X1
61.5
—
ns
tHCYL
Clock cycle
time
X0
X1: open
83.4
30.8
—
—
—
1000
1000
—
ns
When the external clock is used
ns
X0, X1
X0A, X1A
X0
*
tLCYL
tWH1
tWL1
tWH2
tWL2
tCR
tCF
tCRHWK
tCRLWK
—
X1: open
*
30.5
—
µs When the subclock is used
ns
33.4
12.4
—
When the external clock is used,
the duty ratio should range
between 40% and 60%.
Input clock
pulse width
X0, X1
—
—
ns
X0A
—
—
15.2
—
µs
Inputclockrise
time and fall
time
X0
X1: open
*
—
—
—
—
5
5
ns
When the external clock is used
X0, X1
ns
—
—
—
—
—
—
—
—
80
10
µs When the main CR clock is used
µs When the sub-CR clock is used
CR oscillation
start time
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
Document Number: 002-07475 Rev. *A
Page 53 of 85
MB95410H/470H Series
Input waveform generated when an external clock (main clock) is used
t
HCYL
t
WH1
t
WL1
tCR
t
CF
0.8 VCC 0.8 VCC
0.2 VCC
X0, X1
0.2 VCC
0.2 VCC
Figure of main clock input port external connection
When a crystal oscillator or When the external clock is used When the external clock is used
a ceramic oscillator is used (X1 is open)
X0
X1
X0
X1
X0
X1
Open
FCH
FCH
FCH
Input waveform generated when an external clock (subclock) is used
t
LCYL
t
WH2
t
WL2
tCR
t
CF
0.8 VCC 0.8 VCC
0.2 VCC
X0A
0.2 VCC
0.2 VCC
Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
When the external clock is used
X0A X1A
X0A X1A
Open
F
CL
FCL
Document Number: 002-07475 Rev. *A
Page 54 of 85
MB95410H/470H Series
17.4.2 Source Clock/Machine Clock
(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Typ
Pin
name
Parameter
Symbol
Unit
Remarks
Min
Max
When the main oscillation clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
61.5
—
—
—
2000
ns
ns
ns
When the main oscillation clock is used
Min: FCH = 8.125 MHz, multiplied by the PLL
multiplier of 2
61.5
80
2000
1000
Max: FCH = 1 MHz, divided by 2
Source clock
cycle time*1
tSCLK
—
When the main CR clock is used
Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
—
61
20
—
—
µs
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.50
1
—
—
16.25
12.5
—
MHz When the main oscillation clock is used
MHz When the main CR clock is used
kHz When the sub-oscillation clock is used
FSP
Source clock
frequency
—
—
—
—
16.384
FSPL
When the sub-CR clock is used
kHz
—
50
—
—
FCRL = 100 kHz, divided by 2
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
61.5
32000
ns
ns
When the main CR clock is used
Min: FSP = 12.5 MHz
Machine clock
cycle time*2
(minimum
instruction
execution time)
80
61
20
—
—
—
16000
976.5
320
Max: FSP = 1 MHz, divided by 16
tMCLK
When the sub-oscillation clock is used
µs Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
When the sub-CR clock is used
µs Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
0.0625
1.024
—
—
—
16.25
12.5
MHz When the main oscillation clock is used
MHz When the main CR clock is used
kHz When the sub-oscillation clock is used
FMP
Machine clock
frequency
16.384
FMPL
When the sub-CR clock is used
kHz
3.125
—
50
F
CRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select bits (SYCC:DIV1,
DIV0). This source clock is divided to become a machine clock according to the division ratio set by the machine clock divide ratio
select bits (SYCC:DIV1, DIV0). In addition, a source clock can be selected from the following.
• Main clock divided by 2
• PLL multiplication of main clock (select from 2, 2.5, 4 multiplication)
• Main CR clock divided by 2
• Subclock divided by 2
• Sub-CR clock divided by 2
(Continued)
Document Number: 002-07475 Rev. *A
Page 55 of 85
MB95410H/470H Series
(Continued)
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
Schematic diagram of the clock generation block
Main PLL
× 2
× 2.5
× 4
Divided
by 2
FCH
(main oscillation)
Division
circuit
FCRH
(Main CR clock)
MCLK
SCLK
(source clock)
×
1
Divided
by 2
× 1/4
× 1/8
×1/16
(machine clock)
FCL
(sub-oscillation)
Divided
by 2
FCRL
(Sub-CR clock)
Clock mode select bits
(SYCC2: RCS1, RCS0)
Machine clock divide ratio select bits
(SYCC: DIV1, DIV0)
Document Number: 002-07475 Rev. *A
Page 56 of 85
MB95410H/470H Series
Operating voltage - Operating frequency (When T = 40C to 85C)
A
Without the on-chip debug function
5.5
5.0
A/D converter operation range
4.0
3.5
3.0
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL
)
Operating voltage - Operating frequency (When T = 40C to 85C)
A
With the on-chip debug function
5.5
5.0
A/D converter operation range
4.0
3.5
3.0
2.9
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
Document Number: 002-07475 Rev. *A
Page 57 of 85
MB95410H/470H Series
17.4.3 External Reset
(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Symbol
Unit
Remarks
In normal operation
Min
Max
1
2 tMCLK
*
—
ns
µs
µs
RST “L” level
pulse width
Oscillation time of the
In stop mode, subclock mode, subsleep
mode, watch mode, and power-on
tRSTL
—
—
oscillator*2 100
100
In time-base timer mode
*1: See “17.4.2. Source Clock/Machine Clock” for tMCLK
.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of
between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms.
The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and several
ms.
In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
In stop mode, subclock mode, subsleep mode, watch mode and power-on
t
RSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
100 μs
Oscillation
time of
oscillator
Oscillation stabilization wait time
Internal reset
Execute instruction
Document Number: 002-07475 Rev. *A
Page 58 of 85
MB95410H/470H Series
17.4.4 Power-on Reset
(VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min
—
1
Max
50
Power supply rising time
Power supply cutoff time
tR
—
—
ms
ms Wait time until power-on
tOFF
—
t
R
tOFF
2.5 V
0.2 V
0.2 V
0.2 V
VCC
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage
during the operation, set the slope of rising to a value below within 30 mV/ms as shown below.
VCC
Set the slope of rising to
a value below 30 mV/ms.
2.3 V
Hold condition in stop mode
V
SS
17.4.5 Peripheral Input Timing
(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Symbol
Pin name
Unit
Min
Max
—
Peripheral input “H” pulse width
Peripheral input “L” pulse width
tILIH
2 tMCLK
*
*
ns
ns
INT00 to INT07, EC0, EC1, ADTG
tIHIL
2 tMCLK
—
*: See “17.4.2. Source Clock/Machine Clock” for tMCLK
.
t
ILIH
t
IHIL
0.8 VCC 0.8 VCC
INT00 to INT07,
EC0, EC1, ADTG
0.2 VCC
0.2 VCC
Document Number: 002-07475 Rev. *A
Page 59 of 85
MB95410H/470H Series
17.4.6 UART/SIO, Serial I/O Timing
(VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
UCK0, UCK1, UCK2
4 tMCLK
*
—
ns
ns
UCK0, UCK1, UCK2,
UO0, UO1, UO2
UCK UO time
190
2 tMCLK
2 tMCLK
190
—
Internal clock
operation output pin:
CL = 80 pF 1 TTL
UCK0,UCK1,UCK2, UI0,
UI1, UI2
Valid UI UCK
tIVSHI
*
*
ns
ns
UCK0,UCK1,UCK2, UI0,
UI1, UI2
UCK valid UI hold time
tSHIXI
tSHSL
tSLSH
—
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK0, UCK1, UCK2
UCK0, UCK1, UCK2
4 tMCLK
*
*
—
—
ns
ns
4 tMCLK
UCK0, UCK1, UCK2,
UO0, UO1, UO2
UCK UO time
tSLOVE
tIVSHE
tSHIXE
External clock
operation output pin:
CL = 80 pF 1 TTL
—
190
—
ns
ns
ns
UCK0,UCK1,UCK2, UI0,
UI1, UI2
Valid UI UCK
2 tMCLK
*
*
UCK0,UCK1,UCK2, UI0,
UI1, UI2
UCK valid UI hold time
2 tMCLK
—
*: See “17.4.2. Source Clock/Machine Clock” for tMCLK
.
Document Number: 002-07475 Rev. *A
Page 60 of 85
MB95410H/470H Series
Internal shift clock mode
t
SCYC
2.4 V
UCK0,
UCK1,
UCK2
0.8 V
0.8 V
t
SLOVI
UO0,
UO1,
UO2
2.4 V
0.8 V
t
IVSHI
t
SHIXI
UI0,
UI1,
UI2
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
External shift clock mode
tSLSH
t
SHSL
UCK0,
UCK1,
UCK2
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t
SLOVE
UO0,
UO1,
UO2
2.4 V
0.8 V
t
IVSHE
t
SHIXE
UI0,
UI1,
UI2
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
Document Number: 002-07475 Rev. *A
Page 61 of 85
MB95410H/470H Series
17.4.7 Low-voltage Detection
(VSS = 0.0 V, TA = -40°C to +85°C)
Value
Typ
2.7
Parameter
Symbol
Unit
Remarks
Min
2.52
2.42
70
Max
2.88
2.78
—
Release voltage
VDL+
VDL-
VHYS
Voff
V
V
At power supply rise
Detection voltage
2.6
At power supply fall
Hysteresis width
100
—
mV
V
Power supply start voltage
Power supply end voltage
—
2.3
Von
4.9
—
—
V
Power supply voltage change
time
(at power supply rise)
Slope of power supply that the reset release
tr
tf
3000
300
—
—
—
—
µs
µs
signal generates within the rating (VDL+
)
Power supply voltage change
time
(at power supply fall)
Slope of powersupply that the reset detection
signal generates within the rating (VDL-
)
Reset release delay time
Reset detection delay time
td1
td2
—
—
—
—
300
20
µs
µs
VCC
Von
Voff
time
tf
tr
V
V
DL+
DL-
VHYS
Internal reset signal
time
td2
td1
Document Number: 002-07475 Rev. *A
Page 62 of 85
MB95410H/470H Series
17.4.8 I2C Timing
(VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Symbol
Pin name
Conditions Standard-mode
Fast-mode
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL
0
100
0
400
—
kHz
µs
(Repeat) Start condition hold time SDA ↓ →
SCL ↓
tHD;STA SCL, SDA
4.0
—
0.6
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
SCL
SCL
4.7
4.0
—
—
1.3
0.6
—
—
µs
µs
(Repeat) Start condition setup time SCL ↑ →
SDA ↓
tSU;STA SCL, SDA
tHD;DAT SCL, SDA
tSU;DAT SCL, SDA
tSU;STO SCL, SDA
4.7
0
—
3.45*2
—
0.6
0
—
0.9*3
—
µs
µs
µs
µs
µs
R = 1.7 k,
C = 50 pF*1
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
0.25
4.0
4.7
0.1
0.6
1.3
Stop condition setup time
SCL ↑ → SDA ↑
—
—
Bus free time between stop condition and
start condition
tBUF
SCL, SDA
—
—
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal
at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT ≥ 250 ns is
fulfilled.
tWAKEUP
SDA
tHD;STA
tHD;DAT
tHIGH
tBUF
tLOW
SCL
tSU;STO
tHD;STA
tSU;DAT
fSCL
tSU;STA
(Continued)
Document Number: 002-07475 Rev. *A
Page 63 of 85
MB95410H/470H Series
(VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
Value*2
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
SCL clock “L”
width
tLOW
tHIGH
SCL
(2 nm / 2)tMCLK 20
—
ns Master mode
SCL clock “H”
width
SCL
(nm / 2)tMCLK 20
(nm / 2)tMCLK 20
ns Master mode
Master mode
Maximum value is
applied when
ns m, n = 1, 8.
Otherwise, the
minimum value is
applied.
Start condition
hold time
SCL,
SDA
tHD;STA
( 1 nm / 2)tMCLK 20 ( 1 nm)tMCLK 20
Stop condition
setup time
SCL,
SDA
tSU;STO
tSU;STA
(1 nm / 2)tMCLK 20 (1 nm / 2)tMCLK 20
(1 nm / 2)tMCLK 20 (1 nm / 2)tMCLK 20
ns Master mode
ns Master mode
Start condition
setup time
SCL,
SDA
Bus free time
between stop
condition and
start condition
SCL,
SDA
tBUF
(2 nm 4)tMCLK 20
3 tMCLK 20
—
—
ns
R = 1.7 k,
SCL,
SDA
C = 50 pF*1
Data hold time
tHD;DAT
ns Master mode
Master mode
When assuming that
“L” of SCL is not
extended, the
SCL,
SDA
minimum value is
Data setup time tSU;DAT
( 2 nm / 2)tMCLK 20 ( 1 nm / 2)tMCLK 20 ns
applied to first bit of
continuous data.
Otherwise, the
maximum value is
applied.
Setup time
between
clearing
interrupt and
SCL rising
Minimum value is
applied to interrupt at
ns 9th SCL↓. Maximum
tSU;INT SCL
(nm / 2)tMCLK 20
(1 nm / 2)tMCLK 20
value is applied to
interrupt at 8th SCL↓.
SCL clock “L”
width
tLOW
tHIGH
SCL
SCL
4 tMCLK 20
4 tMCLK 20
—
—
ns At reception
SCL clock “H”
width
ns At reception
(Continued)
Document Number: 002-07475 Rev. *A
Page 64 of 85
MB95410H/470H Series
(Continued)
(VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
Value*2
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Not detected when 1
ns tMCLK is used at
Start condition
detection
SCL,
SDA
tHD;STA
2 tMCLK 20
—
reception
Not detected when 1
ns tMCLK is used at
reception
Stop condition
detection
SCL,
SDA
tSU;STO
2 tMCLK 20
—
—
Not detected when 1
ns tMCLK is used at
reception
Restart condition
detection condition
SCL,
SDA
tSU;STA
2 tMCLK 20
SCL,
SDA
Bus free time
tBUF
2 tMCLK 20
2 tMCLK 20
—
—
—
—
—
ns At reception
R = 1.7 k,
SCL,
SDA
At slave transmission
mode
Data hold time
Data setup time
Data hold time
Data setup time
tHD;DAT
tSU;DAT
tHD;DAT
tSU;DAT
C = 50 pF*1
ns
SCL,
SDA
tLOW 3 tMCLK
At slave transmission
mode
ns
20
SCL,
SDA
0
ns At reception
ns At reception
SCL,
SDA
tMCLK 20
Oscillation
stabilization wait
SDA↓→SCL↑
(at wakeup function)
SCL,
SDA
tWAKEUP
—
ns
time
2 tMCLK 20
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: • See “17.4.2. Source Clock/Machine Clock” for tMCLK
.
• m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
• n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
• The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the CS4 to CS0 bits in the
ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
: 0.9 MHz < tMCLK ≤ 2 MHz
: 0.9 MHz < tMCLK ≤ 4 MHz
: 0.9 MHz < tMCLK ≤ 10 MHz
: 0.9 MHz < tMCLK ≤ 16.25 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
(m, n) = (8, 22)
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
: 3.3 MHz < tMCLK ≤ 16.25 MHz
(m, n) = (1, 22), (5, 4)
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
(m, n) = (5, 8)
Document Number: 002-07475 Rev. *A
Page 65 of 85
MB95410H/470H Series
17.4.9 Voltage Comparator Timing
(AVCC = 4.0 V to 5.5 V, AVSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Pin name
Unit
Remarks
Min
0
Typ
—
Max
AVCC 1.3
10
Voltage range
Offset voltage
CMPP, CMPN
CMPP, CMPN
V
mV
ns
10
—
—
650
140
1210
5 mV overdrive
Delay time
CMPO
—
420
ns
50 mV overdrive
Power down recovery
PD: 1 0
—
0
—
—
1210
—
ns
ns
Power down delay
CMPO
Power down effective
PD: 0 1
Output: “H” level
Output stabilization time at
power up
Power up stabilization time
Bandgap reference voltage
CMPO
—
—
—
1210
1.27
ns
V
1.17
1.22
Document Number: 002-07475 Rev. *A
Page 66 of 85
MB95410H/470H Series
17.5 A/D Converter
17.5.1 A/D Converter Electrical Characteristics
(AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
Value
Parameter
Resolution
Symbol
Unit
Remarks
Min
—
Typ
—
Max
10
bit
LSB
LSB
LSB
V
Total error
3
—
3
—
Linearity error
2.5
1.9
—
2.5
1.9
Differential linear error
Zero transition voltage
—
VOT
AVSS 1.5 LSB AVSS 0.5 LSB AVSS 2.5 LSB
Full-scale transition
voltage
VFST
AVCC 4.5 LSB AVCC 2 LSB
AVCC 0.5 LSB
V
0.9
1.8
—
—
16500
16500
µs 4.5 V VCC 5.5 V
µs 4.0 V VCC <4.5 V
Compare time
Sampling time
—
—
4.5 V VCC 5.5 V, with
µs external impedance
< 5.4 k
0.6
1.2
—
—
∞
∞
4.0 V VCC <4.5 V, with
µs external impedance
< 2.4 k
Analog input current
Analog input voltage
IAIN
0.3
—
—
0.3
µA
V
VAIN
AVSS
AVCC
Document Number: 002-07475 Rev. *A
Page 67 of 85
MB95410H/470H Series
17.5.2 Notes on Using the A/D Converter
External impedance of analog input and its sampling time
The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog
voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision.
Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and
minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the
sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of
about 0.1 µF to the analog input pin.
Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
4.0 V ≤ VCC < 4.5 V
1.95 kΩ (Max)
8.98 kΩ (Max)
17 pF (Max)
17 pF (Max)
Note: The values are reference values.
Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
[External impedance = 0 kΩ to 20 kΩ]
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
(VCC ≥ 4.5 V)
(VCC ≥ 4.0 V)
(VCC ≥ 4.5 V)
(VCC ≥ 4.0 V)
6
4
2
0
0
2
4
6
8
10
12
14
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
A/D conversion error
As |VCCVSS| decreases, the A/D conversion error increases proportionately.
Document Number: 002-07475 Rev. *A
Page 68 of 85
MB95410H/470H Series
17.5.3 Definitions of A/D Converter Terms
Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point
(“00 0000 0000” “00 0000 0001”) of a device to the full-scale transition point (“11 1111 1111” “11 1111 1110”)
of the same device.
Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value.
Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a
full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
3FFH
3FEH
3FDH
3FFH
3FEH
3FDH
VFST
Actual conversion
characteristic
2 LSB
{1 LSB × (N-1) + 0.5 LSB}
004H
003H
002H
001H
004H
003H
002H
001H
VOT
VNT
Actual conversion
characteristic
1 LSB
Ideal characteristic
0.5 LSB
VSS
Analog input
VCC - VSS
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
Total error of
digital output N
1 LSB =
(V)
=
[LSB]
1024
1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
Document Number: 002-07475 Rev. *A
Page 69 of 85
MB95410H/470H Series
(Continued)
Zero transition error
Full-scale transition error
004H
003H
002H
001H
Ideal characteristic
Actual conversion
characteristic
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristic
VFST
(measurement
value)
Actual conversion
Ideal
characteristic
characteristic
Actual conversion
characteristic
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
Linearity error
Differential linearity error
Ideal characteristic
Actual conversion
characteristic
3FFH
3FEH
3FDH
(N+1)H
NH
Actual conversion
characteristic
{1 LSB × N + VOT}
V(N+1)T
VFST
(measurement
value)
VNT
004H
003H
002H
001H
VNT
(N-1)H
(N-2)H
Actual conversion
characteristic
Ideal
Actual conversion
characteristic
characteristic
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
V(N+1)T - VNT
1 LSB
VNT - {1 LSB × N + VOT}
Differential linear error
of digital output N
Linearity error
of digital output N
=
- 1
=
1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
Document Number: 002-07475 Rev. *A
Page 70 of 85
MB95410H/470H Series
17.6 Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
The time of writing 00H prior to erasure is
excluded.
—
0.2*1
0.5*2
s
s
Sector erase time
(16 Kbyte sector)
The time of writing 00H prior to erasure is
excluded.
—
0.5*1
7.5*2
Byte writing time
—
21
—
6100*2
—
µs
System-level overhead is excluded.
Program/erase cycle
100000
cycle
Power supply voltage at
program/erase
3.0
—
—
5.5
—
V
Flash memory data retention time
20*3
year Average TA = 85C
*1: TA = +25°C, VCC = 5.0 V, 100000 cycles
*2: TA = +85°C, VCC = 3.0 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from the result of a high
temperature accelerated test using the Arrhenius equation with the average temperature being +85°C).
Document Number: 002-07475 Rev. *A
Page 71 of 85
MB95410H/470H Series
18. Sample Characteristics
Power supply current temperature characteristics
ICC - VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
ICC - TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
F
= 16 MHz
FMP = 10 MHz
MP = 8 MHz
FMP = 4 MHz
MMPP = 2 MHz
F
F
MP = 16 MHz
MP = 10 MHz
F
F
15
10
5
15
10
5
0
0
−50
0
+50
[°C]
+100
+150
2
3
4
5
6
7
T
A
V
CC[V]
I
CCS - VCC
ICCS - TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
20
20
F
= 16 MHz
MP = 10 MHz
FMP = 8 MHz
MP = 4 MHz
FMMPP = 2 MHz
FMP = 16 MHz
F
FMP = 10 MHz
F
15
10
5
15
10
5
0
0
−50
0
+50
[°C]
+100
+150
2
3
4
5
6
7
T
A
V
CC[V]
ICCL - VCC
I
CCL - TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
100
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
100
75
50
25
0
75
50
25
0
−50
0
+50
[°C]
+100
+150
(Continued)
2
3
4
5
6
7
T
A
V
CC[V]
Document Number: 002-07475 Rev. *A
Page 72 of 85
MB95410H/470H Series
ICCLS - VCC
ICCLS - TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
100
75
50
25
0
100
75
50
25
0
−50
0
+50
+100
+150
2
3
4
5
6
7
T
A[°C]
VCC[V]
ICCT - VCC
ICCT - TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
100
75
50
25
0
100
75
50
25
0
−50
0
+50
+100
+150
2
3
4
5
6
7
T
A[°C]
VCC[V]
I
CCTS - VCC
I
CCTS - TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock operating
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock operating
2.0
2.0
F
= 16 MHz
FMP = 10 MHz
F
F
MP = 16 MHz
MP = 10 MHz
FMP = 8 MHz
MP = 4 MHz
FMMPP = 2 MHz
F
1.5
1.0
0.5
0.0
1.5
1.0
0.5
0.0
−50
0
+50
[°C]
+100
+150
2
3
4
5
6
7
T
A
V
CC[V]
(Continued)
Page 73 of 85
Document Number: 002-07475 Rev. *A
MB95410H/470H Series
(Continued)
ICCH - VCC
TA = +25°C, FMPL = (stop)
Substop mode with the external clock stopping
ICCH - TA
VCC = 5.5 V, FMPL = (stop)
Substop mode with the external clock stopping
20
20
15
10
5
15
10
5
0
0
−50
0
+50
+100
+150
2
3
4
5
6
7
T
A[°C]
VCC[V]
I
CCMCR - VCC
I
CCMCR - TA
TA = +25°C, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
VCC = 5.5 V, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
20
20
F = 12.5 MHz
F
MP = 10 MHz
F
MP = 8 MHz
F
MMPP = 1 MHz
F
F
F
F
MP = 10 MHz
= 12.5 MHz
MP = 8 MHz
MMPP = 1 MHz
15
10
5
15
10
5
0
0
−50
0
+50
[°C]
+100
+150
2
3
4
5
6
7
T
A
V
CC[V]
I
CCSCR - VCC
I
CCSCR - TA
TA = +25°C, FMPL = 50 kHz (divided by 2)
VCC = 5.5 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
Subclock mode with the sub-CR clock operating
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
20
0
0
−50
0
+50
[°C]
+100
+150
2
3
4
5
6
7
T
A
V
CC[V]
Document Number: 002-07475 Rev. *A
Page 74 of 85
MB95410H/470H Series
Input voltage characteristics
VIHI - VCC and VILI - VCC
VIHS - VCC and VILS - VCC
TA = +25°C
TA = +25°C
5
4
3
2
1
0
5
4
3
2
1
0
VIHI
VILI
VIHS
VILS
2
3
4
5
6
7
2
3
4
5
6
7
VCC[V]
VCC[V]
VIHM - VCC and VILM - VCC
TA = +25°C
5
4
3
2
1
0
VIHM
VILM
2
3
4
5
6
7
VCC[V]
Document Number: 002-07475 Rev. *A
Page 75 of 85
MB95410H/470H Series
Output voltage characteristics
(VCC - VOH1) - IOH
VOL1 - IOL
TA = +25°C
TA = +25°C
1.0
1.0
0.8
0.8
0.6
0.4
0.2
0.0
0.6
0.4
0.2
0.0
0
−2
−4
−6
−8
−10
0
2
4
6
8
10
IOH [mA]
IOL [mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
Document Number: 002-07475 Rev. *A
Page 76 of 85
MB95410H/470H Series
Pull-up characteristics
RPULL VCC
TA 25C
250
200
150
100
50
0
2
3
4
5
6
V
CC[V]
Document Number: 002-07475 Rev. *A
Page 77 of 85
MB95410H/470H Series
19. Mask Options
MB95F414H
MB95F416H
MB95F418H
MB95F474H
MB95F476H
MB95F478H
MB95F414K
MB95F416K
MB95F418K
MB95F474K
MB95F476K
MB95F478K
Part Number
No.
Selectable/Fixed
Low-voltage detection reset
Reset
Fixed
1
Without low-voltage detection reset
With dedicated reset input
With low-voltage detection reset
Without dedicated reset input
2
Document Number: 002-07475 Rev. *A
Page 78 of 85
MB95410H/470H Series
20. Ordering Information
Part Number
Package
MB95F414HPMC-G-SNE2
MB95F414KPMC-G-SNE2
MB95F416HPMC-G-SNE2
MB95F416KPMC-G-SNE2
MB95F418HPMC-G-SNE2
MB95F418KPMC-G-SNE2
80-pin plastic LQFP
(FPT-80P-M37)
MB95F474HPMC1-G-SNE2
MB95F474KPMC1-G-SNE2
MB95F476HPMC1-G-SNE2
MB95F476KPMC1-G-SNE2
MB95F478HPMC1-G-SNE2
MB95F478KPMC1-G-SNE2
64-pin plastic LQFP
(FPT-64P-M38)
MB95F474HPMC2-G-SNE2
MB95F474KPMC2-G-SNE2
MB95F476HPMC2-G-SNE2
MB95F476KPMC2-G-SNE2
MB95F478HPMC2-G-SNE2
MB95F478KPMC2-G-SNE2
64-pin plastic LQFP
(FPT-64P-M39)
Document Number: 002-07475 Rev. *A
Page 79 of 85
MB95410H/470H Series
21. Package Dimension
80-pin plastic LQFP
Lead pitch
0.50 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.47 g
Sealing method
Mounting height
Weight
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00 0.20(.551 .008)SQ
*12.00 0.10(.472 .004)SQ
0.145 0.055
(.006 .002)
60
41
Details of "A" part
61
40
1.50 –+00..1200
(Mounting height)
.059 –+..000048
0.25(.010)
0~8°
0.08(.003)
0.50 0.20
(.020 .008)
0.10 0.05
(.004 .002)
(Stand off)
0.60 0.15
(.024 .006)
INDEX
80
21
"A"
1
20
0.50(.020)
0.22 0.05
(.009 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
(Continued)
Document Number: 002-07475 Rev. *A
Page 80 of 85
MB95410H/470H Series
64-pin plastic LQFP
Lead pitch
0.50 mm
10.00 mm × 10.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.32 g
Sealing method
Mounting height
Weight
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00 0.20(.472 .008)SQ
*10.00 0.10(.394 .004)SQ
0.145 0.055
(.006 .002)
48
33
Details of "A" part
1.50 –+00..1200
49
32
0.08(.003)
(Mounting height)
.059 –+..000048
0.25(.010)
0~8°
INDEX
0.50 0.20
(.020 .008)
0.10 0.10
(.004 .004)
(Stand off)
64
17
0.60 0.15
(.024 .006)
"A"
1
16
0.50(.020)
0.22 0.05
(.009 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
(Continued)
Document Number: 002-07475 Rev. *A
Page 81 of 85
MB95410H/470H Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.65 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00 0.20(.551 .008)SQ
12.00 0.10(.472 .004)SQ
48
33
Details of "A" part
49
32
1.50 +0.20
.059 +.008
–0.10
–.004
0~8˚
0.10(.004)
0.10 0.10
(.004 .004)
INDEX
0.50 0.20
(.020 .008)
0.25(.010)BSC
64
17
0.60 0.15
(.024 .006)
1
16
"A"
0.65(.026)
0.32 0.05
(.013 .002)
M
0.13(.005)
C
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
Document Number: 002-07475 Rev. *A
Page 82 of 85
MB95410H/470H Series
22. Major Changes
Spansion Publication Number: DS702-00004-1v0-E
Page
Section
Details
Changed the family name.
1
—
F2MC-8FX New 8FX
Changed the values of the following power supply current param-
eters:
Electrical Characteristics
3. DC Characteristics
49 to 51
ICC, ICCS, ICCL, ICCLS, ICCT, ICCMPLL, ICCMCR, ICCSCR, ICCTS, ICCH, IA,
IV, ILVD
.
Electrical Characteristics
4. AC Characteristics
(1) Clock Timing
52
64
Changed the values of the clock frequency (FCRH).
Electrical Characteristics
4. AC Characteristics
(8) I2c Timing
Changed the settings related to the machine clock shown in *2.
Added “Sample Characteristics”.
71 to 76 Sample Characteristics
NOTE: Please see “Document History” about later revised information.
Document Number: 002-07475 Rev. *A
Page 83 of 85
MB95410H/470H Series
Document History
Document Title: MB95410H/470H Series New 8FX 8-bit Microcontrollers
Document Number: 002-07475
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
–
AKIH
05/17/2011 Migrated to Cypress and assigned document number 002-07475.
No change to document contents or format
*A
5198834
AKIH
04/04/2016 Updated to Cypress format.
Document Number: 002-07475 Rev. *A
Page 84 of 85
MB95410H/470H Series
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© Cypress Semiconductor Corporation 2010-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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Document Number: 002-07475 Rev. *A
Revised April 4, 2016
Page 85 of 85
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