MB9AF104NABGL [CYPRESS]
Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 40MHz, CMOS, PBGA112,;
| 型号： | MB9AF104NABGL |
| 厂家： | 
CYPRESS |
| 描述： | Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 40MHz, CMOS, PBGA112, 时钟 微控制器 外围集成电路 |
| 文件： | 总101页 (文件大小：1318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS706-00022-1v0-E
32-bit ARMTM CortexTM-M3 based Microcontroller
MB9A100A Series
MB9AF102NA/RA, F104NA/RA, F105NA/RA
ꢀDESCRIPTION
The MB9A100A Series are a highly integrated 32-bit microcontroller that target for high-performance and
cost-sensitive embedded control applications.
The MB9A100A Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM,
and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (UART,
CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE0 product categories in
"FM3 FAMILY MB9Axxx/MB9Bxxx SERIES PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.8
MB9A100A Series
ꢀFEATURES
ꢁ32-bit ARM Cortex-M3 Core
・Processor version: r2p0
・Up to 40MHz Frequency Operation
・Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
・24-bit System timer (Sys Tick): System timer for OS task management
ꢁOn-chip Memories
[Flash memory]
・Up to 384 Kbyte
・Read cycle: 0wait-cycle
・Security function for code protection
[SRAM]
This series contain a total of up to 48Kbyte on-chip SRAM memories. This is composed of two independent
SRAM (SRAM0,SRAM1) . SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1
is connected to System bus.
・SRAM0: Up to 24 Kbyte.
・SRAM1: Up to 24 Kbyte.
ꢁExternal Bus Interface
・Supports SRAM, NOR& NAND Flash device
・Up to 8 chip selects
・8/16-bit Data width
・Up to 25-bit Address bit
ꢁMulti-function Serial Interface (Max. 8channels)
・4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
・Operation mode is selectable from the followings for each channel.
・UART
・CSIO
・LIN
・I2C
[UART]
・Full-duplex double buffer
・Selection with or without parity supported
・Built-in dedicated baud rate generator
・External clock available as a serial clock
・Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
・Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
・Full-duplex double buffer
・Built-in dedicated baud rate generator
・Overrun error detect function available
[LIN]
・LIN protocol Rev.2.1 supported
・Full-duplex double buffer
・Master/Slave mode supported
・LIN break field generate (can be changed 13-16bit length)
・LIN break delimiter generate (can be changed 1-4bit length)
・Various error detect functions available (parity errors, framing errors, and overrun errors)
DS706-00022-1v0-E
2
MB9A100A Series
[I2C]
・Standard mode (Max.100kbps) / High-speed mode (Max.400Kbps) supported
ꢁDMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・8 independently configured and operated channels
・Transfer can be started by software or request from the built-in peripherals
・Transfer address area: 32bit(4Gbyte)
・Transfer mode: Block transfer/Burst transfer/Demand transfer
・Transfer data type: byte/half-word/word
・Transfer block count: 1 to 16
・Number of transfers: 1 to 65536
ꢁA/D Converter (Max. 16channels)
[12-bit A/D Converter]
・Successive Approximation Register type
・Built-in 3unit
・Conversion time: 1.0μs@5V
・Priority conversion available (priority at 2levels)
・Scanning conversion mode
・Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
ꢁBase Timer (Max. 8channels)
Operation mode is selectable from the followings for each channel.
・16-bit PWM timer
・16-bit PPG timer
・16/32-bit reload timer
・16/32-bit PWC timer
ꢁGeneral Purpose I/O Port
This series can use its pins as I/O ports when they are not used for external bus or peripherals. Moreover,
the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.
・Capable of pull-up control per pin
・Capable of reading pin level directly
・Built-in the port relocate function
・Up to 100 fast I/O Ports@120pin Package
DS706-00022-1v0-E
3
MB9A100A Series
ꢁMulti-function Timer (Max. 2unit)
The Multi-function timer is composed of the following blocks.
・16-bit free-run timer × 3ch/unit
・Input capture × 4ch/unit
・Output compare × 6ch/unit
・A/D activating compare × 3ch/unit
・Waveform generator × 3ch/unit
・16-bit PPG timer × 3ch/unit
The following function can be used to achieve the motor control.
・PWM signal output function
・DC chopper waveform output function
・Dead time function
・Input capture function
・A/D convertor activate function
・DTIF (Motor emergency stop) interrupt function
ꢁQuadrature Position/Revolution Counter (QPRC) (Max. 2unit)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
・The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
・16-bit position counter
・16-bit revolution counter
・Two 16-bit compare registers
ꢁDual Timer (Two 32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・Free-running
・Periodic (=Reload)
・One-shot
ꢁWatch Counter
The Watch counter is used for wake up from power saving mode.
・Interval timer: up to 64s(Max.)@ Sub Clock : 32.768kHz
ꢁExternal Interrupt Controller Unit
・Up to 16 external vectors
・Include one non-maskable interrupt(NMI)
ꢁWatch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low speed CR oscillator. Therefore,”Hardware" watchdog is
active in any power saving mode except STOP.
DS706-00022-1v0-E
4
MB9A100A Series
ꢁCRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・CCITT CRC16 Generator Polynomial: 0x1021
・IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
ꢁClock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and Main PLL) that are dynamically selectable.
・Main Clock
・Sub Clock
: 4MHz to 48MHz
: 32.768kHz
・High-speed CR Clock : 4MHz
・Low-speed CR Clock : 100kHz
・Main PLL Clock
[Resets]
Reset requests from INITX pins, Power on reset, Software reset, watchdog timers reset, low voltage
detector reset and clock supervisor reset.
ꢁClock Super Visor (CSV)
Clocks generated by CR oscillators are used to supervise abnormality of the external clocks.
・External OSC clock failure (clock stop) is detected, reset is asserted.
・External OSC frequency anomaly is detected, interrupt or reset is asserted.
ꢁLow Voltage Detector (LVD)
This series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has
been set, Low Voltage Detector generates an interrupt or reset.
・LVD1: error reporting via interrupt
・LVD2: auto-reset operation
ꢁLow Power Mode
Three power saving modes supported.
・SLEEP
・TIMER
・STOP
ꢁDebug
・Serial Wire JTAG Debug Port (SWJ-DP)
・Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.
ꢁPower Supply
・VCC = 2.7V to 5.5V: Correspond to the wide range voltage.
DS706-00022-1v0-E
5
MB9A100A Series
ꢀPRODUCT LINEUP
ꢁMemory size
Product device
MB9AF102NA/RA
MB9AF104NA/RA
256Kbyte
MB9AF105NA/RA
384Kbyte
On-chip Flash
128Kbyte
On-chip SRAM
16Kbyte
32Kbyte
48Kbyte
ꢁFunction
MB9AF102NA
MB9AF102RA
MB9AF104RA
MB9AF105RA
120
Product device
MB9AF104NA
MB9AF105NA
100
Pin count
CPU
Cortex-M3
40MHz
Freq.
Power supply voltage range
DMAC
2.7V to 5.5V
8ch
Addr:25bit (Max.)
Data:8/16 bit
Addr:25bit (Max.)
Data:8/16 bit
External Bus Interface
CS:5(Max.)
CS:8(Max.)
Support: SRAM, NOR Flash
Support: SRAM, NOR & NAND Flash
MF Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D
8ch (Max.)
8ch (Max.)
activation 3ch
compare
Input
capture
4ch
MF- Free-run
Timer timer
3ch
2 units (Max.)
Output
compare
6ch
Waveform
generator
3ch
PPG
3ch
QPRC
Dual Timer
2ch (Max.)
1 unit
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
1 unit
Yes
1ch(SW) + 1ch(HW)
16pins (Max.)+ NMI × 1
80pins (Max.)
100pins (Max.)
12 bit A/D converter
CSV (Clock Super Visor)
LVD
16ch (3 units)
Yes
2ch
(Low Voltage Detector)
Internal
OSC
Debug Function
High-speed
Low-speed
4MHz ( ± 2%)
100kHz (Typ)
SWJ-DP/ETM
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
DS706-00022-1v0-E
6
MB9A100A Series
ꢀPACKAGES
MB9AF102NA
MB9AF104NA
MB9AF105NA
MB9AF102RA
MB9AF104RA
MB9AF105RA
Product name
Package
LQFP: FPT-100P-M20*/M23
LQFP: FPT-120P-M21/M37
ꢂ
-
-
ꢂ
-
QFP:
FPT-100P-M06
BGA-112P-M04
ꢂ
ꢂ
BGA:
-
ꢂ
*
: Supported
: ES product only
Note : Refer to "ꢀPACKAGE DIMENSIONS" for detailed information on each package.
DS706-00022-1v0-E
7
MB9A100A Series
PIN ASSIGNMENT
z FPT-100P-M20/M23
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MDATA0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MDATA1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MDATA2
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MDATA3
P54/SOT6_0/TIOB1_2/RTO14_0/MDATA4
P55/SCK6_0/ADTG_1/RTO15_0/MDATA5
P56/INT08_2/DTTI1X_0/MCSX7
1
2
3
4
5
6
7
8
9
75 VSS
74 P20/INT05_0/CROUT/AIN1_1
73 P21/SIN0_0/INT06_1/BIN1_1
72 P22/SOT0_0/TIOB7_1/ZIN1_1
71 P23/SCK0_0/TIOA7_1/RTO00_1
70 P1F/AN15/ADTG_5/FRCK0_1/MDATA15
69 P1E/AN14/RTS4_1/DTTI0X_1/MDATA14
68 P1D/AN13/CTS4_1/IC03_1/MDATA13
67 P1C/AN12/SCK4_1/IC02_1/MDATA12
66 P1B/AN11/SOT4_1/IC01_1/MDATA11
65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MDATA10
64 P19/AN09/SCK2_2/MDATA9
63 P18/AN08/SOT2_2/MDATA8
62 AVSS
P30/AIN0_0/TIOB0_1/INT03_2/MDATA6
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MDATA7 10
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MDQM0 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MDQM1 12
P34/FRCK0_0/TIOB4_1/MAD24 13
P35/IC03_0/TIOB5_1/INT08_1/MAD23 14
P36/IC02_0/SIN5_2/INT09_1/MCSX3 15
P37/IC01_0/SOT5_2/INT10_1/MCSX2 16
P38/IC00_0/SCK5_2/INT11_1 17
P39/DTTI0X_0/ADTG_2 18
LQFP - 100
61 AVRH
60 AVCC
59 P17/AN07/SIN2_2/INT04_1/MWEX
58 P16/AN06/SCK0_1/MOEX
57 P15/AN05/SOT0_1/MCSX0
56 P14/AN04/SIN0_1/INT03_1/MCSX1
55 P13/AN03/SCK1_1/MAD08
54 P12/AN02/SOT1_1/MAD09
53 P11/AN01/SIN1_1/INT02_1
52 P10/AN00
P3A/RTO00_0/TIOA0_1 19
P3B/RTO01_0/TIOA1_1 20
P3C/RTO02_0/TIOA2_1 21
P3D/RTO03_0/TIOA3_1 22
P3E/RTO04_0/TIOA4_1 23
P3F/RTO05_0/TIOA5_1 24
VSS 25
51 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS706-00022-1v0-E
8
MB9A100A Series
z FPT-120P-M21/M37
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MDATA0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MDATA1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MDATA2
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MDATA3
P54/SOT6_0/TIOB1_2/RTO14_0/MDATA4
P55/SCK6_0/ADTG_1/RTO15_0/MDATA5
P56/SIN1_0/INT08_2/DTTI1X_0/MCSX7
P57/SOT1_0/MNALE
1
2
3
4
5
6
7
8
9
90 VSS
89 P20/INT05_0/CROUT/AIN1_1
88 P21/SIN0_0/INT06_1/BIN1_1
87 P22/SOT0_0/TIOB7_1/ZIN1_1
86 P23/SCK0_0/TIOA7_1/RTO00_1
85 P24/SIN2_1/INT01_2/RTO01_1
84 P25/SOT2_1/RTO02_1
83 P26/SCK2_1/RTO03_1/MCSX4
82 P27/INT02_2/RTO04_1/MCSX5
81 P28/ADTG_4/RTO05_1/MCSX6
80 P1F/AN15/ADTG_5/FRCK0_1/MDATA15
79 P1E/AN14/RTS4_1/DTTI0X_1/MDATA14
78 P1D/AN13/CTS4_1/IC03_1/MDATA13
77 P1C/AN12/SCK4_1/IC02_1/MDATA12
76 P1B/AN11/SOT4_1/IC01_1/MDATA11
75 P1A/AN10/SIN4_1/INT05_1/IC00_1/MDATA10
74 P19/AN09/SCK2_2/MDATA9
73 P18/AN08/SOT2_2/MDATA8
72 AVSS
P58/SCK1_0/MNCLE 10
P59/SIN7_0/INT09_2/MNWEX 11
P5A/SOT7_0/MNREX 12
P5B/SCK7_0 13
LQFP - 120
P30/AIN0_0/TIOB0_1/INT03_2/MDATA6 14
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MDATA7 15
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MDQM0 16
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MDQM1 17
P34/FRCK0_0/TIOB4_1/MAD24 18
P35/IC03_0/TIOB5_1/INT08_1/MAD23 19
P36/IC02_0/SIN5_2/INT09_1/MCSX3 20
P37/IC01_0/SOT5_2/INT10_1/MCSX2 21
P38/IC00_0/SCK5_2/INT11_1 22
P39/DTTI0X_0/ADTG_2 23
71 AVRH
70 AVCC
69 P17/AN07/SIN2_2/INT04_1/MWEX
68 P16/AN06/SCK0_1/MOEX
67 P15/AN05/SOT0_1/MCSX0
66 P14/AN04/SIN0_1/INT03_1/MCSX1
65 P13/AN03/SCK1_1/MAD08
64 P12/AN02/SOT1_1/MAD09
63 P11/AN01/SIN1_1/INT02_1
62 P10/AN00
P3A/RTO00_0/TIOA0_1 24
P3B/RTO01_0/TIOA1_1 25
P3C/RTO02_0/TIOA2_1 26
P3D/RTO03_0/TIOA3_1 27
P3E/RTO04_0/TIOA4_1 28
P3F/RTO05_0/TIOA5_1 29
VSS 30
61 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS706-00022-1v0-E
9
MB9A100A Series
z BGA-112P-M04
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS706-00022-1v0-E
10
MB9A100A Series
z FPT-100P-M06
(TOP VIEW)
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MDATA1 81
50 P22/SOT0_0/TIOB7_1/ZIN1_1
49 P23/SCK0_0/TIOA7_1/RTO00_1
48 P1F/AN15/ADTG_5/FRCK0_1/MDATA15
47 P1E/AN14/RTS4_1/DTTI0X_1/MDATA14
46 P1D/AN13/CTS4_1/IC03_1/MDATA13
45 P1C/AN12/SCK4_1/IC02_1/MDATA12
44 P1B/AN11/SOT4_1/IC01_1/MDATA11
43 P1A/AN10/SIN4_1/INT05_1/IC00_1/MDATA10
42 P19/AN09/SCK2_2/MDATA9
41 P18/AN08/SOT2_2/MDATA8
40 AVSS
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MDATA2 82
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MDATA3 83
P54/SOT6_0/TIOB1_2/RTO14_0/MDATA4 84
P55/SCK6_0/ADTG_1/RTO15_0/MDATA5 85
P56/INT08_2/DTTI1X_0/MCSX7 86
P30/AIN0_0/TIOB0_1/INT03_2/MDATA6 87
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MDATA7 88
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MDQM0 89
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MDQM1 90
P34/FRCK0_0/TIOB4_1/MAD24 91
QFP - 100
P35/IC03_0/TIOB5_1/INT08_1/MAD23 92
P36/IC02_0/SIN5_2/INT09_1/MCSX3 93
P37/IC01_0/SOT5_2/INT10_1/MCSX2 94
P38/IC00_0/SCK5_2/INT11_1 95
39 AVRH
38 AVCC
37 P17/AN07/SIN2_2/INT04_1/MWEX
36 P16/AN06/SCK0_1/MOEX
35 P15/AN05/SOT0_1/MCSX0
34 P14/AN04/SIN0_1/INT03_1/MCSX1
33 P13/AN03/SCK1_1/MAD08
32 P12/AN02/SOT1_1/MAD09
31 P11/AN01/SIN1_1/INT02_1
P39/DTTI0X_0/ADTG_2 96
P3A/RTO00_0/TIOA0_1 97
P3B/RTO01_0/TIOA1_1 98
P3C/RTO02_0/TIOA2_1 99
P3D/RTO03_0/TIOA3_1 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS706-00022-1v0-E
11
MB9A100A Series
PIN DESCRIPTION
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
79
1
B1
1
VCC
P50
-
INT00_0
AIN0_2
SIN3_1
80
2
C1
2
E
H
RTO10_0
(PPG10_0)
MDATA0
P51
INT01_0
BIN0_2
SOT3_1
(SDA3_1)
81
3
C2
3
E
H
RTO11_0
(PPG10_0)
MDATA1
P52
INT02_0
ZIN0_2
SCK3_1
(SCL3_1)
82
4
B3
4
E
H
RTO12_0
(PPG12_0)
MDATA2
P53
SIN6_0
TIOA1_2
INT07_2
83
84
5
6
D1
D2
5
6
E
E
H
RTO13_0
(PPG12_0)
MDATA3
P54
SOT6_0
(SDA6_0)
I
TIOB1_2
RTO14_0
(PPG14_0)
MDATA4
DS706-00022-1v0-E
12
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P55
SCK6_0
(SCL6_0)
ADTG_1
85
7
D3
7
E
I
RTO15_0
(PPG14_0)
MDATA5
P56
SIN1_0
(120pin only)
86
8
D5
8
E
H
INT08_2
DTTI1X_0
MCSX7
P57
SOT1_0
(SDA1_0)
-
-
-
-
-
-
9
E
E
I
I
MNALE
P58
SCK1_0
(SCL1_0)
10
MNCLE
P59
SIN7_0
-
-
-
11
E
H
INT09_2
MNWEX
P5A
SOT7_0
(SDA7_0)
-
-
-
-
-
-
12
13
E
E
I
I
MNREX
P5B
SCK7_0
(SCL7_0)
P30
AIN0_0
TIOB0_1
INT03_2
87
9
E1
E2
14
15
E
E
H
H
MDATA6
P31
BIN0_0
TIOB1_1
88
10
SCK6_1
(SCL6_1)
INT04_2
MDATA7
DS706-00022-1v0-E
13
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P32
ZIN0_0
TIOB2_1
89
90
11
12
E3
E4
16
17
E
H
SOT6_1
(SDA6_1)
INT05_2
MDQM0
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
MDQM1
P34
E
H
FRCK0_0
TIOB4_1
MAD24
P35
91
92
13
14
F1
F2
18
19
E
E
I
IC03_0
TIOB5_1
INT08_1
MAD23
P36
H
IC02_0
SIN5_2
INT09_1
MCSX3
P37
93
94
15
16
F3
20
21
E
E
E
H
H
H
IC01_0
SOT5_2
(SDA5_2)
G1
INT10_1
MCSX2
P38
IC00_0
95
96
17
18
G2
F4
22
23
SCK5_2
(SCL5_2)
INT11_1
P39
E
I
I
DTTI0X_0
ADTG_2
P3A
RTO00_0
(PPG00_0)
97
-
19
-
G3
B2
24
-
G
TIOA0_1
VSS
-
DS706-00022-1v0-E
14
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P3B
RTO01_0
(PPG00_0)
98
99
100
1
20
21
22
23
24
H1
H2
G4
H3
J2
25
26
27
28
29
G
I
TIOA1_1
P3C
RTO02_0
(PPG02_0)
G
G
G
G
I
I
I
I
TIOA2_1
P3D
RTO03_0
(PPG02_0)
TIOA3_1
P3E
RTO04_0
(PPG04_0)
TIOA4_1
P3F
RTO05_0
(PPG04_0)
2
TIOA5_1
VSS
3
4
25
26
L1
J1
30
31
-
-
VCC
P40
TIOA0_0
RTO10_1
(PPG10_1)
5
27
J4
32
G
H
INT12_1
MAD22
P41
TIOA1_0
RTO11_1
(PPG10_1)
6
7
8
28
29
30
L5
K5
J5
33
34
35
G
G
G
H
INT13_1
MAD21
P42
TIOA2_0
I
RTO12_1
(PPG12_1)
MAD20
P43
TIOA3_0
RTO13_1
(PPG12_1)
I
ADTG_7
MAD19
VSS
-
-
-
-
K2
J3
-
-
-
-
VSS
DS706-00022-1v0-E
15
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
-
-
H4
-
VSS
P44
-
TIOA4_0
9
31
H5
36
G
I
RTO14_1
(PPG14_1)
MAD18
P45
TIOA5_0
10
32
L6
37
G
I
RTO15_1
(PPG14_1)
MAD17
C
11
12
13
33
34
35
L2
L4
K1
38
39
40
-
-
-
VSS
VCC
P46
14
36
L3
41
D
M
X0A
P47
15
16
37
38
K3
K4
42
43
D
B
N
C
X1A
INITX
P48
DTTI1X_1
INT14_1
SIN3_2
17
39
K6
44
E
H
MAD16
P49
TIOB0_0
IC10_1
AIN0_1
18
40
J6
45
E
I
SOT3_2
(SDA3_2)
MAD15
P4A
TIOB1_0
IC11_1
BIN0_1
19
20
41
42
L7
K7
46
47
E
E
I
I
SCK3_2
(SCL3_2)
MAD14
P4B
TIOB2_0
IC12_1
ZIN0_1
MAD13
DS706-00022-1v0-E
16
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P4C
TIOB3_0
IC13_1
21
43
H6
48
E
I
SCK7_1
(SCL7_1)
AIN1_2
MAD12
P4D
TIOB4_0
FRCK1_1
22
23
44
45
J7
49
50
E
E
I
I
SOT7_1
(SDA7_1)
BIN1_2
MAD11
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
K8
MAD10
P70
-
-
-
-
-
-
51
52
E
E
I
TIOA4_2
P71
INT13_2
H
TIOB4_2
P72
SIN2_0
-
-
-
53
E
H
INT14_2
P73
SOT2_0
(SDA2_0)
-
-
-
-
-
-
54
55
E
E
H
I
INT15_2
P74
SCK2_0
(SCL2_0)
24
25
26
27
28
29
46
47
48
49
50
51
K9
L8
56
57
58
59
60
61
MD1
MD0
X0
C
C
A
A
D
D
A
B
L9
L10
L11
K11
X1
VSS
VCC
P10
-
-
30
52
J11
62
F
K
AN00
DS706-00022-1v0-E
17
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P11
AN01
SIN1_1
INT02_1
VSS
31
53
J10
63
F
L
-
-
-
-
K10
J9
-
-
-
-
VSS
P12
AN02
32
33
54
55
J8
64
65
F
F
K
K
SOT1_1
(SDA1_1)
MAD09
P13
AN03
H10
SCK1_1
(SCL1_1)
MAD08
P14
AN04
SIN0_1
INT03_1
MCSX1
P15
34
56
H9
66
F
L
AN05
35
36
57
58
H7
67
68
F
F
K
K
SOT0_1
(SDA0_1)
MCSX0
P16
AN06
G10
SCK0_1
(SCL0_1)
MOEX
P17
AN07
SIN2_2
INT04_1
MWEX
AVCC
AVRH
AVSS
P18
37
59
G9
69
F
L
38
39
40
60
61
62
H11
F11
G11
70
71
72
-
-
-
AN08
41
63
G8
73
F
K
SOT2_2
(SDA2_2)
MDATA8
DS706-00022-1v0-E
18
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P19
AN09
42
64
F10
74
F
K
SCK2_2
(SCL2_2)
MDATA9
P1A
AN10
SIN4_1
INT05_1
IC00_1
MDATA10
VSS
43
65
F9
75
F
L
-
-
H8
-
-
P1B
AN11
SOT4_1
(SDA4_1)
44
66
E11
76
F
F
K
K
IC01_1
MDATA11
P1C
AN12
SCK4_1
(SCL4_1)
45
67
E10
77
IC02_1
MDATA12
P1D
AN13
46
47
48
-
68
69
70
-
F8
E9
D11
-
78
79
80
81
CTS4_1
IC03_1
MDATA13
P1E
F
F
F
E
K
K
K
I
AN14
RTS4_1
DTTI0X_1
MDATA14
P1F
AN15
ADTG_5
FRCK0_1
MDATA15
P28
ADTG_4
RTO05_1
(PPG04_1)
MCSX6
DS706-00022-1v0-E
19
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P27
INT02_2
-
-
-
-
-
-
-
-
-
82
83
84
E
H
RTO04_1
(PPG04_1)
MCSX5
P26
SCK2_1
(SCL2_1)
E
E
I
I
RTO03_1
(PPG02_1)
MCSX4
P25
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
-
-
-
-
B10
C9
-
-
VSS
VSS
-
-
P24
SIN2_1
-
-
-
85
86
87
E
E
E
H
INT01_2
RTO01_1
(PPG00_1)
P23
SCK0_0
(SCL0_0)
49
50
71
72
D10
I
TIOA7_1
RTO00_1
(PPG00_1)
P22
SOT0_0
(SDA0_0)
E8
I
TIOB7_1
ZIN1_1
P21
SIN0_0
51
52
73
74
C11
C10
88
89
E
E
H
H
INT06_1
BIN1_1
P20
INT05_0
CROUT
AIN1_1
53
54
75
76
A11
A10
90
91
VSS
-
-
VCC
DS706-00022-1v0-E
20
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P00
TRSTX
P01
55
56
57
58
77
78
79
80
A9
92
93
94
95
E
E
B9
E
E
E
E
E
E
TCK
SWCLK
P02
B11
A8
TDI
P03
TMS
SWDIO
P04
59
81
B8
96
E
E
E
F
TDO
SWO
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
VSS
60
-
82
-
C8
D8
97
-
-
P06
TRACED1
TIOB5_2
61
62
83
84
D9
A7
98
99
E
E
F
SOT4_2
(SDA4_2)
INT01_1
P07
TRACED2
ADTG_0
G
SCK4_2
(SCL4_2)
P08
TRACED3
TIOA0_2
63
64
85
86
B7
C7
100
101
E
E
G
G
CTS4_2
P09
TRACECLK
TIOB0_2
RTS4_2
P0A
SIN4_0
INT00_2
FRCK1_0
MAD07
65
87
D7
102
E
H
DS706-00022-1v0-E
21
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P0B
SOT4_0
(SDA4_0)
66
67
88
89
A6
B6
103
E
I
TIOB6_1
IC10_0
MAD06
P0C
SCK4_0
(SCL4_0)
104
E
I
TIOA6_1
IC11_0
MAD05
P0D
RTS4_0
TIOA3_2
IC12_0
MAD04
P0E
68
69
90
91
C6
A5
105
106
E
E
I
I
CTS4_0
TIOB3_2
IC13_0
MAD03
VSS
-
-
-
-
D4
C3
-
-
-
-
VSS
P0F
70
92
B5
107
E
E
J
NMIX
MAD02
P68
SCK3_0
(SCL3_0)
-
-
-
108
H
TIOB7_2
INT12_2
P67
SOT3_0
(SDA3_0)
-
-
-
-
-
-
-
-
-
109
110
111
E
E
E
I
H
I
TIOA7_2
P66
SIN3_0
ADTG_8
INT11_2
P65
TIOB7_0
SCK5_1
(SCL5_1)
DS706-00022-1v0-E
22
MB9A100A Series
Pin no.
I/O circuit Pin state
Pin name
type
type
QFP-100 LQFP-100 BGA-112 LQFP-120
P64
TIOA7_0
-
-
-
112
113
114
E
H
SOT5_1
(SDA5_1)
INT10_2
P63
71
-
93
-
D6
-
INT03_0
MAD01
SIN5_1
P62
E
E
H
I
SCK5_0
(SCL5_0)
72
94
C5
ADTG_3
MAD00
P61
SOT5_0
(SDA5_0)
73
74
95
96
B4
C4
115
116
E
E
I
TIOB2_2
P60
SIN5_0
TIOA2_2
INT15_1
VCC
H
75
76
77
78
97
98
A4
A3
A2
A1
117
118
119
120
-
-
P80
H
H
O
O
99
P81
100
VSS
DS706-00022-1v0-E
23
MB9A100A Series
SIGNAL DESCRIPTION
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
62
85
96
72
-
48
90
8
84
7
A7
D3
F4
C5
-
D11
E4
J5
99
7
18
94
-
70
12
30
-
23
114
81
80
17
35
110
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
32
24
100
45
14
101
33
25
5
A/D converter external trigger input pin.
-
-
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
5
97
63
18
87
64
6
98
83
19
88
84
7
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
27
19
85
40
9
86
28
20
5
41
10
6
29
21
96
42
11
95
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
J4
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN09
AN10
AN11
AN12
AN13
AN14
AN15
Base Timer
0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
Base timer ch.0 TIOA pin.
Base timer ch.0 TIOB pin.
Base timer ch.1 TIOA pin.
Base timer ch.1 TIOB pin.
Base timer ch.2 TIOA pin.
Base timer ch.2 TIOB pin.
G3
B7
J6
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
Base Timer
1
46
15
6
34
26
116
47
16
115
Base Timer
2
99
74
20
89
73
DS706-00022-1v0-E
24
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Base Timer
3
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_1
TIOB6_1
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
8
100
68
21
90
69
9
30
22
90
43
12
91
31
23
-
J5
G4
C6
H6
E4
A5
H5
H3
-
35
Base timer ch.3 TIOA pin.
27
105
48
Base timer ch.3 TIOB pin.
Base timer ch.4 TIOA pin.
Base timer ch.4 TIOB pin.
Base timer ch.5 TIOA pin.
Base timer ch.5 TIOB pin.
17
106
36
Base Timer
4
1
28
-
51
22
91
-
44
13
-
J7
49
F1
-
18
52
Base Timer
5
10
2
32
24
82
45
14
83
89
88
-
L6
J2
37
29
60
23
92
61
67
66
-
C8
K8
F2
D9
B6
A6
-
97
50
19
98
Base Timer
6
Base timer ch.6 TIOA pin.
Base timer ch.6 TIOB pin.
104
103
112
86
Base Timer
7
Base timer ch.7 TIOA pin.
Base timer ch.7 TIOB pin.
49
-
71
-
D10
-
109
111
87
-
-
-
50
-
72
-
E8
-
108
DS706-00022-1v0-E
25
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Debugger
SWCLK
SWDIO
SWO
TCK
TDI
TDO
Serial wire debug interface clock input.
Serial wire debug interface data input / output.
Serial wire viewer output.
J-TAG test clock input.
J-TAG test data input.
56
58
59
56
57
59
58
64
60
61
62
63
55
72
71
70
69
68
67
66
65
33
32
23
22
21
20
19
18
17
10
9
78
80
81
78
79
81
80
86
82
83
84
85
77
94
93
92
91
90
89
88
87
55
54
45
44
43
42
41
40
39
32
31
30
29
28
27
14
13
57
56
16
15
-
B9
A8
B8
B9
B11
B8
A8
C7
C8
D9
A7
B7
A9
C5
D6
B5
A5
C6
B6
A6
D7
H10
J8
K8
J7
H6
K7
L7
J6
K6
L6
H5
J5
K5
L5
J4
93
95
96
93
94
96
95
101
97
98
99
100
92
114
113
107
106
105
104
103
102
65
64
50
49
48
47
46
45
44
37
36
35
34
33
32
19
18
J-TAG debug data output.
J-TAG test mode state input/output.
TMS
TRACECLK Trace CLK output of ETM.
TRACED0
TRACED1
Trace data output of ETM.
TRACED2
TRACED3
TRSTX
MAD00
MAD01
MAD02
MAD03
MAD04
MAD05
MAD06
MAD07
MAD08
MAD09
MAD10
MAD11
MAD12
MAD13
MAD14
MAD15
MAD16
MAD17
MAD18
MAD19
MAD20
MAD21
MAD22
MAD23
MAD24
MCSX0
MCSX1
MCSX2
MCSX3
MCSX4
MCSX5
MCSX6
MCSX7
J-TAG test reset Input.
External
Bus
External bus interface address bus.
8
7
6
5
92
91
35
34
94
93
-
F2
F1
H7
H9
G1
F3
-
-
-
D5
67
66
21
20
83
82
81
8
External bus interface chip select output pin.
-
-
86
-
-
8
DS706-00022-1v0-E
26
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
External
Bus
MDATA0
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7
MDATA8
MDATA9
MDATA10
MDATA11
MDATA12
MDATA13
MDATA14
MDATA15
MDQM0
80
81
82
83
84
85
87
88
41
42
43
44
45
46
47
48
89
90
2
3
4
5
6
7
9
10
63
64
65
66
67
68
69
70
11
12
C1
C2
B3
D1
D2
D3
E1
2
3
4
5
6
7
14
15
73
74
75
76
77
78
79
80
16
17
E2
External bus interface data bus.
G8
F10
F9
E11
E10
F8
E9
D11
E3
External bus interface byte mask signal output.
MDQM1
E4
External bus interface ALE signal to control
NAND Flash output pin.
External bus interface CLE signal to control
NAND Flash output pin.
External bus interface read enable signal to
control NAND Flash.
External bus interface write enable signal to
control NAND Flash.
External bus interface read enable signal for
SRAM.
External bus interface write enable signal for
SRAM.
MNALE
MNCLE
MNREX
MNWEX
MOEX
-
-
-
-
-
-
9
10
12
11
68
69
-
-
-
-
-
-
36
37
58
59
G10
G9
MWEX
DS706-00022-1v0-E
27
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
NMIX
80
60
65
81
61
-
82
31
-
71
34
87
90
37
88
52
43
89
51
23
83
92
86
93
-
94
-
95
-
5
-
6
-
17
-
74
-
2
82
87
3
83
-
4
53
-
C1
C8
D7
C2
D9
-
B3
J10
-
D6
H9
E1
E4
G9
E2
C10
F9
E3
C11
K8
D1
F2
D5
F3
-
G1
-
G2
-
J4
-
L5
-
K6
-
C4
-
B5
2
97
102
3
98
85
4
63
82
113
66
14
17
69
15
89
75
16
88
50
5
External interrupt request 00 input pin.
External interrupt request 01 input pin.
External interrupt request 02 input pin.
External interrupt request 03 input pin.
External interrupt request 04 input pin.
External interrupt request 05 input pin.
93
56
9
12
59
10
74
65
11
73
45
5
14
8
15
-
16
-
17
-
27
-
28
-
External interrupt request 06 input pin.
External interrupt request 07 input pin.
External interrupt request 08 input pin.
19
8
20
11
21
112
22
110
32
108
33
52
44
53
116
54
107
External interrupt request 09 input pin.
External interrupt request 10 input pin.
External interrupt request 11 input pin.
External interrupt request 12 input pin.
External interrupt request 13 input pin.
External interrupt request 14 input pin.
39
-
96
-
External interrupt request 15 input pin.
Non-Maskable Interrupt input.
70
92
DS706-00022-1v0-E
28
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
-
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
-
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
89
88
87
86
85
General-purpose I/O port 0.
General-purpose I/O port 1.
E11
E10
F8
E9
D11
C10
C11
E8
D10
-
General-purpose I/O port 2.
-
-
-
-
-
-
-
-
-
-
-
-
84
83
82
81
DS706-00022-1v0-E
29
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
9
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
41
42
44
45
46
47
48
49
50
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
General-purpose I/O port 3.
2
5
6
7
8
9
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
-
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
-
General-purpose I/O port 4.
3
4
5
6
7
8
-
-
3
4
5
6
7
8
9
10
11
12
13
General-purpose I/O port 5.
-
-
-
-
-
-
-
-
-
-
-
DS706-00022-1v0-E
30
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
GPIO
P60
P61
P62
P63
P64
P65
P66
P67
P68
74
73
72
71
-
-
-
-
-
96
95
94
93
-
-
-
-
-
C4
B4
C5
D6
-
-
-
-
-
116
115
114
113
112
111
110
109
108
51
General-purpose I/O port 6.
P70
-
-
-
P71
-
-
-
52
General-purpose I/O port 7.
P72
-
-
-
53
P73
-
-
-
54
P74
-
-
-
55
P80
P81
SIN0_0
SIN0_1
76
77
51
34
98
99
73
56
A3
A2
C11
H9
118
119
88
General-purpose I/O port 8.
Multi
Function
Serial
0
Multifunction serial interface ch.0 input pin.
66
Multifunction serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA0 when it is used in an I2C (operation
mode 4).
Multifunction serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL0 when it is used in an I2C (operation
mode 4).
SOT0_0
(SDA0_0)
50
35
49
72
57
71
E8
H7
87
67
86
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
D10
SCK0_1
(SCL0_1)
36
58
G10
68
Multi
Function
Serial
1
SIN1_0
SIN1_1
-
31
-
53
-
8
63
Multifunction serial interface ch.1 input pin.
J10
Multifunction serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA1 when it is used in an I2C (operation
mode 4).
Multifunction serial interface ch.1 clock I/O
pin.
This pin operates as SCK1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL1 when it is used in an I2C (operation
mode 4).
SOT1_0
(SDA1_0)
-
32
-
-
54
-
-
J8
-
9
SOT1_1
(SDA1_1)
64
10
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
33
55
H10
65
DS706-00022-1v0-E
31
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Multi
Function
Serial
2
SIN2_0
SIN2_1
SIN2_2
-
-
37
-
-
59
-
-
G9
53
85
69
Multifunction serial interface ch.2 input pin.
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
-
-
-
-
-
-
54
84
73
55
83
74
Multifunction serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA2 when it is used in an I2C (operation
mode 4).
41
-
63
-
G8
-
Multifunction serial interface ch.2 clock I/O
pin.
This pin operates as SCK2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL2 when it is used in an I2C (operation
mode 4).
-
-
-
42
64
F10
Multi
Function
Serial
3
-
-
2
-
110
2
Multifunction serial interface ch.3 input pin.
SIN3_1
80
17
C1
K6
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
39
44
-
-
3
-
109
3
Multifunction serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA3 when it is used in an I2C (operation
mode 4).
81
18
-
C2
J6
-
40
-
45
108
4
Multifunction serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL3 when it is used in an I2C (operation
mode 4).
82
19
4
B3
L7
41
46
DS706-00022-1v0-E
32
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Multi
Function
Serial
4
SIN4_0
SIN4_1
SIN4_2
65
43
60
87
65
82
D7
F9
C8
102
75
97
Multifunction serial interface ch.4 input pin.
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
66
44
61
67
45
62
88
66
83
89
67
84
A6
E11
D9
103
76
Multifunction serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA4 when it is used in an I2C (operation
mode 4).
98
Multifunction serial interface ch.4 clock I/O
pin.
This pin operates as SCK4 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL4 when it is used in an I2C (operation
mode 4).
B6
104
77
E10
A7
99
68
47
64
69
46
63
74
-
90
69
86
91
68
85
96
-
C6
E9
C7
A5
F8
B7
C4
-
105
79
101
106
78
100
116
113
20
Multifunction serial interface ch.4 RTS output
pin.
Multifunction serial interface ch.4 CTS input
pin.
Multi
Function
Serial
5
Multifunction serial interface ch.5 input pin.
SIN5_1
SIN5_2
93
15
F3
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
73
-
95
-
B4
-
115
112
21
Multifunction serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA5 when it is used in an I2C (operation
mode 4).
94
72
-
16
94
-
G1
C5
-
Multifunction serial interface ch.5 clock I/O
pin.
This pin operates as SCK5 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL5 when it is used in an I2C (operation
mode 4).
114
111
22
95
17
G2
DS706-00022-1v0-E
33
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Multi
Function
Serial
6
SIN6_0
SIN6_1
SOT6_0
83
90
5
12
D1
E4
5
17
Multifunction serial interface ch.6 input pin.
Multifunction serial interface ch.6 output pin.
84
89
85
6
11
7
D2
E3
D3
6
16
7
(SDA6_0) This pin operates as SOT6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SOT6_1
(SDA6_1)
SDA6 when it is used in an I2C (operation
mode 4).
SCK6_0
(SCL6_0)
Multifunction serial interface ch.6 clock I/O
pin.
This pin operates as SCK6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL6 when it is used in an I2C (operation
mode 4).
SCK6_1
(SCL6_1)
88
10
E2
15
Multi
Function
Serial
7
SIN7_0
SIN7_1
-
23
-
45
-
K8
11
50
Multifunction serial interface ch.7 input pin.
Multifunction serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA7 when it is used in an I2C (operation
mode 4).
Multifunction serial interface ch.7 clock I/O
pin.
This pin operates as SCK7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL7 when it is used in an I2C (operation
mode 4).
SOT7_0
(SDA7_0)
-
-
-
12
SOT7_1
(SDA7_1)
22
-
44
-
J7
-
49
13
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
21
43
H6
48
DS706-00022-1v0-E
34
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Multi
Function
Timer
0
DTTI0X_0 Input signal controlling wave form generator
96
18
F4
23
outputs RTO00 to RTO05 of multi-function
timer 0.
DTTI0X_1
47
69
E9
79
FRCK0_0 16-bit free-run timer ch.0 external clock input
91
48
95
43
94
44
93
45
92
46
13
70
17
65
16
66
15
67
14
68
F1
D11
G2
F9
G1
E11
F3
E10
F2
F8
18
80
22
75
21
76
20
77
19
78
pin.
FRCK0_1
IC00_0
IC00_1
IC01_0
IC01_1
IC02_0
IC02_1
IC03_0
IC03_1
RTO00_0
16-bit input capture ch.0 input pin of
multi-function timer 0.
ICxx desicribes chanel number.
Wave form generator output of multi-function
97
49
98
-
19
71
20
-
G3
D10
H1
-
24
86
25
85
26
84
27
83
28
82
29
81
(PPG00_0) timer 0.
This pin operates as PPG00 when it is used in
PPG 0 output modes.
Wave form generator output of multi-function
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0) timer 0.
This pin operates as PPG00 when it is used in
PPG 0 output modes.
Wave form generator output of multi-function
RTO01_1
(PPG00_1)
RTO02_0
99
-
21
-
H2
-
(PPG02_0) timer 0.
This pin operates as PPG02 when it is used in
PPG 0 output modes.
Wave form generator output of multi-function
RTO02_1
(PPG02_1)
RTO03_0
100
-
22
-
G4
-
(PPG02_0) timer 0.
This pin operates as PPG02 when it is used in
PPG 0 output modes.
Wave form generator output of multi-function
RTO03_1
(PPG02_1)
RTO04_0
1
23
-
H3
-
(PPG04_0) timer 0.
This pin operates as PPG04 when it is used in
PPG 0 output modes.
Wave form generator output of multi-function
RTO04_1
(PPG04_1)
RTO05_0
-
2
24
-
J2
-
(PPG04_0) timer 0.
This pin operates as PPG04 when it is used in
PPG 0 output modes.
RTO05_1
(PPG04_1)
-
DS706-00022-1v0-E
35
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Multi
Function
Timer
1
DTTI1X_0 Input signal controlling wave form generator
86
8
D5
8
outputs RTO10 to RTO15 of multi-function
timer 1.
DTTI1X_1
17
39
K6
44
FRCK1_0 16-bit free-run timer ch.1 external clock input
65
22
66
18
67
19
68
20
69
21
87
44
88
40
89
41
90
42
91
43
D7
J7
A6
J6
B6
L7
C6
K7
A5
H6
102
49
103
45
104
46
105
47
pin.
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
16-bit input capture ch.0 input pin of
multi-function timer 1.
ICxx desicribes chanel number.
106
48
Wave form generator output of multi-function
80
5
2
27
3
C1
J4
2
32
3
(PPG10_0) timer 1.
This pin operates as PPG10 when it is used in
PPG 1 output modes.
Wave form generator output of multi-function
RTO10_1
(PPG10_1)
RTO11_0
81
6
C2
L5
B3
K5
D1
J5
(PPG10_0) timer 1.
This pin operates as PPG10 when it is used in
PPG 1 output modes.
Wave form generator output of multi-function
RTO11_1
(PPG10_1)
RTO12_0
28
4
33
4
82
7
(PPG12_0) timer 1.
This pin operates as PPG12 when it is used in
PPG 1 output modes.
Wave form generator output of multi-function
RTO12_1
(PPG12_1)
RTO13_0
29
5
34
5
83
8
(PPG12_0) timer 1.
This pin operates as PPG12 when it is used in
PPG 1 output modes.
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
30
6
35
6
Wave form generator output of multi-function
timer 1.
84
D2
This pin operates as PPG14 when it is used in
PPG 1 output modes.
RTO14_1
(PPG14_1)
9
31
H5
36
RTO15_0
(PPG14_0) timer 1.
RTO15_1
(PPG14_1)
Wave form generator output of multi-function
85
10
7
D3
L6
7
This pin operates as PPG14 when it is used in
PPG 1 output modes.
32
37
DS706-00022-1v0-E
36
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
87
18
80
88
19
81
89
20
82
52
21
51
22
50
23
9
E1
14
45
2
QPRC ch.0 AIN input pin.
40
2
J6
C1
E2
L7
C2
E3
K7
B3
C10
H6
C11
J7
10
41
3
15
46
3
QPRC ch.0 BIN input pin.
QPRC ch.0 ZIN input pin.
11
42
4
16
47
4
Quadrature
Position/
Revolution
Counter
1
74
43
73
44
72
45
89
48
88
49
87
50
QPRC ch.1 AIN input pin.
QPRC ch.1 BIN input pin.
QPRC ch.1 ZIN input pin.
E8
K8
DS706-00022-1v0-E
37
MB9A100A Series
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No.
Module
RESET
Mode
Pin name
Function
QFP- LQFP- BGA- LQFP-
100 100 112 120
External Reset Input. A reset is valid when
INITX
16
25
24
38
47
46
K4
L8
K9
43
57
56
INITX=L.
Mode 0 pin.
During normal operation, MD0=L must be
input. During serial programming to flash
memory, MD0=H must be input.
Mode 1 pin. Input must always be at the "L"
MD0
MD1
level.
POWER
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
Power Pin.
Power Pin.
Power pin.
Power pin.
Power pin.
Power pin.
GND Pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
GND pin.
79
4
1
26
35
51
76
97
-
25
-
-
B1
J1
1
31
40
61
91
117
-
30
-
-
13
29
54
75
-
3
-
-
-
12
28
-
-
-
-
-
53
-
-
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
-
-
34
50
-
-
-
-
-
75
-
-
39
60
-
-
-
-
-
90
-
-
-
-
-
78
26
14
27
15
52
38
100
48
36
49
37
74
60
A1
L9
L3
L10
K3
C10
H11
120
58
41
59
42
89
70
CLOCK
Main clock (oscillation) input pin.
Sub clock (oscillation) input pin.
Main clock (oscillation) I/O pin.
Sub clock (oscillation) I/O pin.
Internal CR-osc clock output port.
A/D converter analog power pin.
A/D converter analog reference voltage input
pin.
X0A
X1
X1A
CROUT
AVCC
ADC
POWER
AVRH
39
61
F11
71
ADC
GND
C-pin
AVSS
C
A/D converter GND pin.
40
11
62
33
G11
L2
72
38
Power stabilization capacity pin.
DS706-00022-1v0-E
38
MB9A100A Series
I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
・Oscillation feedback resistor
: Approximately 1MΩ
X1
・With Standby mode control
Clock input
X0
Standby mode control
B
・CMOS level hysteresis input
・pull-up resistor
: Approximately 50kΩ
Pull-up resistor
CMOS level
hysteresis input
C
・CMOS level input
Control pin
Mode input
DS706-00022-1v0-E
39
MB9A100A Series
Type
Circuit
Remarks
D
・It is possible to select the low
speed oscillation / GPIO
function.
When the low speed oscillation
is selected.
・Oscillation feedback resistor
: Approximately 20MΩ
・With Standby mode control
P-ch
N-ch
Digital output
Digital output
P-ch
X1A
When the GPIO is selected.
・CMOS level output.
R
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・pull-up resistor
Pull-up resistor control
Digital input
Standby mode control
: Approximately 50kΩ
・IOH=-4mA, IOL=4mA
Clock input
Standby mode control
Digital input
Standby mode control
R
P-ch
P-ch
N-ch
Digital output
Digital output
X0A
Pull-up resistor control
DS706-00022-1v0-E
40
MB9A100A Series
Type
Circuit
Remarks
E
・CMOS level output
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・pull-up resistor
: Approximately 50kΩ
・IOH=-4mA, IOL=4mA
P-ch
P-ch
N-ch
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
F
・CMOS level output
・CMOS level hysteresis input
・With input control
・Analog input
・With pull-up resistor control
・With standby mode control
・pull-up resistor
: Approximately 50kΩ
・IOH=-4mA, IOL=4mA
P-ch
N-ch
P-ch
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
DS706-00022-1v0-E
41
MB9A100A Series
Type
Circuit
Remarks
G
・CMOS level output
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・pull-up resistor
: Approximately 50kΩ
・IOH=-12mA, IOL=12mA
P-ch
P-ch
N-ch
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
H
・CMOS level output
・CMOS level hysteresis input
・With standby mode control
・IOH=-25.3mA, IOL=19.7mA
P-ch
N-ch
Digital output
Digital output
Digital input
Standby mode control
DS706-00022-1v0-E
42
MB9A100A Series
HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your FUJITSU SEMICONDUCTOR semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
・ Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
・ Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
・ Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
・ Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-1Ea
43
DS706-00022-1v0-E
MB9A100A Series
・ Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
・ Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
・ Precautions Related to Usage of Devices
FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications
(computers, office automation and other office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under FUJITSU SEMICONDUCTOR's recommended conditions.
For detailed information about mount conditions, contact your sales representative.
・ Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended
mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
・ Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder
reflow method, and has established a ranking of mounting conditions for each product. Users are advised to
mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions.
DS706-00022-1v0-E
44
MB9A100A Series
・ Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
・ Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly
moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in
their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
・ Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.
Condition: 125°C/24 h
・ Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
DS706-00022-1v0-E
45
MB9A100A Series
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU SEMICONDUCTOR products in other special
environmental conditions should consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://edevice.fujitsu.com/fj/handling-e.pdf
DS706-00022-1v0-E
46
MB9A100A Series
HANDLING DEVICES
z Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at low impedance.
It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor
between VCC and VSS near this device.
z Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
z Using an external clock
When using an external clock, the clock signal should be input to the X0,X0A pin only and the X1,X1A pin
should be kept open.
・Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
z Handling when using Multi function serial pin as I2C pin
If it is using multi function serial pin as I2C pins, P-ch transistor of digital output is always disable.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C
bus system with power OFF.
DS706-00022-1v0-E
47
MB9A100A Series
z C Pin
As this series includes an internal regulator, always connect a bypass capacitor of approximately 4.7 µF to
the C pin for use by the regulator.
C
Device
4.7μF
VSS
GND
z Mode pins (MD0, MD1)
Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that
the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS
pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as
for switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
z Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
z Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, restransmit the data.
z Differences in features among the products with different memory sizes and
between FLASH products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between FLASH products
and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
DS706-00022-1v0-E
48
MB9A100A Series
BLOCK DIAGRAM
MB9AF102A/F104A/F105A
TRSTX,TCK
TDI,TMS
TDO
SRAM0
8/16/24
Kbyte
SWJ-DP
TPIU
ETM
ROM
Table
TRACED[3:0],
TRACECLK
On-Chip
Cortex-M3 Core
@40MHz(Max.)
Flash I/F
I
Flash
128/256/384
Kbyte
D
Security
NVIC
Sys
SRAM1
8/16/24
Kbyte
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch
CSV
RST
CLK
X0
Main
Osc
Sub.
Osc
PLL
X1
CR
4MHz
CR
100KHz
X0A
X1A
MAD[24:0]
AVCC,
AVSS,AVRH
MDATA[15:0]
A/D Converter x3
12bit A/D Converter
12bit A/D Converter
12bit A/D Converter
External Bus IF
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE
MNWEX,
AN[15:0]
MNREX,
MDQM[1:0]
ADTG[8:0]
Power On
Reset
TIOA[7:0]
TIOB[7:0]
Base Timer
16-bit 8ch
/32-bit 4ch
LVD
LVD Ctrl
C
Regulator
IRQ-Monitor
AIN[1:0]
BIN[1:0]
ZIN[1:0]
QPRC
2ch
CRC
Accelerator
A/D Activation
Compare
3ch
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:0]
NMIX
IC0[3:0]
IC1[3:0]
16-bit Input Capture
4ch
16-bit FreeRun Timer
3ch
FRCK[1:0]
MD[1:0]
MODE-Ctrl
GPIO
16-bit Output
Compare
6ch
Waveform
Generator
3ch
P0[F:0],
P1[F:0],
PIN-Function-Ctrl
DTTI[1:0]X
RTO0[5:0]
RTO1[5:0]
Px[x:0],
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
Multi Serial IF
8ch
(with FIFO ch.4～7)
*HW flow control(ch.4)
16-bit PPG
3ch
RTS4
Multi Function Timer x2
Product device
MB9AF102A
MB9AF104A
MB9AF105A
On-Chip Flash
SRAM0
SRAM1
128Kbyte
8Kbyte
8Kbyte
256Kbyte
16Kbyte
16Kbyte
384Kbyte
24Kbyte
24Kbyte
DS706-00022-1v0-E
49
MB9A100A Series
MEMORY MAP
z MB9A100A Series Memory Map(1)
Peripherals Area
Reserved
0x41FF_FFFF
0x4006_4000
0xFFFF_FFFF
Reserved
Reserved
Reserved
Reserved
DMAC
0x4006_3000
0x4006_2000
0x4006_1000
0x4006_0000
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
Reserved
0x4005_0000
Reserved
EXT-bus I/F
Reserved
0x4004_0000
0x4003_F000
External Device Area
0x4003_B000
Watch Counter
CRC
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x6000_0000
MFS
Reserved
Reserved
Reserved
LVD
0x4400_0000
0x4200_0000
0x4000_0000
32Mbyte
Bit band alias
Reserved
GPIO
Peripherals
Reserved
Reserved
Int-Req. Read
EXTI
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbyte
Bit band alias
Reserved
0x4002_8000
A/DC
QPRC
Reserved
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
Base Timer
PPG
0x2008_0000
0x2000_0000
0x1FF8_0000
SRAM1
SRAM0
Reserved
0x4002_2000
0x4002_1000
Reserved
Please refer to
the next page for
the memory size
details.
MFT unit1
MFT unit0
0x0010_2000
0x0010_0000
Security/CR Trim
0x4002_0000
Reserved
0x4001_6000
0x4001_5000
Dual Timer
Reserved
FLASH
0x4001_3000
0x0000_0000
SW WDT
HW WDT
Clock/Reset
0x4001_2000
0x4001_1000
0x4001_0000
Reserved
0x4000_1000
0x4000_0000
FLASH I/F
DS706-00022-1v0-E
50
MB9A100A Series
z MB9A100A Series Memory Map(2)
DS706-00022-1v0-E
51
MB9A100A Series
z Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_F000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_EFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x41FF_FFFF
Flash I/F register
Reserved
AHB
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
APB1
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Internal CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
GPIO
Reserved
Low Voltage Detector
Reserved
APB2
Reserved
Multi-function serial Interface
CRC
Watch Counter
Reserved
External Memory interface
Reserved
Reserved
DMAC register
Reserved
AHB
Reserved
Reserved
Reserved
DS706-00022-1v0-E
52
MB9A100A Series
PIN STATUS IN EACH CPU STATE
The terms used for pin status have the following meanings.
・INITX=0
This is the period when the INITX pin is the "L" level.
・INITX=1
This is the period when the INITX pin is the "H" level.
・SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "0".
・SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "1".
・Input enabled
Indicates that the input function can be used.
・Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
・Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
・Setting disabled
Indicates that the setting is disabled.
・Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
・Analog input is enabled
Indicates that the analog input is enabled.
・Trace output
Indicates that the trace function can be used.
DS706-00022-1v0-E
53
MB9A100A Series
z LIST OF PIN STATUS
Power-on reset
Device
internal reset sleep mode
Run mode or
INITX input
state
Timer mode or sleep mode
state
or low voltage
detection state
Function group Power supply
state
state
Power supply
stable
Pin status
type
Power supply stable
Power supply stable
INITX=1
unstable
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
SPL=1
A
B
Main crystal
oscillator input
pin
Input enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Main crystal
oscillator output
pin
H output/
Internal input
fixed at "0"/
or Input
H output/
Internal
input fixed
at "0"
H output/
Internal
input fixed
at "0"
Maintain
previous
state/
H output at
oscillation
stop (*1)/
Internal
input fixed
at "0"
Maintain
previous
state/
H output at
oscillation
stop (*1)/
Internal
input fixed
at "0"
Maintain
previous
state/
H output at
oscillation
stop (*1)/
Internal
input fixed
at "0"
enabled
C
INITX input pin
Mode input pin
Pull-up/ Input
enabled
Pull-up/
Input
enabled
Input
enabled
Pull-up/
Input
enabled
Setting
disabled
Pull-up/
Input
enabled
Input
enabled
Pull-up/
Input
enabled
Setting
disabled
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
D
E
Input enabled
Hi-Z
JTAG
selected
GPIO
selected
Setting
disabled
Output
Hi-Z/
Internal
input fixed
at "0"
F
Trace selected
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Trace output
Maintain
previous
state
GPIO
selected, or other
than above
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Hi-Z/
Internal
input fixed
at "0"
resource selected
DS706-00022-1v0-E
54
MB9A100A Series
Power-on reset
or low voltage
detection state
Function group Power supply
Device
internal reset sleep mode
Run mode or
INITX input
state
Timer mode or sleep mode
state
state
state
Power supply
stable
Pin status
type
Power supply stable
Power supply stable
INITX=1
unstable
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
Maintain
previous
state
SPL=1
G
Trace selected
Setting
disabled
Hi-Z
Setting
disabled
Hi-Z/
Input
enabled
Setting
disabled
Hi-Z/
Input
enabled
Maintain
previous
state
Trace output
GPIO selected,
or other than
above resource
selected
Hi-Z/
Internal
input fixed
at "0"
H
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO selected,
or other than
above resource
selected
Hi-Z
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Hi-Z/
Internal
input fixed
at "0"
I
GPIO selected,
resource selected
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed
at "0"
J
NMIX selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO selected,
or other than
above resource
selected
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Hi-Z/
Internal
input fixed
at "0"
DS706-00022-1v0-E
55
MB9A100A Series
Power-on reset
or low voltage
detection state
Device
internal reset sleep mode
Run mode or
INITX input
state
Timer mode or sleep mode
state
state
state
Power supply
stable
Pin status
Function group Power supply
type
Power supply stable
Power supply stable
INITX=1
unstable
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
SPL=1
K
Analog input
selected
Hi-Z
Hi-Z/
Internal
input fixed
at "0"/
Hi-Z/
Internal
input fixed
at "0"/
Hi-Z/
Internal
input fixed
at "0"/
Hi-Z/
Hi-Z/
Internal
input fixed
at "0"/
Internal
input fixed
at "0"/
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled
Setting
disabled
enabled
Setting
disabled
enabled
Maintain
previous
state
enabled
Maintain
previous
state
enabled
Hi-Z/
Internal
input fixed
at "0"
GPIO selected,
or other than
above resource
selected
Setting
disabled
L
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Analog input
selected
Hi-Z
Hi-Z/
Internal
input fixed
at "0"/
Hi-Z/
Internal
input fixed
at "0"/
Hi-Z/
Hi-Z/
Hi-Z/
Internal
input fixed
at "0"/
Internal
input fixed
at "0"/
Internal
input fixed
at "0"/
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled
Setting
disabled
enabled
Setting
disabled
enabled
Maintain
previous
state
enabled
Maintain
previous
state
enabled
Hi-Z/
Internal
input fixed
at "0"
GPIO selected,
or other than
above resource
selected
Setting
disabled
M
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed
at "0"
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Sub crystal
oscillator input
pin
Input
enabled
Input
enabled
DS706-00022-1v0-E
56
MB9A100A Series
Power-on reset
or low voltage
detection state
Device
internal reset or sleep
Run mode
INITX input
state
Timer mode or sleep mode
state
state
mode state
Power
supply
stable
INITX=1
-
Pin status
type
Function group Power supply
unstable
Power supply stable
Power supply stable
INITX=1
-
-
INITX=0
-
INITX=1
-
SPL=0
SPL=1
N
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous state
Output
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state/ Hi-Z at
oscillation
stop (*2)/
Sub crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state/ Hi-Z at
oscillation
stop (*2)/
Internal input Internal input
fixed at "0"
Maintain
previous state Hi-Z/ Internal
fixed at "0"
Output
O
GPIO selected
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
input fixed at
"0"
*1 : Oscillation is stopped at sub timer mode, Low speed CR timer mode, and stop mode.
*2 : Oscillation is stopped at stop mode.
DS706-00022-1v0-E
57
MB9A100A Series
ELECTRICAL CHARACTERISTICS
This section describes the electrical characteristics of MB9A100A series.
z Absolute Maximum Ratings / Recommended Operating Conditions
The following tables show the absolute maximum ratings and recommended operating conditions.
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Vss + 6.5
Vss + 6.5
Vss + 6.5
Vcc + 0.5
(≤ 6.5V)
AVcc + 0.5
(≤ 6.5V)
Vcc + 0.5
(≤ 6.5V)
10
Power supply voltage*1,*2
Vcc
AVcc
AVRH
Vss - 0.5
Vss - 0.5
Vss - 0.5
V
V
V
Analog power supply voltage*1,*3
Analog reference voltage*1,*3
Input voltage*1
VI
VIA
VO
Vss - 0.5
V
V
V
Analog pin input voltage*1
Output voltage*1
Vss - 0.5
Vss - 0.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
4mA type
12mA type
4mA type
12mA type
"L" level maximum output current*4
"L" level average output current*5
IOL
-
-
20
4
12
100
50
- 10
- 20
- 4
- 12
- 100
- 50
480
IOLAV
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
-
4mA type
12mA type
4mA type
12mA type
"H" level maximum output current*4
IOH
-
-
"H" level average output current*5
IOHAV
"H" level total maximum output current
"H" level total average output current*6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
+ 150
*1 : These parameters are based on the condition that Vss = AVss = 0.0V.
*2 : Vcc must not drop below Vss - 0.5V.
*3 : Be careful not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output is the average current for a single pin over a period of 100 ms.
*6 : The total average output current is the average current for all pins over a period of 100 ms.
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS706-00022-1v0-E
58
MB9A100A Series
2. Recommended Operating Conditions
(Vss = AVss = 0.0V)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
2.7
Max
5.5
Power supply voltage
Analog power supply voltage
Analog reference voltage
FPT-120P-M21
Vcc
AVcc
AVRH
-
-
-
V
V
V
2.7
5.5
AVcc = Vcc
AVss
AVcc
FPT-120P-M37
FPT-100P-M20
FPT-100P-M23
BGA-112P-M04
-
- 40
- 40
+ 85
+ 85
°C
°C
When
mounted on
four-layer
PCB
Operating
Temperature
Ta
FPT-100P-M06
When
- 40
- 40
+ 85
+ 70
Icc ≤ 74mA
Icc > 74mA
mounted on
double-sided
single-layer
PCB
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
DS706-00022-1v0-E
59
MB9A100A Series
z DC Characteristics
The following tables show the DC characteristics.
1. Current rating
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V Ta = - 40°C to + 85°C)
Pin
name
Value
Min Typ Max
Parameter Symbol
Conditions
Unit
Remarks
CPU : 40MHz,
Peripheral : 40MHz,
FLASH 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*1
CPU : 40MHz,
Peripheral : 40MHz,
FLASH 3Wait
FRWTR.RWT = 00
FSYNDN.SD = 011
*1
-
60
74
mA
Normal operation
(PLL)
-
-
-
44
6.0
0.2
55
9.2
mA
CPU/ Peripheral :
4MHz *1, *2
Normal operation
(built-in
high-speed CR)
Icc
mA FLASH 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral :
32kHz
FLASH 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*1
CPU/ Peripheral :
100kHz
FLASH 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*1
Power
supply
current
Normal operation
(sub oscillation)
Vcc
2.24
mA
mA
Normal operation
(built-in
low-speed CR)
-
0.3
2.36
SLEEP operation
(PLL)
SLEEP operation
(built-in
high-speed CR)
SLEEP operation
(sub oscillation)
SLEEP operation
(built in
Peripheral : 40MHz
*1
-
-
-
-
33
42
mA
mA
mA
mA
Peripheral : 4MHz
*1, *2
3.5
6.2
Iccs
Peripheral : 32kHz
*1
0.15
0.22
2.18
2.27
Peripheral : 100kHz
*1
low-speed CR)
DS706-00022-1v0-E
60
MB9A100A Series
(Continued)
Pin
name
Value
Min Typ Max
Parameter Symbol
Conditions
Unit
Remarks
Ta = + 25°C,
μA When LVD is off
-
-
-
-
50
-
200
*1
ICCH
STOP mode
Ta = + 85°C,
2
mA When LVD is off
Power
supply
current
*1
Ta = + 25°C,
μA When LVD is off
*1
Ta = + 85°C,
mA When LVD is off
110
-
300
2.2
Vcc
Timer mode
(sub oscillation)
ICCT
*1
Low voltage
detection
circuit (LVD)
power supply
current
for occurrence of
interrupt
ICCLVD
At operation
-
2
10
μA
*1:When all ports are fixed.
*2: When setting it to 4MHz by trimming.
DS706-00022-1v0-E
61
MB9A100A Series
2. Pin Characteristics
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V Ta = - 40°C to + 85°C)
Value
Min Typ Max
Parameter Symbol Pin name Conditions
Unit
Remarks
"H" level
CMOS
input
voltage
(hysteresis
input)
hysteresis
input pin,
MD0,1
Vcc
× 0.8
Vcc
+ 0.3
VIHS
-
-
V
"L" level input
voltage
(hysteresis
input)
CMOS
hysteresis
input pin,
MD0,1
Vss
- 0.3
Vcc
× 0.2
VILS
-
-
-
-
-
-
-
V
V
V
V
V
V
V
Vcc ≥ 4.5 V
OH = - 4mA
I
Vcc
- 0.5
4mA type
12mA type
P80, P81
Vcc
Vcc
Vcc
0.4
Vcc < 4.5 V
IOH = - 2mA
Vcc ≥ 4.5 V
OH = - 12mA
Vcc < 4.5 V
IOH = - 8mA
Vcc ≥ 4.5 V
"H" level
output voltage
I
Vcc
- 0.5
VOH
I
OH = - 25.3mA Vcc
- 0.4
Vcc < 4.5 V
IOH = - 13.4mA
Vcc ≥ 4.5 V
OL = 4mA
I
4mA type
12mA type
Vss
Vcc < 4.5 V
IOL = 2mA
Vcc ≥ 4.5 V
OL = 12mA
Vcc < 4.5 V
IOL = 8mA
Vcc ≥ 4.5 V
OL = 19.7mA
Vcc < 4.5 V
"L" level
output voltage
I
VOL
Vss
0.4
I
P80, P81
-
Vss
- 5
-
-
0.4
5
IOL = 11.9mA
Input leak
current
Pull-up
resistance
value
IIL
-
μA
kΩ
Vcc ≥ 4.5 V
Vcc < 4.5 V
25
30
50
80
100
200
RPU Pull-up pin
Other than
Input
capacitance
Vcc, Vss,
AVcc, AVss,
CIN
-
-
5
15
pF
AVRH
DS706-00022-1v0-E
62
MB9A100A Series
z AC Characteristics
The following tables show the AC characteristics.
(1) Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Pin
name
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
Remarks
Min
Max
48
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
PWH/tCYLH
PWL/tCYLH
4
4
4
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
When using external
clock
MHz
MHz
ns
20
48
20
250
250
FCH
4
X0
X1
20.83
50
tCYLH
-
Input clock pulse
width
Input clock rise
time and fall time
45
-
55
5
%
tCF
tCR
-
-
-
-
-
-
-
-
-
ns
Base clock
FCC
FCP0
-
-
-
-
-
-
-
-
-
40
40
40
40
-
MHz
MHz
MHz
MHz
ns
(HCLK/FCLK)
APB0 bus clock
(PCLK0)
APB1 bus clock
(PCLK1)
APB2 bus clock
(PCLK2)
Base clock
(HCLK/FCLK)
APB0 bus clock
(PCLK0)
APB1 bus clock
(PCLK1)
Internal operating
clock
frequency
-
FCP1
-
FCP2
-
tCYCC
tCYCP0
tCYCP1
tCYCP2
25
25
25
25
Internal operating
clock
cycle time
-
ns
-
ns
APB2 bus clock
(PCLK2)
-
ns
tCYLH
0.8×Vcc
0.8×Vcc
0.2×Vcc
0.8×Vcc
0.2×Vcc
X0
PW H
PWL
tCF
tCR
Note: Please see the block diagram to refer the APB bus which peripherals connected.
Please see the clock chapter of peripheral manual to refer the detail of internal operating clock.
DS706-00022-1v0-E
63
MB9A100A Series
(2) Sub Clock Input Characteristics
Pin
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Typ
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
Remarks
name
Min
Max
When crystal
-
-
32.768
-
kHz oscillator is
connected
FCL
When using
external clock
When using
external clock
When using
external clock
X0A
X1A
-
-
32
10
45
-
-
-
100
31.25
55
kHz
tCYLL
-
μs
Input clock pulse
width
PWH/tCYLL
PWL/tCYLL
%
tCYLL
0.8×Vcc
0.8×Vcc
0.2×Vcc
0.8×Vcc
0.2×Vcc
X0A
PW H
PWL
(3) Built-in CR Oscillation Characteristics
・Built-in high-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
When trimming*
When not trimming
Min
Ta = + 25°C
3.92
4
4.08
Ta =
0°C to + 70°C
Ta =
- 40°C to + 85°C
Ta =
3.84
3.8
3
4
4
4
4.16
4.2
5
Clock frequency
FCRH
MHz
- 40°C to + 85°C
*: In the case of using the values in CR trimming area of FLASH memory at shipment for frequency trimming.
・Built-in low-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Min
Clock frequency
FCRL
-
50
100
150
kHz
DS706-00022-1v0-E
64
MB9A100A Series
(4-1) Operating Conditions of Main PLL(In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time
(LOCK UP time)*
tLOCK 100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
fPLLI
-
fPLLO
4
4
60
-
-
-
30
MHz
30 multiple
120 MHz
*: Time from when the PLL starts operating until the oscillation stabilizes.
(4-2) Operating Conditions of Main PLL(In the case of using built-in high speed CR)
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time
(LOCK UP time)*
tLOCK 100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
fPLLI
-
fPLLO
3.8
15
57
4
-
-
4.2
MHz
28 multiple
120 MHz
*: Time from when the PLL starts operating until the oscillation stabilizes.
Note:It needs to input to PLL after trimming.
(5) Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
(6) Power-on Reset Timing
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Pin
name
Symbol
Unit
Remarks
Min
Max
Power supply rising time
Tr
0
1
-
-
ms
ms
Vcc
Power supply shut down time
Toff
Tr
Toff
2.7V
Vcc
0.2V
0.2V
0.2V
DS706-00022-1v0-E
65
MB9A100A Series
(7) External Bus Timing
・Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Parameter
Symbol
tOEW
Pin name Conditions
Unit Remarks
Min
Max
MOEX
Min pulse width
MOEX ↓ ⇒
Address delay time
MOEX ↑ ⇒
Address delay time
MOEX ↓ ⇒
MCSX ↓ delay time
MOEX ↑ ⇒
MCSX ↑ delay time
Data set up
⇒MOEX ↑ time
MOEX ↑ ⇒
Data hold time
MCSX ↓ ⇒
MWEX ↓ delay time
MWEX ↑ ⇒
MCSX ↑ delay time
Address ⇒
MWEX ↓ delay time
MWEX ↑ ⇒
Address delay time
MWEX ↓ ⇒
MDQM ↓ delay time
MWEX ↑ ⇒
MDQM ↑ delay time
MWEX
Min pulse width
MWEX ↓ ⇒
Data delay time
MWEX ↑ ⇒
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
MOEX
THCLK×1 - 3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MOEX
MAD24 to 00
MOEX
0
0
0
0
10
20
10
20
tOEL - AV
tOEH - AX
tOEL - CSL
tOEH - CSH
tDS - OE
MAD24 to 00
MOEX
MCSX
MOEX
MCSX
0
0
10
10
MOEX
20
38
-
-
MDATA15 to 0
MOEX
MDATA15 to 0
MCSX
tDH - OE
0
-
Vcc ≥ 4.5V THCLK×1 - 5
-
-
-
-
-
-
-
-
5
10
5
10
tCSL - WEL
tWEH - CSH
tAV - WEL
tWEH - AX
tWEL - DQML
tWEH - DQMH
tWEW
MWEX
MCSX
MWEX
MWEX
Vcc < 4.5V HCLK×1 - 10
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 10
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V HCLK×1 - 15
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 15
T
MAD24 to 00
T
MWEX
MAD24 to 00
MWEX
MDQM0 to 1
MWEX
MDQM0 to 1
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
0
0
0
0
MWEX
THCLK×1 - 3
-
MWEX
MDATA15 to 0
MWEX
- 5
-15
5
15
-
tWEL - DV
tWEH - DX
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 15
Data delay time
MDATA15 to 0
-
Note: When the external load capacitance = 50pF.
DS706-00022-1v0-E
66
MB9A100A Series
(Continued)
SRAM read
tCYC
VOH
VOH
HCLK
tOEH-CSH
tOEL-CSL
VO H
MCSX0 to 7
VO L
tOEL-AV
tOEH-AX
VO H
VO L
VOH
VOL
MAD24 to 00
tOEW
VOH
MOEX
VO L
tDS-OE
tDH-OE
VIH
VIL
VIH
VIL
MDATA15 to 0
Read
SRAM write
tCYC
HCLK
tW EH-CSH
tCSL-W EL
VO H
MCSX0 to 7
VO L
tAV-W EL
tW EH-AX
VO H
VO L
VOH
VOL
M AD24 to 00
M DQM 0 to 1
tW EH-DQMH
tW EL-DQML
VO H
VOL
tW EW
VOH
MW EX
VOL
tW EH-DX
tW EL-DV
VOH
VOL
VOH
VOL
M DATA15 to 0
W rite
DS706-00022-1v0-E
67
MB9A100A Series
・NAND FLASH mode
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Parameter
Symbol
tNREW
Pin name Conditions
Unit Remarks
Min
Max
MNREX
Min pulse width
Data set up
⇒ MNREX ↑ tiime
MNREX ↑ ⇒
Data hold time
MNALE ↑ ⇒
MNWEX delay time
MNWEX ↑ ⇒
MNALE delay time
MNCLE ↑ ⇒
MNWEX delay time
MNWEX ↑ ⇒
MNCLE delay time
MNWEX
Min pulse width
MNWEX ↓ ⇒
Data delay time
MNWEX ↑ ⇒
Data delay time
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
MNREX
THCLK×1 - 3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MNREX
MDATA15 to 0
MNREX
20
38
0
-
-
-
-
-
-
-
-
-
-
-
-
tDS - NRE
tDH - NRE
MDATA15 to 0
0
MNALE
MNWEX
MNALE
MNWEX
MNCLE
MNWEX
MNCLE
MNWEX
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 15
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 15
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 15
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 15
tALEH - NWEL
tNWEH - ALEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
Vcc ≥ 4.5V
THCLK×1 - 3
Vcc < 4.5V
MNWEX
-
MNWEX
MDATA15 to 0
MNWEX
Vcc ≥ 4.5V
Vcc < 4.5V
- 5
-15
+ 5
+15
-
tNWEL - DV
tNWEH - DX
Vcc ≥ 4.5V THCLK×1 - 5
Vcc < 4.5V THCLK×1 - 15
MDATA15 to 0
-
Note: when the external load capacitance = 50pF.
DS706-00022-1v0-E
68
MB9A100A Series
(Continued)
NAND FLASH read
tCYC
VOH
VOH
HCLK
tNREW
VOH
VO L
MNREX
tDS-NRE
tDH-NR E
VIH
VIL
VIH
VIL
MDATA15 to 0
Read
NAND FLASH write
tCYC
HCLK
tNW EH-ALEL
tALEH-NW EL
VOH
VOL
MNALE
tNW EH-CLEL
tCLEH-NW EL
VOH
VOL
M NCLE
MNWEX
tNW EW
VOH
VOL
tNW EH-DX
tNW EL-DV
VOH
VOL
VOH
VOL
MDATA15 to 0
W rite
DS706-00022-1v0-E
69
MB9A100A Series
(8) Base Timer Input Timing
・Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK,TIN)
tTIWH
tTIWL
Input pulse width
-
2tCYCP
-
ns
t
TIWL
t
TIWH
ECK
TIN
VIHS
VIHS
VILS
VILS
・Trigger input timing
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Symbol Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
tTRGH
tTRGL
Input pulse width
(when using as
TGIN)
-
2tCYCP
-
ns
t
TRGL
t
TRGH
V
IHS
V
IHS
VILS
VILS
TGIN
DS706-00022-1v0-E
70
MB9A100A Series
(9) UART Timing
・Synchronous serial (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Pin
name
tSCYC SCKx
Vcc ≥ 4.5V
Vcc < 4.5V
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
Symbol
Conditions
Unit
ns
Min
Max
Min
Max
4tcycp
-
4tcycp
-
SCKx
SOTx
SCKx
SINx
SCKx
SINx
tSLOVI
-30
50
0
+30
- 20
30
0
+ 20
ns
Internal shift
clock
operation
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
tSHIXI
2tcycp -
10
2tcycp -
10
tSLSH SCKx
tSHSL SCKx
-
-
tcycp +
10
tcycp +
10
-
-
SCKx
tSLOVE
-
50
-
-
30
-
External shift
clock
operation
SOTx
SCKx
SINx
SCKx
SINx
tIVSHE
10
20
10
20
tSHIXE
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: ・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time. Please see the block diagram to refer the APB bus
number which UART is connected.
・These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance = 50pF.
DS706-00022-1v0-E
71
MB9A100A Series
t SCY C
VO H
S CK
VOL
tSLOVI
V OH
S O T
V OL
tIV SH I
tSH IXI
V IH
VI H
S IN
VI L
V IL
MS b it= 0
t S L S H
t S H S L
V I H
V I H
t R
S C K
V I L
V I L
t F
t SLOVE
V O H
S O T
V O L
t I V S H E
V I H
t S H I X E
V I H
S IN
V I L
V I L
M S b it = 1
DS706-00022-1v0-E
72
MB9A100A Series
・Synchronous serial(SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Pin
name
tSCYC SCKx
Vcc ≥ 4.5V
Vcc < 4.5V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
Conditions
Unit
ns
Min
Max
Min
Max
4tcycp
-
4tcycp
-
SCKx
SOTx Internal shift
SCKx
SINx
SCKx
SINx
tSHOVI
-30
50
0
+30
- 20
30
0
+ 20
ns
clock
operation
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
2tcycp
- 10
2tcycp -
10
tSLSH SCKx
tSHSL SCKx
-
-
tcycp +
10
tcycp +
10
-
-
SCKx
tSHOVE
-
50
-
-
30
-
External shift
clock
operation
SOTx
SCKx
SINx
SCKx
SINx
tIVSLE
10
20
10
20
tSLIXE
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: ・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time. Please see the block diagram to refer the APB bus
number which UART is connected.
・These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance = 50pF.
DS706-00022-1v0-E
73
MB9A100A Series
tSC YC
VO H
S C K
VOL
t SHO VI
VOH
S O T
VOL
t IVS LI
tS LIX I
VIH
VIH
S IN
VIL
VIL
M S b it = 0
tS HSL
tSL SH
VIH
VI H
tF
S C K
S O T
S IN
V IL
tR
V IL
VI L
tSH OV E
V OH
tIV SL E
t SLI XE
M S b i t= 1
DS706-00022-1v0-E
74
MB9A100A Series
・Synchronous serial(SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Pin
name
tSCYC SCKx
Vcc ≥ 4.5V
Vcc < 4.5V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
Conditions
Unit
ns
Min
Max
Min
Max
4tcycp
-
4tcycp
-
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SOTx
tSHOVI
-30
50
0
+30
- 20
30
0
+ 20
ns
Internal shift
clock
operation
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SOT → SCK ↓ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tSLIXI
2tcycp
- 30
2tcycp -
30
tSOVLI
-
-
2tcycp
- 10
2tcycp -
10
tSLSH SCKx
tSHSL SCKx
-
-
tcycp +
10
tcycp +
10
-
-
SCKx
tSHOVE
-
50
-
-
30
-
External shift
clock
operation
SOTx
SCKx
SINx
SCKx
SINx
tIVSLE
10
20
10
20
tSLIXE
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: ・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time. Please see the block diagram to refer the APB bus
number which UART is connected.
・These characteristics only guarantees the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance = 50pF.
DS706-00022-1v0-E
75
MB9A100A Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
tIVSLI
tSLIXI
VIH
VIH
VIL
SIN
VIL
MS bit=0
tSLSH
tSHSL
VIH
VIH
VIH
SCK
VIL
VIL
tR
VIL
ｔF
tSHOVE
VOH
*2
VOH
SOT
VOL
VOL
tIVSLE
tSLIXE
VIH
VIH
VIL
SIN
VIL
*2 : Changes when writing to TDR register
MS bit=1
DS706-00022-1v0-E
76
MB9A100A Series
・Synchronous serial(SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Pin
name
Vcc ≥ 4.5V
Vcc < 4.5V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC SCKx
4tcycp
-
4tcycp
-
ns
SCKx
tSLOVI
SCK ↓ → SOT delay time
-30
+30
- 20
+ 20
ns
SOTx
Internal shift
clock
operation
SCKx
tIVSHI
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
50
0
-
-
30
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
SINx
SCKx
SINx
tSHIXI
SCKx
SOTx
2tcycp
- 30
2tcycp
- 10
tcycp +
10
2tcycp -
30
2tcycp -
10
tcycp +
10
tSOVHI
-
-
tSLSH SCKx
tSHSL SCKx
-
-
-
-
SCKx
tSLOVE
-
50
-
-
30
-
External shift
clock
operation
SOTx
SCKx
SINx
tIVSHE
10
20
10
20
SCKx
SINx
tSHIXE
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: ・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time. Please see the block diagram to refer the APB bus
number which UART is connected.
・These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance = 50pF.
DS706-00022-1v0-E
77
MB9A100A Series
tSCYC
VOH
VOH
SCK
VOL
tSLOVI
tSOVHI
VOH
VOL
VOH
VOL
SOT
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
SIN
MS bit=0
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
SOT
VIL
tSLOVE
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
SIN
MS bit=1
・External clock(EXT = 1) : asynchronous only
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Parameter
Symbol Conditions
Min
Max
Unit Remarks
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
tSLSH
tSHSL
CL = 50pF
tF
tcycp + 10
tcycp + 10
-
-
5
5
ns
ns
ns
ns
-
-
SCK rise time
tR
tR
tF
tSHSL
tSLSH
SCK
VIH
VIL
VIH
VIH
VIL
VIL
DS706-00022-1v0-E
78
MB9A100A Series
(10) External input timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Min
Parameter Symbol Pin name Conditions
Unit
Remarks
Max
A/D converter
trigger input
Free-run timer input
clock
Input capture
Wave form
ADTG
-
2tCYCP *1
-
ns
FRCKx
tINH
tINL
Input pulse width
ICxx
DTTIxX
-
-
2tCYCP *1
-
ns
generator
INT00 to INT15,
NMIX
2tCYCP + 100 *1
500 *2
-
-
ns External interrupt
NMI
ns
*1 : tCYCP indicates the APB bus clock cycle time except stop when in stop mode. Please see the block diagram to
refer the APB bus number which Multi function timer is connected.
*2 : When in stop mode, in timer mode.
tINH
tINL
VIHS
VIHS
VILS
VILS
DS706-00022-1v0-E
79
MB9A100A Series
(11) Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
Unit
Min
Max
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
tAHL
tALL
tBHL
tBLL
-
-
-
-
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
QCR:CGSC="0"
QCR:CGSC="0"
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
2tCYCP
*
-
ns
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and fall time
from determined ZIN level
Determined ZIN level from
AIN/BIN rise and fall time
tZHL
tZLL
tZABE
tABEZ
QCR:CGSC="1"
QCR:CGSC="1"
* : tCYCP indicates the APB bus clock cycle time except stop when in stop mode. Please see the block diagram to
refer the APB bus number which QPRC is connected.
tAHL
tALL
AIN
tBUAD
tAUBU
tADBD
tBDAU
BIN
tBHL
tBLL
DS706-00022-1v0-E
80
MB9A100A Series
tBHL
tBLL
BIN
tBUAU
tBDAD
tADBU
tAUBD
AIN
tAHL
tALL
tZHL
ZIN
tZLL
ZIN
tABEZ
tZABE
AIN/BIN
DS706-00022-1v0-E
81
MB9A100A Series
(12) I2C timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C )
Typical High-speed
Parameter
Symbol
fSCL
Conditions
mode
Min Max Min Max
mode
Unit Remarks
SCL clock frequency
(Repeated) START condition
hold time
0
100
-
0
400 kHz
tHDSTA
4.0
0.6
-
μs
SDA ↓ → SCL ↓
SCLclock "L" width
SCLclock "H" width
(Repeated) START setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
tHDDAT
tSUDAT
tSUSTO
4.7
0
-
0.6
0
-
μs
μs
ns
μs
CL = 50pF,
R = (Vp/IOL)
(*1)
3.45
(*2)
0.9
(*3)
250
4.0
-
-
100
0.6
-
-
Bus free time between
"STOP condition" and
"START condition"
tBUF
tSP
4.7
-
-
1.3
-
-
μs
2 tCYCP
(*4)
2 tCYCP
(*4)
Noise filter
-
ns
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL
signal.
*3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time. Please see the block diagram to refer the APB bus number which I2C
is connected. To use I2C, set the APB bus clock at 8 MHz or more.
SDA
tSUSTA
tSUDAT
tBUF
tLOW
SCL
tHDSTA
tHDDAT tHIGH
tHDSTA
tSP
tSUSTO
DS706-00022-1v0-E
82
MB9A100A Series
(13) ETM timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Min Max
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Vcc ≥ 4.5V
Vcc < 4.5V
2
9
TRACECLK
TRACED3 - 0
Data hold
tETMH
ns
2
15
Vcc ≥ 4.5V
Vcc＜4.5V
Vcc ≥ 4.5V
Vcc＜4.5V
-
-
40 MHz
32 MHz
TRACECLK
Frequency
1/tTRACE
TRACECLK
25
-
-
ns
ns
TRACECLK
clock cycle time
tTRACE
31.25
Note: When the external load capacitance = 50pF.
tC YC
H CL K
tTR A C E
V OH
V OH
V OL
TR AC E CL K
tET MH
tET MH
VO H
VO L
V OH
T RA C E D3 -0
V OL
DS706-00022-1v0-E
83
MB9A100A Series
(14) JTAG timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40°C to + 85°C)
Value
Parameter
Symbol Pin name Conditions
Unit
ns
Remarks
Min
Max
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
TMS,TDI setup
time
TCK
TMS,TDI
tJTAGS
tJTAGH
tJTAGD
15
-
TCK
TMS,TDI
TMS,TDI hold time
TDO delay time
15
-
ns
TCK
TDO
-
-
25
45
ns
Note: When the external load capacitance = 50pF.
V O H
T C K
V O L
tJTAG S
tJTAG H
V O
H
V O
V O
H
L
V O L
T M S /TM I
tJ TAG D
V O H
V O L
T D O
DS706-00022-1v0-E
84
MB9A100A Series
z 12bit A/D Converter
This chapter shows the electrical characteristics for the A/D converter.
1. Electrical characteristics for the A/D converter.
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V Ta = - 40°C to + 85°C)
Pin
name
Value
Typ
-
-
Parameter
Unit
Remarks
Min
-
- 4.5
Max
12
+ 4.5
Resolution
-
-
bit
LSB
Linearity error
Differential linearity
error
-
-2.5
- 20
- 20
-
-
-
+ 2.5
+ 20
+ 20
LSB
mV
mV
AVRH = 2.7V to 5.5V
AN0
to AN15
AN0
to AN15
-
Zero transition voltage
Full transition voltage
Conversion time
Sampling time
1.0 (*1)
*2
*2
55.5
-
-
-
-
-
-
μs AVcc ≥ 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
Ts
ns
ns
μs
Compare clock cycle *3
Tcck
-
10000
166.6(*4)
State transition time to
operation permission
Power supply current
(analog + digital)
Reference power supply
current
Tstt
2.5
-
-
-
-
2.3
0.1
3.6
2
mA A/D 1unit operation
μA When ADC stop
AVCC
A/D 1unit operation
AVRH=5.5V
-
-
-
2.2
0.03
-
3.0
0.6
mA
AVRH
(between AVRH to
AVSS)
μA When ADC stop
Analog input capacity
Analog input resistance
Cin
Rin
14.5
pF
0.93
2.04
4
AVcc ≥ 4.5V
kΩ
-
-
-
-
-
-
AVcc < 4.5V
Interchannel disparity
Analog port input
current
-
LSB
AN0
to AN15
AN0
to AN15
AVRH
5
μA
Analog input voltage
Reference voltage
AVSS
AVSS
-
-
AVRH
AVCC
V
V
*1: Conversion time is the value of sampling time(Ts) + compare time(Tc).
The condition of the minimum conversion time is when HCLK=72MHz, the value of sampling time: 0.222μs,
the value of sampling time: 778ns (AVcc ≥ 4.5V)
Ensure that it satisfies the value of sampling time(Ts) and compare clock cycle (Tcck).
For setting of sampling time and compare clock cycle, see chapter "12-bit A/D Converter" in "Peripheral
Manual".
ADC register is set at APB bus clock timing. Sampling and compare clock is set at Base clock(HCLK).
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1)
*3: Compare time (Tc) is the value of (Equation 2)
DS706-00022-1v0-E
85
MB9A100A Series
(Continued)
*4: When 12bit A/D converter is used at AVcc<4.5V, there is a limitation as follows.
It cannot be used at minimum compare clock cycle when HCLK is set over 54MHz, because maximum
compare clock division ratio is “9”(please refer FM3 PERIPHERAL MANUAL chapter “12bit A/D
converter”),
Please set the HCLK frequency under 54MHz.
AN0 to AN15
Analog input pin
comparator
Rext
Rin
Analog signal
source
Cin
(Equation 1) Ts ≥ ( Rin + Rext ) × Cin × 9
Ts : Sampling time
Rin : input resistance of A/D = 0.93kΩ 4.5 ≤ AVCC ≤ 5.5
input resistance of A/D = 2.04kΩ 2.7 ≤ AVCC < 4.5
Cin : input capacity of A/D = 14.5pF
2.7 ≤ AVCC ≤ 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Comrare clock cycle
DS706-00022-1v0-E
86
MB9A100A Series
・Definition of 12-bit A/D Converter Terms
・Resolution
・Linearity error
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion
characteristics.
・Differential linearity error : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Linearity error
Differential linearity error
0xFFF
Actual conversion
Actual conversion
characteristics
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
{1 LSB(N-1) + VOT
}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VOT
Actual conversion characteristics
AVss
AVRH
AVss
AVRH
Analog input
V
NT - {1LSB × (N - 1) + VOT}
Linearity error of digital output N =
[LSB]
1LSB
V
(N + 1) T - VNT
1LSB
Differential linearity error of digital output N =
- 1 [LSB]
V
FST - VOT
4094
1LSB =
N
: A/D converter digital output value.
VOT : Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
DS706-00022-1v0-E
87
MB9A100A Series
z Low voltage detection characteristics
1. Low voltage detection reset
(Ta = - 40°C to + 85°C)
Value
Min Typ Max
Parameter
Symbol Conditions
Unit
Remarks
Detected voltage
Released voltage
VDL
VDH
-
-
2.20
2.30
2.40
2.50
2.60
2.70
V
V
When voltage drops
When voltage rises
2. Interrupt of low voltage detection
(Ta = - 40°C to + 85°C)
Value
Min Typ Max
Parameter
Symbol Conditions
Unit
Remarks
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 0000
VDH
VDL
SVHI = 0001
VDH
VDL
SVHI = 0010
VDH
VDL
SVHI = 0011
VDH
VDL
SVHI = 0100
VDH
VDL
SVHI = 0111
VDH
VDL
SVHI = 1000
VDH
VDL
SVHI = 1001
VDH
LVD stabilization
wait time
2040 ×
tcycp *
TLVDW
-
-
-
μs
* : tCYCP indicates the APB2 bus clock cycle time.
DS706-00022-1v0-E
88
MB9A100A Series
z Flash Memory Write/Erase Characteristics
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Value
Typ
Parameter
Value
Remarks
Min
Max
Large Sector
Small Sector
0.6
3.1
Sector erase
time
Excludes write time prior to internal
erase
-
s
0.3
25
1.6
Half word (16 bit)
write time
Not including system-level overhead
time.
Excludes write time prior to internal
erase
-
-
400
μs
Chip erase time
7.2
37.6
s
Erase/write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
Remarks
1,000
10,000
100,000
20 *
10 *
5 *
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C) .
DS706-00022-1v0-E
89
MB9A100A Series
EXAMPLE OF CHARACTERISTIC
Power supply current (PLL run mode, PLL sleep mode)
Icc normal operation(PLL) temperature characteristics
Vcc:5.5V, CPU:40MHｚ, Peripheral:40MHｚ, FLASH 0Wait
Iccs sleep operation(PLL) temperature characteristics
Vcc:5.5V, Peripheral:40MHｚ
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature T a[
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
]
℃
℃
]
Temperature Ta[
Power supply current (Sub run mode)
Icc normal operation(sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, CPU/Peripheral:32KHz
Icc normal operation(sub oscillation) temperature
characteristics Vcc:5.5V, CPU/Peripheral:32KHz
1000
100
10
500
450
400
350
300
250
200
150
100
50
1
0
-40 -30 -20 -10
0
10 20 30 40
Temperature Ta[℃]
50 60 70 80
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature Ta[℃]
Power supply current (Sub sleep mode)
Iccs sleep operation(sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, Peripheral:32KHz
Iccs sleep op eration(su b oscillation) temp erature
characteristics Vcc:5.5V, Peripheral:32KHz
500
1000
100
10
450
400
350
300
250
200
150
100
50
1
0
-40 -30 -20 -10
0
10
20 30 40
50 60 70 80
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature Ta[℃]
Temperature Ta[℃]
DS706-00022-1v0-E
90
MB9A100A Series
Power supply current (Sub timer mode)
ICCT timer mode(sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, LVD is Off
ICCT timer mode(sub oscillation) temperature characteristics
Vcc:5.5V, LVD is Off
1000
100
10
500
450
400
350
300
250
200
150
100
50
1
0
-40 -30 -20 -10
0
10
20 30 40
50 60 70 80
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature Ta[℃]
Temperature Ta[℃]
Power supply current (Stop mode)
ICCH stop mode (sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, LVD is Off
ICCH stop mode (sub oscillation) temperature characteristics
Vcc:5.5V, LVD is Off
1000
100
10
500
450
400
350
300
250
200
150
100
50
1
0
-40 -30 -20 -10
0
10 20 30 40
Temperature Ta[℃]
50 60
70
80
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature Ta[℃]
DS706-00022-1v0-E
91
MB9A100A Series
ORDERING INFORMATION
Part number
Package
MB9AF102NAPMC
MB9AF104NAPMC
MB9AF105NAPMC
MB9AF102RAPMC
MB9AF104RAPMC
MB9AF105RAPMC
MB9AF102NABGL
MB9AF104NABGL
MB9AF105NABGL
MB9AF102NAPF
Plastic・LQFP(0.5mm pitch),100-pin
(FPT-100P-M20*/M23)
Plastic・LQFP(0.5mm pitch),120-pin
(FPT-120P-M21/M37)
Plastic・PFBGA(0.8mm pitch),112-pin
(BGA-112P-M04)
Plastic・QFP(0.65mm pitch),100-pin
MB9AF104NAPF
(FPT-100P-M06)
MB9AF105NAPF
* : ES product only
DS706-00022-1v0-E
92
MB9A100A Series
PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50–+00..1200 .059–+..000048
(Mounting height)
INDEX
0.10 0.10
(.004 .004)
(Stand off)
100
26
0°~8°
"A"
0.50 0.20
(.020 .008)
0.25(.010)
1
25
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
0.145 0.055
(.006 .002)
M
0.08(.003)
(.008 .002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00022-1v0-E
93
MB9A100A Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.65 g
Sealing method
Mounting height
Weight
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*
14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
1.50
-0.10
+.008
.059
-.004
(
)
(Mounting height)
0°~8°
INDEX
0.10 0.10
(.004 .004)
(Stand off)
100
26
0.50 0.20
(.020 .008)
"A"
0.25(.010)
0.60 0.15
(.024 .006)
1
25
0.50(.020)
0.22 0.05
(.009 .002)
0.145 0.055
(.006 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parenthesesare reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00022-1v0-E
94
MB9A100A Series
(Continued)
120-pin plastic LQFP
Lead pitch
0.50 mm
16.0 × 16.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.88 g
Code
(Reference)
(FPT-120P-M21)
P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 0.20(.709 .008)SQ
+0.40
16.00 –0.10
+.016
.630 –.004 SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
INDEX
0~8°
"A"
120
31
0.10 0.05
1
30
LEAD No.
(.004 .002)
0.22 0.05
(.009 .002)
0.145+–00..0035
.006+–.0021
(Stand off)
0.60 0.15
(.024 .006)
M
0.50(.020)
0.08(.003)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parenthesesare reference values.
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F120033S-c-4-7
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00022-1v0-E
95
MB9A100A Series
(Continued)
120-pin plastic LQFP
Lead pitch
0.50 mm
16.0 mm × 16.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.88 g
Code
(Reference)
(FPT-120P-M37)
P-LFQFP120-16 × 16-0.50
120-pin plastic LQFP
(FPT-120P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00± 0.20 (.709 ±. 008) SQ
*
16.00± 0.10 (.630 ±. 004) SQ
90
61
Details of "A" part
91
60
1.50+–00..1200 .059–+..000048
(Mounting height)
0.25(.010)
0.08(.003)
0˚~8˚
INDEX
0.60± 0.15
(.024±. 006)
"A"
0.10±0.05
120
31
(.004±.002)
(Stand off)
1
30
LEAD No.
0.145+–00..0035
+.002
)
(
.006–.001
0.50(.020)
0.22± 0.05
(.009±. 002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc1)-1-1
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00022-1v0-E
96
MB9A100A Series
(Continued)
112-ball plastic PFBGA
Ball pitch
0.80 mm
10.00 × 10.00 mm
Soldering ball
Plastic mold
Ф 0.45 mm
Package width ×
package length
Lead shape
Sealing method
Ball size
Mounting height
Weight
1.45 mm Max.
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00 0.10(.394 .004)
0.20(.008) S
B
0.80(.031)
REF
B
11
10
9
0.80(.031)
REF
8
A
7
10.00 0.10
(.394 .004)
6
5
4
3
2
1
L
K
J
H
G
F
E D
C
B
A
(INDEX AREA)
0.20(.008) S
1.25 0.20
(.049 .008)
(Seated height)
INDEX
0.35 0.10
(.014 .004)
(Stand off)
A
112-Ф0.45 010
(112-Ф0.18 .004)
M
Ф0.08(.003) S A B
S
0.10(.004) S
Dimensions in mm (inches).
Note: The values in parenthesesare reference values.
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00022-1v0-E
97
MB9A100A Series
DS706-00022-1v0-E
98
MB9A100A Series
DS706-00022-1v0-E
99
MB9A100A Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Tel: +1-408-737-5600
Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of
any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR
assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would
result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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