MB9AF112LPMC-G-JNE2 [CYPRESS]
32-bit ARM® Cortex®-M3 FM3 Microcontroller;
| 型号： | MB9AF112LPMC-G-JNE2 |
| 厂家： | 
CYPRESS |
| 描述： | 32-bit ARM® Cortex®-M3 FM3 Microcontroller 微控制器 |
| 文件： | 总112页 (文件大小：4178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
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For More Information
Please contact your local sales office for additional information about Cypress products and
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9A110A/MB9A110 Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9A110A/MB9A110 Series are highly integrated 32-bit microcontrollers that target for high-performance and cost-sensitive
embedded control applications.
The MB9A110A Series are based on the ARM® Cortex®-M3 Processor and on-chip Flash memory and SRAM, and peripheral
functions, including Motor Control Timers, ADCs, Communication Interfaces (UART, CSIO, I2C, LIN).
The products which are described in this datasheet are placed into TYPE1 product categories in “FM3 Family Peripheral Manual”.
Features
32-bit ARM® Cortex®-M3 Core
Processor version: r2p1
[UART]
Full duplex double buffer
Up to 40 MHz Frequency Operation
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)*
24-bit System timer (Sys Tick): System timer for OS task
management
Various error detection functions available (parity errors,
framing errors, and overrun errors)
*: MB9AF111LA, F112LA, F114LA, F112L and F114L do not
support Hardware Flow control
On-chip Memories
[Flash memory]
Up to 512 Kbyte
[CSIO]
Read cycle: 0 wait-cycle
Security function for code protection
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
[SRAM]
This Series contain a total of up to 32 Kbyte on-chip SRAM.
On-chip SRAM is composed of two independent SRAM
(SRAM0, SRAM1). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M3 core. SRAM1 is connected to System
bus.
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed 13- 16bit length)
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
LIN break delimiter generation (can be changed 1 - 4bit
length)
Multi-function Serial Interface (Max 8 channels)
4 channels with 16 steps×9bit FIFO (ch.4-ch.7), 4 channels
without FIFO (ch.0-ch3)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[I2C]
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
I2C
Cypress Semiconductor Corporation
Document Number: 002-04672 Rev. *D
• 198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2017
MB9A110A/MB9A110 Series
External Bus Interface*
Supports SRAM, NOR Flash device
Up to 8 chip selects
Multi-function Timer (Max 2 units)
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch/unit
Input capture × 4 ch/unit
8-/16-bit Data width
Output compare × 6 ch/unit
Up to 25-bit Address bit
A/D activation compare × 3 ch/unit
Waveform generator × 3 ch/unit
16-bit PPG timer × 3 ch/unit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
*: MB9AF111LA, F112LA and F114LA do not support
External Bus Interface
The following function can be used to achieve the motor
control.
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
PWM signal output function
DC chopper waveform output function
Dead timer function
8 independently configured and operated channels
Input capture function
Transfer can be started by software or request from the
built-in peripherals
A/D converter activate function
DTIF (Motor emergency stop) interrupt function
Transfer address area: 32bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Quadrature Position/Revolution Counter (QPRC)
(Max 2 units)
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
Number of transfers: 1 to 65536
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
A/D Converter (Max 16 channels)
[12-bit A/D Converter]
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Successive Approximation type
Built-in 3units*
Conversion time: 1.0 μs@5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each timer
channel.
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4steps)
*: MB9AF111LA, F112LA, F114LA built-in 2units
Free-running
Periodic (=Reload)
One-shot
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
Watch Counter
16-bit PWM timer
16-bit PPG timer
The Watch counter is used for wake up from Low-Power
Consumption mode.
Interval timer: up to 64 s(Max)@ Sub Clock: 32.768 kHz
16-/32-bit reload timer
16-/32-bit PWC timer
Document Number: 002-04672 Rev. *D
Page 2 of 111
MB9A110A/MB9A110 Series
Watch dog Timer (2 channels)
[Resets]
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Reset requests from INITX pin
Power-on reset
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
Software reset
The "Hardware" watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except STOP
modes.
Watchdog timers reset
Low-voltage detector reset
Clock Supervisor reset
External Interrupt Controller Unit
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
External clock failure (clock stop) is detected, reset is
asserted.
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
External frequency anomaly is detected, interrupt or reset is
asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage that has been set,
Low-Voltage Detector generates an interrupt or reset.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Up to 83 fast General Purpose I/O Ports@ 100 pin Package
Some ports are 5V tolerant I/O (MB9AF115MA/NA,
MB9AF116MA/NA only)
Please see "Pin Description" to confirm the corresponding
pins.
Low-Power Consumption Mode
Three Low-Power Consumption modes supported.
SLEEP
TIMER
STOP
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
Debug
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM)*
*: Mb9AF111LA/MA, F112LA/MA, F114LA/MA, F115MA and
F116MA support only SWJ-DP.
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
Power Supply
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
VCC = 2.7 V to 5.5 V: Correspond to the wide range voltage.
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock:
Main PLL Clock
100 kHz
Document Number: 002-04672 Rev. *D
Page 3 of 111
MB9A110A/MB9A110 Series
Contents
1. Product Lineup.................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 14
5. I/O Circuit Type................................................................................................................................................................ 39
6. Handling Precautions ..................................................................................................................................................... 44
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 44
Precautions for Package Mounting.............................................................................................................................. 45
Precautions for Use Environment................................................................................................................................ 46
7. Handling Devices ............................................................................................................................................................ 47
8. Block Diagram................................................................................................................................................................. 49
9. Memory Size .................................................................................................................................................................... 50
10. Memory Map .................................................................................................................................................................... 50
11. Pin Status in Each CPU State ........................................................................................................................................ 54
12. Electrical Characteristics ............................................................................................................................................... 58
12.1 Absolute Maximum Ratings......................................................................................................................................... 58
12.2 Recommended Operating Conditions.......................................................................................................................... 60
12.3 DC Characteristics....................................................................................................................................................... 61
12.3.1 Current rating............................................................................................................................................................... 61
12.3.2 Pin Characteristics ....................................................................................................................................................... 63
12.4 AC Characteristics....................................................................................................................................................... 64
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 64
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 65
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 65
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)......................................... 66
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the input clock
of the main PLL)........................................................................................................................................................... 66
12.4.6 Reset Input Characteristics .......................................................................................................................................... 67
12.4.7 Power-on Reset Timing................................................................................................................................................ 67
12.4.8 External Bus Timing..................................................................................................................................................... 68
12.4.9 Base Timer Input Timing.............................................................................................................................................. 75
12.4.10 CSIO/UART Timing .................................................................................................................................................. 76
12.4.11 External Input Timing................................................................................................................................................ 84
12.4.12 Quadrature Position/Revolution Counter timing........................................................................................................ 85
12.4.13 I2C Timing................................................................................................................................................................. 87
12.4.14 ETM timing ............................................................................................................................................................... 88
12.4.15 JTAG Timing............................................................................................................................................................. 89
12.5 12-bit A/D Converter.................................................................................................................................................... 90
12.6 Low-voltage detection characteristics.......................................................................................................................... 93
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 94
12.7.1 Write / Erase time......................................................................................................................................................... 94
12.7.2 Erase/Write cycles and data hold time......................................................................................................................... 94
12.8 Return Time from Low-Power Consumption Mode...................................................................................................... 95
12.8.1 Return Factor: Interrupt................................................................................................................................................ 95
12.8.2 Return Factor: Reset.................................................................................................................................................... 97
13. Ordering Information ...................................................................................................................................................... 99
14. Package Dimensions .................................................................................................................................................... 100
15. Errata.............................................................................................................................................................................. 107
Document Number: 002-04672 Rev. *D
Page 4 of 111
MB9A110A/MB9A110 Series
15.1 Part Numbers Affected .............................................................................................................................................. 107
15.2 Qualification Status.................................................................................................................................................... 107
15.3 Errata Summary ........................................................................................................................................................ 107
16. Major Changes .............................................................................................................................................................. 108
Document History............................................................................................................................................................... 110
Sales, Solutions, and Legal Information........................................................................................................................... 111
Document Number: 002-04672 Rev. *D
Page 5 of 111
MB9A110A/MB9A110 Series
1. Product Lineup
Memory Size
Product name
MB9AF112LA/MA/NA
MB9AF112L
MB9AF114LA/MA/NA
MB9AF114L
MB9AF111LA/MA/NA
64 Kbytes
On-chip Flash memory
On-chip SRAM
128 Kbytes
16 Kbytes
256 Kbytes
32 Kbytes
16 Kbytes
Product name
On-chip Flash memory
On-chip SRAM
MB9AF115MA/NA
MB9AF116MA/NA
384 Kbytes
32 Kbytes
512 Kbytes
32 Kbytes
Function
Product name
Pin count
MB9AF111LA
MB9AF111MA
MB9AF112MA
MB9AF114MA
MB9AF115MA
MB9AF116MA
MB9AF111NA
MB9AF112NA
MB9AF114NA
MB9AF115NA
MB9AF116NA
MB9AF112LA
MB9AF114LA
MB9AF112L
MB9AF114L
64
80
100
Cortex-M3
40 MHz
CPU
Freq.
Power supply voltage range
DMAC
2.7 V to 5.5 V
8 ch.
Addr:21-bit (Max)
Data:8-bit
CS:4 (Max)
Addr:25-bit (Max)
Data:8-/16-bit
CS:8 (Max)
External Bus Interface
-
Support: SRAM, NOR Flash
Support: SRAM, NOR Flash
8 ch. (Max)
ch.4 to ch.7: FIFO (16 steps x 9-bit)
ch.0 to ch.3: No FIFO
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
8 ch. (Max)
A/D activation
compare
3 ch.
Input capture
Free-run timer
Output compare
Waveform generator
PPG
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
1 unit
2 units (Max)
QPRC
2 ch. (Max)
1 unit
Dual Timer
Watch Counter
1 unit
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
Yes
1 ch. (SW) + 1 ch. (HW)
8 pins (Max) + NMI × 1
51 pins (Max)
9 ch. (2 units)
Yes
11 pins (Max) + NMI × 1
66 pins (Max)
16 pins (Max) + NMI × 1
83 pins (Max)
12 ch. (3 units)
16 ch. (3 units)
2 ch.
High-speed
Low-speed
4 MHz
100 kHz
Built-in CR
Debug Function
SWJ-DP
SWJ-DP/ETM
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-04672 Rev. *D
Page 6 of 111
MB9A110A/MB9A110 Series
2. Packages
MB9AF111MA
MB9AF112MA
MB9AF114MA
MB9AF115MA
MB9AF116MA
MB9AF111NA
MB9AF112NA
MB9AF114NA
MB9AF115NA
MB9AF116NA
MB9AF111LA
MB9AF112LA
MB9AF114LA
Product name
MB9AF112L
MB9AF114L
Package
LQFP:LQD064 (0.5 mm pitch)
LQFP:LQG064 (0.65 mm pitch)
QFN :VNC064 (0.5 mm pitch)
LQFP:LQH080 (0.5 mm pitch)
LQFP:LQI100 (0.65 mm pitch)
QFP :PQH100 (0.65 mm pitch)
BGA :LBC112 (0.8 mm pitch)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
*
-
-
-
-
-
-
: Supported
*: MB9AF115NA, MB9AF116NA are planning
Note:
−
Refer to “14. Package Dimensions” for detailed information on each package.
Document Number: 002-04672 Rev. *D
Page 7 of 111
MB9A110A/MB9A110 Series
3. Pin Assignment
LQI100
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
75 VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
P56/INT08_2/DTTI1X_0/MADATA06_1
74 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
73 P21/SIN0_0/INT06_1/BIN1_1
72 P22/SOT0_0/TIOB7_1/ZIN1_1
71 P23/SCK0_0/TIOA7_1/RTO00_1
70 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
69 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
68 P1D/AN13/CTS4_1/IC03_1/MAD21_1
67 P1C/AN12/SCK4_1/IC02_1/MAD20_1
66 P1B/AN11/SOT4_1/IC01_1/MAD19_1
65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
64 P19/AN09/SCK2_2/MAD17_1
63 P18/AN08/SOT2_2/MAD16_1
62 AVSS
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12
P34/FRCK0_0/TIOB4_1/MADATA11_1 13
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 14
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 15
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 16
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 17
P39/DTTI0X_0/ADTG_2 18
LQFP - 100
61 AVRH
60 AVCC
59 P17/AN07/SIN2_2/INT04_1/MAD15_1
58 P16/AN06/SCK0_1/MAD14_1
57 P15/AN05/SOT0_1/IC03_2/MAD13_1
56 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
55 P13/AN03/SCK1_1/IC01_2/MAD11_1
54 P12/AN02/SOT1_1/IC00_2/MAD10_1
53 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
52 P10/AN00
P3A/RTO00_0/TIOA0_1 19
P3B/RTO01_0/TIOA1_1 20
P3C/RTO02_0/TIOA2_1 21
P3D/RTO03_0/TIOA3_1 22
P3E/RTO04_0/TIOA4_1 23
P3F/RTO05_0/TIOA5_1 24
VSS 25
51 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 8 of 111
MB9A110A/MB9A110 Series
PQH100
(TOP VIEW)
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 81
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 82
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 83
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 84
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 85
P56/INT08_2/DTTI1X_0/MADATA06_1 86
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 87
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90
P34/FRCK0_0/TIOB4_1/MADATA11_1 91
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 92
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 93
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 94
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 95
P39/DTTI0X_0/ADTG_2 96
50 P22/SOT0_0/TIOB7_1/ZIN1_1
49 P23/SCK0_0/TIOA7_1/RTO00_1
48 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
47 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
46 P1D/AN13/CTS4_1/IC03_1/MAD21_1
45 P1C/AN12/SCK4_1/IC02_1/MAD20_1
44 P1B/AN11/SOT4_1/IC01_1/MAD19_1
43 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
42 P19/AN09/SCK2_2/MAD17_1
41 P18/AN08/SOT2_2/MAD16_1
40 AVSS
QFP - 100
39 AVRH
38 AVCC
37 P17/AN07/SIN2_2/INT04_1/MAD15_1
36 P16/AN06/SCK0_1/MAD14_1
35 P15/AN05/SOT0_1/IC03_2/MAD13_1
34 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
33 P13/AN03/SCK1_1/IC01_2/MAD11_1
32 P12/AN02/SOT1_1/IC00_2/MAD10_1
31 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
P3A/RTO00_0/TIOA0_1 97
P3B/RTO01_0/TIOA1_1 98
P3C/RTO02_0/TIOA2_1 99
P3D/RTO03_0/TIOA3_1 100
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 9 of 111
MB9A110A/MB9A110 Series
LQH080
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
P56/INT08_2/DTTI1X_0/MADATA06_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
P39/DTTI0X_0/ADTG_2
1
2
60 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
59 P21/SIN0_0/INT06_1/BIN1_1
58 P22/SOT0_0/TIOB7_1/ZIN1_1
57 P23/SCK0_0/TIOA7_1
3
4
5
56 P1B/AN11/SOT4_1/IC01_1/MAD19_1
55 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
54 P19/AN09/SCK2_2/MAD17_1
53 P18/AN08/SOT2_2/MAD16_1
52 AVSS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1/MAD15_1
48 P16/AN06/SCK0_1/MAD14_1
47 P15/AN05/SOT0_1/IC03_2/MAD13_1
46 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
45 P13/AN03/SCK1_1/IC01_2/MAD11_1
44 P12/AN02/SOT1_1/IC00_2/MAD10_1
43 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
42 P10/AN00
P3A/RTO00_0/TIOA0_1
P3B/RTO01_0/TIOA1_1
P3C/RTO02_0/TIOA2_1
P3D/RTO03_0/TIOA3_1
P3E/RTO04_0/TIOA4_1
P3F/RTO05_0/TIOA5_1
VSS
41 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 10 of 111
MB9A110A/MB9A110 Series
LQD064/LQG064
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
48 P21/SIN0_0/INT06_1
47 P22/SOT0_0/TIOB7_1
46 P23/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P50/INT00_0/AIN0_2/SIN3_1
P51/INT01_0/BIN0_2/SOT3_1
P52/INT02_0/ZIN0_2/SCK3_1
P30/AIN0_0/TIOB0_1/INT03_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/ADTG_2
42 AVRH
LQFP - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05/IC03_2
38 P14/AN04/INT03_1/IC02_2
37 P13/AN03/SCK1_1/IC01_2
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2
34 P10/AN00
P3A/RTO00_0/TIOA0_1 10
P3B/RTO01_0/TIOA1_1 11
P3C/RTO02_0/TIOA2_1 12
P3D/RTO03_0/TIOA3_1 13
P3E/RTO04_0/TIOA4_1 14
P3F/RTO05_0/TIOA5_1 15
VSS 16
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 11 of 111
MB9A110A/MB9A110 Series
LBC112
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
TRSTX
VSS
VCC
P50
P53
P30
P34
P37
P3B
VCC
VCC
VSS
P81
VSS
P51
P54
P31
P35
P38
P3C
P3F
VSS
C
P80
P52
VSS
P55
P32
P36
P3A
P3E
VSS
X1A
X0A
VCC
P61
P60
VSS
P33
P39
P3D
VSS
P40
INITX
VSS
P0E
P0F
P62
P0B
P0C
P0D
P63
P07
P08
P09
P0A
VCC
VSS
P20
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P05
VSS
P22
VSS
P06
P21
P56
P23
AN15
AN11
Index
AN14
AN10
AN07
AN04
VSS
MD1
X0
AN12
AN13
AN08
VSS
AN02
P4E
AN09 AVRH
AN06 AVSS
AN03 AVCC
G
H
J
P44
P43
P42
P41
P4C
P49
P48
P45
AN05
P4D
P4B
P4A
AN01
VSS
X1
AN00
VCC
VSS
K
L
MD0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 12 of 111
MB9A110A/MB9A110 Series
VNC064
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1
1
2
3
4
5
6
7
8
9
48 P21/SIN0_0/INT06_1
47 P22/SOT0_0/TIOB7_1
46 P23/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P51/INT01_0/BIN0_2/SOT3_1
P52/INT02_0/ZIN0_2/SCK3_1
P30/AIN0_0/TIOB0_1/INT03_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/ADTG_2
42 AVRH
QFN - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05/IC03_2
38 P14/AN04/INT03_1/IC02_2
37 P13/AN03/SCK1_1/IC01_2
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2
34 P10/AN00
P3A/RTO00_0/TIOA0_1 10
P3B/RTO01_0/TIOA1_1 11
P3C/RTO02_0/TIOA2_1 12
P3D/RTO03_0/TIOA3_1 13
P3E/RTO04_0/TIOA4_1 14
P3F/RTO05_0/TIOA5_1 15
VSS 16
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 13 of 111
MB9A110A/MB9A110 Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
79
BGA-112
B1
LQFP-80
1
1
2
1
2
VCC
P50
-
INT00_0
AIN0_2
SIN3_1
2
80
C1
E
H
RTO10_0
(PPG10_0)
-
MADATA00_1
P51
INT01_0
BIN0_2
3
-
SOT3_1
(SDA3_1)
3
81
C2
3
E
H
RTO11_0
(PPG10_0)
MADATA01_1
P52
INT02_0
ZIN0_2
4
-
SCK3_1
(SCL3_1)
4
82
B3
4
E
H
RTO12_0
(PPG12_0)
MADATA02_1
P53
SIN6_0
TIOA1_2
INT07_2
5
83
D1
5
-
E
H
RTO13_0
(PPG12_0)
MADATA03_1
P54
SOT6_0
(SDA6_0)
6
84
D2
6
-
TIOB1_2
E
I
RTO14_0
(PPG14_0)
MADATA04_1
Document Number: 002-04672 Rev. *D
Page 14 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P55
SCK6_0
(SCL6_0)
7
85
D3
7
-
-
ADTG_1
E
I
RTO15_0
(PPG14_0)
MADATA05_1
P56
INT08_2
DTTI1X_0
MADATA06_1
P30
8
9
86
87
D5
E1
8
9
E
E
H
H
AIN0_0
5
-
TIOB0_1
INT03_2
MADATA07_1
P31
BIN0_0
TIOB1_1
6
-
10
88
E2
10
E
H
SCK6_1
(SCL6_1)
INT04_2
MADATA08_1
P32
ZIN0_0
TIOB2_1
7
11
89
E3
11
E
H
SOT6_1
(SDA6_1)
INT05_2
MADATA09_1
P33
-
INT04_0
TIOB3_1
SIN6_1
8
12
13
90
91
E4
F1
12
E
E
H
ADTG_6
MADATA10_1
P34
-
-
FRCK0_0
TIOB4_1
MADATA11_1
-
I
Document Number: 002-04672 Rev. *D
Page 15 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P35
IC03_0
14
92
F2
-
-
-
-
TIOB5_1
INT08_1
MADATA12_1
P36
E
H
H
IC02_0
15
16
93
94
F3
SIN5_2
E
E
INT09_1
MADATA13_1
P37
IC01_0
SOT5_2
(SDA5_2)
G1
-
-
-
H
H
INT10_1
MADATA14_1
P38
IC00_0
SCK5_2
(SCL5_2)
17
95
G2
-
E
INT11_1
MADATA15_1
P39
18
19
96
97
F4
13
14
9
DTTI0X_0
ADTG_2
P3A
E
I
I
RTO00_0
(PPG00_0)
G3
10
11
12
G
TIOA0_1
P3B
RTO01_0
(PPG00_0)
20
21
98
99
H1
H2
15
16
G
G
I
I
I
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
P3D
RTO03_0
(PPG02_0)
22
-
100
-
G4
B2
17
-
13
-
G
-
TIOA3_1
VSS
Document Number: 002-04672 Rev. *D
Page 16 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P3E
RTO04_0
(PPG04_0)
23
1
2
H3
18
14
G
I
I
TIOA4_1
P3F
RTO05_0
(PPG04_0)
24
J2
19
15
G
TIOA5_1
VSS
25
26
3
4
L1
J1
20
-
16
-
-
-
VCC
P40
TIOA0_0
27
5
J4
-
-
G
H
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
28
29
30
6
7
8
L5
K5
J5
-
-
-
-
-
-
G
G
G
H
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
I
RTO12_1
(PPG12_1)
P43
TIOA3_0
I
RTO13_1
(PPG12_1)
ADTG_7
P44
21
-
TIOA4_0
MAD00_1
31
32
9
H5
L6
-
-
G
G
I
I
RTO14_1
(PPG14_1)
P45
22
-
TIOA5_0
MAD01_1
10
RTO15_1
(PPG14_1)
-
-
-
-
-
-
K2
J3
-
-
-
-
-
-
VSS
VSS
VSS
-
-
-
H4
Document Number: 002-04672 Rev. *D
Page 17 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
17
LQFP-100
33
QFP-100
11
BGA-112
LQFP-80
23
L2
C
-
-
-
34
35
12
13
L4
24
25
-
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
K1
18
36
14
L3
26
19
D
M
37
38
15
16
K3
K4
27
28
20
21
D
B
N
C
DTTI1X_1
INT14_1
SIN3_2
MAD02_1
P49
39
17
K6
29
-
E
H
22
-
TIOB0_0
AIN0_1
IC10_1
40
18
J6
30
E
I
SOT3_2
(SDA3_2)
MAD03_1
P4A
23
-
TIOB1_0
BIN0_1
IC11_1
41
42
43
19
20
21
L7
K7
H6
31
32
33
E
I
I
I
SCK3_2
(SCL3_2)
MAD04_1
P4B
24
-
TIOB2_0
ZIN0_1
IC12_1
MAD05_1
P4C
E
TIOB3_0
25
-
SCK7_1
(SCL7_1)
E / I*
AIN1_2
IC13_1
MAD06_1
Document Number: 002-04672 Rev. *D
Page 18 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P4D
TIOB4_0
26
SOT7_1
(SDA7_1)
44
22
J7
34
E / I*
I
I
BIN1_2
FRCK1_1
MAD07_1
P4E
-
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MAD08_1
MD1
27
45
23
K8
35
E / I*
-
46
47
48
24
25
26
K9
L8
L9
36
37
38
28
29
30
C
J
P
D
A
PE0
MD0
X0
A
PE2
X1
49
27
L10
39
31
A
B
K
L
PE3
50
51
28
29
L11
K11
40
41
32
33
VSS
-
-
VCC
P10
52
53
30
31
J11
J10
42
43
34
F
F
AN00
P11
AN01
35
-
SIN1_1
INT02_1
FRCK0_2
MAD09_1
P12
AN02
36
SOT1_1
(SDA1_1)
54
32
J8
44
F
K
IC00_2
MAD10_1
VSS
-
-
-
-
-
-
-
K10
J9
-
-
-
-
VSS
Document Number: 002-04672 Rev. *D
Page 19 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P13
AN03
37
SCK1_1
(SCL1_1)
55
33
H10
45
F
K
IC01_2
MAD11_1
P14
-
AN04
38
INT03_1
IC02_2
SIN0_1
MAD12_1
P15
56
57
34
35
H9
H7
46
47
F
F
L
-
39
AN05
IC03_2
K
SOT0_1
(SDA0_1)
-
-
MAD13_1
P16
AN06
58
59
36
37
G10
G9
48
49
F
F
K
L
SCK0_1
(SCL0_1)
MAD14_1
P17
AN07
40
SIN2_2
INT04_1
MAD15_1
AVCC
AVRH
AVSS
-
60
61
62
38
39
40
H11
F11
G11
50
51
52
41
42
43
-
-
-
P18
AN08
44
-
63
41
G8
53
F
K
K
SOT2_2
(SDA2_2)
MAD16_1
P19
AN09
45
SCK2_2
(SCL2_2)
64
-
42
-
F10
H8
54
-
F
-
-
-
MAD17_1
VSS
Document Number: 002-04672 Rev. *D
Page 20 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P1A
AN10
SIN4_1
INT05_1
IC00_1
MAD18_1
P1B
65
43
F9
55
-
F
L
AN11
SOT4_1
(SDA4_1)
66
67
44
45
E11
E10
56
-
-
F
F
K
K
IC01_1
MAD19_1
P1C
AN12
SCK4_1
(SCL4_1)
-
IC02_1
MAD20_1
P1D
AN13
68
69
70
46
47
48
F8
-
-
-
-
-
-
CTS4_1
IC03_1
MAD21_1
P1E
F
F
F
K
K
K
AN14
E9
RTS4_1
DTTI0X_1
MAD22_1
P1F
AN15
D11
ADTG_5
FRCK0_1
MAD23_1
VSS
-
-
-
-
B10
C9
-
-
-
-
-
-
VSS
Document Number: 002-04672 Rev. *D
Page 21 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P23
SCK0_0
(SCL0_0)
57
46
71
49
D10
E
I
TIOA7_1
RTO00_1
(PPG00_1)
-
-
P22
SOT0_0
(SDA0_0)
47
72
73
50
51
E8
58
E
E
I
TIOB7_1
ZIN1_1
P21
-
48
-
SIN0_0
INT06_1
BIN1_1
P20
C11
59
60
H
INT05_0
CROUT_0
AIN1_1
MAD24_1
VSS
74
52
C10
-
E
H
75
76
53
54
A11
A10
-
-
-
-
-
-
VCC
P00
49
-
77
78
79
80
81
55
56
57
58
59
A9
B9
B11
A8
B8
61
62
63
64
65
TRSTX
MCSX7_1
P01
E
E
E
E
E
E
E
E
E
E
50
TCK
SWCLK
P02
51
-
TDI
MCSX6_1
P03
52
53
TMS
SWDIO
P04
TDO
SWO
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
MCSX5_1
VSS
82
-
60
-
C8
D8
-
-
-
-
E
-
F
Document Number: 002-04672 Rev. *D
Page 22 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P06
TRACED1
TIOB5_2
83
61
D9
-
-
-
E
F
SOT4_2
(SDA4_2)
INT01_1
MCSX4_1
P07
66
-
ADTG_0
MCLKOUT_1
TRACED2
84
62
A7
E
G
SCK4_2
(SCL4_2)
P08
TRACED3
TIOA0_2
CTS4_2
MCSX3_1
P09
85
86
87
63
64
65
B7
C7
D7
-
-
-
E
G
G
H
TRACECLK
TIOB0_2
RTS4_2
MCSX2_1
P0A
-
E
54
-
SIN4_0
INT00_2
FRCK1_0
MCSX1_1
P0B
67
E / I*
SOT4_0
(SDA4_0)
55
-
88
89
66
67
A6
B6
68
69
E / I*
I
I
TIOB6_1
IC10_0
MCSX0_1
P0C
SCK4_0
(SCL4_0)
56
-
E / I*
TIOA6_1
IC11_0
MALE_1
VSS
-
-
-
-
D4
C3
-
-
-
-
-
-
VSS
Document Number: 002-04672 Rev. *D
Page 23 of 111
MB9A110A/MB9A110 Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
P0D
RTS4_0
TIOA3_2
IC12_0
MDQM0_1
P0E
90
68
C6
70
-
-
E
I
I
CTS4_0
TIOB3_2
IC13_0
MDQM1_1
P0F
91
69
A5
71
E
92
93
70
71
B5
D6
72
73
57
-
NMIX
E
E
J
CROUT_1
P63
INT03_0
MWEX_1
P62
H
SCK5_0
(SCL5_0)
58
-
94
95
96
72
73
74
C5
B4
C4
74
75
76
E
I
ADTG_3
MOEX_1
P61
SOT5_0
(SDA5_0)
59
E
I
TIOB2_2
P60
SIN5_0
TIOA2_2
INT15_1
MRDY_1
VCC
60
E / I*
H
-
97
75
76
77
78
A4
A3
A2
A1
77
78
79
80
61
62
63
64
-
98
P80
H
H
-
O
O
99
P81
100
VSS
*: 5V tolerant I/O on MB9AF115MA/NA and MB9AF116MA/NA
Document Number: 002-04672 Rev. *D
Page 24 of 111
MB9A110A/MB9A110 Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Module
ADC
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
62
BGA-112 LQFP-80
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
84
7
A7
D3
F4
66
7
-
85
96
72
-
-
18
94
-
13
74
-
9
C5
-
58
-
A/D converter external trigger input
pin
70
12
30
-
48
90
8
D11
E4
J5
-
-
12
-
8
-
-
-
-
-
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
27
19
85
40
9
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
5
J11
J10
J8
42
43
44
45
46
47
48
49
53
54
55
56
-
34
35
36
37
38
39
-
AN01
AN02
AN03
H10
H9
H7
G10
G9
G8
F10
F9
AN04
AN05
AN06
AN07
40
44
45
-
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN08
AN09
AN10
AN11
E11
E10
F8
-
AN12
-
AN13
-
-
AN14
E9
D11
J4
-
-
AN15
-
-
Base Timer
0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
-
-
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
97
63
18
87
64
6
G3
B7
J6
14
-
10
-
30
9
22
5
E1
C7
L5
86
28
20
5
-
-
Base Timer
1
-
-
98
83
19
88
84
H1
D1
L7
15
5
11
-
41
10
6
31
10
6
23
6
E2
D2
-
Document Number: 002-04672 Rev. *D
Page 25 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112 LQFP-80
Base Timer
2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_1
TIOB6_1
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
29
21
96
42
11
95
30
22
90
43
12
91
31
23
-
7
K5
H2
C4
K7
E3
B4
J5
G4
C6
H6
E4
A5
H5
H3
-
-
-
Base timer ch.2 TIOA pin
99
74
20
89
73
8
16
76
32
11
75
-
12
60
24
7
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
59
-
Base Timer
3
100
68
21
90
69
9
17
70
33
12
71
21
18
-
13
-
25
8
-
Base Timer
4
-
1
14
-
-
44
13
-
22
91
-
J7
F1
-
34
-
26
-
-
-
Base Timer
5
32
24
82
45
14
83
89
88
-
10
2
L6
J2
C8
K8
F2
D9
B6
A6
-
22
19
-
-
15
-
60
23
92
61
67
66
-
35
-
27
-
-
-
Base Timer
6
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
69
68
-
56
55
-
Base Timer
7
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
71
-
49
-
D10
-
57
-
46
-
-
-
-
-
-
72
-
50
-
E8
-
58
-
47
-
Document Number: 002-04672 Rev. *D
Page 26 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
56
BGA-112 LQFP-80
Debugger
Serial wire debug interface clock
SWCLK
SWDIO
78
80
B9
A8
62
64
50
52
input
Serial wire debug interface data input
/ output
58
SWO
Serial wire viewer output
JTAG test clock input
81
78
79
81
80
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
59
56
57
59
58
64
60
61
62
63
55
9
B8
65
62
63
65
64
-
53
50
51
53
52
-
TCK
B9
TDI
JTAG test data input
B11
B8
TDO
JTAG debug data output
JTAG test mode state input/output
Trace CLK output of ETM
TMS
A8
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
C7
C8
D9
A7
-
-
-
-
Trace data output of ETM
JTAG test reset input
-
-
B7
-
-
A9
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
-
49
-
External
Bus
MAD00_1
MAD01_1
MAD02_1
MAD03_1
MAD04_1
MAD05_1
MAD06_1
MAD07_1
MAD08_1
MAD09_1
MAD10_1
MAD11_1
MAD12_1
MAD13_1
MAD14_1
MAD15_1
MAD16_1
MAD17_1
MAD18_1
MAD19_1
MAD20_1
MAD21_1
MAD22_1
MAD23_1
MAD24_1
H5
L6
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
-
K6
-
J6
-
L7
-
K7
-
H6
J7
-
-
K8
-
J10
J8
-
-
H10
H9
H7
G10
G9
G8
F10
F9
-
External bus interface address bus
-
-
-
-
-
-
-
E11
E10
F8
-
-
-
-
E9
-
-
D11
C10
-
-
60
-
Document Number: 002-04672 Rev. *D
Page 27 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
66
BGA-112 LQFP-80
External
Bus
MCSX0_1
MCSX1_1
MCSX2_1
MCSX3_1
MCSX4_1
MCSX5_1
MCSX6_1
MCSX7_1
MDQM0_1
MDQM1_1
88
87
86
85
83
82
79
77
90
91
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
-
-
65
64
63
61
60
57
55
68
69
-
-
-
-
-
-
-
-
-
-
External bus interface chip select
output pin
-
-
63
61
70
71
External bus interface byte mask
signal output
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
MOEX_1
MWEX_1
94
93
72
71
C5
D6
74
73
-
-
MADATA00_1
MADATA01_1
MADATA02_1
MADATA03_1
MADATA04_1
MADATA05_1
MADATA06_1
MADATA07_1
MADATA08_1
MADATA09_1
MADATA10_1
MADATA11_1
MADATA12_1
MADATA13_1
MADATA14_1
MADATA15_1
2
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
2
3
4
5
6
7
8
9
10
11
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
4
5
6
7
8
9
External bus interface data bus
10
11
12
13
14
15
16
17
-
-
-
-
Address Latch enable signal for
multiplex
MALE_1
89
67
B6
69
-
MRDY_1
MCLKOUT_1
External RDY input signal
External bus clock output
96
84
74
62
C4
A7
76
66
-
-
Document Number: 002-04672 Rev. *D
Page 28 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
80
BGA-112 LQFP-80
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
2
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
E4
G9
E2
C10
F9
2
2
External interrupt request 00
input pin
82
87
3
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
-
-
67
3
54
3
External interrupt request 01
input pin
83
4
-
-
4
4
External interrupt request 02
input pin
53
93
56
9
43
73
46
9
35
-
External interrupt request 03
input pin
38
5
12
59
10
74
65
11
73
45
12
49
10
60
55
11
59
35
8
External interrupt request 04
input pin
40
6
-
External interrupt request 05
input pin
-
E3
C11
K8
7
48
27
External interrupt request 06
input pin
External interrupt request 07
input pin
INT07_2
5
83
D1
5
-
INT08_1
INT08_2
14
8
92
86
F2
D5
-
-
-
External interrupt request 08
input pin
8
External interrupt request 09
input pin
External interrupt request 10
input pin
External interrupt request 11
input pin
External interrupt request 12
input pin
External interrupt request 13
input pin
External interrupt request 14
input pin
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
15
16
17
27
28
39
93
94
95
5
F3
G1
G2
J4
-
-
-
-
-
-
-
-
-
-
6
L5
K6
-
17
29
External interrupt request 15
input pin
Non-Maskable Interrupt input
INT15_1
NMIX
96
92
74
70
C4
B5
76
72
60
57
Document Number: 002-04672 Rev. *D
Page 29 of 111
MB9A110A/MB9A110 Series
Pin No
Module
GPIO
Pin name
P00
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
55
BGA-112 LQFP-80
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
A9
B9
B11
A8
B8
61
62
63
64
65
-
49
50
51
52
53
-
-
-
-
-
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
C8
D9
-
A7
B7
66
-
General-purpose I/O port 0
C7
-
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
-
54
55
56
-
-
57
34
35
36
37
38
39
-
40
44
45
-
-
-
-
-
-
-
48
47
46
H7
G10
G9
G8
F10
F9
E11
E10
F8
General-purpose I/O port 1
-
E9
-
D11
C10
C11
E8
-
60
59
58
57
General-purpose I/O port 2
D10
Document Number: 002-04672 Rev. *D
Page 30 of 111
MB9A110A/MB9A110 Series
Pin No
Module
GPIO
Pin name
P30
Function
LQFP-64
QFN-64
5
6
7
8
-
-
-
-
-
9
10
11
12
13
14
15
-
LQFP-100
QFP-100
87
BGA-112 LQFP-80
9
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
9
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
10
11
12
-
-
-
-
-
General-purpose I/O port 3
13
14
15
16
17
18
19
-
J4
L5
-
-
-
-
-
K5
J5
-
-
H5
L6
L3
K3
K6
J6
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
-
19
20
-
22
23
24
25
26
27
2
3
4
-
-
-
-
60
59
58
-
62
63
28
30
31
General-purpose I/O port 4
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
L10
Document Number: 002-04672 Rev. *D
Page 31 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Serial
0
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
51
BGA-112 LQFP-80
SIN0_0
SIN0_1
73
56
C11
H9
59
46
48
-
Multifunction serial interface ch.0
input pin
34
Multifunction serial interface ch.0
output pin.
SOT0_0
(SDA0_0)
72
57
71
50
E8
58
47
57
47
-
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2)
and as SCL0 when it is used in an I2C
(operation mode 4).
SOT0_1
(SDA0_1)
35
49
H7
SCK0_0
(SCL0_0)
D10
46
SCK0_1
(SCL0_1)
58
53
36
31
G10
J10
48
43
-
Multi
Function
Serial
1
Multifunction serial interface ch.1
input pin
Multifunction serial interface ch.1
output pin.
SIN1_1
35
SOT1_1
(SDA1_1)
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA1 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.1
clock I/O pin.
54
32
J8
44
36
SCK1_1
(SCL1_1)
This pin operates as SCK1 when it is
used in a CSIO (operation mode 2)
and as SCL1 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.2
input pin
55
59
63
33
37
41
H10
G9
45
49
53
37
40
44
Multi
Function
Serial
2
SIN2_2
Multifunction serial interface ch.2
output pin.
SOT2_2
(SDA2_2)
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.2
clock I/O pin.
G8
SCK2_2
(SCL2_2)
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
64
42
F10
54
45
Multi
Function
Serial
3
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
2
39
80
17
C1
K6
2
29
2
-
Multifunction serial interface ch.3
input pin
Multifunction serial interface ch.3
output pin.
3
81
18
82
19
C2
J6
B3
L7
3
3
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a CSIO (operation mode 2)
and as SCL3 when it is used in an I2C
(operation mode 4).
SOT3_2
(SDA3_2)
40
4
30
4
-
SCK3_1
(SCL3_1)
4
-
SCK3_2
(SCL3_2)
41
31
Document Number: 002-04672 Rev. *D
Page 32 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Serial
4
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
65
BGA-112 LQFP-80
SIN4_0
SIN4_1
SIN4_2
87
65
82
D7
F9
C8
67
55
-
54
-
Multifunction serial interface ch.4
input pin
43
60
-
SOT4_0
(SDA4_0)
88
66
83
89
67
84
66
44
61
67
45
62
A6
68
56
-
55
-
Multifunction serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
SOT4_1
(SDA4_1)
E11
D9
SOT4_2
(SDA4_2)
-
SCK4_0
(SCL4_0)
B6
69
-
56
-
Multifunction serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2)
and as SCL4 when it is used in an I2C
(operation mode 4).
SCK4_1
(SCL4_1)
E10
A7
SCK4_2
(SCL4_2)
-
-
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_2
90
69
86
91
68
85
96
15
68
47
64
69
46
63
74
93
C6
E9
C7
A5
F8
B7
C4
F3
70
-
-
Multifunction serial interface ch.4
RTS output pin
-
-
-
71
-
-
Multifunction serial interface ch.4
CTS input pin
-
-
-
Multi
Function
Serial
5
76
-
60
-
Multifunction serial interface ch.5
input pin
Multifunction serial interface ch.5
output pin.
SOT5_0
(SDA5_0)
95
16
94
17
73
94
72
95
B4
G1
C5
G2
75
-
59
-
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
74
-
58
-
SCK5_2
(SCL5_2)
Document Number: 002-04672 Rev. *D
Page 33 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Serial
6
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
83
BGA-112 LQFP-80
SIN6_0
SIN6_1
5
D1
E4
5
-
Multifunction serial interface ch.6
input pin
12
90
12
8
Multifunction serial interface ch.6
output pin.
SOT6_0
(SDA6_0)
6
84
D2
E3
D3
6
-
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2)
and as SCL6 when it is used in an I2C
(operation mode 4).
SOT6_1
(SDA6_1)
11
7
89
85
11
7
7
-
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
10
45
88
23
E2
K8
10
35
6
Multi
Function
Serial
7
Multifunction serial interface ch.7
input pin
Multifunction serial interface ch.7
output pin.
SIN7_1
27
SOT7_1
(SDA7_1)
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2)
and as SCL7 when it is used in an I2C
(operation mode 4).
44
43
22
21
J7
34
33
26
25
SCK7_1
(SCL7_1)
H6
Document Number: 002-04672 Rev. *D
Page 34 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Timer
0
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
96
BGA-112 LQFP-80
Input signal of waveform generator to
control outputs RTO00 to RTO05 of
multi-function timer 0
DTTI0X_0
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
18
69
13
70
53
17
65
54
16
66
55
15
67
56
14
68
57
F4
13
-
9
-
47
91
48
31
95
43
32
94
44
33
93
45
34
92
46
35
E9
F1
-
-
16-bit free-run timer external clock
input pin
D11
J10
G2
F9
-
-
43
-
35
-
IC00_1
55
44
-
-
IC00_2
J8
36
-
IC01_0
G1
E11
H10
F3
IC01_1
56
45
-
-
16-bit input capture input pin of
multi-function timer 0.
ICxx describes channel number.
IC01_2
37
-
IC02_0
IC02_1
E10
H9
F2
-
-
IC02_2
46
-
38
-
IC03_0
IC03_1
F8
-
-
IC03_2
H7
47
39
RTO00_0
(PPG00_0)
Waveform generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG 0 output mode.
19
71
97
49
G3
14
-
10
-
RTO00_1
(PPG00_1)
D10
Waveform generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG 0 output mode.
RTO01_0
(PPG00_0)
20
21
22
23
24
98
99
100
1
H1
H2
G4
H3
J2
15
16
17
18
19
11
12
13
14
15
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
2
Document Number: 002-04672 Rev. *D
Page 35 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Timer
1
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
86
BGA-112 LQFP-80
Input signal of waveform generator to
control outputs RTO10 to RTO15 of
multi-function timer 1
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
8
D5
K6
D7
J7
8
-
39
87
44
88
40
89
41
90
42
91
43
17
65
22
66
18
67
19
68
20
69
21
29
67
34
68
30
69
31
70
32
71
33
-
-
-
-
-
-
-
-
-
-
-
16-bit free-run timer ch.1 external
clock input pin
A6
J6
IC10_1
IC11_0
B6
L7
C6
K7
A5
H6
16-bit input capture input pin of
multi-function timer 1.
ICxx describes channel number.
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG10 when it
is used in PPG 1 output mode.
2
80
5
C1
J4
2
-
-
-
-
-
-
-
-
-
-
-
-
-
RTO10_1
(PPG10_1)
27
3
RTO11_0
(PPG10_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG10 when it
is used in PPG 1 output mode.
81
6
C2
L5
B3
K5
D1
J5
3
-
RTO11_1
(PPG10_1)
28
4
RTO12_0
(PPG12_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG12 when it
is used in PPG 1 output mode.
82
7
4
-
RTO12_1
(PPG12_1)
29
5
RTO13_0
(PPG12_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG12 when it
is used in PPG 1 output mode.
83
8
5
-
RTO13_1
(PPG12_1)
30
6
RTO14_0
(PPG14_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG14 when it
is used in PPG 1 output mode.
84
9
D2
H5
D3
L6
6
21
7
22
RTO14_1
(PPG14_1)
31
7
RTO15_0
(PPG14_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG14 when it
is used in PPG 1 output mode.
85
10
RTO15_1
(PPG14_1)
32
Document Number: 002-04672 Rev. *D
Page 36 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
87
BGA-112 LQFP-80
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
9
E1
J6
9
5
QPRC ch.0 AIN input pin
40
2
18
80
88
19
81
89
20
82
52
21
51
22
50
23
30
2
22
2
C1
E2
L7
10
41
3
10
31
3
6
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
23
3
C2
E3
K7
B3
C10
H6
C11
J7
11
42
4
11
32
4
7
24
4
Quadrature
Position/
Revolution
Counter
1
74
43
73
44
72
45
60
33
59
34
58
35
-
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
25
-
26
-
E8
K8
27
Document Number: 002-04672 Rev. *D
Page 37 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Reset
Pin name
Function
LQFP-64
QFN-64
LQFP-100
QFP-100
16
BGA-112 LQFP-80
External Reset Input. A reset is valid
when INITX="L"
Mode 0 pin.
During normal operation, MD0="L"
must be input. During serial
programming to flash memory,
MD0="H" must be input.
Mode 1 pin.
During serial programming to flash
memory, MD1="L" must be input.
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
GND pin
INITX
38
K4
L8
28
21
Mode
MD0
47
46
25
37
29
MD1
24
K9
36
28
Power
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
1
79
4
B1
J1
1
-
1
-
26
35
51
76
97
-
25
-
-
13
29
54
75
-
3
-
-
-
12
28
-
-
-
-
-
53
-
-
K1
K11
A10
A4
B2
L1
25
41
-
77
-
20
-
-
18
33
-
61
-
16
-
-
-
-
32
-
-
-
-
-
-
-
-
-
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
K2
J3
-
H4
L4
L11
K10
J9
-
34
50
-
-
-
-
-
75
-
-
24
40
-
-
H8
B10
C9
A11
D8
D4
C3
A1
L9
-
-
-
-
-
-
-
80
38
26
39
27
-
-
100
48
36
49
37
78
26
14
27
15
64
30
19
31
20
Clock
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
X0A
X1
X1A
L3
L10
K3
CROUT_0
CROUT_1
74
92
52
70
C10
B5
60
72
-
Built-in high-speed CR-osc clock
output port
57
Analog
Power
A/D converter analog power supply
pin
A/D converter analog reference
voltage input pin
AVCC
AVRH
AVSS
C
60
61
62
33
38
39
40
11
H11
F11
G11
L2
50
51
52
23
41
42
43
17
Analog
GND
C pin
A/D converter GND pin
Power supply stabilization capacity
pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04672 Rev. *D
Page 38 of 111
MB9A110A/MB9A110 Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is selected.
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1
When the GPIO is selected.
• CMOS level output.
N-ch
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-04672 Rev. *D
Page 39 of 111
MB9A110A/MB9A110 Series
Type
Circuit
Remarks
C
• Open drain output
• CMOS level hysteresis input
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 5 MΩ
• With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
• CMOS level output.
N-ch
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-04672 Rev. *D
Page 40 of 111
MB9A110A/MB9A110 Series
Type
Circuit
Remarks
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH=-4 mA, IOL=4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
P-ch
P-ch
N-ch
• Pull-up resistor
: Approximately 50 kΩ
• IOH=-4 mA, IOL=4 mA
• When this pin is used as an I2C pin,
the digital output
Digital output
Digital output
P-ch transistor is always off
• +B input is available
R
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04672 Rev. *D
Page 41 of 111
MB9A110A/MB9A110 Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH=-12 mA, IOL= 12 mA
• +B input is available
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
H
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• IOH = -20.5 mA, IOL = 18.5 mA
Digital output
Digital output
N-ch
R
Digital input
Standby mode control
Document Number: 002-04672 Rev. *D
Page 42 of 111
MB9A110A/MB9A110 Series
Type
Circuit
Remarks
I
• CMOS level output
• CMOS level hysteresis input
• 5V tolerant
• With standby mode control
• IOH=-4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
P-ch
N-ch
Digital output
Digital output
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode Input
Document Number: 002-04672 Rev. *D
Page 43 of 111
MB9A110A/MB9A110 Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04672 Rev. *D
Page 44 of 111
MB9A110A/MB9A110 Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Document Number: 002-04672 Rev. *D
Page 45 of 111
MB9A110A/MB9A110 Series
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04672 Rev. *D
Page 46 of 111
MB9A110A/MB9A110 Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be driven to the X0, X0A pin only and the X1,X1A pin should be kept open.
•
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
Document Number: 002-04672 Rev. *D
Page 47 of 111
MB9A110A/MB9A110 Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation
(F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to
use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Document Number: 002-04672 Rev. *D
Page 48 of 111
MB9A110A/MB9A110 Series
8. Block Diagram
MB9AF111LA/MA/NA, F112LA/MA/NA/L, F114LA/MA/NA/L, F115MA/NA, F116MA/NA
TRSTX,TCK,
TDI,TMS
SRAM0
8/16
Kbyte
SWJ-DP
TPIU*1
ETM*1
TDO
ROM
Table
TRACED[3:0],
TRACECLK
On-Chip
Cortex-M3 Core
@40 MHz(Max)
Flash I/F
I
Flash
64/128/256/384/512
Kbyte
D
Security
NVIC
Sys
SRAM1
8/16
Kbyte
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch
CSV
CLK
Main
Source Clock
X0
PLL
Osc
Sub
Osc
X1
CR
4MHz
CR
100kHz
X0A
MAD[24:0]
CROUT
External Bus I/F*2
MADATA[15:0]
AVCC,
AVSS,AVRH
12-bit A/D Converter x 3
Unit 0
MCSX[7:0],
MOEX,MWEX,
MALE,
MRDY,
MCLKOUT,
MDQM[1:0]
AN[15:0]
ADTGx
Unit 1
Unit 2*2
Power-On
Reset
TIOA[7:0]
TIOB[7:0]
Base Timer
16-bit 8ch. /
32-bit 4ch.
LVD
LVD Ctrl
Regulator
C
IRQ-Monitor
AIN[1:0]
BIN[1:0]
ZIN[1:0]
QPRC
2ch.
CRC
Accelerator
A/D Activation
Compare
3ch.
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:0]
NMIX
IC0[3:0]
IC1[3:0]
16-bit Input Capture
4ch.
16-bit Free-Run
Timer
FRCK[1:0]
MD[1:0]
MODE-Ctrl
GPIO
3ch.
16-bit Output
Compare
6ch.
P0[F:0],
P1[F:0],
.
.
PIN-Function-Ctrl
DTTI[1:0]X
RTO0[5:0]
RTO1[5:0]
Waveform Generator
3ch.
.
Px[x:0]
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
Multi-Function Serial I/F
8ch.
16-bit PPG
3ch.
(with FIFO ch.4 to 7)
& HW flow control(ch.4)*2
RTS4
Multi-Function Timer x 2
*1: For the MB9AF111LA/MA, F112LA/MA, MB9AF114LA/MA, MB9AF115MA and MB9AF116MA, ETM is not available.
*2: For the MB9AF111LA, F112LA and MB9AF114LA, the External Bus Interface and 12-bit A/D Converter (unit 2) are not available.
And the Multi-function Serial Interface does not support hardware flow control in these products.
Document Number: 002-04672 Rev. *D
Page 49 of 111
MB9A110A/MB9A110 Series
9. Memory Size
See “Memory Size” in “1. Product Lineup” to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
Cortex-M3 Private
0x4006_1000
Peripherals
DMAC
Reserved
EXT-bus I/F
Reserved
0xE000_0000
0x4006_0000
0x4005_0000
0x4003_F000
Reserved
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
Watch Counter
CRC
0x7000_0000
External Device
MFS
Area
0x6000_0000
Reserved
LVD
Reserved
0x4003_5000
0x4400_0000
0x4200_0000
0x4000_0000
Reserved
32Mbytes
Bit band alias
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x4002_8000
0x4002_7000
A/DC
QPRC
Reserved
0x4002_6000
0x4002_5000
Base Timer
PPG
0x2008_0000
0x2000_0000
0x1FF8_0000
SRAM1
SRAM0
Reserved
0x4002_2000
0x4002_1000
0x4002_0000
Reserved
See the next page
"nMemory Map
(2),(3)"
MFT Unit1
MFT Unit0
0x0010_2000
0x0010_0000
Security/CR Trim
for the memory size
details.
0x4001_6000
0x4001_5000
Dual Timer
Reserved
Flash
0x4001_3000
SW WDT
HW WDT
0x0000_0000
0x4001_2000
0x4001_1000
Clock/Reset
0x4001_0000
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-04672 Rev. *D
Page 50 of 111
MB9A110A/MB9A110 Series
Memory Map (2)
MB9AF116MA/NA
MB9AF115MA/NA
MB9AF114LA/MA/NA
MB9AF114L
0x2008_0000
0x2008_0000
0x2008_0000
Reserved
Reserved
Reserved
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_4000
SRAM1
16Kbytes
SRAM1
16Kbytes
SRAM1
16Kbytes
0x2000_0000
SRAM0
16Kbytes
SRAM0
16Kbytes
SRAM0
16Kbytes
0x1FFF_C000
Reserved
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
CR trimming
Security
CR trimming
Security
0x0010_1000
0x0010_0000
Reserved
0x0008_0000
Reserved
Reserved
0x0006_0000
SA10-15(64KBx6)
0x0004_0000
SA10-13(64KBx4)
SA10-11(64KBx2)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
0x0000_0000
0x0000_0000
0x0000_0000
See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-04672 Rev. *D
Page 51 of 111
MB9A110A/MB9A110 Series
Memory Map (3)
MB9AF112LA/MA/NA
MB9AF112L
MB9AF111LA/MA/NA
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
0x2000_0000
0x1FFF_E000
SRAM1
8Kbytes
SRAM0
8Kbytes
SRAM1
8Kbytes
SRAM0
8Kbytes
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
CR trimming
Security
Reserved
Reserved
0x0002_0000
0x0000_0000
0x0001_0000
0x0000_0000
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(16KBx2)
SA4-7(8KBx4)
See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-04672 Rev. *D
Page 52 of 111
MB9A110A/MB9A110 Series
Peripheral Address Map
Start address
End address
Bus
AHB
Peripherals
0x4000_0000H
0x4000_1000H
0x4001_0000H
0x4001_1000H
0x4001_2000H
0x4001_3000H
0x4001_5000H
0x4001_6000H
0x4002_0000H
0x4002_1000H
0x4002_2000H
0x4002_4000H
0x4002_5000H
0x4002_6000H
0x4002_7000H
0x4002_8000H
0x4002_E000H
0x4002_F000H
0x4003_0000H
0x4003_1000H
0x4003_2000H
0x4003_3000H
0x4003_4000H
0x4003_5000H
0x4003_6000H
0x4003_7000H
0x4003_8000H
0x4003_9000H
0x4003_A000H
0x4003_B000H
0x4003_F000H
0x4004_0000H
0x4005_0000H
0x4006_0000H
0x4006_1000H
0x4006_2000H
0x4006_3000H
0x4006_4000H
0x4000_0FFFH
0x4000_FFFFH
Flash Memory I/F register
Reserved
0x4001_0FFFH
0x4001_1FFFH
0x4001_2FFFH
0x4001_4FFFH
0x4001_5FFFH
0x4001_FFFFH
0x4002_0FFFH
0x4002_1FFFH
0x4002_3FFFH
0x4002_4FFFH
0x4002_5FFFH
0x4002_6FFFH
0x4002_7FFFH
0x4002_DFFFH
0x4002_EFFFH
0x4002_FFFFH
0x4003_0FFFH
0x4003_1FFFH
0x4003_2FFFH
0x4003_3FFFH
0x4003_4FFFH
0x4003_5FFFH
0x4003_6FFFH
0x4003_7FFFH
0x4003_8FFFH
0x4003_9FFFH
0x4003_AFFFH
0x4003_EFFFH
0x4003_FFFFH
0x4004_FFFFH
0x4005_FFFFH
0x4006_0FFFH
0x4006_1FFFH
0x4006_2FFFH
0x4006_3FFFH
0x41FF_FFFFH
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
APB1
Quadrature Position/Revolution Counter(QPRC)
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
Reserved
Low-Voltage Detector
Reserved
APB2
Reserved
Multi-function serial Interface
CRC
Watch Counter
Reserved
External Bus interface
Reserved
Reserved
DMAC register
Reserved
AHB
Reserved
Reserved
Reserved
Document Number: 002-04672 Rev. *D
Page 53 of 111
MB9A110A/MB9A110 Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
Document Number: 002-04672 Rev. *D
Page 54 of 111
MB9A110A/MB9A110 Series
List of Pin Status
Pin status
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
Device
Run mode
INITX input
state
Timer mode or STOP
internal
or SLEEP
mode state
reset state
mode state
Function group
Power
supply
stable
type
Power supply stable
Power supply stable
INITX=1
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
SPL=1
Hi-Z/ Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
GPIO selected
Setting disabled
Input enabled
previous state
Input enabled
A
Main crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Hi-Z/
Internal input
fixed at "0"
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
GPIO selected
Setting disabled
Maintain
previous
Maintain
previous
B
Hi-Z/
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
Main crystal
oscillator output pin
Internal input
fixed at "0"/
or Input enable
Maintain
previous state
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
C
D
INITX input pin
Mode input pin
Input enabled
Hi-Z
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
JTAG
selected
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
E
Hi-Z/ Internal
input fixed at
"0"
GPIO
selected
Setting
disabled
Setting
disabled
Setting disabled
Setting disabled
Trace selected
Trace output
Setting
disabled
Setting
disabled
External interrupt
enabled selected
Maintain
previous state
Maintain
previous state
Maintain
previous state
F
GPIO
Hi-Z/
Internal input
fixed at "0"
selected, or
resource other than
above selected
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Hi-Z
Document Number: 002-04672 Rev. *D
Page 55 of 111
MB9A110A/MB9A110 Series
Power-on
reset or
low-voltage
detection
state
Device
Run mode
INITX input
state
Timer mode or STOP
internal
or SLEEP
mode state
reset state
mode state
Pin status
type
Function group
Power
supply
Power
supply
stable
Power supply stable
Power supply stable
INITX=1
unstable
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
SPL=1
Setting
disabled
Setting
disabled
Trace selected
Setting disabled
Trace output
Maintain
previous state
Maintain
previous state
G
GPIO selected, or
resource other than
above selected
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Hi-Z
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Maintain
previous state
Setting disabled
Hi-Z
Maintain
previous state
Maintain
previous state
H
I
GPIO selected, or
resource other than
above selected
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Hi-Z/ Internal
input fixed at
"0"
GPIO selected,
resource selected
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
Maintain
previous state
Hi-Z
Setting
disabled
Setting
disabled
Maintain
previous state
NMIX selected
Setting disabled
Hi-Z
Maintain
previous state
Maintain
previous state
J
GPIO selected, or
resource other than
above selected
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Analog input
selected
Hi-Z
K
GPIO selected, or
resource other than
above selected
Hi-Z/
Internal input
fixed at "0"
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Setting disabled
Setting disabled
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Analog input
selected
L
Hi-Z
GPIO selected, or
resource other than
above selected
Hi-Z/
Internal input
fixed at "0"
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Setting disabled
Document Number: 002-04672 Rev. *D
Page 56 of 111
MB9A110A/MB9A110 Series
Power-on
reset or
low-voltage
detection
state
Run
Device
mode or
INITX input
state
Timer mode or STOP mode
internal
SLEEP
mode
state
state
reset state
Pin status
type
Function group
Power
supply
Power
supply
stable
Power supply stable
Power supply stable
INITX=1
unstable
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
SPL=1
Maintain
previous
state
Input
enabled
Hi-Z/ Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Maintain
GPIO selected
Setting disabled
Input enabled
previous state
Input enabled
M
Sub crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Setting
disabled
Setting
disabled
Maintain
previous state
GPIO selected
Setting disabled
Maintain
previous state/
Hi-Z at
oscillation
stop*2/
Maintain
previous state/
Hi-Z at
oscillation
stop*2/
N
Hi-Z/
Internal input
fixed at "0"/
or Input
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state
Sub crystal
oscillator output pin
enabled
Internal input
fixed at "0"
Internal input
fixed at "0"
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
O
P
GPIO pin
Hi-Z
Input
enabled
Mode input pin
GPIO selected
Input enabled
Setting disabled
Input enabled
Input enabled
Input enabled
Input enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Maintain
previous state
Hi-Z/Input
enabled
*1: Oscillation is stopped at sub timer mode, low-speed CR timer mode, and stop mode.
*2: Oscillation is stopped at stop mode.
Document Number: 002-04672 Rev. *D
Page 57 of 111
MB9A110A/MB9A110 Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
VCC
AVCC
AVRH
Unit
Remarks
Min
VSS - 0.5
VSS - 0.5
VSS - 0.5
Max
VSS + 6.5
VSS + 6.5
VSS + 6.5
2
Power supply voltage*1,
*
V
V
V
Analog power supply voltage*1,
*
3
Analog reference voltage*1,
Input voltage*1
*
3
VCC + 0.5
(≤ 6.5 V)
VSS - 0.5
V
VI
VSS - 0.5
VSS - 0.5
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
V
V
5V tolerant
Analog pin input voltage*1
VIA
VO
Output voltage*1
VSS - 0.5
-2
V
Clamp maximum current
ICLAMP
+2
mA
mA
mA
*7
Σ[ICLAMP
]
Clamp total maximum current
+20
10
*7
4mA type
"L" level maximum output current*4
"L" level average output current*5
IOL
-
-
20
39
4
12
18.5
100
50
mA
mA
mA
mA
mA
mA
mA
12mA type
P80, P81
4mA type
12mA type
P80, P81
IOLAV
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
-
- 10
mA
4mA type
"H" level maximum output current*4
IOH
-
-
- 20
- 39
- 4
mA
mA
mA
mA
12mA type
P80, P81
4mA type
12mA type
"H" level average output current*5
IOHAV
- 12
- 20.5
- 100
- 50
300
+ 150
mA
mA
mA
mW
°C
P80, P81
"H" level total maximum output current
"H" level total average output current*6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100 ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
Document Number: 002-04672 Rev. *D
Page 58 of 111
MB9A110A/MB9A110 Series
*7:
• See “4. List of Pin Functions” and “5. I/O Circuit Type” about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
resistor
+B input(0V to 16V)
Digital output
Digital input
N-ch
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04672 Rev. *D
Page 59 of 111
MB9A110A/MB9A110 Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Parameter
Power supply voltage
Symbol
VCC
Conditions
Unit
Remarks
Min
2.7*2
Max
5.5
-
-
-
-
V
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
AVCC
AVRH
CS
2.7
2.7
1
5.5
V
AVCC = VCC
AVCC
10
V
μF
For built-in regulator*1
LQI100
LQH080
LQD064
LQG064
VNC064
TA
-
- 40
+ 105
°C
LBC112
Operating
temperature
When mounted
on four-layer
PCB
When mounted
on double-sided
single-layer PCB
- 40
+ 105
°C
PQH100
TA
- 40
- 40
+ 105
+ 85
°C
°C
ICC ≤ 35 mA
ICC > 35 mA
*1: See "C Pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or
built-in Low-speed CR is possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-04672 Rev. *D
Page 60 of 111
MB9A110A/MB9A110 Series
12.3 DC Characteristics
12.3.1 Current rating
(VCC = AVCC= 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ*3
Max*4
CPU: 40 MHz,
Peripheral: 40 MHz,
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*5
32
41
mA
*1
PLL
RUN mode
CPU: 40 MHz,
Peripheral: 40 MHz,
Flash 3 Wait
21
28
mA
mA
*1
*1
FRWTR.RWT = 00
FSYNDN.SD = 011
*5
RUN
mode
current
ICC
CPU/ Peripheral: 4 MHz *2
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
High-speed
CR
3.9
7.7
RUN mode
CPU/ Peripheral: 32 kHz
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*6
VCC
Sub
RUN mode
0.15
0.2
3.2
3.3
mA
mA
*1
*1
CPU/ Peripheral: 100 kHz
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
Peripheral: 40 MHz
*5
Low-speed
CR
RUN mode
PLL
10
15
mA
mA
mA
mA
*1
*1
*1
*1
SLEEP mode
High-speed
CR
SLEEP mode
Sub
SLEEP mode
Low-speed
CR
Peripheral: 4 MHz *2
1.2
0.1
0.1
4.4
3.1
3.1
SLEEP
mode
ICCS
Peripheral: 32 kHz
*6
current
Peripheral: 100 kHz
SLEEP mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA =+25°C, VCC=5.5 V
*4: TA =+105°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-04672 Rev. *D
Page 61 of 111
MB9A110A/MB9A110 Series
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ*2
Max*2
TA = + 25°C,
When LVD is off
*3
TA = + 105°C,
When LVD is off
*3
TA = + 25°C,
When LVD is off
*4
TA = + 105°C,
When LVD is off
*4
2.5
3
mA
*1
Main
TIMER
mode
-
6
mA
μA
*1
*1
*1
TIMER
mode
ICCT
current
60
-
230
3.1
VCC
Sub
TIMER
mode
mA
TA = + 25°C,
When LVD is off
Ta = + 105°C,
When LVD is off
35
-
200
3
μA
*1
*1
STOP
mode
current
ICCH
STOP mode
mA
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
At operation
for interrupt
Vcc = 5.5 V
Unit
Remarks
Typ
Max
Low-voltage detection
circuit (LVD) power
supply current
ICCLVD
VCC
4
7
μA
At not detect
Flash Memory Current
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Symbol
Conditions
Unit
Remarks
Typ
11.4
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
13.1
mA
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
mA
Remarks
Typ
0.57
Max
At 1unit operation
At stop
0.72
Power supply current
ICCAD
AVCC
0.06
1.1
20
1.96
4
μA
mA
μA
At 1unit operation
AVRH=5.5 V
Reference power
supply current
ICCAVRH
AVRH
At stop
0.06
Document Number: 002-04672 Rev. *D
Page 62 of 111
MB9A110A/MB9A110 Series
12.3.2 Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
CMOS
hysteresis
input pin,
MD0,1
5V tolerant
I/O pin
"H" level input
voltage
(hysteresis
input)
-
-
-
VCC × 0.8
-
-
-
VCC + 0.3
V
VIHS
VCC × 0.8
VSS - 0.3
VSS + 5.5
VCC × 0.2
V
V
"L" level input
voltage
(hysteresis
input)
CMOS
hysteresis
input pin,
MD0,1
VILS
Vcc ≥ 4.5 V
IOH = - 4 mA
4mA type
VCC - 0.5
-
VCC
V
Vcc < 4.5 V
IOH = - 2 mA
Vcc ≥ 4.5 V
IOH = - 12 mA
"H" level
output voltage
VOH
12mA type
P80, P81
VCC - 0.5
VCC - 0.4
-
-
VCC
V
V
Vcc < 4.5 V
IOH = - 8 mA
Vcc ≥ 4.5 V
IOH = - 20.5 mA
Vcc < 4.5 V
VCC
IOH = - 13.0 mA
Vcc ≥ 4.5 V
IOL = 4 mA
4mA type
VSS
-
-
0.4
V
Vcc < 4.5 V
IOL = 2 mA
Vcc ≥ 4.5 V
IOL = 12 mA
"L" level
output voltage
VOL
12mA type
P80, P81
VSS
0.4
0.4
V
V
Vcc < 4.5 V
IOL = 8 mA
Vcc ≥ 4.5 V
IOL = 18.5 mA
Vcc < 4.5 V
IOL = 10.5 mA
-
VSS
-
-
Input leak current
IIL
-
- 5
25
+ 5
μA
kΩ
Vcc≥ 4.5 V
50
80
100
Pull-up resistor
value
RPU
Pull-up pin
Other than
VCC<4.5 V
30
200
VCC, VSS
AVCC, AVSS
,
Input capacitance
CIN
-
-
5
15
pF
,
AVRH
Document Number: 002-04672 Rev. *D
Page 63 of 111
MB9A110A/MB9A110 Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
MHz
Remarks
name
Min
Max
VCC≥ 4.5 V
VCC<4.5 V
VCC≥ 4.5 V
VCC<4.5 V
VCC≥ 4.5 V
4
4
4
4
48
20
48
20
When crystal oscillator is
connected
Input frequency
FCH
When using external
clock
MHz
X0
X1
20.83
50
250
When using external
clock
Input clock cycle
tCYLH
-
ns
%
VCC<4.5 V
PWH/tCYLH
PWL/tCYLH
250
When using external
clock
Input clock pulse width
45
55
Input clock rising time and tCF
When using external
clock
-
-
-
-
-
-
5
ns
falling time
tCR
FCM
-
-
40
40
MHz
MHz
Master clock
Base clock
(HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
FCC
Internal operating
clock*1
frequency
FCP0
FCP1
FCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz
MHz
MHz
Base clock
(HCLK/FCLK)
tCYCC
-
-
25
-
ns
Internal operating
clock*1
cycle time
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
25
25
25
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this datasheet.
X0
Document Number: 002-04672 Rev. *D
Page 64 of 111
MB9A110A/MB9A110 Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
When crystal oscillator is
connected
-
-
32.768
-
kHz
Input frequency
FCL
tCYLL
-
-
-
32
10
-
-
100
kHz
When using external clock
When using external clock
X0A
X1A
Input clock cycle
31.25
μs
PWH/tCYLL
PWL/tCYLL
Input clock pulse width
45
-
55
%
When using external clock
X0A
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
4.04
TA = + 25°C
3.96
4
When trimming *1
Clock frequency
FCRH
MHz
TA = 0°C to + 70°C
3.84
4
4.16
TA = - 40°C to + 105°C
TA = - 40°C to + 105°C
3.8
3
4
4
4.2
5
When not trimming
*2
Frequency stability time
tCRWT
-
-
-
90
μs
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the
High-speed CR clock as a source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
50
Typ
Max
150
Clock frequency
FCRL
-
100
kHz
Document Number: 002-04672 Rev. *D
Page 65 of 111
MB9A110A/MB9A110 Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
100
Max
PLL oscillation stabilization wait time (LOCK UP time) *1
PLL input clock frequency
tLOCK
-
μs
fPLLI
-
fPLLO
FCLKPLL
4
-
-
-
-
16
MHz
PLL multiple rate
13
200
-
75
multiple
MHz
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency *2
300
40
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the input clock of the main
PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min
100
Typ
Max
PLL oscillation stabilization wait time (LOCK UP time) *1
tLOCK
-
-
μs
PLL input clock frequency
PLL multiple rate
fPLLI
-
fPLLO
FCLKPLL
3.8
50
190
-
4
-
4.2
71
MHz
multiple
MHz
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency *2
-
-
300
40
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master
clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
PLL input
clock
PLL macro
clock
Main clock (CLKMO)
oscillation clock
(CLKPLL)
K
M
Main
PLL
High-speed CR clock (CLKHC)
divider
divider
N
divider
Document Number: 002-04672 Rev. *D
Page 66 of 111
MB9A110A/MB9A110 Series
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
Value
Parameter
Reset input time
Symbol
tINITX
Pin name
Conditions
Unit
ns
Remarks
Min
Max
INITX
-
500
-
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol Pin name
Conditions
Unit
Remarks
*1
Min
Max
Power supply shut down time
Power ramp rate
tOFF
-
50
0.9
-
-
-
-
ms
VCC
dV/dt
Vcc:0.2 V to 2.70 V
-
1000
0.744
mV/us *2
ms
Time until releasing Power-on reset
tPRT
0.446
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.6. Low-voltage detection characteristics”
Document Number: 002-04672 Rev. *D
Page 67 of 111
MB9A110A/MB9A110 Series
12.4.8 External Bus Timing
External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
VCC ≥ 4.5 V
Unit
MHz
Min
Max
-
40
32
-
Output frequency
tCYCLE
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
-
MHz
ns
MCLKOUT
25
Minimum clock cycle time
-
31.25
-
ns
Note:
−
The external bus clock output is a divided clock of HCLK. For more information about setting of clock divider,
see "Chapter 12: External Bus Interface" in "FM3 Family Peripheral Manual"
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
MCLKOUT
External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Value
Unit
Remarks
VIH
VIL
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
-
VOH
VOL
Signal output characteristics
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
Document Number: 002-04672 Rev. *D
Page 68 of 111
MB9A110A/MB9A110 Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
MOEX
MOEX
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min pulse width
MCSX ↓→Address output
delay time
-9
-12
+ 9
+ 12
MCSX[7:0]
MAD[24:0]
MOEX
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
MOEX ↑→
Address hold time
0
MAD[24:0]
MCLK×m-9
MCLK×m-12
MCSX ↓→
MOEX ↓ delay time
MOEX ↑→
MOEX
MCSX[7:0]
0
MCSX ↑ time
MCLK×m-9
MCLK×m-12
MCSX ↓→
MCSX
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑→
MDQM[1:0]
20
38
MOEX
MADATA[15:0]
MOEX
MADATA[15:0]
-
tDH - OE
0
-
-
Data hold time
MWEX
tWEW
MWEX
MCLK×n-3
0
Min pulse width
MWEX ↑→ Address output
delay time
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MWEX
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
MAD[24:0]
MCLK×n-9
MCLK×n-12
MCSX ↓→
MWEX ↓ delay time
MWEX
MCSX[7:0]
MWEX ↑→
MCSX ↑ delay time
MCSX ↓ →
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCSX
MDQM ↓ delay time
MDQM[1:0]
MCSX ↓ →
Data output time
MWEX ↑→
MCSX
MADATA[15:0]
MWEX
MADATA[15:0]
MCLK-12
MCLK+12
MCLK×m+9
MCLK×m+12
0
Data hold time
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Document Number: 002-04672 Rev. *D
Page 69 of 111
MB9A110A/MB9A110 Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
MAD[24:0]
MOEX
tWEH-AX
tCSL-AV
tOEH-AX
tCSL-AV
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
MWEX
tCSL-WEL
tWEW
tDS-OE
tDH-OE
tWEH-DX
MADATA[15:0]
Invalid
RD
WD
tCSL-DV
Document Number: 002-04672 Rev. *D
Page 70 of 111
MB9A110A/MB9A110 Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
ns
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC< 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
9
12
9
12
9
12
9
12
9
12
MCLK
Address delay time
tAV
1
1
1
1
1
MAD[24:0]
tCSL
tCSH
tREL
tREH
tDS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
MCSX delay time
MOEX delay time
MCSX[7:0]
MCLK
MOEX
19
37
Data set up→
MCLK ↑time
MCLK ↑→
MCLK
-
-
MADATA[15:0]
MCLK
tDH
0
1
1
1
1
Data hold time
MADATA[15:0]
9
12
9
12
9
12
9
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
MCLK
MWEX
MWEX delay time
MDQM[1:0]
delay time
MCLK
MDQM[1:0]
12
MCLK+18
MCLK+24
18
MCLK ↑→
Data output time
MCLK,
MCLK+1
MADATA[15:0]
1
1
MCLK ↑→
Data output time
MCLK
MADATA[15:0]
24
Note:
−
When the external load capacitance CL = 30 pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
Address
MAD[24:0]
MOEX
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
tWEL
MWEX
tDS
tDH
RD
Invalid
WD
MADATA[15:0]
tODS
Document Number: 002-04672 Rev. *D
Page 71 of 111
MB9A110A/MB9A110 Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Multiplexed
Symbol
tALE-CHMADV
Pin name
Conditions
Unit
ns
Min
Max
VCC ≥ 4.5 V
10
20
0
Address delay time
VCC < 4.5 V
MALE
MADATA[15:0]
VCC ≥ 4.5 V
MCLK×n+0
MCLK×n+0
MCLK×n+10
MCLK×n+20
Multiplexed
Address hold time
tCHMADH
ns
VCC < 4.5 V
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04672 Rev. *D
Page 72 of 111
MB9A110A/MB9A110 Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit
ns
ns
ns
ns
Remarks
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC≥ 4.5 V
VCC < 4.5 V
9
12
9
1
1
MCLK
MALE delay time
ALE
tCHAH
12
MCLK ↑→
Multiplexed
VCC ≥ 4.5 V
tCHMADV
1
1
tOD
ns
ns
Address delay time
MCLK
MADATA[15:0]
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
MCLK ↑→
Multiplexed
Data output time
tCHMADX
tOD
Note:
−
When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04672 Rev. *D
Page 73 of 111
MB9A110A/MB9A110 Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
MCLK ↑
MRDY input
setup time
VCC ≥ 4.5 V
19
37
MCLK
MRDY
tRDYI
-
ns
VCC < 4.5 V
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-04672 Rev. *D
Page 74 of 111
MB9A110A/MB9A110 Series
12.4.9 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
TIOAn/TIOBn
(when using as
ECK,TIN)
Conditions
Unit
Remarks
Min
2tCYCP
Max
tTIWH
tTIWL
Input pulse width
-
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
2tCYCP
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
,
Input pulse width
-
-
ns
tTRGL
tTRGH
tTRGL
TGIN
VIHS
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see “8. Block Diagram” in this datasheet.
Document Number: 002-04672 Rev. *D
Page 75 of 111
MB9A110A/MB9A110 Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC<4.5 V
Min Max
VCC≥ 4.5 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
-
8
-
8
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCK ↓→ SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVI
-30
50
0
+30
- 20
30
0
+ 20
ns
ns
ns
Master mode
tIVSHI
-
-
-
-
tSHIXI
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓→ SOT delay time
SIN → SCK ↑ setup time
SCK ↑→ SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 76 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-04672 Rev. *D
Page 77 of 111
MB9A110A/MB9A110 Series
CSIO (SPI = 0, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
VCC<4.5 V
Min Max
VCC≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
tSHOVI
tIVSLI
SCKx
4tCYCP
4tCYCP
SCKx
SOTx
SCK ↑→ SOT delay time
- 30
+30
- 20
+ 20
ns
Master mode
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
50
0
-
-
30
0
-
-
ns
ns
tSLIXI
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑→ SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 78 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-04672 Rev. *D
Page 79 of 111
MB9A110A/MB9A110 Series
CSIO (SPI = 1, SCINV = 0)
Parameter
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
VCC<4.5 V
Min Max
VCC≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx
SOTx
SCK ↑→ SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
tIVSLI
tSLIXI
tSOVLI
50
-
-
-
30
-
-
-
ns
ns
ns
Master mode
0
0
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 80 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
VOL
VOL
SCK
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-04672 Rev. *D
Page 81 of 111
MB9A110A/MB9A110 Series
CSIO (SPI = 1, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
VCC<4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx
SOTx
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCK ↓→ SOT delay time
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
Master mode
tIVSHI
tSHIXI
tSOVHI
50
-
-
-
30
-
-
-
ns
ns
ns
SIN → SCK ↑ setup time
SCK ↑→SIN hold time
SOT → SCK ↑ delay time
0
0
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑→ SIN hold time
Slave mode
10
20
10
20
SCKx
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 82 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
Symbol
Conditions
Min
tCYCP + 10
Max
Unit
Remarks
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
tSLSH
tSHSL
tF
-
ns
ns
ns
ns
tCYCP + 10
-
CL = 30 pF
-
-
5
5
SCK rising time
tR
tR
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
VIL
Document Number: 002-04672 Rev. *D
Page 83 of 111
MB9A110A/MB9A110 Series
12.4.11 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
ADTG
A/D converter trigger input
-
-
2tCYCP
*
-
ns
FRCKx
ICxx
Free-run timer input clock
Input capture
tINH
tINL
DTTIxX
2tCYCP
*
-
-
ns
ns
Wave form generator
Input pulse width
Except
Timer mode,
Stop mode
Timer mode,
Stop mode
2tCYCP + 100*
500
INTxx,
NMIX
External interrupt
NMI
-
ns
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see “8. Block
Diagram” in this datasheet.
Document Number: 002-04672 Rev. *D
Page 84 of 111
MB9A110A/MB9A110 Series
12.4.12 Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
Symbol
tAHL
tALL
tBHL
tBLL
Conditions
Unit
Min
Max
-
-
-
-
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
2tCYCP
*
-
ns
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and fall time from
determined ZIN level
Determined ZIN level from AIN/BIN
rise and fall time
tZHL
tZLL
QCR:CGSC = "0"
QCR:CGSC = "0"
tZABE
tABEZ
QCR:CGSC = "1"
QCR:CGSC = "1"
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "8. Block Diagram" in this
datasheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
Document Number: 002-04672 Rev. *D
Page 85 of 111
MB9A110A/MB9A110 Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-04672 Rev. *D
Page 86 of 111
MB9A110A/MB9A110 Series
12.4.13 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Standard-mode
Min Max
100
Fast-mode
Min Max
Parameter
Symbol
Conditions
Unit
Remarks
SCL clock frequency
(Repeated) START condition hold time
SDA ↓→ SCL ↓
FSCL
0
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SCL clock "L" width
SCL clock "H" width
(Repeated) START condition setup time
SCL ↑→ SDA ↓
Data hold time
SCL ↓→ SDA ↓↑
Data setup time
SDA ↓↑→ SCL ↑
STOP condition setup time
SCL ↑→ SDA ↑
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
tHDDAT
tSUDAT
tSUSTO
4.7
0
-
0.6
0
-
μs
μs
ns
μs
CL = 30 pF,
R = (Vp/IOL) *1
*2
3.45
0.9 *3
250
4.0
-
-
100
0.6
-
-
Bus free time between
"STOP condition" and
"START condition"
Noise filter
tBUF
tSP
4.7
-
-
1.3
-
-
μs
4
4
-
2 tCYCP
*
2 tCYCP
*
ns
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of
"tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "8. Block Diagram" in this datasheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-04672 Rev. *D
Page 87 of 111
MB9A110A/MB9A110 Series
12.4.14 ETM timing
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Symbol
Pin name
Conditions
VCC≥ 4.5 V
Unit
Remarks
Min
Max
2
2
9
TRACECLK
TRACED[3:0]
Data hold
tETMH
ns
VCC< 4.5 V
15
40
VCC≥ 4.5 V
-
MHz
MHz
ns
TRACECLK
frequency
1/tTRACE
VCC < 4.5 V
VCC≥ 4.5 V
VCC < 4.5 V
-
32
-
TRACECLK
25
TRACECLK
Clock cycle time
tTRACE
31.25
-
ns
Note:
−
When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-04672 Rev. *D
Page 88 of 111
MB9A110A/MB9A110 Series
12.4.15 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
TMS, TDI setup time
TMS, TDI hold time
Symbol
tJTAGS
Pin name
TCK
Conditions
VCC≥ 4.5 V
Unit
ns
Remarks
Min
Max
15
-
TMS,TDI
VCC < 4.5 V
VCC≥ 4.5 V
VCC < 4.5 V
VCC≥ 4.5 V
TCK
TMS,TDI
tJTAGH
15
-
-
ns
ns
25
45
TCK
TDO
TDO delay time
tJTAGD
VCC < 4.5 V
-
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-04672 Rev. *D
Page 89 of 111
MB9A110A/MB9A110 Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
Parameter
Resolution
Symbol
Unit
bit
LSB
LSB
mV
Remarks
name
Min
Max
-
-
-
-
-
-
-
-
-
-
-
-
12
Integral Nonlinearity
± 1.7
± 1.7
± 8
AVRH±8
-
± 4.5
± 2.5
± 15
AVRH±15
-
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
AVRH = 2.7 V to 5.5 V
VZT
VFST
ANxx
ANxx
mV
1.0*1
1.2*1
AVCC ≥ 4.5 V
AVCC < 4.5 V
Conversion time
-
-
μs
*2
*2
-
-
-
-
AVCC ≥ 4.5 V
Sampling time
Ts
-
ns
AVCC < 4.5 V
Compare clock cycle*3
Tcck
Tstt
-
-
-
50
-
-
-
-
2000
1.0
ns
μs
pF
State transition time to
operation permission
Analog input capacity
Analog input resistor
CAIN
-
12.9
2
AVCC ≥ 4.5 V
RAIN
-
-
-
kΩ
3.8
4
AVCC < 4.5 V
Interchannel disparity
Analog port input leak current
Analog input voltage
Reference voltage
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
ANxx
ANxx
AVRH
-
5
AVSS
2.7
AVRH
AVCC
V
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns
AVCC< 4.5 V, HCLK=40 MHz sampling time: 500 ns, compare time: 700 ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral Manual
Analog Macro Part".
The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this datasheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1)
*3: The compare time (Tc) is the value of (Equation 2)
Document Number: 002-04672 Rev. *D
Page 90 of 111
MB9A110A/MB9A110 Series
Comparator
ANxx
RAIN
Analog input pin
Rext
Analog
signal source
CAIN
(Equation 1) Ts≥ (RAIN + Rext) × CAIN × 9
Ts:
Sampling time
RAIN
:
Input resistor of A/D = 2 kΩ
4.5 V ≤ AVCC≤ 5.5 V
2.7 V ≤ AVCC< 4.5 V
2.7 V ≤ AVCC≤ 5.5 V
Input resistor of A/D = 3.8 kΩ
Input capacity of A/D = 12.9 pF
Output impedance of external circuit
CAIN
:
Rext:
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Compare clock cycle
Tcck:
Document Number: 002-04672 Rev. *D
Page 91 of 111
MB9A110A/MB9A110 Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
Integral Nonlinearity:
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
0xFFE
0xFFD
Actual conversion
Actual conversion
characteristics
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actual
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Asured
value)
Ideal characteristics
0x001
ly-measured value)
Analog input
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST – VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-04672 Rev. *D
Page 92 of 111
MB9A110A/MB9A110 Series
12.6 Low-voltage detection characteristics
Low-voltage detection reset
(TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.25
2.30
Max
2.65
2.70
Detected voltage
Released voltage
VDL
VDH
-
-
2.45
2.50
V
V
When voltage drops
When voltage rises
Interrupt of low-voltage detection
(TA = - 40°C to + 105°C)
Value
Typ
2.8
Parameter
Symbol
Conditions
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
Unit
Remarks
Min
Max
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
3.02
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
SVHI = 1001
-
LVD stabilization wait time
tLVDW
-
-
2240 × tCYCP
*
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04672 Rev. *D
Page 93 of 111
MB9A110A/MB9A110 Series
12.7 Flash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(Vcc = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Large Sector
Unit
Remarks
Typ*
Max*
0.7
0.3
3.7
1.1
Sector erase
time
s
Includes write time prior to internal erase
Small Sector
Half word (16-bit)
write time
12
384
μs
Not including system-level overhead time
Includes write time prior to internal erase
64K/128K/256KByte
384K/512KByte
5.2
8
23.6
38.4
s
s
Chip erase time
*: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.7.2 Erase/Write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
Remarks
1,000
20*
10*
5*
10,000
100,000
*: At average + 85°C
Document Number: 002-04672 Rev. *D
Page 94 of 111
MB9A110A/MB9A110 Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
tCYCC
40
ns
High-speed CR TIMER mode,
Main TIMER mode,
80
μs
PLL TIMER mode
Ticnt
Low-speed CR TIMER mode
Sub TIMER mode
453
453
453
737
737
737
μs
μs
μs
STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-04672 Rev. *D
Page 95 of 111
MB9A110A/MB9A110 Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual
about the return factor from Low-Power consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in “FM3 Family Peripheral Manual".
Document Number: 002-04672 Rev. *D
Page 96 of 111
MB9A110A/MB9A110 Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
308
308
444
444
μs
μs
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Trcnt
Low-speed CR TIMER mode
Sub TIMER mode
428
428
428
684
684
684
μs
μs
μs
STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
Document Number: 002-04672 Rev. *D
Page 97 of 111
MB9A110A/MB9A110 Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
The return factor is different in each Low-Power consumption modes.
See “Chapter 6: Low Power Consumption Mode” and “Operations of Standby Modes” in FM3 Family Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption
mode transition. See “Chapter 6: Low Power Consumption Mode” in “FM3 Family Peripheral Manual”.
The time during the power-on reset/low-voltage detection reset is excluded. See “12.4.7. Power-on Reset Timing in
12.4. AC Characteristics in 12. Electrical Characteristics” for the detail on the time during the power-on reset/low -voltage
detection reset.
−
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04672 Rev. *D
Page 98 of 111
MB9A110A/MB9A110 Series
13.Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
MB9AF111LAPMC1-G-JNE2
MB9AF112LAPMC1-G-JNE2
MB9AF114LAPMC1-G-JNE2
MB9AF111LAPMC-G-JNE2
MB9AF112LAPMC-G-JNE2
MB9AF114LAPMC-G-JNE2
MB9AF112LPMC-G-MJE1
MB9AF114LPMC-G-MJE1
MB9AF111LAQN-G-AVE2
MB9AF112LAQN-G-AVE2
MB9AF114LAQN-G-AVE2
MB9AF111MAPMC-G-JNE2
MB9AF112MAPMC-G-JNE2
MB9AF114MAPMC-G-JNE2
MB9AF115MAPMC-G-JNE2
MB9AF116MAPMC-G-JNE2
MB9AF111NAPMC-G-JNE2
MB9AF112NAPMC-G-JNE2
MB9AF114NAPMC-G-JNE2
MB9AF115NAPMC-G-JNE2
MB9AF116NAPMC-G-JNE2
MB9AF111NAPF-G-JNE1
MB9AF112NAPF-G-JNE1
MB9AF114NAPF-G-JNE1
MB9AF115NAPF-G-JNE1
MB9AF116NAPF-G-JNE1
MB9AF111NABGL-GE1
64 Kbyte
16 Kbyte
Plastic LQFP
128 Kbyte
256 Kbyte
64 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
32 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
32 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
32 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
(0.5 mm pitch), 64-pin
(LQD064)
128 Kbyte
256 Kbyte
128 Kbyte
256 Kbyte
64 Kbyte
Plastic LQFP
(0.65 mm pitch), 64-pin
(LQG064)
Plastic QFN
128 Kbyte
256 Kbyte
64 Kbyte
(0.5 mm pitch), 64-pin
(VNC064)
128 Kbyte
256 Kbyte
384 Kbyte
512 Kbyte
64 Kbyte
Plastic LQFP
(0.5 mm pitch), 80-pin
(LQH080)
Tray
128 Kbyte
256 Kbyte
384 Kbyte
512 Kbyte
64 Kbyte
Plastic LQFP
(0.5 mm pitch), 100-pin
(LQI100)
128 Kbyte
256 Kbyte
384 Kbyte
512 Kbyte
64 Kbyte
Plastic QFP
(0.65 mm pitch), 100-pin
(PQH100)
Plastic PFBGA
MB9AF112NABGL-GE1
128 Kbyte
256 Kbyte
(0.8 mm pitch), 112-pin
(LBC112)
MB9AF114NABGL-GE1
Document Number: 002-04672 Rev. *D
Page 99 of 111
MB9A110A/MB9A110 Series
14.Package Dimensions
Package Type
Package Code
LQFP 100
LQI100
4
4
D
D
5
7
5
7
D1
D1
75
51
51
75
76
50
50
76
E1
E1
E
E
5
7
5
7
4
4
3
6
100
26
26
100
1
1
25
25
2
5
7
e
0.1 0
C
A-B
D
3
BOTTOM VIEW
0.2 0
C A-B D
b
8
0.0 8
C
A-B
D
TOP VIEW
2
A
9
A
SEATING
PLANE
c
A1
A'
0.25
b
L1
0.0 8
C
10
SECTION A-A'
L
SIDE VIEW
DETAIL A
NOTES :
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING
LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY.
3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H.
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
4. TO BE DETERMINED AT SEATING PLANE C.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLEPROTRUSION IS 0.25mm PRE SIDE.
c
D
D1
e
16.00 BSC
14.00 BSC
0.50 BSC
DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
E
16.00 BSC
14.00 BSC
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY
SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS.
BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER
SECTIONS OF THE MOLDER BODY.
E1
L
0.45
0.60 0.75
L1
0.30 0.50 0.70
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b
MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE LEAD FOOT.
9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOWEST POINT OF THE PACKAGE BODY.
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
002-11500 *A
Document Number: 002-04672 Rev. *D
Page 100 of 111
MB9A110A/MB9A110 Series
Package Type
Package Code
QFP 100
PQH100
D
4
D1
5
7
80
51
51
80
81
50
50
81
E1
E
4
5
7
6
3
100
31
31
100
1
30
30
1
2
5
7
e
0.20
C
A-B
D
3
BOTTOM VIEW
b
0.40
C A-B D
0.13
C
A-B
D
8
TOP VIEW
2
9
c
A
SEATING
PLANE
L2
A'
10
0.10
C
b
SECTION A-A'
DETAIL A
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
3.35
A
A1
b
0.05
0.27
0.11
0.45
0.37
0.23
0.32
c
D
23.90 BSC
20.00 BSC
0.65 BSC
D1
e
E
17.90 BSC
14.00 BSC
E1
0
8
L
0.73
0.88 1.03
1.95 REF
0.25 BSC
L1
L2
002-15156 **
PACKAGE OUTLINE, 100 LEAD QFP
20.00X14.00X3.35 MM PQH100 REV**
Document Number: 002-04672 Rev. *D
Page 101 of 111
MB9A110A/MB9A110 Series
Package Type
Package Code
LQFP 80
LQH080
4
5
D
7
D1
60
41
41
60
61
40
40
61
5
7
E1
E
4
3
6
80
21
21
80
1
20
20
1
2
5
8
7
D
3
0.10
C
C A-B D
BOTTOM VIEW
e
0.08
A-B
D
b
0.20
C A-B D
TOP VIEW
2
A
A
SEATING
PLANE
9
c
A'
L1
0.25
0.08
C
A1
b
L
10
SIDE VIEW
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
c
D
D1
e
14.00 BSC.
12.00 BSC.
0.50 BSC
E
14.00 BSC.
12.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
002-11501 **
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
Document Number: 002-04672 Rev. *D
Page 102 of 111
MB9A110A/MB9A110 Series
Package Type
Package Code
LQFP 64
LQD064
4
5
D
D1
7
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
A-B
5
7
e
A-B D
3
0.10
0.08
C
D
BOTTOM VIEW
0.20
C
C
A-B
D
b
8
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
L
A'
A1
10
SECTION A-A'
L1
0.08
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
c
0.20
D
D1
e
12.00 BSC.
10.00 BSC.
0.50 BSC
E
12.00 BSC.
10.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
002-11499 **
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
Document Number: 002-04672 Rev. *D
Page 103 of 111
MB9A110A/MB9A110 Series
Package Type
Package Code
LQFP 64
LQG064
4
D
5
7
D1
48
33
33
48
49
32
32
49
E1
E
5
7
4
3
64
17
17
64
1
16
16
1
2
5
7
BOTTOM VIEW
e
3
0.10
C A-B D
0.20
C A-B D
0.13
C
A-B
D
b
8
TOP VIEW
2
A
A
9
SEATI NG
PLA NE
A1
0.2 5
L
c
A'
10
L1
b
0.10
C
SECTION A -A'
SIDE VIEW
DIMENSION
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.27 0.32 0.37
0.09 0.20
0.20
c
D
D1
e
14.00 BSC
12.00 BSC
0.65 BSC
E
14.00 BSC
12.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
0
L1
002-13881 **
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
Document Number: 002-04672 Rev. *D
Page 104 of 111
MB9A110A/MB9A110 Series
Package Type
Package Code
PFBGA 112
LBC112
A
0.20
2X
C
11
10
9
6
8
7
6
5
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
PIN A1
CORNER
6
B
7
0.20
C
2X
TOP VIEW
BOTTOM VIEW
DETAILA
5
C
112xφ b
0.10
C
SIDE VIEW
0.08
C A B
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. SOLDER BALL POSITION DESIGNATIO
DIMENSIONS
NOM.
SYMBOL
N PER JEP95, SECTION 3, SPP-020.
MIN.
-
MAX.
1.45
0.45
3. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A
A1
D
-
0.35
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.25
10.00 BSC
E
10.00 BSC
8.00 BSC
8.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
11
112
0.45
WHEN THERE IS AN ODD NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
b
0.35
0.55
eD
eE
SD
SE
0.80 BSC
0.80 BSC
0.00
WHEN THERE IS AN EVEN NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
7.
0.00
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATESTHE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
002-13225 **
PACKAGE OUTLINE, 112 BALL FBGA
10.00X10.00X1.45 MM LBC112 REV**
Document Number: 002-04672 Rev. *D
Page 105 of 111
MB9A110A/MB9A110 Series
Package Type
Package Code
QFN 64
VNC064
0.10
C
A B
D2
A
D
48
33
32
33
48
0.10
2X
C
32
49
49
0.10
C A B
5
(ND-1)
e
E
E2
17
16
64
64
17
1
16
1
4
INDEXMARK
8
9
e
B
b
L
0.10
0.05
C A B
0.10
2X
C
C
TOP VIEW
SIDE VIEW
BOTTOMVIEW
0.10
C
A
SEATINGPLANE
0.05
C
C
A1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
0.90
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
A
0.00
9.00 BSC
9.00 BSC
0.05
1
4
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL,
D
E
b
THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
0.20 0.25 0.30
6.00 BSC
5
D
2
6.
7.
8
E
2
e
6.00 BSC
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
0.50 BSC
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
R
L
N
0.20 REF
0.40 0.45
0.35
64
16
ND
002-13234 **
PACKAGE OUTLINE, 64 LEAD QFN
9.0X9.0X0.9 MM VNC064 6.0X6.0 MM EPAD (SAWN) Rev*.*
Document Number: 002-04672 Rev. *D
Page 106 of 111
MB9A110A/MB9A110 Series
15.Errata
This chapter describes the errata for MB9A110 product family. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
Initial Revision
MB9AF111LPMC1-G-JNE2, MB9AF112LPMC1-G-JNE2, MB9AF114LPMC1-G-JNE2,
MB9AF111LPMC-G-JNE2, MB9AF112LPMC-G-JNE2, MB9AF114LPMC-G-JNE2,
MB9AF112LPMC-G-MJE1, MB9AF114LAPMC-G-JNE2,
MB9AF111LQN-G-AVE2, MB9AF112LQN-G-AVE2, MB9AF114LQN-G-AVE2,
MB9AF111MPMC-G-JNE2, MB9AF112MPMC-G-JNE2, MB9AF114MPMC-G-JNE2,
MB9AF115MPMC-G-JNE2, MB9AF116MPMC-G-JNE2,
MB9AF111NPMC-G-JNE2, MB9AF112NPMC-G-JNE2, MB9AF114NPMC-G-JNE2,
MB9AF115NPMC-G-JNE2, MB9AF116NPMC-G-JNE2,
MB9AF111NPF-G-JNE1, MB9AF112NPF-G-JNE1, MB9AF114NPF-G-JNE1,
MB9AF115NPF-G-JNE1, MB9AF116NPF-G-JNE1,
MB9AF111NBGL-GE1, MB9AF112NBGL-GE1, MB9AF114NBGL-GE1
15.2 Qualification Status
Product Status: In Production − Qual.
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Silicon Revision
Fix Status
Watch Counter issue
Refer to 15.1
Rev. initial rev.
Fixed in Rev. A
Watch Counter issue
PROBLEM DEFINITION
The underflow interruption does not occur.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
The condition is when underflow interruption occurs.
SCOPE OF IMPACT
The underflow interruption does not occur as specified.
WORKAROUND
This error cannot be avoided by any software, except not using Watch Counter interrupt.
FIX STATUS
This issue was fixed in Rev. A.
Document Number: 002-04672 Rev. *D
Page 107 of 111
MB9A110A/MB9A110 Series
16.Major Changes
Spansion Publication Number: DS706-00011
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
Revised series name and part number:
MB9A110 Series→MB9A110A Series
MB9AF111L → MB9AF111LA
MB9AF112L → MB9AF112LA
MB9AF114L → MB9AF114LA
MB9AF111M → MB9AF111MA
MB9AF112M → MB9AF112MA
MB9AF114M → MB9AF114MA
MB9AF115M → MB9AF115MA
MB9AF116M → MB9AF116MA
MB9AF111N → MB9AF111NA
MB9AF112N → MB9AF112NA
MB9AF114N → MB9AF114NA
MB9AF115N → MB9AF115NA
MB9AF116N → MB9AF116NA
Added the package.
-
-
LCC-64P-M24
PRODUCT LINEUP
Function
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
External Interrupts
Added the following description.
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
8
Corrected the following description.
7pins (Max) → 8pins (Max)
SIGNAL DESCRIPTION
34 to 37 Multi-function Serial (ch.0 to ch.7)
Corrected the description for function.
Added "LIN pin"
Deleted "UART pin"
I/O CIRCUIT TYPE
42, 43
Corrected the following schematic for "TypeB".
CMOS level hysteresis input → Digital input
Corrected the following schematic for "TypeC".
Control Pin → Digital output
HANDLING DEVICES
Power supply pins
Corrected the description.
51
MEMORY SIZE
Added "MEMORY SIZE".
54
69
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Added the items FCM to the Internal operating clock frequency.
(1) Main Clock Input Characteristics
(4-2) Operating Conditions of Main PLL
Added the description.
71
72
(7) External Bus Timing
External bus clock output Characteristics
(8) Base Timer Input Timing
Trigger input timing
Added the Note.
79
88
(10) External input timing
Corrected the footnote.
12-bit A/D Converter
Electrical characteristics for the A/D converter
Corrected the value of "Full-scale transition voltage".
Min: -20 → AVRH-20
Max: +20 → AVRH+20
94
Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
Corrected the value of "Reference voltage".
Min: AVSS → 2.7
Revision 2.1
-
-
Company name and layout design change
Added the description of Maximum area size
Revision 3.0
FEATURES
External Bus Interface
3
Document Number: 002-04672 Rev. *D
Page 108 of 111
MB9A110A/MB9A110 Series
Page
Section
Change Results
9
PACKAGES
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
Added the description of I2C to the type of E, F and I
Added about +B input
44, 46
44, 45
51
I/O CIRCUIT TYPE
I/O CIRCUIT TYPE
HANDLING DEVICES
HANDLING DEVICES
Crystal oscillator circuit
HANDLING DEVICES
C Pin
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
51
52
53
54
Changed the description
BLOCK DIAGRAM
Modified the block diagram
Changed to the following description
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
MEMORY SIZE
MEMORY MAP
Memory map(1)
MEMORY MAP
Memory map(2)(3)
55
Modified the area of "External Device Area"
56, 57
Added the summary of Flash memory sector and the note
Added the Clamp maximum current
Added the output current of P80 and P81
Added about +B input
Modified the minimum value of Analog reference voltage
Added Smoothing capacitor
Added the note about less than the minimum power supply voltage
Changed the table format
Added Main TIMER mode current
Added Flash Memory Current
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
64, 65
66
ELECTRICAL CHARACTERISTICS
2. Recommended Operation Conditions
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current rating
67, 68
Moved A/D Converter Current
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
71
Added Frequency stability time at Built-in high-speed CR
(3) Built-in CR Oscillation Characteristics
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-1)(4-2) Operating Conditions of Main PLL
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(6) Power-on Reset Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Added Main PLL clock frequency
Added the figure of Main PLL connection
72
Added Time until releasing Power-on reset
Changed the figure of timing
73
75-77
82-89
Modified Data output time
(7) External Bus Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero
transition voltage and Full-scale transition voltage
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage
(8) CSIO/UART Timing
ELECTRICAL CHARACTERISTICS
5. 12bit A/D Converter
96
ELECTRICAL CHARACTERISTICS
9. Return Time from Low-Power Consumption
Mode
101
Added Return Time from Low-Power Consumption Mode
105
106
ORDERING INFORMATION
Change to full part number
PACKAGE DIMENSIONS
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
Note: Please see “Document History” about later revised information.
Document Number: 002-04672 Rev. *D
Page 109 of 111
MB9A110A/MB9A110 Series
Document History
Document Title: MB9A110A/MB9A110 Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-04672
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-04672.
No change to document contents or format.
**
AKIH
AKIH
12/16/2014
–
*A
5198491
04/07/2016 Updated to Cypress format.
Added series “MB9A110”. (Page1)
Changed package code as the following in 2 Packages (Page 7), 3 Pin Assignment
(Page 8 to 12), 12.2 Recommended Operating Conditions (Page 60), 13 Ordering
Information (Page 99) and 14 Package Dimensions (Page 100 to 106).
“FTP-64P-M38” to LQD064, “FTP-64P-M39” to LQG064,
“LCC-64P-M24” to “VNC064”, FPT-80P-M37” to “LQH080”,
“FPT-100P-M23” to “LQI100”, “FTP-100P-M06” to “PQH100”,
“BGA-112P-M04” to “LBC112”
*B
5316949
MMIW
06/21/2016
Changed “J-TAG” to” JTAG” in 4 List of Pin Functions (Page 27).
Added note 4 List of Pin Functions (Page 38).
Changed “Ta” to “TA” in 12.2 Recommended Operating Conditions (Page 60).
Added Product number “MB9AF112L” and “MB9AF114L” in Features (Page1), in 1
Product Lineup (Page6), 2 Packages (Page7) and 10 Memory Map (Page51 to 52).
Added Part number “MB9AF112LPMC-G-MJE1” and “MB9AF114LPMC-G-MJE1” in
13 Ordering Information (Page 99).
Updated “12.4.7 Power-on Reset Timing”(page 67)
Updated “14. Package Dimensions”(page 100-106)
Added “15. Errata”(page 107)
*C
*D
5490454
5768637
YSKA
YSAT
03/09/2017
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 90)
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”(Page 76, 78, 80, 82)
06/12/2017 Adapted new cypress logo
Document Number: 002-04672 Rev. *D
Page 110 of 111
MB9A110A/MB9A110 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
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ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2011-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or
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then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source
code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It
is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the
failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress
from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs,
damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04672 Rev. *D
June 12, 2017
Page 111 of 111
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