MB9AF121KPMC-G-JNE2 [CYPRESS]
32-bit ARM® Cortex®-M3 FM3 Microcontroller;![MB9AF121KPMC-G-JNE2](http://pdffile.icpdf.com/pdf2/p00327/img/icpdf/MB9AF121KPMC_2012398_icpdf.jpg)
型号: | MB9AF121KPMC-G-JNE2 |
厂家: | ![]() |
描述: | 32-bit ARM® Cortex®-M3 FM3 Microcontroller 微控制器 |
文件: | 总90页 (文件大小:1628K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MB9A120L Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9A120L Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral
functions such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE11 product categories in FM3 Family Peripheral Manual.
Features
32-bit ARM® Cortex®-M3 Core
Processor version: r2p1
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Up to 40 MHz frequency operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
Various error detection functions available (parity errors,
framing errors, and overrun errors)
24-bit system timer (Sys Tick): System timer for OS task
management
[CSIO]
On-Chip Memories
Full duplex double buffer
[Flash memory]
Built-in dedicated baud rate generator
Overrun error detection function available
64 Kbytes
Read cycle: 0 wait-cycle
Security function for code protection
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
[SRAM]
This series contains 4 Kbyte on-chip SRAM memories that is
connected to System bus of Cortex-M3 core.
LIN break field generation (can be changed to 13-bit to 16-bit
length)
SRAM1: 4 Kbyte
Multi-function Serial Interface (Max four channels)
LIN break delimiter generation (can be changed to 1-bit to
4-bit length)
4 channels without FIFO (ch.0, ch.1, ch.3, ch.5)
Various error detection functions available (parity errors,
Operation mode is selectable from the followings for each
framing errors, and overrun errors)
channel.
UART
CSIO
LIN
[I2C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
I2C
Cypress Semiconductor Corporation
Document Number: 002-05669 Rev.*B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 13, 2017
MB9A120L Series
A/D Converter (Max eight channels)
Multi-function Timer
The Multi-function timer is composed of the following blocks.
[12-bit A/D Converter]
16-bit free-run timer × 3 ch.
Successive Approximation type
Conversion time: 0.8 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Input capture × 3 ch.
Output compare × 6 ch.
A/D activation compare × 1 ch.
Waveform generator × 3 ch.
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion:
4 steps)
16-bit PPG timer × 3 ch.
IGBT mode is contained
D/A Converter (Max one channel)
R-2R type
The following function can be used to achieve the motor
control.
PWM signal output function
10-bit resolution
DC chopper waveform output function
Dead time function
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
Input capture function
16-bit PWM timer
16-bit PPG timer
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
16-/32-bit reload timer
16-/32-bit PWC timer
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built-in. It can set which I/O port the peripheral
function can be allocated to.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Up to 51 high-speed general-purpose I/O Ports@64 pin
Package
External Interrupt Controller Unit
Some ports are 5V tolerant
Up to 19 external interrupt input pins @ 64 pin Package
Include one non-maskable interrupt (NMI) input pin
See List of Pin Functions and I/O Circuit Type to confirm the
corresponding pins.
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
The Hardware watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption modes except RTC, Stop
modes.
Free-running
Periodic (=Reload)
One-shot
Document Number: 002-05669 Rev.*B
Page 2 of 90
MB9A120L Series
Clock and Reset
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Low-Power Consumption Mode
Four low-power consumption modes supported.
Built-in high-speed CR Clock: 4 MHz
Built-in low-speed CR Clock: 100 kHz
Main PLL Clock
Sleep
Timer
RTC
Stop
[Resets]
Reset requests from INITX pin
Power-on reset
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage: VCC = 2.7 V to 5.5 V
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is
asserted.
If external frequency anomaly is detected, interrupt or reset is
asserted.
Document Number: 002-05669 Rev.*B
Page 3 of 90
MB9A120L Series
Contents
1. Product Lineup.................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 13
5. I/O Circuit Type................................................................................................................................................................ 24
6. Handling Precautions ..................................................................................................................................................... 31
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 31
Precautions for Package Mounting.............................................................................................................................. 32
Precautions for Use Environment................................................................................................................................ 33
7. Handling Devices ............................................................................................................................................................ 34
8. Block Diagram................................................................................................................................................................. 36
9. Memory Size .................................................................................................................................................................... 36
10. Memory Map .................................................................................................................................................................... 37
11. Pin Status in Each CPU State ........................................................................................................................................ 40
12. Electrical Characteristics ............................................................................................................................................... 45
12.1 Absolute Maximum Ratings......................................................................................................................................... 45
12.2 Recommended Operating Conditions.......................................................................................................................... 47
12.3 DC Characteristics....................................................................................................................................................... 48
12.3.1Current Rating.............................................................................................................................................................. 48
12.3.2 Pin Characteristics ....................................................................................................................................................... 51
12.4 AC Characteristics....................................................................................................................................................... 52
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 52
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 53
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 54
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL) ......................................... 55
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL).............. 55
12.4.6 Reset Input Characteristics .......................................................................................................................................... 56
12.4.7 Power-on Reset Timing................................................................................................................................................ 56
12.4.8 Base Timer Input Timing.............................................................................................................................................. 57
12.4.9 CSIO/UART Timing...................................................................................................................................................... 58
12.4.10 External Input Timing................................................................................................................................................ 66
12.4.11 I2C Timing................................................................................................................................................................. 67
12.4.12 JTAG Timing............................................................................................................................................................. 68
12.5 12-bit A/D Converter.................................................................................................................................................... 69
12.6 10-bit D/A Converter.................................................................................................................................................... 72
12.7 Low-Voltage Detection Characteristics........................................................................................................................ 73
12.7.1 Low-Voltage Detection Reset....................................................................................................................................... 73
12.7.2 Interrupt of Low-Voltage Detection............................................................................................................................... 74
12.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 75
12.8.1 Write / Erase time......................................................................................................................................................... 75
12.8.2 Write cycles and data hold time ................................................................................................................................... 75
12.9 Return Time from Low-Power Consumption Mode...................................................................................................... 76
12.9.1 Return Factor: Interrupt................................................................................................................................................ 76
12.9.2 Return Factor: Reset.................................................................................................................................................... 78
13. Ordering Information ...................................................................................................................................................... 80
14. Package Dimensions ...................................................................................................................................................... 81
15. Major Changes ................................................................................................................................................................ 87
Document Number: 002-05669 Rev.*B
Page 4 of 90
MB9A120L Series
Document History................................................................................................................................................................. 89
Sales, Solutions, and Legal Information............................................................................................................................. 90
Document Number: 002-05669 Rev.*B
Page 5 of 90
MB9A120L Series
1. Product Lineup
Memory Size
Product name
MB9AF121K/L
On-chip Flash memory
64 Kbytes
4 Kbytes
On-chip SRAM
SRAM1
Function
Product name
MB9AF121K
MB9AF121L
Pin count
CPU
48/52
Cortex-M3
40 MHz
64
Freq.
Power supply voltage range
2.7 V to 5.5 V
4 ch. (Max)
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
ch.0, ch.1, ch.3, ch.5: No FIFO
(In ch.5, only UART and LIN are
available.)
4 ch. (Max)
ch.0, ch.1, ch.3, ch.5: No FIFO
Base Timer
(PWC/Reload timer/PWM/PPG)
8 ch. (Max)
A/D activation
compare
1 ch.
Input capture
Free-run timer
Output compare 6 ch.
Waveform
generator
3 ch.
3 ch.
MF-
Timer
1 unit
1 unit
3 ch.
PPG
(IGBT mode)
3 ch.
Dual Timer
Real-Time Clock
1 unit
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
1 ch. (SW) + 1 ch. (HW)
14 pins (Max) + NMI × 1
36 pins (Max)
8 ch. (1 unit)
1 ch. (Max)
Yes
19 pins (Max) + NMI × 1
51 pins (Max)
2 ch.
High-speed
Low-speed
4 MHz
100 kHz
Built-in CR
Debug Function
Unique ID
SWJ-DP
Yes
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See Electrical Characteristics 12.4 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR.
Document Number: 002-05669 Rev.*B
Page 6 of 90
MB9A120L Series
2. Packages
Product name
MB9AF121K
MB9AF121L
Package
-
LQFP:
QFN:
LQA048 (0.5 mm pitch)
WNY048 (0.5 mm pitch)
-
-
LQFP:
LQFP:
LQFP:
QFN:
LQC052 (0.65 mm pitch)
LQD064 (0.5 mm pitch)
LQG064 (0.65 mm pitch)
WNS064 (0.5 mm pitch)
-
-
-
: Supported
Note:
−
See Package Dimensions for detailed information on each package.
Document Number: 002-05669 Rev.*B
Page 7 of 90
MB9A120L Series
3. Pin Assignment
LQD064/ LQG064
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1
P51/INT01_0/SOT3_1
P52/INT02_0/SCK3_1
P30/TIOB0_1/INT03_2
P31/TIOB1_1/INT04_2
P32/TIOB2_1/INT05_2
1
2
48 P21/AN14/SIN0_0/INT06_1
47 P22/AN13/SOT0_0/TIOB7_1
46 P23/AN12/SCK0_0/TIOA7_1
45 P19
3
4
5
44 P18
6
43 AVRL
7
42 AVRH
P33/INT04_0/TIOB3_1/ADTG_6
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
8
41 AVCC
LQFP- 64
9
40 P17/INT04_1
10
11
12
13
14
15
16
39 P15/AN05/SOT0_1/INT14_0/IC03_2
38 P14/AN04/SIN0_1/INT03_1/IC02_2
37 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2
34 P10/AN00/SCK1_1
33 VCC
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05669 Rev.*B
Page 8 of 90
MB9A120L Series
WNS064
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1
1
2
48 P21/AN14/SIN0_0/INT06_1
47 P22/AN13/SOT0_0/TIOB7_1
46 P23/AN12/SCK0_0/TIOA7_1
45 P19
P51/INT01_0/SOT3_1
3
P52/INT02_0/SCK3_1
4
P30/TIOB0_1/INT03_2
5
44 P18
P31/TIOB1_1/INT04_2
6
43 AVRL
P32/TIOB2_1/INT05_2
7
42 AVRH
QFN- 64
P33/INT04_0/TIOB3_1/ADTG_6
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
8
41 AVCC
9
40 P17/INT04_1
10
11
12
13
14
15
16
39 P15/AN05/SOT0_1/INT14_0/IC03_2
38 P14/AN04/SIN0_1/INT03_1/IC02_2
37 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2
34 P10/AN00/SCK1_1
33 VCC
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05669 Rev.*B
Page 9 of 90
MB9A120L Series
LQA048
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1
1
2
36 P21/AN14/SIN0_0/INT06_1
35 P22/AN13/SOT0_0/TIOB7_1
34 P23/AN12/SCK0_0/TIOA7_1
33 AVRL
P51/INT01_0/SOT3_1
3
P52/INT02_0/SCK3_1
4
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
5
32 AVRH
6
31 AVCC
LQFP- 48
7
30 P15/AN05/SOT0_1/INT14_0/IC03_2
29 P14/AN04/SIN0_1/INT03_1/IC02_2
28 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
8
9
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
10
11
12
27 P12/AN02/SOT1_1/IC00_2
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2
25 P10/AN00/SCK1_1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05669 Rev.*B
Page 10 of 90
MB9A120L Series
WNY048
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1
1
2
36 P21/AN14/SIN0_0/INT06_1
35 P22/AN13/SOT0_0/TIOB7_1
34 P23/AN12/SCK0_0/TIOA7_1
33 AVRL
P51/INT01_0/SOT3_1
3
P52/INT02_0/SCK3_1
4
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
5
32 AVRH
6
31 AVCC
QFN- 48
7
30 P15/AN05/SOT0_1/INT14_0/IC03_2
29 P14/AN04/SIN0_1/INT03_1/IC02_2
28 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
8
9
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
10
11
12
27 P12/AN02/SOT1_1/IC00_2
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2
25 P10/AN00/SCK1_1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05669 Rev.*B
Page 11 of 90
MB9A120L Series
LQC052
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1
1
2
39 P21/AN14/SIN0_0/INT06_1
38 P22/AN13/SOT0_0/TIOB7_1
37 P23/AN12/SCK0_0/TIOA7_1
36 NC
P51/INT01_0/SOT3_1
3
P52/INT02_0/SCK3_1
4
NC
5
35 AVRL
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
6
34 AVRH
LQFP- 52
7
33 AVCC
8
32 P15/AN05/SOT0_1/INT14_0/IC03_2
31 P14/AN04/SIN0_1/INT03_1/IC02_2
30 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
9
10
11
12
13
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
29 P12/AN02/SOT1_1/IC00_2
28 P11/AN01/SIN1_1/INT02_1/FRCK0_2
27 P10/AN00/SCK1_1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05669 Rev.*B
Page 12 of 90
MB9A120L Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-52
1
2
1
2
1
2
VCC
P50
-
INT00_0
SIN3_1
P51
H*1
K
INT01_0
3
4
3
4
3
4
H*2
K
K
SOT3_1
(SDA3_1)
P52
INT02_0
H*2
SCK3_1
(SCL3_1)
P30
5
6
7
-
-
-
-
-
-
TIOB0_1
INT03_2
P31
E
E
E
K
K
K
TIOB1_1
INT04_2
P32
TIOB2_1
INT05_2
P33
INT04_0
TIOB3_1
ADTG_6
P39
8
9
-
-
E
E
K
K
DTTI0X_0
INT06_0
ADTG_2
P3A
6
5
RTO00_0
(PPG00_0)
TIOA0_1
INT07_0
SUBOUT_2
RTCCO_2
P3B
10
11
7
8
6
7
G
G
K
J
RTO01_0
(PPG00_0)
TIOA1_1
Document Number: 002-05669 Rev.*B
Page 13 of 90
MB9A120L Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-52
P3C
RTO02_0
(PPG02_0)
12
13
14
15
9
8
G
G
G
G
K
TIOA2_1
INT18_2
P3D
RTO03_0
(PPG02_0)
10
11
12
9
J
TIOA3_1
P3E
RTO04_0
(PPG04_0)
10
11
K
J
TIOA4_1
INT19_2
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
C
16
17
18
13
14
15
12
13
14
-
-
-
VCC
P46
19
16
15
D
F
X0A
P47
20
21
17
18
16
17
D
B
G
C
X1A
INITX
P49
TIOB0_0
INT20_1
DA0_0
SOT3_2
(SDA3_2)
19
18
22
K
K
-
-
P4A
20
-
19
-
TIOB1_0
INT21_1
23
24
E
E
K
K
SCK3_2
(SCL3_2)
P4B
TIOB2_0
INT22_1
IGTRG_0
P4C
-
-
25
26
-
-
-
-
TIOB3_0
INT12_0
P4D
E
E
K
K
TIOB4_0
INT13_0
Document Number: 002-05669 Rev.*B
Page 14 of 90
MB9A120L Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-52
P4E
27
-
-
TIOB5_0
INT06_2
PE0
E
K
28
29
30
22
23
24
20
21
22
C
J
E
D
A
MD1
MD0
PE2
A
X0
PE3
31
25
23
A
B
X1
32
33
26
-
24
-
VSS
VCC
P10
-
-
AN00
34
27
25
F
L
SCK1_1
(SCL1_1)
P11
AN01
35
28
26
SIN1_1
INT02_1
FRCK0_2
P12
F
M
AN02
36
37
38
29
30
31
27
28
29
F
-
L
SOT1_1
(SDA1_1)
IC00_2
AVSS
P14
AN04
SIN0_1
INT03_1
IC02_2
P15
F
M
AN05
SOT0_1
(SDA0_1)
39
40
32
-
30
-
F
E
M
K
INT14_0
IC03_2
P17
INT04_1
AVCC
AVRH
AVRL
P18
41
42
43
44
45
33
34
35
-
31
32
33
-
-
-
-
E
E
J
J
-
-
P19
Document Number: 002-05669 Rev.*B
Page 15 of 90
MB9A120L Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-52
P23
AN12
46
37
34
I*2
M
SCK0_0
(SCL0_0)
TIOA7_1
P22
AN13
47
48
38
39
35
36
I*2
M
M
SOT0_0
(SDA0_0)
TIOB7_1
P21
AN14
I*1
SIN0_0
INT06_1
P00
49
50
51
52
41
42
43
44
37
38
39
40
E
E
E
E
I
I
I
I
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
53
54
55
45
-
41
-
TDO
E
E
E
I
SWO
P0A
K
K
INT00_2
P0B
-
-
TIOB6_1
INT18_0
P0C
56
57
-
-
TIOA6_1
INT19_0
P0F
E
E
K
H
NMIX
46
42
SUBOUT_0
CROUT_1
RTCCO_0
P62
SCK5_0
(SCL5_0)
58
-
-
E
J
ADTG_3
Document Number: 002-05669 Rev.*B
Page 16 of 90
MB9A120L Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-52
P61
SOT5_0
(SDA5_0)
59
60
47
48
43
44
E
J
TIOB2_2
DTTI0X_2
P60
SIN5_0
TIOA2_2
INT15_1
IGTRG_1
P80
I*2
K
K
61
62
49
50
45
46
L
L
INT16_1
P81
K
J
INT17_1
P82
63
64
-
51
52
47
48
-
L
-
VSS
5, 21, 36, 40
NC
-
*1: 5 V tolerant I/O, without PZR function
*2: 5 V tolerant I/O, with PZR function
Document Number: 002-05669 Rev.*B
Page 17 of 90
MB9A120L Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-52
Pin
function
Pin name
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
ADC
ADTG_2
ADTG_3
ADTG_6
AN00
AN01
AN02
AN04
AN05
AN12
AN13
9
58
8
6
-
-
5
-
-
A/D converter external trigger input pin
34
35
36
38
39
46
47
48
10
22
5
27
28
29
31
32
37
38
39
7
19
-
8
20
-
25
26
27
29
30
34
35
36
6
18
-
7
19
-
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN14
Base Timer TIOA0_1
0
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
TIOB0_0
TIOB0_1
Base Timer TIOA1_1
1
11
23
6
TIOB1_0
TIOB1_1
Base Timer TIOA2_1
12
60
24
7
59
13
25
8
9
48
-
8
44
-
-
43
9
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
2
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
-
47
10
-
Base Timer TIOA3_1
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
3
TIOB3_0
TIOB3_1
-
-
-
Base Timer TIOA4_1
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input pin
Serial wire debug interface data input /
output pin
14
26
15
27
56
55
46
47
50
11
-
12
-
-
-
37
38
42
10
-
11
-
-
-
34
35
38
4
TIOB4_0
Base Timer TIOA5_1
5
TIOB5_0
Base Timer TIOA6_1
6
TIOB6_1
Base Timer TIOA7_1
7
TIOB7_1
SWCLK
Debugger
SWDIO
52
44
40
SWO
TCK
TDI
TDO
TMS
TRSTX
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
JTAG test reset input pin
53
50
51
53
52
49
45
42
43
45
44
41
41
38
39
41
40
37
Document Number: 002-05669 Rev.*B
Page 18 of 90
MB9A120L Series
Pin No
Pin
function
Pin name
Function description
LQFP-64
QFN-64
LQFP-48
LQFP-52
QFN-48
External
Interrupt
INT00_0
INT00_2
INT01_0
INT02_0
INT02_1
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT12_0
INT13_0
INT14_0
INT15_1
INT16_1
INT17_1
INT18_0
INT18_2
INT19_0
INT19_2
INT20_1
INT21_1
INT22_1
NMIX
2
2
-
2
-
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
54
3
3
4
3
4
4
35
38
5
28
31
-
26
29
-
External interrupt request 03 input pin
8
-
-
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
40
6
-
-
-
-
7
-
-
9
6
5
48
27
10
25
26
39
60
61
62
55
12
56
14
22
23
24
57
39
-
36
-
External interrupt request 07 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
External interrupt request 16 input pin
External interrupt request 17 input pin
7
6
-
-
-
-
32
48
49
50
-
30
44
45
46
-
External interrupt request 18 input pin
External interrupt request 19 input pin
9
8
-
-
11
19
20
-
10
18
19
-
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
Non-Maskable Interrupt input pin
46
42
Document Number: 002-05669 Rev.*B
Page 19 of 90
MB9A120L Series
Pin No
Pin
Pin name
P00
Function description
LQFP-64
QFN-64
49
LQFP-48
QFN-48
function
LQFP-52
GPIO
41
37
38
39
40
41
-
P01
P02
P03
P04
P0A
P0B
P0C
P0F
P10
P11
P12
P14
P15
P17
P18
P19
P21
P22
P23
P30
P31
P32
P33
P39
P3A
P3B
P3C
P3D
P3E
P3F
P46
P47
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P60
P61
P62
P80
P81
P82
PE0
PE2
PE3
50
51
52
53
54
55
56
57
34
35
36
38
39
40
44
45
48
47
46
5
42
43
44
45
-
General-purpose I/O port 0
-
-
-
-
46
27
28
29
31
32
-
-
-
39
38
37
-
-
-
-
6
7
8
9
10
11
12
16
17
19
20
-
-
-
-
2
42
25
26
27
29
30
-
-
-
36
35
34
-
-
-
-
5
6
7
8
9
10
11
15
16
18
19
-
-
-
-
2
General-purpose I/O port 1
General-purpose I/O port 2
6
7
8
9
General-purpose I/O port 3
10
11
12
13
14
15
19
20
22
23
24
25
26
27
2
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
3
4
3
4
3
4
60
59
58
61
62
63
28
30
31
48
47
-
49
50
51
22
24
25
44
43
-
45
46
47
20
22
23
Document Number: 002-05669 Rev.*B
Page 20 of 90
MB9A120L Series
Pin No
Pin
function
Pin name
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-52
Multi-
function
Serial
0
SIN0_0
SIN0_1
48
39
36
29
Multi-function serial interface ch.0 input pin
38
47
31
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA0 when it is used in an I2C
(operation mode 4).
SOT0_0
(SDA0_0)
38
35
30
SOT0_1
(SDA0_1)
39
32
37
Multi-function serial interface ch.0 clock I/O
pin.
SCK0_0
(SCL0_0)
This pin operates as SCK0 when it is used in 46
a CSIO (operation mode 2) and as SCL0
when it is used in an I2C (operation mode 4).
34
Multi-
function
Serial
1
SIN1_1
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output
pin.
This pin operates as SOT1 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA1 when it is used in an I2C
(operation mode 4).
35
28
29
26
27
SOT1_1
(SDA1_1)
36
Multi-function serial interface ch.1 clock I/O
pin.
This pin operates as SCK1 when it is used in 34
a CSIO (operation mode 2) and as SCL1
when it is used in an I2C (operation mode 4).
SCK1_1
(SCL1_1)
27
25
Multi-
function
Serial
3
SIN3_1
Multi-function serial interface ch.3 input pin
2
2
3
2
3
Multi-function serial interface ch.3 output
pin.
This pin operates as SOT3 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA3 when it is used in an I2C
(operation mode 4).
SOT3_1
(SDA3_1)
3
SOT3_2
(SDA3_2)
22
-
-
Multi-function serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in
a CSIO (operation mode 2) and as SCL3
when it is used in an I2C (operation mode 4).
SCK3_1
(SCL3_1)
4
4
-
4
-
SCK3_2
(SCL3_2)
23
Document Number: 002-05669 Rev.*B
Page 21 of 90
MB9A120L Series
Pin No
Pin
function
Pin name
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-52
Multi-
function
Serial
5
SIN5_0
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output
pin.
This pin operates as SOT5 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA5 when it is used in an I2C
(operation mode 4).
60
48
44
43
SOT5_0
(SDA5_0)
59
47
Multi-function serial interface ch.5 clock I/O
pin.
This pin operates as SCK5 when it is used in 58
a CSIO (operation mode 2) and as SCL5
when it is used in an I2C (operation mode 4).
SCK5_0
(SCL5_0)
-
-
Multi-
function
Timer
0
Input signal of waveform generator to
control outputs RTO00 to RTO05 of
Multi-function timer 0.
DTTI0X_0
DTTI0X_2
FRCK0_2
9
6
5
59
35
47
28
43
26
16-bit free-run timer ch.0 external clock
input pin
IC00_2
IC02_2
IC03_2
36
38
39
29
31
32
27
29
30
16-bit input capture input pin of
Multi-function timer 0.
ICxx describes channel number.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used
in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used
in PPG0 output mode.
RTO00_0
(PPG00_0)
10
11
7
8
6
7
RTO01_0
(PPG00_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used
in PPG0 output mode.
RTO02_0
(PPG02_0)
12
13
14
15
9
8
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used
in PPG0 output mode.
RTO03_0
(PPG02_0)
10
11
12
9
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used
in PPG0 output mode.
RTO04_0
(PPG04_0)
10
11
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used
in PPG0 output mode.
RTO05_0
(PPG04_0)
IGTRG_0
IGTRG_1
24
60
-
48
-
44
PPG IGBT mode external trigger input pin
Document Number: 002-05669 Rev.*B
Page 22 of 90
MB9A120L Series
Pin No
Pin
function
Pin name
Function description
LQFP-64
QFN-64
LQFP-48
LQFP-52
QFN-48
Real-time
clock
RTCCO_0
RTCCO_2
SUBOUT_0
SUBOUT_2
DA0_0
57
46
7
46
7
19
42
6
42
6
0.5 seconds pulse output pin of Real-time
clock
10
57
10
22
Sub clock output pin
DAC
Reset
D/A converter ch.0 analog output pin
External Reset Input pin.
A reset is valid when INITX="L".
18
INITX
21
18
23
17
21
Mode
Mode 0 pin.
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
Mode 1 pin.
MD0
29
MD1
VCC
VSS
During serial programming to Flash memory, 28
MD1="L" must be input.
22
20
Power
GND
1
1
15
-
13
26
52
24
16
25
17
1
14
-
12
24
48
22
15
23
16
Power supply Pin
GND Pin
18
33
16
32
64
30
19
31
20
Clock
X0
X0A
X1
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
X1A
CROUT_1
AVCC
Built-in high-speed CR-osc clock output port 57
46
33
42
31
Analog
Power
A/D converter and D/A converter analog
41
power supply pin
A/D converter analog reference voltage
input pin
A/D converter and D/A converter GND pin
A/D converter analog reference voltage
input pin
AVRH
AVSS
AVRL
C
42
34
30
35
14
32
28
33
13
Analog
GND
37
43
17
C pin
Power supply stabilization capacity pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05669 Rev.*B
Page 23 of 90
MB9A120L Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is selected.
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
N-ch
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05669 Rev.*B
Page 24 of 90
MB9A120L Series
Type
Circuit
Remarks
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
C
• Open drain output
• CMOS level hysteresis input
Digital input
Digital output
N-ch
Document Number: 002-05669 Rev.*B
Page 25 of 90
MB9A120L Series
Type
Circuit
Remarks
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 5 MΩ
• With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
• CMOS level output.
N-ch
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05669 Rev.*B
Page 26 of 90
MB9A120L Series
Type
Circuit
Remarks
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Digital output
Digital output
P-ch
P-ch
N-ch
• +B input is available
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
Document Number: 002-05669 Rev.*B
Page 27 of 90
MB9A120L Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -12 mA, IOL= 12 mA
• +B input is available
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
H
• CMOS level output
• CMOS level hysteresis input
• 5 V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
P-ch
P-ch
Digital output
Digital output
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
• Only P51, P52.
• When this pin is used as an I2C pin,
the digital output
N-ch
R
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05669 Rev.*B
Page 28 of 90
MB9A120L Series
Type
Circuit
Remarks
I
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• 5 V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
Digital output
Digital output
P-ch
P-ch
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
N-ch
Only P23, P22, P60.
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
J
CMOS level hysteresis input
Mode input
Document Number: 002-05669 Rev.*B
Page 29 of 90
MB9A120L Series
Type
Circuit
Remarks
K
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Digital output
Digital output
P-ch
P-ch
N-ch
Pull-up resistor control
Digital input
R
Standby mode control
Analog output
L
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• IOH= -4 mA, IOL= 4 mA
P-ch
Digital output
Digital output
N-ch
R
Digital input
Standby mode control
Document Number: 002-05669 Rev.*B
Page 30 of 90
MB9A120L Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05669 Rev.*B
Page 31 of 90
MB9A120L Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05669 Rev.*B
Page 32 of 90
MB9A120L Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05669 Rev.*B
Page 33 of 90
MB9A120L Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin, between AVRH pin and AVRL pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
• Surface mount type
Size:
Load capacitance: Approximately 6 pF to 7 pF
• Lead type
Load capacitance: Approximately 6 pF to 7 pF
More than 3.2 mm × 1.5 mm
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as
Can be used as
general-purpose
I/O ports.
External clock
input
X1(PE3),
X1A (P47)
Document Number: 002-05669 Rev.*B
Page 34 of 90
MB9A120L Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05669 Rev.*B
Page 35 of 90
MB9A120L Series
8. Block Diagram
MB9AF121K/L
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
ROM Table
Cortex-M3 Core
@40MHz (Max)
I
D
NVIC
Sys
SRAM1
4 Kbytes
Dual-Timer
WatchDog Timer
( Software)
Flash I/F
Security
On- Chip Flash
64 Kbytes
Clock Reset
Generator
INITX
WatchDog Timer
( Hardware)
CSV
CLK
Main
Osc
Source clock
X0
X1
PLL
Sub
Osc
CR
4MHz
CR
100kHz
X0A
X1A
CROUT
AVCC,
AVSS,
AVRH,
AVRL
ANxx
12-bit A /D Converter
Unit 0
ADTG_x
Power-On
Reset
10-bit D/A Converter
1units
DAx
LVD
LVD Ctrl
C
Regulator
Base Timer
16-bit8ch./
32-bit4ch.
TIOAx
TIOBx
IRQ - Monitor
RTCCO_x,
Real -Time Colck
External Interrupt
SUBOUT_
x
A/D Activation
Compare1ch.
INTx
Controller
NMIX
19 pin + NMI
16-bit Input Capture
3ch.
IC0x
MD0,
MD1
P0x,
P1x,
・
MODE-Ctrl
GPIO
16-bit Free-run Timer
3ch.
FRCKx
PIN-Function-Ctrl
・
16 - bit Output
Compare6ch.
・
Pxx
DTTI0X
RTO0x
Waveform Generator
3ch.
Multi -function Serial I/F
4ch.
(without FIFO ch.0/1/3/5)
SCKx
SINx
SOTx
16- bit PPG
3ch.
IGTRG_x
Multi -function Timer
9. Memory Size
See Memory size in Product Lineup to confirm the memory size.
Document Number: 002-05669 Rev.*B
Page 36 of 90
MB9A120L Series
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
0xE010_0000
0xE000_0000
Reserved
Cortex-M3 Private
Peripherals
0x4006_4000
0x4006_3000
Reserved
Reserved
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5800
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
Reserved
Reserved
Reserved
Reserved
RTC
Reserved
Reserved
MFS
Reserved
Reserved
Reserved
LVD
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
D/AC
Reserved
0x6000_0000
Reserved
0x4400_0000
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Peripherals
Reserved
32Mbytes
Bit band alias
Reserved
0x2008_0000
0x2000_0000
0x1FF8_0000
SRAM1
Reserved
A/DC
Reserved
Base Timer
PPG
Reserved
0x0020_8000
0x0020_0000
0x0010_0008
0x0010_0000
Reserved
Reserved
Security/CR Trim
See " Memory Map
(2)" for the memory size
details.
Reserved
0x4002_1000
0x4002_0000
MFT unit0
Reserved
Dual Timer
Reserved
Flash
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-05669 Rev.*B
Page 37 of 90
MB9A120L Series
Memory Map (2)
MB9AF121L
0x2008_0000
Reserved
0x2000_1000
0x2000_0000
SRAM1
4Kbytes
Reserved
0x0010_0008
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
0x0000_FFF8
0x0000_0000
SA0-7 (8KBx8)
Flash 64Kbytes *
*: See MB9A420L/120L/MB9B120J Series Flash Programming Manual to confirm the detail of Flash memory.
Document Number: 002-05669 Rev.*B
Page 38 of 90
MB9A120L Series
Peripheral Address Map
Start address
End address
Bus
AHB
Peripherals
Flash Memory I/F register
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_3000
0x4006_4000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_8FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_2FFF
0x4006_3FFF
0x41FF_FFFF
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Reserved
PPG
Base Timer
Reserved
APB1
A/D Converter
D/A Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Resister
Reserved
GPIO
Reserved
Low-Voltage Detector
Reserved
APB2
Reserved
Reserved
Multi-function serial Interface
Reserved
Reserved
Real-time clock
Reserved
Reserved
Reserved
Reserved
AHB
Reserved
Reserved
Reserved
Document Number: 002-05669 Rev.*B
Page 39 of 90
MB9A120L Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Document Number: 002-05669 Rev.*B
Page 40 of 90
MB9A120L Series
List of Pin Status
Power-on
reset or
low-voltage
detection
state
Device
internal
reset state
Run mode or
Sleep mode
state
Timer mode,
RTC mode, or
Stop mode state
INITX
input state
Function
group
Power
Power supply
stable
supply
unstable
Power supply stable
Power supply stable
-
-
INITX = 0
-
INITX = 1
-
INITX = 1
-
INITX = 1
SPL = 1
SPL = 0
Maintain
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Hi-Z / Internal input fixed
at 0
previous state
Main crystal
A
oscillator input
pin/
Input enabled Input enabled
Input enabled Input enabled
Input enabled
Input enabled
External main
clock input
selected
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal input fixed
at 0
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal input fixed
at 0
B
Maintain
Maintain
previous state
/ When
previous state
/ When
Hi-Z /
Maintain previous state /
When oscillation stops*1,
Hi-Z /
Main crystal
oscillator output
pin
Internal input
fixed at 0/
or Input
Hi-Z / Internal
input fixed at
0
Hi-Z / Internal
input fixed at 0
oscillation
oscillation
stops*1,
stops*1,
Hi-Z /
Internal input
fixed at 0
Hi-Z /
Internal input
fixed at 0
Internal input fixed at 0
enable
INITX
input pin
Pull-up / Input Pull-up / Input
enabled enabled
Pull-up /
Input enabled enabled
Pull-up / Input
Pull-up / Input
enabled
C
D
Pull-up / Input enabled
Mode
input pin
Input enabled Input enabled
Input enabled Input enabled
Input enabled Input enabled
Input enabled Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Mode
input pin
E
GPIO
Setting
Setting
Setting
Maintain
Maintain
Hi-Z /
selected
disabled
disabled
disabled
previous state
previous state
Input enabled
Document Number: 002-05669 Rev.*B
Page 41 of 90
MB9A120L Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset state
Run mode or
Sleep mode
state
Timer mode,
RTC mode, or
Stop mode state
INITX
input state
Function
group
Power
Power supply
stable
supply
unstable
Power supply stable
Power supply stable
-
-
INITX = 0
-
INITX = 1
-
INITX = 1
-
INITX = 1
SPL = 1
SPL = 0
Maintain
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Hi-Z / Internal input fixed
at 0
previous state
Sub crystal
oscillator input
pin /
External sub
clock input
selected
F
Input enabled Input enabled
Input enabled Input enabled
Input enabled
Input enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal input fixed
at 0
External sub
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal input fixed
at 0
G
Maintain
Hi-Z /
previous
Maintain previous
state/When oscillation
stops*2,
Hi-Z / Internal input fixed
at 0
Sub crystal
oscillator output
pin
Internal input
fixed at 0/
or Input
Hi-Z / Internal
input fixed at
0
state/When
oscillation
stops*2,
Hi-Z / Internal
input fixed at 0
Hi-Z / Internal
input fixed at 0
Maintain
previous state
enable
Setting
disabled
Setting
disabled
Setting
disabled
NMIX selected
Maintain previous state
Resource other
than above
selected
Maintain
previous state
Maintain
previous state
H
Hi-Z /
Input enabled
Hi-Z /
Input enabled
Hi-Z / Internal input fixed
at 0
Hi-Z
Hi-Z
GPIO
selected
JTAG
selected
Pull-up / Input
enabled
Pull-up /
Input enabled
Maintain previous state
Maintain
previous state
Maintain
previous state
I
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z / Internal input fixed
at 0
Document Number: 002-05669 Rev.*B
Page 42 of 90
MB9A120L Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset state
Run mode or
Sleep mode
state
Timer mode,
RTC mode, or
Stop mode state
INITX
input state
Function
group
Power
Power supply
stable
supply
unstable
Power supply stable
Power supply stable
-
-
INITX = 0
-
INITX = 1
-
INITX = 1
-
INITX = 1
SPL = 1
SPL = 0
Resource
selected
Hi-Z /
Input enabled
Hi-Z /
Maintain
Maintain
previous state
Hi-Z / Internal input fixed
at 0
J
Hi-Z
Input enabled previous state
GPIO
selected
External
interrupt
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain previous state
selected
Resource other
than above
selected
Maintain
previous state
Hi-Z /
Maintain
previous state
K
Hi-Z /
Input enabled
Hi-Z / Internal input fixed
at 0
Hi-Z
Hi-Z
Input enabled
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input
fixed at 0 /
Internal input
fixed at 0 /
Analog input
enabled
Internal input
fixed at 0 /
Analog input
enabled
Internal input
fixed at 0 /
Analog input
enabled
Internal input
fixed at 0 /
Analog input
enabled
Analog input
selected
Analog input enabled
L
Resource other
than above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal input fixed
at 0
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input
fixed at 0 /
Internal input
fixed at 0 /
Analog input
enabled
Internal input
fixed at 0 /
Analog input
enabled
Internal input
fixed at 0 /
Analog input
enabled
Internal input
fixed at 0 /
Analog input
enabled
Analog input
selected
Hi-Z
Analog input enabled
External
interrupt
enabled
selected
M
Maintain previous state
Resource other
than above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal input fixed
at 0
GPIO
selected
Document Number: 002-05669 Rev.*B
Page 43 of 90
MB9A120L Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset state
Run mode or
Sleep mode
state
Timer mode,
RTC mode, or
Stop mode state
INITX
input state
Function
group
Power
Power supply
stable
supply
unstable
Power supply stable
Power supply stable
-
-
INITX = 0
-
INITX = 1
-
INITX = 1
-
INITX = 1
SPL = 1
SPL = 0
Analog
output
selected
Setting
disabled
Setting
disabled
Setting
disabled
*3
*4
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain previous state
N
Maintain
previous state
Resource other
than above
selected
Maintain
previous state
Hi-Z /
Input enabled
Hi-Z /
Input enabled
Hi-Z /
Hi-Z
Internal input fixed at 0
GPIO
selected
*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode.
*2: Oscillation is stopped at Stop mode.
*3: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode.
*4: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.
Document Number: 002-05669 Rev.*B
Page 44 of 90
MB9A120L Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
VCC
Unit
Remarks
Min
Max
VSS + 6.5
VSS + 6.5
Power supply voltage*1, *2
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
AVCC
AVRH
VSS + 6.5
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
Input voltage*1
VI
5 V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
-2
V
Clamp maximum current
ICLAMP
+2
+20
10
mA *7
Clamp total maximum current
Σ[ICLAMP
]
mA *7
mA 4 mA type
mA 12 mA type
mA 4 mA type
mA 12 mA type
mA
L level maximum output current*4
L level average output current*5
IOL
-
-
20
4
IOLAV
12
L level total maximum output current
L level total average output current*6
∑IOL
-
-
100
50
∑IOLAV
mA
- 10
- 20
- 4
mA 4 mA type
mA 12 mA type
mA 4 mA type
mA 12 mA type
mA
H level maximum output current*4
H level average output current*5
IOH
-
-
IOHAV
- 12
- 100
- 50
350
+ 150
H level total maximum output current
H level total average output current*6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
mA
mW
Storage temperature
TSTG
- 55
°C
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100 ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
Document Number: 002-05669 Rev.*B
Page 45 of 90
MB9A120L Series
*7:
• See List of Pin Functions and I/O Circuit Type about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
resistor
Digital output
Digital input
+B input (0V to 16V)
N-ch
R
AVCC
Analog input
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-05669 Rev.*B
Page 46 of 90
MB9A120L Series
12.2 Recommended Operating Conditions
(VSS = AVSS = AVRL = 0.0V)
Value
Parameter
Symbol
VCC
Conditions
Unit
Remarks
Min
2.7*2
2.7
Max
5.5
Power supply voltage
-
-
-
-
-
V
V
Analog power supply voltage
AVCC
AVRH
AVRL
CS
5.5
AVCC = VCC
2.7
AVCC
AVSS
10
V
Analog reference voltage
Smoothing capacitor
AVSS
1
V
μF
For Regulator*1
When mounted
on four-layer
PCB
When mounted
on double-sided
single-layer PCB
LQG064,
LQC052,
LQD064,
- 40
- 40
+ 105
+ 85
°C
°C
Operating
TA
temperature LQA048,
WNS064,
WNY048
*1: See C Pin in Handling Devices for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions, or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05669 Rev.*B
Page 47 of 90
MB9A120L Series
12.3 DC Characteristics
12.3.1 Current Rating
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
Typ
Max
CPU: 40 MHz,
Peripheral: 40 MHz
Instruction on Flash
CPU: 40 MHz,
15.5
16
mA
*1, *5
PLL
Run mode
Peripheral: the clock stops
NOP operation
Instruction on Flash
CPU: 40 MHz,
Peripheral: 40 MHz
Instruction on RAM
9
10.6
15
mA
mA
*1, *5
*1
Run
14
mode
ICC
current
High-speed
CR
Run mode
CPU/ Peripheral: 4 MHz*2
Instruction on Flash
1.7
63
88
9
3.0
900
920
12
mA
μA
μA
mA
mA
μA
μA
*1
Sub
CPU/ Peripheral: 32 kHz
Instruction on Flash
*1, *6
*1
VCC
Run mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
CPU/ Peripheral: 100 kHz
Instruction on Flash
Peripheral: 40 MHz
Peripheral: 4 MHz*2
Peripheral: 32 kHz
Peripheral: 100 kHz
*1, *5
*1
1
2.1
Sleep
mode
current
ICCS
58
71
880
890
*1, *6
*1
Sleep mode
Low-speed
CR
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+105°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05669 Rev.*B
Page 48 of 90
MB9A120L Series
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter Symbol
Conditions
Unit
mA
mA
μA
Remarks
*1
name
Typ
Max
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
1.8
2.1
Main
Timer mode
ICCT
-
13
-
2.7
44
*1
*1
*1
*1
*1
*1
*1
Timer
mode
current
Sub
Timer mode
ICCT
730
38
μA
VCC
10
-
μA
RTC
mode
ICCR
RTC mode
Stop mode
current
570
32
μA
9
μA
Stop
mode
current
ICCH
-
540
μA
When LVD is off
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
LVD current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
At not detect
name
Typ
Max
At operation
for reset
Vcc = 5.5 V
At operation
for interrupt
Vcc = 5.5 V
Low-Voltage
detection
circuit (LVD)
power supply
current
0.13
0.3
μA
ICCLVD
VCC
0.13
0.3
μA
At not detect
Flash memory current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Flash
Symbol
Conditions
Unit
Remarks
Typ
Max
memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
9.5
11.2
mA
Document Number: 002-05669 Rev.*B
Page 49 of 90
MB9A120L Series
A/D convertor current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
At operation
At stop
0.7
0.13
0.9
13
mA
μA
Power supply
current
ICCAD
AVCC
AVRH
At operation
At stop
1.1
0.1
1.97
1.7
mA AVRH=5.5V
μA AVRH=5.5V
Reference
power supply
current
ICCAVRH
D/A convertor current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
IDDA
IDSA
Conditions
Unit
Remarks
name
Typ
Max
At operation
AVCC = 3.3 V
At operation
AVCC = 5.0 V
At stop
315
380
μA
*
Power supply
current
AVCC
475
-
580
8
μA
μA
*
*
*: No-load
Document Number: 002-05669 Rev.*B
Page 50 of 90
MB9A120L Series
12.3.2 Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
CMOS
hysteresis
input pin,
MD0, MD1
5V
tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V
tolerant
input pin
-
VCC × 0.8
-
VCC + 0.3
V
H level input
voltage
(hysteresis
input)
VIHS
-
-
-
VCC × 0.8
VSS - 0.3
VSS - 0.3
-
-
-
VSS + 5.5
VCC × 0.2
VCC × 0.2
V
V
V
L level input
voltage
(hysteresis
input)
VILS
VCC ≥ 4.5 V,
IOH = - 4 mA
4mA type
12mA type
4mA type
12mA type
VCC - 0.5
VCC - 0.5
VSS
-
-
-
VCC
VCC
0.4
V
V
V
V
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
H level
output voltage
VOH
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
L level
output voltage
VOL
VCC ≥ 4.5 V,
IOL = 12 mA
VSS
- 5
-
-
0.4
+ 5
VCC < 4.5 V,
IOL = 8 mA
Input leak
current
IIL
-
-
μA
kΩ
Pull-up
resistance
value
VCC ≥ 4.5 V
33
-
50
-
90
RPU
Pull-up pin
VCC < 4.5 V
180
Other than
VCC,
VSS,
Input
capacitance
CIN
AVCC,
AVSS,
AVRH,
AVRL
-
-
5
15
pF
Document Number: 002-05669 Rev.*B
Page 51 of 90
MB9A120L Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
4
4
48
20
When crystal oscillator is
connected
MHz
MHz
Input frequency
Input clock cycle
fCH
When using external
Clock
-
-
4
48
When using external
Clock
X0,
X1
tCYLH
20.83
45
250
55
ns
%
Input clock pulse
width
PWH/tCYLH,
PWL/tCYLH
When using external
Clock
-
Input clock rising
time and falling
time
tCF,
tCR
When using external
Clock
-
-
5
ns
fCM
fCC
-
-
-
-
-
-
40
40
MHz Master clock
MHz Base clock (HCLK/FCLK)
Internal operating
clock frequency*1
fCP0
fCP1
fCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz APB0 bus clock*2
MHz APB1 bus clock*2
MHz APB2 bus clock*2
-
-
-
-
-
-
-
-
25
25
25
25
-
-
-
-
ns
ns
ns
ns
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
tCYCC
tCYCP0
tCYCP1
tCYCP2
Internal operating
clock cycle time*1
APB2 bus clock*2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
Document Number: 002-05669 Rev.*B
Page 52 of 90
MB9A120L Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal oscillator is
connected
kHz When using external clock
-
-
32.768
-
kHz
Input frequency
Input clock cycle
fCL
-
-
32
10
-
-
100
X0A,
X1A
tCYLL
-
31.25
μs
When using external clock
Input clock pulse
width
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external clock
*: See Sub crystal oscillator in Handling Devices for the crystal oscillator used.
X0A
Document Number: 002-05669 Rev.*B
Page 53 of 90
MB9A120L Series
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Conditions
TA = + 25°C,
Unit
Remarks
Min
Max
3.92
4
4.08
3.6 V < VCC ≤ 5.5 V
TA =0°C to + 85°C,
3.6 V < VCC ≤ 5.5 V
TA = - 40°C to + 105°C,
3.6 V < VCC ≤ 5.5 V
TA = + 25°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 20°C to + 85°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 20°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 40°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
3.9
3.88
3.94
3.92
3.9
4
4
4
4
4
4
4
-
4.1
4.12
4.06
4.08
4.1
When trimming*1
Clock frequency
fCRH
MHz
3.88
2.8
4.12
5.2
TA = - 40°C to + 105°C
-
When not trimming
*2
Frequency
stabilization time
tCRWT
-
30
μs
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming.
*2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock.
After setting the trim value, the period when the frequency stability time passes can use the High-speed CR
clock as a source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
Clock frequency
fCRL
-
50
100
150
kHz
Document Number: 002-05669 Rev.*B
Page 54 of 90
MB9A120L Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
fPLLI
-
fPLLO
fCLKPLL
4
5
75
-
-
-
-
-
16
37
150
40
MHz
multiplier
MHz
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
fPLLI
-
fPLLO
fCLKPLL
3.8
19
72
-
4
-
-
4.2
35
150
40
MHz
multiplier
MHz
-
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been
trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
PLL input
clock
PLL macro
clock
oscillation clock
(CLKPLL)
K
M
Main
PLL
divider
divider
N
divider
Document Number: 002-05669 Rev.*B
Page 55 of 90
MB9A120L Series
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol Pin name
Conditions
Unit
Remarks
Min
1
Max
-
Power supply shut down time
Power ramp rate
tOFF
-
-
-
ms
*1
dV/dt
Vcc:0.2 V to 2.7 V
1.2
1000
mV/μs *2
VCC
Time until releasing Power-on
reset
tPRT
-
0.34
-
3.15
ms
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.7 Low-Voltage Detection Characteristics”
Document Number: 002-05669 Rev.*B
Page 56 of 90
MB9A120L Series
12.4.8 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using
as TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet.
Document Number: 002-05669 Rev.*B
Page 57 of 90
MB9A120L Series
12.4.9 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
VCC ≥ 4.5 V
Pin
Parameter
Symbol
Conditions
Unit
name
Min
-
Max
Min
-
Max
8
-
Baud rate
Serial clock cycle time
-
-
-
8
-
Mbps
ns
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVI
tIVSHI
tSHIXI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Master mode
-
-
-
-
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 002-05669 Rev.*B
Page 58 of 90
MB9A120L Series
tSCYC
VOH
SCK
SOT
VOL
VOL
tSLOVI
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
SIN
Master mode
tSLSH
tSHSL
VIH
tR
VIH
tF
VIH
SCK
VIL
VIL
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05669 Rev.*B
Page 59 of 90
MB9A120L Series
CSIO (SPI = 0, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
VCC ≥ 4.5 V
Pin
Symbol
Conditions
Unit
name
Min
-
Max
Min
-
Max
8
-
Baud rate
Serial clock cycle time
-
-
-
8
-
Mbps
ns
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
Master mode
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
50
0
-
-
30
0
-
-
ns
ns
tSLIXI
tSLSH
tSHSL
Serial clock L pulse width
Serial clock H pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 002-05669 Rev.*B
Page 60 of 90
MB9A120L Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05669 Rev.*B
Page 61 of 90
MB9A120L Series
CSIO (SPI = 1, SCINV = 0)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
VCC ≥ 4.5 V
Pin
Symbol
Conditions
Unit
name
Min
-
Max
Min
-
Max
8
-
Baud rate
Serial clock cycle time
-
-
-
8
-
Mbps
ns
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
tIVSLI
tSLIXI
tSOVLI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
Master mode
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 002-05669 Rev.*B
Page 62 of 90
MB9A120L Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05669 Rev.*B
Page 63 of 90
MB9A120L Series
CSIO (SPI = 1, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
VCC ≥ 4.5 V
Pin
name
Symbol
Conditions
Unit
Min
Max
Min
Max
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 002-05669 Rev.*B
Page 64 of 90
MB9A120L Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol Conditions
Unit Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tCYCP + 10
tCYCP + 10
-
-
5
5
ns
ns
ns
ns
tSHSL
CL = 30 pF
tF
-
-
SCK rising time
tR
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
Document Number: 002-05669 Rev.*B
Page 65 of 90
MB9A120L Series
12.4.10 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Min
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Max
ADTG
A/D converter trigger input
1
-
2tCYCP
*
-
ns
FRCKx
ICxx
DTTIxX
IGTRG
INTxx,
NMIX
Free-run timer input clock
Input capture
Waveform enerator
PPG IGBT mode
External interrupt,
NMI
Input pulse
width
tINH,
tINL
1
1
-
-
*2
*3
2tCYCP
2tCYCP
*
*
-
-
-
-
ns
ns
ns
ns
2tCYCP + 100*1
500
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to,
see Block Diagram in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in stop mode, in RTC mode, in timer mode.
Document Number: 002-05669 Rev.*B
Page 66 of 90
MB9A120L Series
12.4.11 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Standard-mode
Fast-mode
Parameter
Symbol Conditions
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
(Repeated) Start condition hold
time
fSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCLclock L width
SCLclock H width
(Repeated) Start condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
CL = 30 pF,
R =
(Vp/IOL)*1
tHDDAT
tSUDAT
tSUSTO
0
3.45*2
0
0.9*3
μs
ns
μs
250
4.0
-
-
100
0.6
-
-
Bus free time between
Stop condition and
Start condition
tBUF
tSP
4.7
-
-
1.3
-
-
μs
4
4
Noise filter
-
2 tCYCP
*
2 tCYCP
*
ns
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05669 Rev.*B
Page 67 of 90
MB9A120L Series
12.4.12 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
TCK,
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
TMS, TDI setup time tJTAGS
TMS, TDI hold time tJTAGH
15
-
ns
TMS, TDI
TCK,
TMS, TDI
15
-
ns
ns
-
-
25
45
TCK,
TDO
TDO delay time
tJTAGD
VCC < 4.5 V
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05669 Rev.*B
Page 68 of 90
MB9A120L Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
Symbol
Unit
Remarks
name
Min
Typ
Max
-
-
-
-
-
-
-
-
-
-
-
12
bit
± 2.0
± 1.5
± 8
± 4.5
± 2.5
± 15
LSB
LSB
mV
AVRH =
2.7 V to 5.5 V
VZT
ANxx
VFST
ANxx
-
AVRH ± 8
AVRH ± 15
mV
0.8*1
-
-
-
μs
AVCC ≥ 4.5 V
AVCC < 4.5 V
Conversion time
-
-
1.0*1
0.24
40
-
-
-
μs
μs
ns
Sampling time*2
tS
tCCK
-
-
10
1000
Compare clock cycle*3
State transition time to
operation permission
Analog input capacity
tSTT
-
-
-
-
-
-
1.0
μs
CAIN
9.7
1.5
2.2
4
pF
AVCC ≥ 4.5 V
AVCC < 4.5 V
Analog input resistor
RAIN
-
-
-
kΩ
Interchannel disparity
Analog port input leak
current
-
-
-
-
-
-
-
-
LSB
μA
V
ANxx
5
Analog input voltage
ANxx
AVRH
AVRL
AVRL
2.7
AVSS
-
-
-
AVRH
AVCC
AVSS
Reference voltage
-
V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=25 MHz
AVCC < 4.5 V, HCLK=40 MHz
sampling time: 240 ns, compare time: 560 ns
sampling time: 300 ns, compare time: 700 ns
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual
Analog Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.
The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05669 Rev.*B
Page 69 of 90
MB9A120L Series
Comparator
REXT
ANxx
RAIN
Analog signal
source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time
RAIN
:
Input resistor of A/D = 1.3 kΩ at 4.5 V < AVCC < 5.5 V ch.0 to ch.2, ch.4, ch.5
Input resistor of A/D = 1.5 kΩ at 4.5 V < AVCC < 5.5 V ch.12 to ch.14
Input resistor of A/D = 1.9 kΩ at 2.7 V < AVCC < 4.5 V ch.0 to ch.2, ch.4, ch.5
Input resistor of A/D = 2.2 kΩ at 2.7 V < AVCC < 4.5 V ch.12 to ch.14
Input capacity of A/D = 9.7 pF at 2.7 V < AVCC < 5.5 V
CAIN
:
REXT
:
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK
:
Compare clock cycle
Document Number: 002-05669 Rev.*B
Page 70 of 90
MB9A120L Series
Definition of 12-bit A/D Converter Terms
• Resolution:
• Integral Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
• Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVRL
AVRH
AVRL
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
Differential Nonlinearity of digital output N =
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-05669 Rev.*B
Page 71 of 90
MB9A120L Series
12.6 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Resolution
Symbol
Unit
Remarks
name
Min
Typ
Max
-
-
-
10
0.69
3.43
+ 4.0
+ 0.9
10.0
+ 5.4
4.50
-
bit
μs
μs
LSB
LSB
mV
mV
kΩ
tC20
tC100
INL
0.47
2.37
- 4.0
- 0.9
-
- 20.0
3.10
2.0
0.58
2.90
-
-
-
-
3.80
-
-
Load 20 pF
Load 100 pF
*
Conversion time
Integral Nonlinearity
Differential Nonlinearity
DNL
*
DAx
Code is 0x000
Code is 0x3FF
D/A operation
D/A stop
Output Voltage offset
VOFF
Analog output impedance
Output undefined period
RO
tR
MΩ
ns
-
70
*: No-load
Document Number: 002-05669 Rev.*B
Page 72 of 90
MB9A120L Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.25
2.30
2.39
Max
2.65
2.70
2.81
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
2.45
2.50
2.60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHR*1 = 00000
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
SVHR*1 = 01000
SVHR*1 = 01001
SVHR*1 = 01010
Same as SVHR = 0000 value
2.48 2.70 2.92
Same as SVHR = 0000 value
2.58 2.80 3.02
Same as SVHR = 0000 value
2.76 3.00 3.24
Same as SVHR = 0000 value
2.94 3.20 3.46
Same as SVHR = 0000 value
3.31 3.60 3.89
Same as SVHR = 0000 value
3.40 3.70 4.00
Same as SVHR = 0000 value
3.68 4.00 4.32
Same as SVHR = 0000 value
3.77 4.10 4.43
Same as SVHR = 0000 value
3.86 4.20 4.54
Same as SVHR = 0000 value
LVD stabilization
tLVDW
*2
-
-
-
-
-
-
8160 × tCYCP
μs
μs
wait time
LVD detection
tLVDDL
200
delay time
*1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low voltage detection
reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05669 Rev.*B
Page 73 of 90
MB9A120L Series
12.7.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Detected voltage
VDL
2.58
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
3.02
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 00011
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
Released voltage VDH
Detected voltage VDL
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
Released voltage VDH
LVD stabilization
tLVDW
-
-
-
-
-
-
8160 × tCYCP
*
μs
μs
wait time
LVD detection
tLVDDL
200
delay time
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05669 Rev.*B
Page 74 of 90
MB9A120L Series
12.8 Flash Memory Write/Erase Characteristics
12.8.1 Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Unit
s
Remarks
Typ
Max
Sector erase time
0.3
0.7
282
5.6
Includes write time prior to internal erase
Half word (16-bit) write time
Chip erase time
16
μs
s
Not including system-level overhead time
Includes write time prior to internal erase
2.4
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
12.8.2 Write cycles and data hold time
Data hold time (year)
Remarks
Erase/write cycles (cycle)
1,000
20*
10*
10,000
*: At average + 85C
Document Number: 002-05669 Rev.*B
Page 75 of 90
MB9A120L Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
tCYCC
μs
High-speed CR Timer mode,
Main Timer mode,
43
83
μs
PLL Timer mode
tICNT
Low-speed CR Timer mode
Sub Timer mode
310
534
620
724
μs
μs
RTC mode,
Stop mode
278
479
μs
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05669 Rev.*B
Page 76 of 90
MB9A120L Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3
Family Peripheral Manual.
Document Number: 002-05669 Rev.*B
Page 77 of 90
MB9A120L Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max*
Sleep mode
149
264
High-speed CR Timer mode,
Main Timer mode,
149
264
μs
PLL Timer mode
tRCNT
Low-speed CR Timer mode
Sub Timer mode
318
308
248
603
583
443
μs
μs
μs
RTC/Stop mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
Document Number: 002-05669 Rev.*B
Page 78 of 90
MB9A120L Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
−
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
The time during the power-on reset/low-voltage detection reset is excluded. See (12.4.7)
Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on
the time during the power-on reset/low -voltage detection reset.
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time
or the main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05669 Rev.*B
Page 79 of 90
MB9A120L Series
13.Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Plastic・QFN
(0.5 mm pitch), 48-pin
(WNY048)
MB9AF121KWQN-G-JNE2
MB9AF121KPMC-G-JNE2
MB9AF121KPMC1-G-JNE2
MB9AF121LPMC1-G-JNE2
MB9AF121LPMC-G-JNE2
MB9AF121LWQN-G-JNE2
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Plastic・LQFP
(0.5 mm pitch), 48-pin
(LQA048)
Plastic・LQFP
(0.65 mm pitch), 52-pin
(LQC052)
Tray
Plastic・LQFP
(0.5 mm pitch), 64-pin
(LQD064)
Plastic・LQFP
(0.65 mm pitch), 64-pin
(LQG064)
Plastic・QFN
(0.5 mm pitch), 64-pin
(WNS064)
Document Number: 002-05669 Rev.*B
Page 80 of 90
MB9A120L Series
14.Package Dimensions
Package Type
Package Code
LQFP 64
LQD064
4
5
D
D1
7
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
5
7
e
A-B D
3
0.10
0.08
C A-B D
BOTTOM VIEW
0.20
C
C
A-B
D
b
8
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A'
A1
10
SECTION A-A'
L1
0.08
C
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
c
0.20
D
D1
e
12.00 BSC.
10.00 BSC.
0.50 BSC
E
12.00 BSC.
10.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
002-13879 **
Document Number: 002-05669 Rev.*B
Page 81 of 90
MB9A120L Series
Package Type
Package Code
LQFP 64
LQG064
4
D
5
7
D1
48
33
33
48
49
32
32
49
E1
E
5
7
4
3
64
17
17
64
1
16
16
1
2
5
7
BOTTOM VIEW
e
3
0.10
C A-B D
0.20
C A-B D
0.13
C
A-B
D
b
8
TOP VIEW
2
A
A
9
SEATI NG
PLA NE
A1
10
0.2 5
L
c
A'
L1
b
0.10
C
SECTION A -A'
SIDE VIEW
DIMENSION
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.27 0.32 0.37
0.09 0.20
0.20
c
D
D1
e
14.00 BSC
12.00 BSC
0.65 BSC
E
14.00 BSC
12.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
0
L1
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
002-13881 **
Document Number: 002-05669 Rev.*B
Page 82 of 90
MB9A120L Series
Package Type
Package Code
LQFP 48
LQA048
4
D
5
7
D1
36
36
25
25
37
24
24
37
E1
E
5
7
4
3
6
48
13
13
48
1
1
12
12
2
A-B
5
D
7
e
0.10
C
3
0.20
C A-B D
0.80
C
A-B
D
b
8
2
A
9
A
SEATING
PLANE
c
A'
0.25
A1
10
b
0.80
C
L1
L
SECTION A-A'
DIMENSIONS
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.15
0.09
0.20
0.27
0.20
c
D
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0
0.75
0.70
8
L1
0.50
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
002-13731 **
Document Number: 002-05669 Rev.*B
Page 83 of 90
MB9A120L Series
Package Type
Package Code
LQFP 52
LQC052
4
D
5
7
D1
39
27
27
39
40
26
26
40
E1
E
4
5
7
3
6
52
14
14
52
1
13
13
1
2
5 7
0.10
C
A-B
D
BOTTOMVIEW
e
3
0.13
C
A-B
D
0.20
C
A-B D
b
8
TOP VIEW
A
2
9 c
A
A1
0.25
SEATING
PLANE
10
L1
b
A'
SECTION A-A'
0.10
C
L
SIDE VIEW
DIMENSION
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.265 0.30 0.365
0.09 0.20
0.20
c
D
D1
e
12.00 BSC
10.00 BSC
0.65 BSC
E
12.00 BSC
10.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
0
L1
PACKAGE OUTLINE, 52 LEAD LQFP
10.0X10.0X1.7 MM LQC052 REV**
002-13880 **
Document Number: 002-05669 Rev.*B
Page 84 of 90
MB9A120L Series
Package Type
Package Code
QFN 48
WNY048
0.15
C
A B
D
D2
A
25
36
0.10
2X
C
24
37
0.15
C A B
(ND-1)
5
e
E2
E
13
48
9
c
12
1
INDEX MARK
8
L
b
e
0.10
0.05
C
C
A B
B
0.10
2X
C
TOP VIEW
4
BOTTOM VIEW
A
SEATING PLANE
0.05
C
A1
9
C
SIDE VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTALNUMBER OFTERMINALS.
MIN. NOM. MAX.
0.80
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OFTHE TERMINAL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
A
0.00
0.05
1
D
E
b
7.00 BSC
7.00 BSC
0.25
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
6. MAX. PACKAGE WARPAGE IS 0.05mm.
0.18
0.30
D
4.65 BSC
4.65 BSC
0.50 BSC
0.30 REF
0.50
2
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILLBE LOCATEDWITHIN INDICATEDZONE.
E
e
2
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT
SINK SLUG AS WELL AS THE TERMINALS.
c
10. JEDEC SPECIFICATION NO. REF : N/A
L
0.45
0.55
PACKAGE OUTLINE, 48 LEADQFN
7.00X7.00X0.80 MMWNY0484.65X4.65MMEPAD(SAWN) REV**
002-16422 **
Document Number: 002-05669 Rev.*B
Page 85 of 90
MB9A120L Series
Package Type
Package Code
QFN 64
WNS064
0.15
C
A B
D2
D
A
33
48
0.10
2X
C
0.15
C
A B
32
49
(ND-1)
5
e
E
E2
17
64
c
16
1
INDEX MARK
8
L
9
b
e
0.10
C
C
A B
B
0.05
0.10
2X
C
4
TOP VIEW
BOTTOM VIEW
A
SEATING PLANE
0.05
C
A1
9
C
SIDE VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTALNUMBER OFTERMINALS.
MIN. NOM. MAX.
0.80
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OFTHE TERMINAL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
A
1
0.00
0.05
D
E
b
9.00 BSC
9.00 BSC
0.25
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
6. MAX. PACKAGE WARPAGE IS 0.05mm.
0.20
0.30
D
E
e
7.20 BSC
7.20 BSC
0.50 BSC
0.50 REF
0.40
2
2
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILLBE LOCATEDWITHIN INDICATEDZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT
SINK SLUG AS WELL AS THE TERMINALS.
c
10. JEDEC SPECIFICATION NO. REF : N/A
L
0.35
0.45
PACKAGE OUTLINE, 64 LEADQFN
9.00X9.00X0.80MMWNS0647.20X7.20MMEPAD(SAWN) REV**
002-16424 **
Document Number: 002-05669 Rev.*B
Page 86 of 90
MB9A120L Series
15.Major Changes
Spansion Publication Number: MB9A120L_DS706-00064
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 0.2
-
-
Company name and layout design change
Revision 1.0
-
-
Preliminary → Full Production
2
3
4
Features
Features
Features
Revised I2C operation mode name
Revised the value of A/D conversion time
Revised Channel number of MFT A/D activation compare
・Added notes of Built-in high speed CR accuracy
・Revised channel number of MFT A/D activation compare
6
Product Lineup
List Of Pin Function
・List of pin numbers
17
Corrected I/O circuit type of P80,P81,P82
29
37
I/O Circuit Type
Block Diagram
Added the remarks of type L
Revised Channel number of MFT A/D activation compare
Electrical Characteristics
2. Recommended Operating Conditions
Electrical Characteristics
3.DC Characteristics (1) Current Rating
47
Corrected the minimum value of AVRH voltage
48,49
Revised the values of “TBD”
・Corrent the pin name of power supply current
・Added the at stop condition of power supply current
・Added the remark of reference power supply current
Electrical Characteristics
3.DC Characteristics (1) Current Rating
・A/D converter current
49
Electrical Characteristics
3.AC Characteristics (6)Power-on Reset
Timing
55
66
Revised the values of “TBD”
・Revised I2C operation mode name
・Revised the value of noise filter
Electrical Characteristics
3.AC Characteristics (10) I2C Timing
・Revised the value of zero transition valtage and full-scale
transiton valtage
・Revised the value of conversion time, sampling time,
compare clock cycle
・Corrected the value of state transition time to operation
permission
Electrical Characteristics
5. 12-bit A/D Converter
68
・Corrected the minimum value of AVRH voltage
・Revised the notes explanation
・Delete (Preliminary value) description
Electrical Characteristics
6. 10-bit D/A Converter
Electrical Characteristics
7. Low-Voltage Detection Characteristics
71
・Delete (Preliminary value) description
・Corrected the values of SVHR and SVHI
72,73
・Revised the values of “TBD”
・Revised the values of typical
・Revised the notes of Erase/write cycles and data hold time
・Delete (target value) description
Electrical Characteristics
8. Flash Memory Write/Erase
Characteristics
74
Electrical Characteristics
9. Return Time from Low-Power
Consumption Mode
75,77
84,85
Revised the values of “TBD”
Package Dimensions
Added the figures of LCC-48P-M74 and LCC-64P-M25
Revision 2.0
26
I/O Circuit Type
Added about +B input
Memory Map
· Memory map(2)
39
Added the summary of Flash memory sector and the note
Document Number: 002-05669 Rev.*B
Page 87 of 90
MB9A120L Series
Page
46, 47
48
Section
Change Results
Electrical Characteristics
1. Absolute Maximum Ratings
Electrical Characteristics
2. Recommended Operation Conditions
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
· Added the Clamp maximum current
· Added about +B input
Added the note about less than the minimum power supply
voltage
· Changed the table format
· Added Main TIMER mode current
49, 50
56
Added the figure of Main PLL connection
57
Changed the figure of timing
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition
voltage
59-66
(8) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
70
81
Ordering Information
Changed notation of part number
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05669 Rev.*B
Page 88 of 90
MB9A120L Series
Document History
Document Title: MB9A120L Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05669
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-05669.
No change to document contents or format.
**
-
AKIH
AKIH
03/31/2015
*A
5168181
03/28/2016 Updated to Cypress format.
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply
rise time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments
(Page 56)
Modified RTC description in “Features, Real-Time Clock(RTC)” as below
Changed starting count value from 01 to 00. Deleted “second , or day of the week” in
the Interrupt function (Page 2)
Added Notes for JTAG (Page 23), Changed “J-TAG” to” JTAG” in “4 List of Pin
Functions” (Page 18)
*B
5658524
YSKA
03/13/2017
Updated Package code and dimensions as follows (Page 7-12, 47, 80 -86)
FPT-48P-M49 -> LQA048, LCC-48P-M74 -> WNY048,
FPT-52P-M02 -> LQC052, FPT-64P-M38 -> LQD064,
FPT-64P-M39 -> LQG064, LCC-64P-M25 -> WNS064
Added the Baud rate spec in “12.4.9 CSIO/UART Timing”(Page 58, 60, 62, 64)
Document Number: 002-05669 Rev.*B
Page 89 of 90
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Document Number: 002-05669 Rev.*B
March 13, 2017
Page 90 of 90
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