MB9AF131LBPMC1-G-SNE2 [CYPRESS]
32-bit ARM® Cortex®-M3 FM3 Microcontroller;型号: | MB9AF131LBPMC1-G-SNE2 |
厂家: | CYPRESS |
描述: | 32-bit ARM® Cortex®-M3 FM3 Microcontroller 微控制器 |
文件: | 总86页 (文件大小:1295K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MB9A130LB Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9A130LB Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power
consumption mode and competitive cost.
The MB9A130LB Series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and has peripheral
functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C).
The products which are described in this data sheet are placed into TYPE3 product categories in FM3 Family Peripheral Manual.
Features
32-bit ARM® Cortex®-M3 Core
Processor version: r2p1
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
Up to 20 MHz Operation Frequency
Integrated Nested Vectored Interrupt Controller (NVIC): 1
channel NMI (non-maskable interrupt) and
32 channels' peripheral interrupts and 8 priority levels
[I2C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
24-bit System timer (Sys Tick): System timer for OS task
management
A/D Converter (Max 8 channels)
On-chip Memories
[12-bit A/D Converter]
[Flash memory]
Successive Approximation type
Conversion time: Min. 1.0 μs
Up to 128 Kbytes
Read cycle: 0 wait-cycle
Security function for code protection
Priority conversion available (priority at 2 levels)
Scanning conversion mode
[SRAM]
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion:
4 steps)
This series contains 8 Kbyte on-chip SRAM that is connected
to System bus of Cortex-M3 core.
SRAM1: 8 Kbytes
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
Multi-function Serial Interface (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
UART
CSIO
I2C
16-/32-bit reload timer
16-/32-bit PWC timer
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Cypress Semiconductor Corporation
Document Number: 002-05671 Rev.*B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 23, 2017
MB9A130LB Series
General Purpose I/O Port
Watchdog Timer (2 channels)
This series can use its pins as general purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated.
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
Capable of pull-up control per pin
Hardware watchdog timer is clocked by built-in Low-speed CR
oscillator. Therefore, Hardware watchdog is active in any low
power consumption mode except RTC and Stop and Deep
Standby RTC and Deep Standby Stop modes.
Capable of reading pin level directly
Built-in the port relocate function
Up to 52 fast general purpose I/O Ports@64 pin Package
Clock and Reset
Some pins are 5V tolerant I/O
See List of Pin Functions and I/O Circuit Type to confirm the
corresponding pins.
[Clocks]
Five clock sources (2 external oscillators, 2 built-in CR
oscillators, and Main PLL) that are dynamically selectable.
Multi-function Timer
Main Clock:
Sub Clock:
4 MHz to 20 MHz
32.768 kHz
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch.
Input capture × 4 ch.
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock:100 kHz
Main PLL Clock
Output compare × 6 ch.
A/D activation compare × 1 ch.
Waveform generator × 3 ch.
16-bit PPG timer × 3 ch.
[Resets]
Reset requests from INITX pin
Power on reset
The following function can be used to achieve the motor
control.
Software reset
PWM signal output function
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
DC chopper waveform output function
Dead time function
Input capture function
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
If external clock failure (clock stop) is detected, reset is
Real-time clock (RTC)
asserted.
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
If external frequency anomaly is detected, interrupt or reset is
asserted.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Low Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage has been set, Low
Voltage Detector generates an interrupt or reset.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
External Interrupt Controller Unit
Up to 8 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Document Number: 002-05671 Rev.*B
Page 2 of 86
MB9A130LB Series
Low Power Consumption Mode
Debug
Six low power consumption modes supported.
Serial Wire JTAG Debug Port (SWJ-DP)
Sleep
Power Supply
Wide range voltage: VCC = 1.8 V to 5.5 V
Timer
RTC
Stop
Deep Standby RTC
Deep Standby Stop
Back up register is 16 bytes.
Document Number: 002-05671 Rev.*B
Page 3 of 86
MB9A130LB Series
Contents
1. Product Lineup.................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 25
6. Handling Precautions ..................................................................................................................................................... 30
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 30
Precautions for Package Mounting.............................................................................................................................. 31
Precautions for Use Environment................................................................................................................................ 32
7. Handling Devices ............................................................................................................................................................ 33
8. Block Diagram................................................................................................................................................................. 35
9. Memory Size .................................................................................................................................................................... 36
10. Memory Map .................................................................................................................................................................... 36
11. Pin Status in Each CPU State ........................................................................................................................................ 39
12. Electrical Characteristics ............................................................................................................................................... 45
12.1 Absolute Maximum Ratings......................................................................................................................................... 45
12.2 Recommended Operating Conditions.......................................................................................................................... 46
12.3 DC Characteristics....................................................................................................................................................... 47
12.3.1 Current Rating.............................................................................................................................................................. 47
12.3.2 Pin Characteristics ....................................................................................................................................................... 50
12.4 AC Characteristics....................................................................................................................................................... 51
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 51
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 52
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 52
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL).................................................. 53
12.4.5 Operating Conditions of Main PLL (In the case of using built-in High-speed CR clock for input clock of Main PLL).... 53
12.4.6 Reset Input Characteristics .......................................................................................................................................... 54
12.4.7 Power-on Reset Timing................................................................................................................................................ 54
12.4.8 Base Timer Input Timing.............................................................................................................................................. 55
12.4.9 CSIO/UART Timing...................................................................................................................................................... 56
12.4.10 External Input Timing................................................................................................................................................ 64
12.4.11 I2C Timing................................................................................................................................................................. 65
12.4.12 JTAG Timing............................................................................................................................................................. 66
12.5 12-bit A/D Converter.................................................................................................................................................... 67
12.6 Low-Voltage Detection Characteristics........................................................................................................................ 70
12.6.1 Low-Voltage Detection Reset....................................................................................................................................... 70
12.6.2 Interrupt of Low-voltage Detection ............................................................................................................................... 71
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 73
12.7.1 Write / Erase time......................................................................................................................................................... 73
12.7.2 Write cycles and data hold time ................................................................................................................................... 73
12.8 Return Time from Low-Power Consumption Mode...................................................................................................... 74
12.8.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 74
12.8.2 Return Factor: Reset.................................................................................................................................................... 76
13. Ordering Information ...................................................................................................................................................... 78
14. Package Dimensions ...................................................................................................................................................... 79
15. Major Changes ................................................................................................................................................................ 84
Document Number: 002-05671 Rev.*B
Page 4 of 86
MB9A130LB Series
Document History................................................................................................................................................................. 85
Sales, Solutions, and Legal Information............................................................................................................................. 86
Document Number: 002-05671 Rev.*B
Page 5 of 86
MB9A130LB Series
1. Product Lineup
Memory size
Product name
On-chip Flash
MB9AF131KB/LB
64 Kbytes
MB9AF132KB/LB
128 Kbytes
8 Kbytes
On-chip SRAM
SRAM1
8 Kbytes
Function
MB9AF131KB
MB9AF132KB
MB9AF131LB
MB9AF132LB
Product name
Pin count
48
64
Cortex-M3
20 MHz
CPU
Freq.
Power supply voltage range
1.8 V to 5.5 V
MF Serial Interface
(UART/CSIO/I2C)
4 ch. (Max)
8 ch. (Max)
(CSIO and I2C is Max 3 ch.)
Base Timer
(PWC/ Reload timer/PWM/PPG)
8 ch. (Max)
A/D activation
1 ch.
compare
Input capture
Free-run timer
4 ch.
3 ch.
MF-
Timer
1 unit (Max)
Output
compare
6 ch.
Waveform
generator
3 ch.
3 ch.
PPG
Real-time clock
1 unit
1 ch. (SW) + 1 ch. (HW)
Watchdog timer
External Interrupts
general purpose I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
6 pins (Max) + NMI × 1
37 pins (Max)
8 pins (Max) + NMI × 1
52 pins (Max)
6 ch. (1 unit)
8 ch. (1 unit)
Yes
LVD (Low Voltage Detector)
2 ch.
High-speed
Built-in CR
4 MHz
100 kHz
SWJ-DP
Low-speed
Debug Function
Note:
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the I/O port according to your function use.
See Electrical Characteristics (12.4) AC Characteristics (12.4.3) Built-in CR Oscillation Characteristics for accuracy of built-in
CR.
Document Number: 002-05671 Rev.*B
Page 6 of 86
MB9A130LB Series
2. Packages
Product name
MB9AF131KB
MB9AF132KB
MB9AF131LB
MB9AF132LB
Package
LQFP:
QFN:
LQA048 (0.5mm pitch)
VNA048
-
-
-
LQFP:
LQFP:
QFN:
LQD064 (0.5mm pitch)
LQG064 (0.65mm pitch)
VNC064
-
-
: Supported
Note:
See Package Dimensions for detailed information on each package.
Document Number: 002-05671 Rev.*B
Page 7 of 86
MB9A130LB Series
3. Pin Assignment
LQA048
(TOP VIEW)
VCC
P50 / SIN3_1 / INT00_0
P51 / SOT3_1 / INT01_0
P52 / SCK3_1 / INT02_0
P39 / DTTI0X_0 / ADTG_2
1
2
3
4
5
6
7
8
9
36 P21 / SIN0_0 / INT06_1 / WKUP2
35 P22 / SOT0_0 / TIOB7_1
34 P23 / SCK0_0 / TIOA7_1
33 AVSS
32 AVRH
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2
P3B / TIOA1_1 / RTO01_0
31 AVCC
LQFP - 48
30 P15 / AN05 / IC03_2
P3C / TIOA2_1 / RTO02_0
29 P14 / AN04 / INT03_1 / IC02_2
28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
27 P12 / AN02 / SOT1_1 / IC00_2
26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1
25 P10 / AN00
P3D / TIOA3_1 / RTO03_0
P3E / TIOA4_1 / RTO04_0 10
P3F / TIOA5_1 / RTO05_0 11
VSS 12
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05671 Rev.*B
Page 8 of 86
MB9A130LB Series
VNA048
(TOP VIEW)
VCC
P50 / SIN3_1 / INT00_0
1
2
3
4
5
6
7
8
9
36 P21 / SIN0_0 / INT06_1 / WKUP2
35 P22 / SOT0_0 / TIOB7_1
34 P23 / SCK0_0 / TIOA7_1
33 AVSS
P51 / SOT3_1 / INT01_0
P52 / SCK3_1 / INT02_0
P39 / DTTI0X_0 / ADTG_2
32 AVRH
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2
P3B / TIOA1_1 / RTO01_0
31 AVCC
QFN - 48
30 P15 / AN05 / IC03_2
P3C / TIOA2_1 / RTO02_0
29 P14 / AN04 / INT03_1 / IC02_2
28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
27 P12 / AN02 / SOT1_1 / IC00_2
26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1
25 P10 / AN00
P3D / TIOA3_1 / RTO03_0
P3E / TIOA4_1 / RTO04_0 10
P3F / TIOA5_1 / RTO05_0 11
VSS 12
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05671 Rev.*B
Page 9 of 86
MB9A130LB Series
LQD064/LQG064
(TOP VIEW)
VCC
P50 / SIN3_1 / INT00_0
1
2
3
4
5
6
7
8
9
48 P21 / SIN0_0 / INT06_1 / WKUP2
47 P22 / SOT0_0 / TIOB7_1
46 P23 / SCK0_0 / TIOA7_1
45 P19 / SCK2_2
P51 / SOT3_1 / INT01_0
P52 / SCK3_1 / INT02_0
P30 / TIOB0_1 / INT03_2
44 P18 / AN08 / SOT2_2
43 AVSS
P31 / SCK6_1 / TIOB1_1 / INT04_2
P32 / SOT6_1 / TIOB2_1 / INT05_2
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6
P39 / DTTI0X_0 / ADTG_2
42 AVRH
41 AVCC
LQFP - 64
40 P17 / AN07 / SIN2_2 / INT04_1
39 P15 / AN05 / IC03_2
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10
P3B / TIOA1_1 / RTO01_0 11
P3C / TIOA2_1 / RTO02_0 12
P3D / TIOA3_1 / RTO03_0 13
P3E / TIOA4_1 / RTO04_0 14
P3F / TIOA5_1 / RTO05_0 15
VSS 16
38 P14 / AN04 / INT03_1 / IC02_2
37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
36 P12 / AN02 / SOT1_1 / IC00_2
35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1
34 P10 / AN00
33 VCC
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05671 Rev.*B
Page 10 of 86
MB9A130LB Series
VNC064
(TOP VIEW)
VCC
P50 / SIN3_1 / INT00_0
1
2
3
4
5
6
7
8
9
48 P21 / SIN0_0 / INT06_1 / WKUP2
47 P22 / SOT0_0 / TIOB7_1
46 P23 / SCK0_0 / TIOA7_1
45 P19 / SCK2_2
P51 / SOT3_1 / INT01_0
P52 / SCK3_1 / INT02_0
P30 / TIOB0_1 / INT03_2
44 P18 / AN08 / SOT2_2
43 AVSS
P31 / SCK6_1 / TIOB1_1 / INT04_2
P32 / SOT6_1 / TIOB2_1 / INT05_2
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6
P39 / DTTI0X_0 / ADTG_2
42 AVRH
41 AVCC
QFN - 64
40 P17 / AN07 / SIN2_2 / INT04_1
39 P15 / AN05 / IC03_2
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10
P3B / TIOA1_1 / RTO01_0 11
P3C / TIOA2_1 / RTO02_0 12
P3D / TIOA3_1 / RTO03_0 13
P3E / TIOA4_1 / RTO04_0 14
P3F / TIOA5_1 / RTO05_0 15
VSS 16
38 P14 / AN04 / INT03_1 / IC02_2
37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
36 P12 / AN02 / SOT1_1 / IC00_2
35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1
34 P10 / AN00
33 VCC
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05671 Rev.*B
Page 11 of 86
MB9A130LB Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-48
QFN-48
1
2
1
2
VCC
-
P50
INT00_0
SIN3_1
P51
G
F
F
INT01_0
3
3
G
SOT3_1
(SDA3_1)
P52
INT02_0
4
5
4
-
G
E
F
F
SCK3_1
(SCL3_1)
P30
TIOB0_1
INT03_2
P31
TIOB1_1
6
7
-
-
E
E
F
F
SCK6_1
(SCL6_1)
INT04_2
P32
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
P39
8
9
-
E
E
F
5
DTTI0X_0
ADTG_2
P3A
H
RTO00_0
(PPG00_0)
10
6
E
H
TIOA0_1
RTCCO_2
SUBOUT_2
Document Number: 002-05671 Rev.*B
Page 12 of 86
MB9A130LB Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-48
QFN-48
P3B
RTO01_0
11
12
13
14
15
7
E
E
E
E
E
H
H
H
H
H
(PPG00_0)
TIOA1_1
P3C
RTO02_0
(PPG02_0)
8
TIOA2_1
P3D
RTO03_0
(PPG02_0)
9
TIOA3_1
P3E
RTO04_0
(PPG04_0)
10
11
TIOA4_1
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
16
17
18
12
13
14
-
-
-
C
VCC
P46
19
15
D
M
X0A
P47
20
21
22
16
17
18
D
B
E
N
C
H
X1A
INITX
P49
TIOB0_0
P4A
23
24
19
-
E
E
H
H
TIOB1_0
P4B
TIOB2_0
Document Number: 002-05671 Rev.*B
Page 13 of 86
MB9A130LB Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-48
QFN-48
P4C
TIOB3_0
25
26
-
-
E
E
H
H
SCK7_1
(SCL7_1)
P4D
TIOB4_0
SOT7_1
(SDA7_1)
P4E
TIOB5_0
INT06_2
SIN7_1
PE0
27
-
E
F
28
29
30
20
21
22
C
H
A
P
D
A
MD1
MD0
PE2
X0
PE3
31
23
A
B
X1
32
33
24
-
VSS
-
-
VCC
P10
34
35
25
26
F
F
J
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
IC02_0
WKUP1
P12
L
AN02
36
37
27
28
F
F
J
J
SOT1_1
(SDA1_1)
IC00_2
P13
AN03
SCK1_1
(SCL1_1)
IC01_2
RTCCO_1
SUBOUT_1
Document Number: 002-05671 Rev.*B
Page 14 of 86
MB9A130LB Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-48
QFN-48
P14
AN04
INT03_1
IC02_2
P15
38
39
40
29
30
-
F
F
F
K
J
AN05
IC03_2
P17
AN07
SIN2_2
INT04_1
AVCC
AVRH
AVSS
P18
K
41
42
43
31
32
33
-
-
-
AN08
44
45
46
-
F
J
SOT2_2
(SDA2_2)
P19
-
E
G
H
H
SCK2_2
(SCL2_2)
P23
SCK0_0
(SCL0_0)
34
TIOA7_1
P22
SOT0_0
(SDA0_0)
47
48
35
36
G
G
H
G
TIOB7_1
P21
SIN0_0
INT06_1
WKUP2
P00
49
50
51
37
38
39
E
E
E
E
E
E
TRSTX
P01
TCK
SWCLK
P02
TDI
Document Number: 002-05671 Rev.*B
Page 15 of 86
MB9A130LB Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFN-64
LQFP-48
QFN-48
P03
52
53
54
40
41
-
TMS
E
E
E
E
E
F
SWDIO
P04
TDO
SWO
P0A
SIN4_0
INT00_2
P0B
SOT4_0
(SDA4_0)
55
56
-
-
E
E
H
H
TIOB6_1
P0C
SCK4_0
(SCL4_0)
TIOA6_1
P0F
NMIX
CROUT_1
RTCCO_0
57
42
E
I
SUBOUT_0
WKUP0
P62
SCK5_0
(SCL5_0)
58
59
-
I
I
H
H
ADTG_3
P61
SOT5_0
(SDA5_0)
43
TIOB2_2
DTTI0X_2
P60
SIN5_0
TIOA2_2
INT15_1
IC00_0
WKUP3
P80
60
44
I
G
61
62
63
64
45
46
47
48
G
G
G
-
O
O
O
P81
P82
VSS
Document Number: 002-05671 Rev.*B
Page 16 of 86
MB9A130LB Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-64
QFN-64
Pin
function
Pin name
Function description
LQFP-48
QFN-48
ADC
ADTG_2
ADTG_3
ADTG_6
AN00
9
5
-
A/D converter external trigger input pin
58
8
-
34
35
36
37
38
39
40
44
10
22
5
25
26
27
28
29
30
-
AN01
AN02
AN03
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN04
AN05
AN07
AN08
-
Base Timer
0
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_1
TIOB1_0
TIOB1_1
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_1
TIOB3_0
TIOB3_1
TIOA4_1
TIOB4_0
TIOA5_1
TIOB5_0
TIOA6_1
TIOB6_1
TIOA7_1
TIOB7_1
SWCLK
SWDIO
SWO
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
6
18
-
Base Timer
1
11
23
6
7
19
-
Base Timer
2
12
60
24
7
8
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
44
-
-
59
13
25
8
43
9
Base Timer
3
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
-
-
Base Timer
4
Base timer ch.4 TIOA pin
14
26
15
27
56
55
46
47
50
52
53
49
50
51
52
53
10
-
Base timer ch.4 TIOB pin
Base Timer
5
Base timer ch.5 TIOA pin
11
-
Base timer ch.5 TIOB pin
Base Timer
6
Base timer ch.6 TIOA pin
-
Base timer ch.6 TIOB pin
-
Base Timer
7
Base timer ch.7 TIOA pin
34
35
38
40
41
37
38
39
40
41
Base timer ch.7 TIOB pin
Debugger
Serial wire debug interface clock input pin
Serial wire debug interface data input / output pin
Serial wire viewer output pin
JTAG reset Input pin
TRSTX
TCK
JTAG test clock input pin
TDI
JTAG test data input pin
TMS
JTAG test mode state input/output pin
JTAG debug data output pin
TDO
Document Number: 002-05671 Rev.*B
Page 17 of 86
MB9A130LB Series
Pin No
LQFP-64
QFN-64
Pin
function
LQFP-48
QFN-48
Pin name
Function description
External
Interrupt
INT00_0
INT00_2
INT01_0
INT02_0
INT02_1
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_2
INT06_1
INT06_2
INIT15_1
NMIX
P00
2
2
-
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
54
3
3
4
4
35
38
5
26
29
-
External interrupt request 03 input pin
External interrupt request 04 input pin
8
-
40
6
-
-
External interrupt request 05 input pin
External interrupt request 06 input pin
7
-
48
27
60
57
49
50
51
52
53
54
55
56
57
34
35
36
37
38
39
40
44
45
48
47
46
36
-
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
44
42
37
38
39
40
41
-
GPIO
P01
P02
P03
P04
General-purpose I/O port 0
P0A
P0B
-
P0C
-
P0F
42
25
26
27
28
29
30
-
P10
P11
P12
P13
P14
General-purpose I/O port 1
General-purpose I/O port 2
P15
P17
P18
-
P19
-
P21
36
35
34
P22
P23
Document Number: 002-05671 Rev.*B
Page 18 of 86
MB9A130LB Series
Pin No
LQFP-64
QFN-64
Pin
function
LQFP-48
QFN-48
Pin name
Function description
GPIO
P30
P31
P32
P33
P39
P3A
P3B
P3C
P3D
P3E
P3F
P46
P47
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P60
P61
P62
P80
P81
P82
PE0
PE2
PE3
5
-
6
-
7
-
8
-
9
5
6
7
8
9
General-purpose I/O port 3
10
11
12
13
14
15
19
20
22
23
24
25
26
27
2
10
11
15
16
18
19
-
General-purpose I/O port 4
-
-
-
2
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
3
3
4
4
60
59
58
61
62
63
28
30
31
44
43
-
45
46
47
20
22
23
Document Number: 002-05671 Rev.*B
Page 19 of 86
MB9A130LB Series
Pin No
LQFP-64
QFN-64
Pin
function
LQFP-48
QFN-48
Pin name
Function description
Multi-
SIN0_0
Multi-function serial interface ch.0 input pin
48
36
function
Serial
0
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA0 when it is used in an I2C (operation mode
4).
SOT0_0
(SDA0_0)
47
35
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL0 when it is used in an I2C (operation mode
4).
SCK0_0
(SCL0_0)
46
35
36
34
26
27
Multi-
function
Serial
1
SIN1_1
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA1 when it is used in an I2C (operation mode
4).
SOT1_1
(SDA1_1)
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL1 when it is used in an I2C (operation mode
4).
SCK1_1
(SCL1_1)
37
40
44
28
-
Multi-
function
Serial
2
SIN2_2
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA2 when it is used in an I2C (operation mode
4).
SOT2_2
(SDA2_2)
-
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL2 when it is used in an I2C (operation mode
4).
SCK2_2
(SCL2_2)
45
-
Document Number: 002-05671 Rev.*B
Page 20 of 86
MB9A130LB Series
Pin No
LQFP-64
QFN-64
LQFP-48
QFN-48
Pin function Pin name
Function description
Multi-
function
Serial
3
SIN3_1
Multi-function serial interface ch.3 input pin
2
3
2
3
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA3 when it is used in an I2C (operation mode
4).
SOT3_1
(SDA3_1)
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL3 when it is used in an I2C (operation mode
4).
SCK3_1
(SCL3_1)
4
4
-
Multi-
function
Serial
4
SIN4_0
Multi-function serial interface ch.4 input pin
54
55
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA4 when it is used in an I2C (operation mode
4).
SOT4_0
(SDA4_0)
-
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL4 when it is used in an I2C (operation mode
4).
SCK4_0
(SCL4_0)
56
60
-
Multi-
function
Serial
5
SIN5_0
Multi-function serial interface ch.5 input pin
44
43
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA5 when it is used in an I2C (operation mode
4).
SOT5_0
(SDA5_0)
59
58
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL5 when it is used in an I2C (operation mode
4).
SCK5_0
(SCL5_0)
-
Document Number: 002-05671 Rev.*B
Page 21 of 86
MB9A130LB Series
Pin No
Pin function Pin name
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
Multi-
function
Serial
6
SIN6_1
Multi-function serial interface ch.6 input pin
8
7
-
-
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA6 when it is used in an I2C (operation mode
4).
SOT6_1
(SDA6_1)
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL6 when it is used in an I2C (operation mode
4).
SCK6_1
(SCL6_1)
6
-
-
-
Multi-
function
Serial
7
SIN7_1
Multi-function serial interface ch.7 input pin
27
26
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA7 when it is used in an I2C (operation mode
4).
SOT7_1
(SDA7_1)
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL7 when it is used in an I2C (operation mode
4).
SCK7_1
(SCL7_1)
25
-
Document Number: 002-05671 Rev.*B
Page 22 of 86
MB9A130LB Series
Pin No
Pin function
Pin name
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
Multi-
function Timer
0
DTTI0X_0
DTTI0X_2
Input signal of waveform generator to control
outputs RTO00 to RTO05 of Multi-function
timer 0
9
5
59
43
26
16-bit free-run timer ch.0 external clock input
pin
FRCK0_2
35
IC00_0
IC00_2
IC01_2
IC02_0
IC02_2
IC03_2
60
36
37
35
38
39
44
27
28
26
29
30
16-bit input capture input pin of Multi-function
timer 0.
ICxx describes a channel number.
Waveform generator output pin of
Multi-function timer 0.
(PPG00_0) This pin operates as PPG00 when it is used in
PPG0 output modes.
RTO00_0
10
11
12
13
14
6
Waveform generator output pin of
Multi-function timer 0.
(PPG00_0) This pin operates as PPG00 when it is used in
PPG0 output modes.
RTO01_0
7
Waveform generator output pin of
Multi-function timer 0.
(PPG02_0) This pin operates as PPG02 when it is used in
PPG0 output modes.
RTO02_0
8
Waveform generator output pin of
Multi-function timer 0.
(PPG02_0) This pin operates as PPG02 when it is used in
PPG0 output modes.
RTO03_0
9
Waveform generator output pin of
Multi-function timer 0.
(PPG04_0) This pin operates as PPG04 when it is used in
PPG0 output modes.
RTO04_0
10
11
Waveform generator output pin of
Multi-function timer 0.
(PPG04_0) This pin operates as PPG04 when it is used in
PPG0 output modes.
RTO05_0
15
57
Real-time
clock
RTCCO_0
42
28
6
RTCCO_1
RTCCO_2
SUBOUT_0
0.5 seconds pulse output pin of Real-time clock 37
10
57
42
28
6
SUBOUT_1 Sub clock output pin
SUBOUT_2
37
10
57
35
48
60
Low Power
Consumption
Mode
WKUP0
WKUP1
WKUP2
WKUP3
Deep stand-by mode return signal input pin 0
42
26
36
44
Deep stand-by mode return signal input pin 1
Deep stand-by mode return signal input pin 2
Deep stand-by mode return signal input pin 3
Document Number: 002-05671 Rev.*B
Page 23 of 86
MB9A130LB Series
Pin No
Pin function
Reset
Pin name
Function description
External Reset Input pin.
LQFP-64
QFN-64
LQFP-48
QFN-48
INITX
21
17
A reset is valid when INITX = L.
Mode
Mode 0 pin.
During normal operation, MD0 = L must be
input During serial programming to flash
memory, MD0 = H must be input.
MD0
MD1
29
21
20
Mode 1 pin.
During normal operation, input is not needed
During serial programming to flash memory,
MD1 = L must be input.
28
Power
GND
1
1
VCC
VSS
Power supply pin
GND pin
18
33
16
32
64
30
19
31
20
57
41
14
-
12
24
48
22
15
23
16
42
31
Clock
X0
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
X0A
X1
X1A
Sub clock (oscillation) I/O pin
CROUT_1
AVCC
Built-in High-speed CR-osc clock output port
A/D converter analog power pin
ADC
Power
A/D converter analog reference voltage input
pin
AVRH
42
32
ADC
GND
C pin
AVSS
C
A/D converter GND pin
43
17
33
13
Power stabilization capacity pin
Note:
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05671 Rev.*B
Page 24 of 86
MB9A130LB Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function.
When the main oscillation is selected.
Pull-up
resistor
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby control
P-ch
P-ch
Digital output
Digital output
X1
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby control
N-ch
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode Control
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
Document Number: 002-05671 Rev.*B
Page 25 of 86
MB9A130LB Series
Type
Circuit
Remarks
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
C
• Open drain output
• CMOS level hysteresis input
Digital input
Digital output
N-ch
Document Number: 002-05671 Rev.*B
Page 26 of 86
MB9A130LB Series
Type
Circuit
Remarks
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is
selected.
• Oscillation feedback resistor
: Approximately 5 MΩ
• With Standby control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby control
N-ch
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode Control
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05671 Rev.*B
Page 27 of 86
MB9A130LB Series
Type
Circuit
Remarks
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode Control
F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Digital output
Digital output
P-ch
P-ch
N-ch
Pull-up resistor control
Digital input
R
Standby mode Control
Analog input
Input control
Document Number: 002-05671 Rev.*B
Page 28 of 86
MB9A130LB Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With standby control
• 5 V tolerant input
• IOH = -4 mA, IOL = 4 mA
Digital output
Digital output
P-ch
• Available to control of PZR
registers. Only P22, P23, P51,
P52
• When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
N-ch
R
Digital input
Standby mode control
H
CMOS level hysteresis input
Mode input
I
• CMOS level output
• CMOS level hysteresis input
• With standby control
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Digital output
Digital output
P-ch
N-ch
R
Digital input
Standby mode control
Document Number: 002-05671 Rev.*B
Page 29 of 86
MB9A130LB Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05671 Rev.*B
Page 30 of 86
MB9A130LB Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
3. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
4. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
5. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
6. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05671 Rev.*B
Page 31 of 86
MB9A130LB Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05671 Rev.*B
Page 32 of 86
MB9A130LB Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins
and GND pins, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pins.
Example of Using an External Clock
Device
X0/PE2 (X0A/P46)
Set as
general-purpose
Can be used as
general-purpose
I/O ports.
X1/PE3 (X1A/P47)
I/O ports.
Handling when using Multi-function serial pin as I2C pin
If it is using the Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF.
Document Number: 002-05671 Rev.*B
Page 33 of 86
MB9A130LB Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7uF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0, MD1)
Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on: VCC → AVCC → AVRH
Turning off: AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Document Number: 002-05671 Rev.*B
Page 34 of 86
MB9A130LB Series
8. Block Diagram
MB9AF131/132
TRSTX,TCK,
TDI,TMS
TDO
ROM
Table
SWJ-DP
On-Chip
Flash
64/128Kbytes
Cortex-M3ꢀCore
@20MHz(Max)
Flash I/F
Security
I
D
NVIC
Sys
SRAM1
8Kbytes
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
CSV
CLK
X0
Main
Source Clock
PLL
Osc
Sub
Osc
X1
CR
4MHz
CR
100kHz
X0A
X1A
CROUT
Deep Standby Ctrl
WKUPx
AVCC,
AVSS,AVRH
12-bit A/D Converter
Unit 0
ANxx
ADTG_x
Power On
Reset
TIOAx
TIOBx
Base Timer
16-bit 8ch. /
32-bit 4ch.
LVD
LVD Ctrl
C
Regulator
IRQ-Monitor
RTCCO
A/D Activation
Compare
1ch.
Real-Time Clock
SUBOUT
External Interrupt
Controller
8-pin + NMI
INTxx
NMIX
IC0x
16-bit Input Capture
4ch.
16-bit FreeRun Timer
3ch.
FRCK0
MD1,
MD0
MODE-Ctrl
GPIO
16-bit Output
Compare
6ch.
P0x,
P1x,
.
PIN-Function-Ctrl
DTTI0X
RTO0x
.
Waveform Generator
3ch.
Pxx
SCKx
SINx
Multi-Function Serial
16-bit PPG
3ch.
SOTx
I/F
8ch.
Multi-Function Timer ×1
Document Number: 002-05671 Rev.*B
Page 35 of 86
MB9A130LB Series
9. Memory Size
See Memory size in Product Lineup to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
0xFFFF_FFFF
Reserved
0xE010_0000
Cortex-M3 Private
Reserved
Peripherals
0xE000_0000
Reserved
0x4003_C000
0x4003_B000
RTC
Reserved
MFS
0x4003_9000
0x4003_8000
0x4400_0000
0x4200_0000
0x4000_0000
Reserved
32Mbytes
Bit band alias
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
LVD/DS mode
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
CR Trim
Reserved
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x2008_0000
0x2000_0000
A/DC
Reserved
Base Timer
PPG
SRAM1
Reserved
0x0010_0008
0x0010_0000
See "lMemory map(2)"
for the memory size
details.
Reserved
MFT unit0
Security/CR Trim
0x4002_1000
0x4002_0000
Flash
Reserved
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-05671 Rev.*B
Page 36 of 86
MB9A130LB Series
Memory Map (2)
MB9AF132KB/LB
MB9AF131KB/LB
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2000_2000
0x2000_0000
0x2000_2000
0x2000_0000
SRAM1
8 Kbytes
SRAM1
8 Kbytes
Reserved
Reserved
0x0010_0008
0x0010_0004
0x0010_0000
0x0010_0008
0x0010_0004
0x0010_0000
CR trimming
Security
CR trimming
Security
Reserved
Reserved
0x0002_0000
0x0000_0000
SA3 (64 KB)
0x0001_0000
0x0000_0000
SA2 (60 KB)
SA1 (4 KB)
SA2 (60 KB)
SA1 (4 KB)
*: See MB9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory.
Document Number: 002-05671 Rev.*B
Page 37 of 86
MB9A130LB Series
Peripheral Address Map
Start address
End address
Bus
AHB
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5100
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_50FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x41FF_FFFF
Flash I/F register
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Reserved
Reserved
Multi-function timer unit0
Reserved
Reserved
PPG
Base Timer
APB1
Reserved
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt Controller
Interrupt Source Check Register
Reserved
GPIO
Reserved
Low Voltage Detector
Deep stand-by mode Controller
Reserved
APB2
Reserved
Multi-function serial Interface
Reserved
Reserved
Real-time clock
Reserved
Reserved
Reserved
Reserved
AHB
Reserved
Reserved
Reserved
Reserved
Document Number: 002-05671 Rev.*B
Page 38 of 86
MB9A130LB Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX = 0
This is the period when the INITX pin is the L level.
INITX = 1
This is the period when the INITX pin is the H level.
SPL = 0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 0.
SPL = 1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep Standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05671 Rev.*B
Page 39 of 86
MB9A130LB Series
List of Pin Status
Power-o
Run
mode or
Sleep
mode
state
n reset or
low
Device
internal
reset
Deep Standby RTC
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Return from
Deep Standby
mode state
mode or Deep
Standby Stop mode
state
voltage
detection
state
state
Function
group
Power
supply
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
Power supply stable
INITX = 1
unstable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
-
-
-
-
SPL = 0
SPL = 1
Main
crystal
Input
Input
Input
Input
Input
Input
Input
Input
enabled
Input enabled
oscillator enabled enabled enabled enabled enabled enabled enabled
input pin
Maintain
previous
Hi-Z /
state /
Input
When
Output
maintain
previous
state /
Internal
input fixed
at 0
enabled /
When
oscillation
stop*1,
Hi-Z /
Internal
input fixed
at 0
External
main
clock
input
selected
oscillation
Hi-Z /
Maintain stop*1,
Setting
Setting
Setting
Internal
input fixed
at 0
previous output
state maintain
GPIO selected
disabled disabled disabled
A
previous
state /
Internal
input fixed
at 0
Output
maintain
Maintain previous
previous state /
Output
maintain
previous
state /
Internal
input fixed
at 0
Hi-Z /
Hi-Z /
GPIO
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
Maintain
selected disabled disabled disabled
input fixed previous state
at 0
state
Internal
input fixed
at 0
Maintain Maintain Maintain
previous previous previous
Maintain
Maintain
previous
state /
previous
Maintain
state /
state /
When
state /
When
state /
When
previous state /
When
Main
Hi-Z /
Hi-Z /
Hi-Z /
When
When
oscillation oscillation oscillation
oscillation
oscillation
stop*1,
crystal
Internal
Internal
Internal
oscillation
stop*1, Hi-Z
output /
Internal
input fixed
at 0
stop*1,
Hi-Z
stop*1,
Hi-Z
stop*1,
Hi-Z
oscillator input fixed input fixed input fixed
stop*1, Hi-Z
Hi-Z
output pin at 0
at 0
at 0
output /
Internal input
output /
Internal
output /
Internal
output /
Internal
output /
B
Internal
fixed at "0"
input fixed
input fixed input fixed input fixed
at 0
at 0
at 0
at 0
Hi-Z /
Hi-Z /
Internal
input fixed previous state
at 0
Maintain Maintain
previous previous
Maintain
previous
state
GPIO
Setting
Setting
Setting
Internal
input fixed
at 0
Maintain
selected disabled disabled disabled
state
state
Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up /
Input Input Input Input Input Input Input
enabled enabled enabled enabled enabled enabled enabled
Pull-up /
Pull-up / Input
Input
INITX
input pin
C
enabled
enabled
Document Number: 002-05671 Rev.*B
Page 40 of 86
MB9A130LB Series
Power-o
n reset or
low
voltage
detection
state
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep Standby RTC
mode or Deep
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep
Standby Stop mode Standby
state
state
mode
state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
-
-
SPL = 0 SPL = 1 SPL = 0 SPL = 1
-
Mode
Input
Input
Input
Input
Input Input Input Input
Input
D
E
input pin enabled enabled enabled enabled enabled enabled enabled enabled enabled
Pull-up / Pull-up /
Input Input
enabled enabled
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
Maintain Maintain
previous previous
state
Maintain
previous
state
Maintain
previous
state
state
Hi-Z /
Hi-Z /
GPIO
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
input fixed
at 0
selected disabled disabled disabled
External
interrupt Setting
enabled disabled disabled disabled
selected
Maintain
previous
state
Setting
Setting
GPIO
selected
GPIO
selected
Hi-Z /
Resource
F other than
above
Maintain Maintain
previous previous
Internal
input fixed
at 0
Hi-Z /
state
state
Hi-Z /
Input
Hi-Z /
Input
Internal
input fixed
at 0
selected
Hi-Z
enabled enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Hi-Z /
Hi-Z /
WKUP
input
WKUP
input
enabled
WKUP
Setting
Setting
Setting
Internal
input fixed
at 0
GPIO
enabled disabled disabled disabled
selected
enabled
External
interrupt Setting
enabled disabled disabled disabled
selected
Maintain
previous
state
Setting
Setting
Maintain Maintain
previous previous
G
GPIO
selected
GPIO
selected
Hi-Z /
state
state
Resource
other than
above
Internal
input fixed
at 0
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at 0
selected
Hi-Z
Hi-Z
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Resource
selected
GPIO
selected
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Input
Hi-Z /
Input
Maintain Maintain
previous previous
enabled enabled state
Internal
input fixed
at 0
Internal
input fixed
at 0
H
Maintain
previous
state
Maintain
previous
state
GPIO
selected
state
Document Number: 002-05671 Rev.*B
Page 41 of 86
MB9A130LB Series
Power-o
n reset or
low
voltage
detection
state
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep Standby RTC
mode or Deep
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep
Standby Stop mode Standby
state
state
mode
state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
-
-
-
SPL = 0 SPL = 1 SPL = 0 SPL = 1
Maintain
previous
state
NMIX
Setting
Setting
Setting
selected disabled disabled disabled
GPIO
selected
Resource
other than
above
Hi-Z /
WKUP
input
Maintain Maintain
previous previous
WKUP
input
enabled
I
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
state
state
selected
Internal
input fixed
at 0
enabled
Hi-Z
Maintain
previous
state
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Analog
input
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Hi-Z
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled enabled enabled enabled enabled enabled enabled enabled
J
Resource
other than
above
GPIO
selected
GPIO
selected
Hi-Z /
Hi-Z /
Maintain Maintain
previous previous
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
input fixed
at 0
selected
disabled disabled disabled
state
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Analog
input
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Hi-Z
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled enabled enabled enabled enabled enabled enabled enabled
External
interrupt
enabled
selected
Maintain
previous
state
K
GPIO
selected
GPIO
selected
Hi-Z /
Resource
other than
above
Maintain Maintain
previous previous
Setting
Setting
Setting
Internal
input fixed
at 0
disabled disabled disabled
Hi-Z /
state
state
Internal
input fixed
at 0
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Document Number: 002-05671 Rev.*B
Page 42 of 86
MB9A130LB Series
Power-o
n reset or
low
voltage
detection
state
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep Standby RTC
mode or Deep
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep
Standby Stop mode Standby
state
state
mode
state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
-
-
-
SPL = 0 SPL = 1 SPL = 0 SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Analog
input
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Hi-Z
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled enabled enabled enabled enabled enabled enabled enabled
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
WKUP
input
WKUP
input
enabled
WKUP
enabled
enabled
L
External
interrupt
enabled
selected
Maintain
previous
state
GPIO
selected
Maintain Maintain
previous previous
Setting
Setting
Setting
GPIO
selected
disabled disabled disabled
Hi-Z /
Internal
input fixed
at 0
state
state
Resource
other than
above
Hi-Z /
Internal
input fixed
at 0
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Sub
crystal
Input
Input
Input
Input
Input
Input
Input
Input
Input
oscillator enabled enabled enabled enabled enabled enabled enabled enabled enabled
input pin
Maintain
previous
state /
Maintain
previous
state /
Maintain
previous
state /
When
Return
from
Deep
Stand-by
STOP
Hi-Z /
Input
enabled /
When
oscillation
stop*2,
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
enabled /
When
oscillation
stop*2,
Hi-Z /
Internal
input fixed
at 0
When
When
oscillation
oscillation
External
Maintain stop*2,
stop*2,
sub clock Setting
Setting
Setting
previous output
state maintain
output
input
M selected
disabled disabled disabled
maintain
previous
state /
Internal
input fixed
at 0
previous
state /
Internal
input fixed
at 0
mode,
GPIO
selected
Output
maintain
Maintain previous
previous state /
Output
maintain
previous
state /
Internal
input fixed
at 0
Hi-Z /
Hi-Z /
Maintain
previous
state
GPIO
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
input fixed
at 0
selected disabled disabled disabled
state
Internal
input fixed
at 0
Document Number: 002-05671 Rev.*B
Page 43 of 86
MB9A130LB Series
Power-o
n reset or
low
voltage
detection
state
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep Standby RTC
mode or Deep
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep
Standby Stop mode Standby
state
state
mode
state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
-
-
-
SPL = 0 SPL = 1 SPL = 0 SPL = 1
Maintain Maintain Maintain Maintain Maintain
previous previous previous previous previous
state /
When
state /
When
state /
When
state /
When
state /
When
Sub
crystal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Maintain
previous
state
oscillation oscillation oscillation oscillation oscillation
stops*2,
Hi-Z /
oscillator input fixed input fixed input fixed
output pin
stops*2,
Hi-Z /
stops*2,
Hi-Z /
stops*2,
Hi-Z /
stops*2,
Hi-Z /
at 0
at 0
at 0
N
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at 0
at 0
at 0
at 0
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain Maintain
previous previous
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
selected disabled disabled disabled
state
state
GPIO/
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Maintain Maintain
previous previous
Maintain
previous
state
O
P
GPIO
Mode
Hi-Z
state
state
Input
Input Input
Input
Input
Input
Input
Input
Input
input pin enabled enabled enabled enabled enabled enabled enabled enabled enabled
Maintain Maintain
previous previous
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Input
enabled
Maintain
previous
state
GPIO
Setting
Setting
Setting
selected disabled disabled disabled
state
state
*1: Oscillation is stopped at Sub run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer
mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
Document Number: 002-05671 Rev.*B
Page 44 of 86
MB9A130LB Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
Unit
Remarks
Min
VSS - 0.5
VSS - 0.5
VSS - 0.5
Max
Power supply voltage*1,*2
Analog power supply voltage*1,*3
Analog reference voltage*1,*3
VCC
VSS + 6.5
VSS + 6.5
VSS + 6.5
V
V
V
AVCC
AVRH
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
Input voltage*1
VI
5V tolerant
AVCC + 0.5
(≤ 6.5 V)
Analog pin input voltage*1
Output voltage*1
VIA
VO
VCC + 0.5
(≤ 6.5 V)
VSS - 0.5
V
L level maximum output current*4
L level average output current*5
L level total maximum output current
L level total average output current*6
H level maximum output current*4
H level average output current*5
H level total maximum output current
H level total average output current*6
Power consumption
IOL
-
10
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
IOLAV
∑IOL
∑IOLAV
IOH
-
4
-
60
-
30
-
-10
- 4
IOHAV
∑IOH
∑IOHAV
PD
-
-
-60
-30
400
+ 150
-
-
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100 ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-05671 Rev.*B
Page 45 of 86
MB9A130LB Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Max
5.5
Parameter
Symbol
Conditions
Unit
Remarks
Min
1.8
Power supply voltage
VCC
-
-
V
V
V
Analog power supply voltage
AVCC
1.8
2.7
AVCC
1
5.5
AVCC = VCC
AVCC
AVCC
10
AVCC ≥ 2.7 V
Analog reference voltage
AVRH
CS
-
-
AVCC < 2.7 V
Smoothing capacitor
LQA048,
μF
For built-in Regulator *
VNA048,
LQD064,
LQG064,
Operating
Temperature
TA
-
- 40
+ 85
°C
VNC064
*: See C Pin in Handling Devices for the connection of the smoothing capacitor.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-05671 Rev.*B
Page 46 of 86
MB9A130LB Series
12.3 DC Characteristics
12.3.1 Current Rating
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ*3
Max*4
CPU: 20 MHz,
Peripheral: 20 MHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
20
25
mA
*1, *5
PLL
Run mode
CPU: 20 MHz,
Peripheral: clock
stopped,
10
15
5
mA
mA
*1, *5
*1
NOP operation
CPU/Peripheral: 4
MHz*2
Flash memory 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
High-speed
CR
Run mode
4.5
ICC
CPU/Peripheral: 32 kHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
Sub
Run mode
Power
supply
current
0.25
0.3
0.35
0.45
mA
mA
*1, *6
*1
VCC
CPU/Peripheral: 100
kHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
Low-speed
CR
Run mode
PLL
Sleep mode
Peripheral: 20 MHz
Peripheral: 4 MHz*2
Peripheral: 32 kHz
Peripheral: 100 kHz
9
13
mA
mA
mA
mA
*1, *5
*1
High-speed
CR
Sleep mode
2
2.5
0.2
0.35
ICCS
Sub
Sleep mode
0.1
0.2
*1, *6
*1
Low-speed
CR
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.3 V
*4: TA=+85°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05671 Rev.*B
Page 47 of 86
MB9A130LB Series
Value
Max*3
Pin
Parameter
Symbol
Conditions
Unit
mA
Remarks
*1, *4
Typ*2
name
TA = + 25°C,
When LVD is off
1
3.6
3.9
70
Main
Timer mode
TA = + 85°C,
When LVD is off
1.7
8.5
18
1.8
7
mA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
*1, *4
*1, *5
*1, *5
*1, *5
*1, *5
*1
ICCT
TA = + 25°C,
When LVD is off
Sub
Timer mode
TA = + 85°C,
When LVD is off
170
7.5
62
TA = + 25C,
When LVD is off
ICCR
RTC mode
Stop mode
TA = + 85C,
When LVD is off
Power
supply
current
VCC
TA = + 25C,
When LVD is off
0.7
6
7
ICCH
TA = + 85C,
When LVD is off
60
*1
TA = + 25C,
When LVD is off
1.6
3.6
0.5
2.5
3
*1, *5
*1, *5
*1
Deep
Standby
RTC mode
ICCRD
TA = + 85C,
When LVD is off
14.5
2.5
12.5
TA = + 25C,
When LVD is off
Deep
Standby
Stop mode
ICCHD
TA = + 85C,
When LVD is off
*1
*1: When all ports are fixed.
*2: VCC = 3.3 V
*3: VCC = 5.5 V
*4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05671 Rev.*B
Page 48 of 86
MB9A130LB Series
Low Voltage Detection Current
Pin
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ*
Max
For occurrence of reset or for
occurrence of interrupt in normal
mode operation
10
20
μA
When not
detected
Low-voltage
detection circuit
(LVD) power
supply current
For occurrence of reset and for
occurrence of interrupt in normal
mode operation
ICCLVD
VCC
14
30
2
μA
μA
For occurrence of interrupt in
low-power mode operation
When not
detected
0.3
*: When VCC = 3.3 V
Flash Memory Current
(VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase 10.8
11.9
mA
A/D Converter Current
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
1.4
Max
At 1unit
operation
2.5
mA
Power supply
current
ICCAD
AVCC
AVRH
At stop
0.1
0.8
0.1
0.35
1.5
μA
At 1unit
operation
AVRH=5.5 V
mA
Reference power
supply current
ICCAVRH
At stop
0.3
μA
Document Number: 002-05671 Rev.*B
Page 49 of 86
MB9A130LB Series
12.3.2 Pin Characteristics
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
MD0, MD1,
PE0, PE2,
PE3,
P46, P47,
INITX
VCC
0.8
×
VCC
0.3
+
-
-
-
-
V
V
P21, P22,
P23,
P50, P51,
P52,
P80, P81,
P82
H level input
voltage
(hysteresis
input)
VIHS
VCC×
VSS
5.5
+
+
5V tolerant
0.7
CMOS
hysteresis
input pins other
than the above
VCC
0.7
×
-
VCC
0.3
-
-
-
-
-
-
V
V
MD0, MD1,
PE0, PE2,
PE3,
P46, P47,
INITX
VSS
0.3
VCC×
L level input
voltage
(hysteresis
input)
0.2
VILS
CMOS
hysteresis
input pins other
than the above
VSS
0.3
-
VCC×
V
V
0.3
VCC ≥ 4.5 V
IOH = - 4 mA
VCC
0.5
-
-
-
-
VCC
VCC
H level
output voltage
VOH
Pxx
Pxx
VCC < 4.5 V
IOH = - 1 mA
VCC
0.5
VCC ≥ 4.5 V
IOL = 4 mA
L level
output voltage
VOL
VSS
-
-
0.4
+5
V
VCC < 4.5 V
IOL = 2 mA
Input leak
current
IIL
-
-
- 5
μA
kΩ
Pull-up
resistance
value
VCC ≥ 4.5 V
25
40
50
100
400
RPU
Pull-up pin
VCC < 4.5 V
100
Other than
VCC, VSS,
AVCC, AVSS,
AVRH
Input
capacitance
CIN
-
-
5
15
pF
Document Number: 002-05671 Rev.*B
Page 50 of 86
MB9A130LB Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Min Max
20
Pin
Parameter
Symbol
Conditions
Unit
MHz
Remarks
name
VCC ≥ 2.0 V
VCC < 2.0 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
4
When crystal oscillator is
connected
4
4
MHz
MHz
MHz
ns
Input frequency
Input clock cycle
fCH
4
20
When using external
clock
4
16
X0,
X1
50
62.5
250
250
When using external
clock
tCYLH
ns
PWH/tCYLH,
PWL/tCYLH
When using external
clock
Input clock pulse
width
-
tCF
tCR
fCM
fCC
fCP0
45
-
55
5
%
,
When using external
clock
Input clock rise
time and fall time
-
ns
-
-
-
-
-
-
-
-
-
20
20
20
MHz
MHz
MHz
Master clock
Base clock (HCLK/FCLK)
APB0 bus clock*2
Internal operating
clock*1
frequency
fCP1
fCP2
-
-
-
-
-
-
20
20
MHz
MHz
APB1 bus clock*2
APB2 bus clock*2
-
-
50
-
ns
Base clock (HCLK/FCLK)
tCYCC
-
-
-
-
50
50
-
-
ns
ns
APB0 bus clock*2
APB1 bus clock*2
tCYCP0
tCYCP1
Internal operating
clock*1
cycle time
-
-
50
-
ns
APB2 bus clock*2
tCYCP2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
Document Number: 002-05671 Rev.*B
Page 51 of 86
MB9A130LB Series
12.4.2 Sub Clock Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Condition
s
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
-
-
32.768
-
kHz When crystal oscillator is connected
kHz When using external clock
Input frequency
Input clock cycle
fCL
tCYLL
-
-
-
32
10
-
-
100
X0A,
X1A
31.25
μs
When using external clock
PWH/tCYLL,
PWL/tCYLL
Input clock pulse
width
45
-
55
%
When using external clock
X0A
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
4
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
TA = + 25°C
3.92
4.08
When trimming*1
When not trimming
When trimming*1
TA =
- 40°C to + 85°C
TA =
3.8
4
4.2
VCC
2.2 V
≥
MHz
2.3
-
7.03
4.6
- 40°C to + 85°C
Clock frequency
fCRH
TA = + 25°C
3.4
4
4
TA =
- 40°C to + 85°C
VCC
2.2 V
<
3.16
4.84
MHz
TA =
- 40°C to + 85°C
2.3
-
-
-
7.03
10
When not trimming
*2
Frequency
stabilization time
tCRWT
-
μs
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
50
Max
150
Clock frequency
fCRL
-
100
kHz
Document Number: 002-05671 Rev.*B
Page 52 of 86
MB9A130LB Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
200
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
4
-
-
-
-
20
5
MHz
1
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
10
-
20
20
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
12.4.5 Operating Conditions of Main PLL (In the case of using built-in High-speed CR clock for input clock of Main PLL)
(VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
fPLLI
-
200
-
-
μs
PLL input clock frequency
PLL multiplication rate
3.8
3
4
-
4.2
4
MHz
multiplier
PLL macro oscillation clock frequency fPLLO
Main PLL clock frequency*2
fCLKPLL
11.4
-
-
16.8 MHz
16.8 MHz
-
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note:
Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
PLL input
clock
PLL macro
clock
Main clock (CLKMO)
oscillation clock
(CLKPLL)
K
M
Main
PLL
High-speed CR clock (CLKHC)
divider
divider
N
divider
Document Number: 002-05671 Rev.*B
Page 53 of 86
MB9A130LB Series
12.4.6 Reset Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
500
Max
-
-
-
ns
When RTC mode or Stop
mode
Reset input time
tINITX
INITX
-
1.5
1.5
ms
ms
When Deep Standby mode
12.4.7 Power-on Reset Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Pin
Parameter
Symbol
dV/dt
Unit
Remarks
name
Min
0.1
Max
Power supply rising time
-
-
V/ms
ms
V
Power supply shut down time tOFF
1
-
-
Reset release voltage
Reset detection voltage
VDETH
VDETL
1.44
1.39
1.60
1.55
1.76
1.71
When voltage rises
VCC
V
When voltage drops
dV/dt ≥ 0.1mV/μs
dV/dt ≥ -0.04mV/μs
Time until releasing
Power-on reset
tPRT
0.46
-
-
-
11.4
0.4
ms
ms
Reset detection delay time
tOFFD
VDETH
VDETL
VCC
dV
dt
0.2V
tOFF
0.2V
tPRT
tOFFD
Reset active
Internal reset
Reset active
Release
start
CPU Operation
Document Number: 002-05671 Rev.*B
Page 54 of 86
MB9A130LB Series
12.4.8 Base Timer Input Timing
Timer input timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK,TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
ns
Remarks
Min
Max
TIOAn/TIOBn
(when using
as TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet.
Document Number: 002-05671 Rev.*B
Page 55 of 86
MB9A130LB Series
12.4.9 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
2.7 V ≤
VCC < 2.7 V
Min Max
VCC ≥ 4.5 V
Pin
VCC < 4.5 V
Parameter
Baud rate
Symbol
Conditions
Unit
name
Min
Max
Min
Max
-
-
-
-
5
-
5
-
5
Mbps
ns
Serial clock cycle
time
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
SCKx
4tCYCP
-
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK ↓ → SOT
delay time
-40
+40 -30
+30 -20
+20
ns
ns
ns
ns
ns
ns
Master mode
SCKx,
SINx
SIN → SCK ↑
setup time
75
-
50
-
30
-
-
-
-
SCKx,
SINx
SCK ↑ → SIN
hold time
0
-
0
-
0
Serial clock L
pulse width
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
Serial clock H
pulse width
-
-
30*1
40*2
SCKx,
SOTx
SCK ↓ → SOT
delay time
75
50
Slave mode
SCKx,
SINx
SIN → SCK ↑
setup time
tIVSHE
tSHIXE
10
20
-
-
10
20
-
-
10
20
-
-
ns
ns
SCKx,
SINx
SCK ↑ → SIN
hold time
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
tR
*1 When PZR = 0.
*2 When PZR = 1.
Notes:
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05671 Rev.*B
Page 56 of 86
MB9A130LB Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05671 Rev.*B
Page 57 of 86
MB9A130LB Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
2.7 V ≤
VCC < 2.7 V
Min Max
VCC ≥ 4.5 V
Pin
VCC < 4.5 V
Unit
Parameter
Baud rate
Symbol
Conditions
name
Min
Max
5
Min
Max
-
-
-
-
5
-
-
5
Mbps
ns
Serial clock cycle
time
tSCYC
SCKx
4tCYCP
-40
-
4tCYCP
-30
-
4tCYCP
-
SCKx,
SOTx
SCK ↑ → SOT
delay time
tSHOVI
+40
+30 -20
+20 ns
Master mode
SCKx,
SINx
SIN → SCK ↓
setup time
tIVSLI
tSLIXI
tSLSH
tSHSL
tSHOVE
75
-
50
-
30
-
-
-
-
ns
ns
ns
ns
ns
SCKx,
SINx
SCK ↓ → SIN
hold time
0
-
0
-
0
Serial clock L
pulse width
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
Serial clock H
pulse width
-
-
30*1
40*2
SCKx,
SOTx
SCK ↑ → SOT
delay time
75
50
Slave mode
SCKx,
SINx
SIN → SCK ↓
setup time
tIVSLE
tSLIXE
10
20
-
-
10
20
-
-
10
20
-
-
ns
ns
SCKx,
SINx
SCK ↓ → SIN
hold time
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
tR
*1 When PZR = 0.
*2 When PZR = 1.
Notes:
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05671 Rev.*B
Page 58 of 86
MB9A130LB Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05671 Rev.*B
Page 59 of 86
MB9A130LB Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
2.7 V ≤
VCC < 2.7 V
Min Max
VCC ≥ 4.5 V
Pin
VCC < 4.5 V
Parameter
Baud rate
Symbol
Conditions
Unit
name
Min
Max
5
Min
Max
-
-
-
-
5
-
-
5
Mbps
ns
Serial clock cycle
time
tSCYC
SCKx
4tCYCP
-40
-
4tCYCP
-
4tCYCP
-20
-
SCKx,
SOTx
SCK ↑ → SOT
delay time
tSHOVI
+40 -30
+30
+20
ns
SCKx,
SINx
SIN → SCK ↓
setup time
tIVSLI
75
-
50
-
30
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Master mode
SCKx,
SINx
SCK ↓ → SIN
hold time
tSLIXI
0
-
0
-
0
SCKx,
SOTx
SOT → SCK ↓
delay time
tSOVLI
tSLSH
tSHSL
tSHOVE
2tCYCP – 30
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
Serial clock L
pulse width
SCKx
SCKx
-
-
Serial clock H
pulse width
-
-
30*1
40*2
SCKx,
SOTx
SCK ↑ → SOT
delay time
75
50
Slave mode
SCKx,
SINx
SIN → SCK ↓
setup time
tIVSLE
tSLIXE
10
20
-
-
10
20
-
-
10
20
-
-
ns
ns
SCKx,
SINx
SCK ↓ → SIN
hold time
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
tR
*1 When PZR = 0.
*2 When PZR = 1.
Notes:
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05671 Rev.*B
Page 60 of 86
MB9A130LB Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05671 Rev.*B
Page 61 of 86
MB9A130LB Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
2.7 V ≤
VCC < 2.7 V
VCC ≥ 4.5 V
Pin
VCC < 4.5 V
Parameter
Baud rate
Symbol
Conditions
Unit
name
Min Max
Min
Max
Min
Max
-
-
-
-
5
-
-
5
-
5
Mbps
ns
Serial clock cycle
time
tSCYC
SCKx
4tCYCP
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK ↓ → SOT
delay time
tSLOVI
-40
+40
-30
+30 -20
+20 ns
SCKx,
SINx
SIN → SCK ↑
setup time
Master mode
tIVSHI
tSHIXI
tSOVHI
tSLSH
tSHSL
tSLOVE
75
-
50
-
30
-
-
-
-
-
ns
ns
ns
ns
ns
ns
SCKx,
SINx
SCK ↑ → SIN
hold time
0
-
0
-
0
SCKx,
SOTx
SOT → SCK ↑
delay time
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP – 30
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
Serial clock L
pulse width
SCKx
SCKx
-
-
Serial clock H
pulse width
-
-
30*1
40*2
SCKx,
SOTx
SCK ↓ → SOT
delay time
75
50
Slave mode
SCKx,
SINx
SIN → SCK ↑
setup time
tIVSHE
tSHIXE
10
20
-
-
10
20
-
-
10
20
-
-
ns
ns
SCKx,
SINx
SCK ↑ → SIN
hold time
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
tR
*1 When PZR = 0.
*2 When PZR = 1.
Notes:
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05671 Rev.*B
Page 62 of 86
MB9A130LB Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tCYCP + 10
-
ns
ns
ns
ns
tSHSL
tCYCP + 10
-
CL = 50 pF
tF
-
-
5
5
SCK rising time
tR
tF
tR
tSHSL
tSLSH
SCK
VIH
VIH
VIH
IL
IL
IL
V
V
V
Document Number: 002-05671 Rev.*B
Page 63 of 86
MB9A130LB Series
12.4.10 External Input Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Min
Condition
s
Parameter
Symbol
Pin name
Unit
Remarks
Max
A/D converter trigger
input
ADTG
1
-
2tCYCP
*
-
ns
FRCKx
ICxx
Free-run timer input clock
Input capture
tINH
tINL
,
1
Input pulse width
DTTIxX
-
2tCYCP
*
-
-
ns
ns
Waveform generator
2tCYCP
100*1
+
*2
INTxx,
NMIX
External interrupt
NMI
*3
*4
500
500
-
-
ns
ns
WKUPx
Deep Standby wake up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which A/D converter, Multi-function Timer, External interrupt, Deep Standby mode Controller is
connected to, see Block Diagram in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Timer mode, in RTC mode, in Stop mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05671 Rev.*B
Page 64 of 86
MB9A130LB Series
12.4.11 I2C Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Standard-mode
Min Max
100
Fast-mode
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
SCL clock frequency
fSCL
0
0
400
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
μs
CL = 50 pF,
R =
Data hold time
SCL ↓ → SDA ↓ ↑
(VP/IOL)*1
tHDDAT
tSUDAT
tSUSTO
0
3.45*2
0
0.9*3
μs
ns
μs
Data setup time
SDA ↓ ↑ → SCL ↑
250
4.0
-
-
100
0.6
-
-
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
STOP condition and
START condition
tBUF
tSP
4.7
-
-
1.3
-
-
μs
4
4
Noise filter
-
2 tCYCP
*
2 tCYCP
*
ns
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement
of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number which I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05671 Rev.*B
Page 65 of 86
MB9A130LB Series
12.4.12 JTAG Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tJTAGS
tJTAGH
Pin name
Conditions
VCC ≥ 4.5 V
Unit
ns
Remarks
Min
Max
TCK,
TMS,TDI
TMS,TDI setup
time
15
-
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
TCK,
TMS,TDI
TMS,TDI hold
time
15
-
-
ns
ns
30
TCK,
TDO
TDO delay time tJTAGD
2.7 V ≤ VCC < 4.5 V
-
-
45
60
VCC < 2.7 V
Note:
When the external load capacitance CL = 50 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05671 Rev.*B
Page 66 of 86
MB9A130LB Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
Pin
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
name
Min
Typ
Max
Resolution
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
bit
± 3.0
± 5.0
± 1.9
± 2.9
± 20
LSB
LSB
LSB
LSB
mV
AVCC ≥ 2.7 V
Integral Nonlinearity
INL
-
AVCC < 2.7 V
AVCC ≥ 2.7 V
AVCC < 2.7 V
Differential Nonlinearity
Zero transition voltage
DNL
VZT
-
ANxx
ANxx
AVRH ±
20
Full-scale transition voltage VFST
-
-
-
-
-
mV
μs
μs
ns
1.0
4.0
0.3
1.2
50
AVCC ≥ 2.7 V
AVCC < 2.7 V
AVCC ≥ 2.7 V
AVCC < 2.7 V
AVCC ≥ 2.7 V
AVCC < 2.7 V
Conversion time*1
Sampling time*2
-
-
-
-
-
tS
10
Compare clock cycle*3
tCCK
1000
1
200
Period of operation enable
state transitions
tSTT
-
-
-
-
-
-
μs
Analog input capacity
Analog input resistor
Interchannel disparity
CAIN
15
0.9
1.6
4.0
4
pF
AVCC ≥ 4.5 V
RAIN
-
-
-
kΩ
2.7 V ≤ AVCC < 4.5 V
AVCC < 2.7 V
-
-
-
-
-
-
-
-
-
LSB
μA
V
Analog port input leak
current
ANxx
0.3
Analog input voltage
ANxx AVSS
AVRH
AVCC
2.7
AVCC ≥ 2.7 V
AVR
H
Reference voltage
-
-
V
AVCC
AVCC < 2.7 V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=20 MHz
AVCC < 2.7 V, HCLK=20 MHz
sampling time: 0.3 μs, compare time: 0.7 μs
sampling time: 1.2 μs, compare time: 2.8 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual
Analog Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.
The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure to set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05671 Rev.*B
Page 67 of 86
MB9A130LB Series
ANxx
Comparator
Analog input pin
Rext
RAIN
Analog signal
source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS: Sampling time
RAIN: Input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V
Input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V
CAIN: Input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V
REXT: Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC: Compare time
tCCK: Compare clock cycle
Document Number: 002-05671 Rev.*B
Page 68 of 86
MB9A130LB Series
Definition of 12-bit A/D Converter Terms
• Resolution
• Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point (0b000000000000 ←→
0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from
the actual conversion characteristics.
• Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
0xFFE
0xFFD
Actual conversion
Actual conversion
characteristics
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-05671 Rev.*B
Page 69 of 86
MB9A130LB Series
12.6 Low-Voltage Detection Characteristics
12.6.1 Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Value
Typ
1.53
Parameter
Symbol
Conditions
Unit
Remarks
Min
1.43
1.53
1.80
1.90
Max
1.63
Detected voltage
Released voltage
Detected voltage
Released voltage
VDLR
VDHR
VDLR
VDHR
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHR = 0001
1.63
1.93
2.03
1.73
2.06
2.16
V
V
V
SVHR = 0100
LVD stabilization wait
time
633 ×
tLVDRW
-
-
-
-
-
μs
μs
tCYCP
*
Detection delay time tLVDRD
dV/dt ≥ -4mV/µs
60
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05671 Rev.*B
Page 70 of 86
MB9A130LB Series
12.6.2 Interrupt of Low-voltage Detection
Normal mode
(TA = - 40°C to + 85°C)
Value
Typ
2.00
Parameter
Symbol
Conditions
Unit
Remarks
Min
1.87
Max
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
VDLI
VDHI
2.13
2.23
2.24
2.34
2.35
2.45
2.45
2.55
2.56
2.66
2.67
2.77
2.77
2.87
2.99
3.09
3.20
3.30
3.41
3.51
3.84
3.94
3.95
4.05
4.27
4.37
4.37
4.47
4.48
4.58
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 0000
1.97
1.96
2.06
2.05
2.15
2.15
2.25
2.24
2.34
2.33
2.43
2.43
2.53
2.61
2.71
2.80
2.90
2.99
3.09
3.36
3.46
3.45
3.55
3.73
3.83
3.83
3.93
3.92
4.02
2.10
2.10
2.20
2.20
2.30
2.30
2.40
2.40
2.50
2.50
2.60
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0101
SVHI = 0110
SVHI = 0111
SVHI = 1000
SVHI = 1001
SVHI = 1010
SVHI = 1011
SVHI = 1100
SVHI = 1101
SVHI = 1110
LVD stabilization
wait time
tLVDIW
-
-
-
-
-
633 × tCYCP
*
μs
μs
dV/dt ≥
-4mV/µs
Detection delay time tLVDID
60
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05671 Rev.*B
Page 71 of 86
MB9A130LB Series
Low power mode
Parameter
(TA = - 40°C to + 85°C)
Value
Typ
2.00
Symbol
Conditions
Unit
Remarks
Min
1.80
Max
2.20
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 0000
1.90
1.89
1.99
1.98
2.08
2.07
2.17
2.16
2.26
2.25
2.35
2.34
2.44
2.52
2.62
2.70
2.80
2.88
2.98
3.24
3.34
3.33
3.43
3.60
3.70
3.69
3.79
3.78
3.88
2.10
2.10
2.20
2.20
2.30
2.30
2.40
2.40
2.50
2.50
2.60
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
2.30
2.31
2.41
2.42
2.52
2.53
2.63
2.64
2.74
2.75
2.85
2.86
2.96
3.08
3.18
3.30
3.40
3.52
3.62
3.96
4.06
4.07
4.17
4.40
4.50
4.51
4.61
4.62
4.72
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0101
SVHI = 0110
SVHI = 0111
SVHI = 1000
SVHI = 1001
SVHI = 1010
SVHI = 1011
SVHI = 1100
SVHI = 1101
SVHI = 1110
LVD stabilization
wait time
8039 × tCYCP
*
tLVDILW
-
-
-
-
-
μs
μs
dV/dt ≥
-0.4mV/μs
Detection delay time tLVDILD
800
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05671 Rev.*B
Page 72 of 86
MB9A130LB Series
12.7 Flash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(VCC = 2.0V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Unit
Remarks
Typ*
Max*
Large Sector 1.6
Small Sector 0.4
7.5
2.1
Sector erase
time
s
Includes write time prior to internal erase
Half word (16-bit)
write time
25
4
400
μs
Not including system-level overhead time.
Includes write time prior to internal erase
Chip erase time
19.2
s
*: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.7.2 Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
Remarks
1,000
20*
10*
5*
10,000
100,000
*: At average + 85C
Document Number: 002-05671 Rev.*B
Page 73 of 86
MB9A130LB Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max*
Sleep mode
tCYCC
High-speed CR Timer mode,
Main Timer mode,
40
80
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
630
630
1260
1260
μs
μs
tICNT
RTC mode,
Stop mode
1083
2100
μs
μs
Deep Standby RTC mode
Deep Standby Stop mode
1099
2127
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05671 Rev.*B
Page 74 of 86
MB9A130LB Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
Document Number: 002-05671 Rev.*B
Page 75 of 86
MB9A130LB Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max*
Sleep mode
359
359
647
647
High-speed CR Timer mode,
Main Timer mode,
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
929
1787
1787
2127
μs
μs
μs
tRCNT
929
RTC/Stop mode
1099
Deep Standby RTC mode
Deep Standby Stop mode
1099
2127
μs
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
Document Number: 002-05671 Rev.*B
Page 76 of 86
MB9A130LB Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on
Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on the time
during the power-on reset/low-voltage detection reset.
When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time
or the Main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05671 Rev.*B
Page 77 of 86
MB9A130LB Series
13.Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Plastic LQFP
(0.5mm pitch), 48-pin
(LQA048)
MB9AF131KBPMC-G-SNE2
MB9AF132KBPMC-G-SNE2
MB9AF131KBQN-G-AVE2
MB9AF132KBQN-G-AVE2
MB9AF131LBPMC1-G-SNE2
MB9AF132LBPMC1-G-SNE2
MB9AF131LBPMC-G-SNE2
MB9AF132LBPMC-G-SNE2
MB9AF131LBQN-G-AVE2
MB9AF132LBQN-G-AVE2
64 Kbyte
8 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
8 Kbyte
8 Kbyte
8 Kbyte
8 Kbyte
8 Kbyte
8 Kbyte
8 Kbyte
8 Kbyte
8 Kbyte
Plastic QFN
(0.5mm pitch), 48-pin
(VNA048)
Plastic LQFP
Tray
(0.5mm pitch), 64-pin
(LQD064)
Plastic LQFP
(0.65mm pitch), 64-pin
(LQG064)
Plastic QFN
(0.5mm pitch), 64-pin
(VNC064)
Document Number: 002-05671 Rev.*B
Page 78 of 86
MB9A130LB Series
14.Package Dimensions
Package Type
Package Code
LQFP 48 (0.5mm pitch)
LQA048
4
D
5
7
D1
36
36
25
25
37
24
24
37
E1
E
5
7
4
3
6
48
13
13
48
1
1
12
12
2
A-B
5
D
7
e
0.10
C
3
0.20
C A-B D
0.80
C
A-B
D
b
8
2
A
9
A
SEATING
PLANE
c
A'
0.25
A1
10
b
0.80
C
L1
L
SECTION A-A'
DIMENSIONS
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.15
0.09
0.20
0.27
0.20
c
D
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0
0.75
0.70
8
L1
0.50
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
002-13731 **
Document Number: 002-05671 Rev.*B
Page 79 of 86
MB9A130LB Series
Package Type
Package Code
QFN 48
VNA048
0.10
C
A
B
D
D2
A
25
36
0.10
2X
C
0.10
C A B
24
37
(ND-1)
e
E
E2
5
13
48
12
1
R
9
INDEX MARK
8
L
0.10
0.05
C
A
B
B
e
b
TOP VIEW
C
4
0.10
2X
C
BOTTOM VIEW
0.10
C
A
SEATING PLANE
C
0.05
A1
9
C
SIDE VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
MIN. NOM. MAX.
0.90
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINALHAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL.THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
A
0.00
0.05
1
D
E
7.00 BSC
7.00 BSC
0.25
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
6. MAX. PACKAGE WARPAGE IS 0.05mm.
0.20
0.30
b
D
5.50 BSC
5.50 BSC
0.50 BSC
0.20 REF
0.40
2
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.
E
e
2
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT
SINK SLUG AS WELL AS THE TERMINALS.
R
L
0.35
0.45
10. JEDEC SPEC IFICATIONNO . REF: N/A
PACKAGE OUTLINE, 48 LEADQFN
7.0X7.0X0.9 MMVNA048 5.5X5.5 MMEPAD(SAWN) REV**
002-15528 **
Document Number: 002-05671 Rev.*B
Page 80 of 86
MB9A130LB Series
Package Type
Package Code
LQFP 64 (0.5mm pitch)
LQD064
4
D
D1
5
7
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
5
7
e
A-B D
3
0.10
0.08
C A-B D
BOTTOM VIEW
0.20
C
C
A-B
D
b
8
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A'
A1
10
SECTION A-A'
L1
0.08
C
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
c
0.20
D
D1
e
12.00 BSC.
10.00 BSC.
0.50 BSC
E
12.00 BSC.
10.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
002-11499 **
Document Number: 002-05671 Rev.*B
Page 81 of 86
MB9A130LB Series
Package Type
Package Code
LQFP 64 (0.65mm pitch)
LQG064
4
5
D
7
D1
48
33
33
48
49
32
32
49
E1
E
5
7
4
3
64
17
17
64
1
16
16
1
2
5
7
BOTTOM VIEW
e
3
0.10
C A-B D
0.20
C A-B D
0.13
C
A-B
D
b
8
TOP VIEW
2
A
A
9
SEATI NG
PLA NE
A1
10
0.2 5
L
c
A'
L1
b
0.10
C
SECTION A -A'
SIDE VIEW
DIMENSION
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.27 0.32 0.37
0.09 0.20
0.20
c
D
D1
e
14.00 BSC
12.00 BSC
0.65 BSC
E
14.00 BSC
12.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
0
L1
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
002-13881 **
Document Number: 002-05671 Rev.*B
Page 82 of 86
MB9A130LB Series
Package Type
Package Code
QFN 64
VNC064
0.10
C
A B
D2
A
D
48
33
33
48
0.10
2X
C
32
32
49
49
0.10
C A B
5
(ND-1)
e
E
E2
17
64
64
17
1
16
16
1
4
INDEXMARK
8
9
e
B
b
L
0.10
0.05
C A B
0.10
2X
C
C
TOP VIEW
SIDE VIEW
BOTTOMVIEW
0.10
C
A
SEATINGPLANE
0.05
C
C
A1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
0.90
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
A
0.00
9.00 BSC
9.00 BSC
0.05
1
4
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL,
D
E
b
THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
0.20 0.25 0.30
6.00 BSC
5
D
2
6.
7.
8
E
2
e
6.00 BSC
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
0.50 BSC
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
R
L
N
0.20 REF
0.40 0.45
0.35
64
16
ND
PACKAGE OUTLINE, 64 LEAD QFN
9.0X9.0X0.9 MM VNC064 6.0X6.0 MM EPAD (SAWN) Rev*.*
002-13234 **
Document Number: 002-05671 Rev.*B
Page 83 of 86
MB9A130LB Series
15.Major Changes
Spansion Publication Number: DS706-00066
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
Features
· On-chip Memories
2
Changed the description of on-chip SRAM
33
Handling Devices
Added "· Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your
mount board."
Handling Devices
Crystal oscillator circuit
33
37
Memory Map
Memory map(2)
Added the summary of Flash memory sector
· Changed the table format
· Added Timer mode current
· Added Flash Memory Current
· Moved A/D Converter Current
Electrical Characteristics
47 - 49 3. DC Characteristics
(1) Current rating
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main
PLL
(4-2) Operating Conditions of Main
PLL
53
54
· Added the figure of Main PLL connection
· Changed the figure of timing
· Changed from Reset release delay time(tOND) to Time until
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
releasing Power-on reset(tPRT
)
· Modified from UART Timing to CSIO/UART Timing
Electrical Characteristics
56 - 63 4. AC Characteristics
(8) CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition
voltage
Electrical Characteristics
5. 12bit A/D Converter
67
· Added Conversion time at AVCC < 2.7 V
Electrical Characteristics
70
73
7. Low-voltage Detection
Characteristics
Deleted the figure
Electrical Characteristics
8. Flash Memory Write/Erase
Characteristics
Change to the erase time of include write time prior to internal
erase
Electrical Characteristics
74 - 77 9. Return Time from Low-Power
Consumption Mode
Added Return Time from Low-Power Consumption Mode
Changed notation of part number
78
Ordering Information
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05671 Rev.*B
Page 84 of 86
MB9A130LB Series
Document History
Document Title: MB9A130LB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05671
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-05671.
No change to document contents or format.
**
-
AKIH
AKIH
06/09/2015
03/10/2016
*A
5162460
Updated to Cypress format.
Adapted new Cypress logo
Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed
starting count value from 01 to 00. Deleted “second, or day of the week” in
the Interrupt function.
Changed package code as the following in chapter :
2. Packages
3. Pin Assignment
*B
5742425
YSKA
05/23/2017
13. Ordering Information
14. Package Dimensions.
FPT-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048
FTP-64P-M38 -> LQD064, FPT-64P-M39 -> LQG064,
LCC-64P-M24 -> VNC064
Corrected “J-TAG" to “JTAG" in 4. List of Pin Functions.
Added Note for JTAG pin in 4. List of Pin Functions.
Added the Baud rate spec in 12.4.9 CSIO/UART Timing.
Document Number: 002-05671 Rev.*B
Page 85 of 86
MB9A130LB Series
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Document Number: 002-05671 Rev.*B
May 23, 2017
Page 86 of 86
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