MB9BF324MPMC-G-JNE2 [CYPRESS]
RISC Microcontroller, CMOS,;型号: | MB9BF324MPMC-G-JNE2 |
厂家: | CYPRESS |
描述: | RISC Microcontroller, CMOS, 微控制器 外围集成电路 |
文件: | 总108页 (文件大小:2172K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MB9B320M Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9B320M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, DACs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in “FM3 Family Peripheral Manual”.
Features
32-bit ARM® Cortex®-M3 Core
[USB device]
USB2.0 Full-Speed supported
Processor version: r2p1
Max 6 EndPoint supported
EndPoint 0 is control transfer
Up to 72 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or
Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 are comprised of Double Buffers.
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64bytes
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
• Endpoint 1: 256bytes
[USB host]
Dual operation Flash memory
USB2.0 Full/Low-speed supported
Dual Operation Flash memory has the upper bank and the
lower bank.
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
So, this series could implement erase, write and read
operations for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
USB Device connected/dis-connected automatic detection
+ 16 Kbytes lower bank)
Automatic processing of the IN/OUT token handshake
packet
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
Max 256-byte packet-length supported
Wake-up function supported
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
Multi-function Serial Interface (Max eight channels)
4 channels with 16 steps×9-bit FIFO (ch.0/1/3/4), 4 channels
without FIFO (ch.2/5/6/7)
Operation mode is selectable from the followings for each
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
channel.
UART
CSIO
LIN
USB Interface
I2C
The USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
Cypress Semiconductor Corporation
Document Number: 002-05652 Rev.*C
• 198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 28, 2017
MB9B320M Series
[UART]
A/D Converter (Max 26 channels)
Full duplex double buffer
[12-bit A/D Converter]
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Successive Approximation type
Built-in 2units
Conversion time: 0.8 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Hardware Flow control : Automatically control the
transmission/reception by CTS/RTS (only ch.4)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion:
4 steps)
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
D/A Converter (Max two channels)
R-2R type
10-bit resolution
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
16-bit PWM timer
16-bit PPG timer
LIN break field generation (can be changed to 13 to 16-bit
length)
16-/32-bit reload timer
16-/32-bit PWC timer
LIN break delimiter generation (can be changed to 1 to 4-bit
length)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated to.
[I2C]
Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps)
supported
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
DMA Controller (Eight channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
8 independently configured and operated channels
Up to 65 high-speed general-purpose I/O Ports @ 80 pin
Package
Transfer can be started by software or request from the
built-in peripherals
Some ports are 5V tolerant.
Transfer address area: 32-bit (4 Gbytes)
See “List of Pin Functions” and “I/O Circuit Type” to confirm
the corresponding pins.
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Operation mode is selectable from the followings for each
channel.
Number of transfers: 1 to 65536
Free-running
Periodic (=Reload)
One-shot
Document Number: 002-05652 Rev.*C
Page 2 of 108
MB9B320M Series
Quadrature Position/Revolution Counter (QPRC)
External Interrupt Controller Unit
(Max two channels)
Up to 23 external interrupt input pins @ 80 pin Package
Include one non-maskable interrupt (NMI) input pin
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
16-bit revolution counter
Two 16-bit compare registers
The "Hardware" watchdog timer is clocked by the built-in
Low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except RTC,
Stop, Deep Standby RTC, Deep Standby Stop modes.
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch./unit
Input capture × 4ch./unit
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
Output compare × 6ch./unit
A/D activation compare × 2ch./unit
Waveform generator × 3ch./unit
16-bit PPG timer × 3ch./unit
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
The following function can be used to achieve the motor
control.
[Clocks]
PWM signal output function
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
DC chopper waveform output function
Dead time function
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Input capture function
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
[Resets]
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Reset requests from INITX pin
Power-on reset
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
Watch Counter
The Watch counter is used for wake up from Sleep and Timer
mode.
If external clock failure (clock stop) is detected, reset is
asserted.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
If external frequency anomaly is detected, interrupt or reset is
asserted.
Document Number: 002-05652 Rev.*C
Page 3 of 108
MB9B320M Series
Low-Voltage Detector (LVD)
Debug
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
Serial Wire JTAG Debug Port (SWJ-DP)
Unique ID
Unique value of the device (41 bits) is set.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Power Supply
Wide range voltage:
Low-Power Consumption Mode
Six low-power consumption modes supported.
VCC
= 2.7 V to 5.5 V
USBVCC = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of
RAM and not)
Deep Standby Stop (selectable between keeping the value of
RAM and not)
Document Number: 002-05652 Rev.*C
Page 4 of 108
MB9B320M Series
Contents
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 15
5. I/O Circuit Type................................................................................................................................................................ 33
6. Handling Precautions ..................................................................................................................................................... 39
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 39
Precautions for Package Mounting.............................................................................................................................. 40
Precautions for Use Environment................................................................................................................................ 41
7. Handling Devices ............................................................................................................................................................ 42
8. Block Diagram................................................................................................................................................................. 44
9. Memory Size .................................................................................................................................................................... 45
10. Memory Map .................................................................................................................................................................... 45
11. Pin Status in Each CPU State ........................................................................................................................................ 48
12. Electrical Characteristics ............................................................................................................................................... 54
12.1 Absolute Maximum Ratings......................................................................................................................................... 54
12.2 Recommended Operating Conditions.......................................................................................................................... 56
12.3 DC Characteristics....................................................................................................................................................... 57
12.3.1 Current Rating.............................................................................................................................................................. 57
12.3.2 Pin Characteristics ....................................................................................................................................................... 60
12.4 AC Characteristics....................................................................................................................................................... 61
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 61
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 62
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 63
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)................................... 64
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL).............. 64
12.4.6 Reset Input Characteristics .......................................................................................................................................... 65
12.4.7 Power-on Reset Timing................................................................................................................................................ 65
12.4.8 Base Timer Input Timing.............................................................................................................................................. 66
12.4.9 CSIO/UART Timing...................................................................................................................................................... 67
12.4.10 External Input Timing................................................................................................................................................ 75
12.4.11 Quadrature Position/Revolution Counter timing........................................................................................................ 76
12.4.12 I2C Timing................................................................................................................................................................. 78
12.4.13 JTAG Timing............................................................................................................................................................. 79
12.5 12-bit A/D Converter.................................................................................................................................................... 80
12.6 10-bit D/A Converter.................................................................................................................................................... 83
12.7 USB Characteristics .................................................................................................................................................... 84
12.8 Low-Voltage Detection Characteristics........................................................................................................................ 88
12.8.1 Low-Voltage Detection Reset....................................................................................................................................... 88
12.8.2 Interrupt of Low-Voltage Detection............................................................................................................................... 89
12.9 Flash Memory Write/Erase Characteristics ................................................................................................................. 90
12.9.1 Write / Erase time......................................................................................................................................................... 90
12.9.2 Write cycles and data hold time ................................................................................................................................... 90
12.10 Return Time from Low-Power Consumption Mode...................................................................................................... 91
12.10.1 Return Factor: Interrupt/WKUP................................................................................................................................. 91
12.10.2 Return Factor: Reset ................................................................................................................................................ 93
Document Number: 002-05652 Rev.*C
Page 5 of 108
MB9B320M Series
13. Ordering Information ...................................................................................................................................................... 95
14. Package Dimensions ...................................................................................................................................................... 96
15. Major Changes .............................................................................................................................................................. 104
Document History............................................................................................................................................................... 107
Sales, Solutions, and Legal Information........................................................................................................................... 108
Document Number: 002-05652 Rev.*C
Page 6 of 108
MB9B320M Series
1. Product Lineup
Memory Size
Product name
MB9BF321K/L/M
64 Kbytes
MB9BF322K/L/M
128 Kbytes
MB9BF324K/L/M
Main area
On-chip
256 Kbytes
Flash memory
Work area
32 Kbytes
8 Kbytes
32 Kbytes
8 Kbytes
32 Kbytes
16 Kbytes
SRAM0
On-chip SRAM
SRAM1
Total
8 Kbytes
16 Kbytes
8 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
Function
MB9BF321K
MB9BF322K
MB9BF324K
MB9BF321L
MB9BF322L
MB9BF324L
MB9BF321M
MB9BF322M
MB9BF324M
Product name
Pin count
CPU
48
64
80/96
Cortex-M3
72 MHz
Freq.
Power supply voltage range
USB2.0 (Device/Host)
DMAC
2.7 V to 5.5 V
1 ch. (Max)
8 ch.
4 ch. (Max)
8 ch. (Max)
ch.0/1/3/4 FIFO
ch.2/5/6/7: No FIFO
(In ch.1, only UART and LIN are available.)
ch.0/1/3: FIFO
ch.5: No FIFO
(In ch.1/5, only UART and LIN
are available.)
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
8ch. (Max)
A/D activation
compare
2 ch.
Input capture
MF-
4 ch.*
3 ch.
6 ch.
3 ch.
3 ch.
1 unit
Free-run timer
Timer
Output compare
Waveform generator
PPG
QPRC
1 ch.
2 ch. (Max)
Dual Timer
1 unit
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
1 unit
1 unit
Yes
1 ch. (SW) + 1ch. (HW)
14 pins (Max) +
NMI × 1
19 pins (Max) +
NMI × 1
23 pins (Max) +
NMI × 1
External Interrupts
I/O ports
35 pins (Max)
14 ch. (2 units)
2ch. (Max)
Yes
50 pins (Max)
23 ch. (2 units)
65 pins (Max)
26 ch. (2 units)
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
2 ch.
High-speed
Low-speed
4 MHz
Built-in CR
100 kHz
SWJ-DP
Yes
Debug Function
Unique ID
*: The external input channel which can be used is shown as follows.
• ch.0 to ch.3 : MB9BF321M/F322M/F324M
• ch.0, ch.2, ch.3 : MB9BF321K/F322K/F324K, MB9BF321L/F322L/F324L
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-05652 Rev.*C
Page 7 of 108
MB9B320M Series
2. Packages
MB9BF321K
MB9BF322K
MB9BF324K
MB9BF321L
MB9BF322L
MB9BF324L
MB9BF321M
MB9BF322M
MB9BF324M
Product name
Package
LQFP:
QFN:
LQA048 (0.5 mm pitch)
-
-
-
-
-
VNA048 (0.5 mm pitch)
LQD064 (0.5 mm pitch)
LQG064 (0.65 mm pitch)
VNC064 (0.5 mm pitch)
LQH080 (0.5 mm pitch)
LQJ080 (0.65 mm pitch)
FDG096 (0.5 mm pitch)
LQFP:
LQFP:
QFN:
-
-
-
-
-
-
LQFP:
LQFP:
BGA:
-
-
-
-
-
: Supported
Note:
−
See “Package Dimensions” for detailed information on each package.
Document Number: 002-05652 Rev.*C
Page 8 of 108
MB9B320M Series
3. Pin Assignment
LQH080/LQJ080
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
60 P20/INT05_0/CROUT_0/AIN1_1
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P53/SIN6_0/TIOA1_2/INT07_2
P54/SOT6_0/TIOB1_2/INT18_1
P55/SCK6_0/ADTG_1/INT19_1
P56/INT08_2
59 P21/AN14/SIN0_0/INT06_1/BIN1_1/WKUP2
58 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
57 P23/AN12/SCK0_0/TIOA7_1
56 P1B/AN11/SOT4_1/INT20_2/IC01_1
55 P1A/AN10/SIN4_1/INT05_1/IC00_1
54 P19/AN09/SCK2_2
53 P18/AN08/SOT2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
52 AVRL
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2 10
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 12
P39/DTTI0X_0/INT06_0/ADTG_2 13
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 14
P3B/RTO01_0/TIOA1_1 15
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1
48 P16/AN06/SCK0_1/INT15_0
47 P15/AN05/SOT0_1/INT14_0/IC03_2
46 P14/AN04/SIN0_1/INT03_1/IC02_2
45 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2 16
P3D/RTO03_0/TIOA3_1 17
44 P12/AN02/SOT1_1/IC00_2
43 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
42 P10/AN00
P3E/RTO04_0/TIOA4_1/INT19_2 18
P3F/RTO05_0/TIOA5_1 19
VSS 20
41 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05652 Rev.*C
Page 9 of 108
MB9B320M Series
LQD064/LQG064
(TOP VIEW)
VCC
P50/AN22/INT00_0/AIN0_2/SIN3_1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P21/AN14/SIN0_0/INT06_1/WKUP2
P22/AN13/SOT0_0/TIOB7_1
P23/AN12/SCK0_0/TIOA7_1
P19/AN09/SCK2_2
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P30/AN25/AIN0_0/TIOB0_1/INT03_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/INT06_0/ADTG_2
3
4
5
P18/AN08/SOT2_2
6
AVRL
7
AVRH
LQFP - 64
8
AVCC
9
P17/AN07/SIN2_2/INT04_1
P15/AN05/SOT0_1/INT14_0/IC03_2
P14/AN04/SIN0_1/INT03_1/IC02_2
AVSS
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
10
11
12
13
14
15
16
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
P12/AN02/SOT1_1/IC00_2
P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
P10/AN00
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
VSS
VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05652 Rev.*C
Page 10 of 108
MB9B320M Series
VNC064
(TOP VIEW)
VCC
P50/AN22/INT00_0/AIN0_2/SIN3_1
1
2
3
4
5
6
7
8
9
48 P21/AN14/SIN0_0/INT06_1/WKUP2
47 P22/AN13/SOT0_0/TIOB7_1
46 P23/AN12/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVRL
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P30/AN25/AIN0_0/TIOB0_1/INT03_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/INT06_0/ADTG_2
42 AVRH
QFN - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05/SOT0_1/INT14_0/IC03_2
38 P14/AN04/SIN0_1/INT03_1/IC02_2
37 AVSS
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10
P3B/RTO01_0/TIOA1_1 11
P3C/RTO02_0/TIOA2_1/INT18_2 12
P3D/RTO03_0/TIOA3_1 13
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
34 P10/AN00
P3E/RTO04_0/TIOA4_1/INT19_2 14
P3F/RTO05_0/TIOA5_1 15
VSS 16
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05652 Rev.*C
Page 11 of 108
MB9B320M Series
LQA048
(TOP VIEW)
VCC
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
P21/AN14/SIN0_0/INT06_1/WKUP2
P22/AN13/SOT0_0/TIOB7_1
3
P23/AN12/SCK0_0/TIOA7_1
4
AVRL
5
AVRH
6
AVCC
LQFP - 48
7
P15/AN05/SOT0_1/INT14_0/IC03_2
P14/AN04/SIN0_1/INT03_1/IC02_2
AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
8
9
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
10
11
12
P12/AN02/SOT1_1/IC00_2
P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
P10/AN00
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05652 Rev.*C
Page 12 of 108
MB9B320M Series
VNA048
(TOP VIEW)
VCC
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P39/DTTI0X_0/INT06_0/ADTG_2
1
2
3
4
5
6
7
8
9
36 P21/AN14/SIN0_0/INT06_1/WKUP2
35 P22/AN13/SOT0_0/TIOB7_1
34 P23/AN12/SCK0_0/TIOA7_1
33 AVRL
32 AVRH
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
31 AVCC
QFN - 48
30 P15/AN05/SOT0_1/INT14_0/IC03_2
29 P14/AN04/SIN0_1/INT03_1/IC02_2
28 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
P3E/RTO04_0/TIOA4_1/INT19_2 10
P3F/RTO05_0/TIOA5_1 11
VSS 12
27 P12/AN02/SOT1_1/IC00_2
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
25 P10/AN00
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05652 Rev.*C
Page 13 of 108
MB9B320M Series
FDG096
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
USBVCC
AN20
AN21
Index
A
B
C
D
E
F
TRSTX
VSS
VSS
VCC
AN22
P53
UDP0 UDM0
VSS
P63
AN18
P0D
P0E
VSS
AN17
AN16
P07
VSS
TDI
TDO/
SWO
TCK/
SWCLK
VSS
AN23
P54
AN25
VSS
P33
P3B
P3E
VSS
C
AN24
VSS
P55
AN19
AN15
VSS
AN13
AN11
AN08
AN06
P20
AN14
VSS
AN09
AN12
AN10
P56
AN26
VSS
P39
VSS
P32
AN07 AVRH
AN05 AVRL
G
H
J
P3A
P3D
VCC
VSS
P3C
VSS
X1A
X0A
AN04 AVSS AVCC
P3F
INITX
VSS
P48
P45
P44
P4A
P49
VSS
P4D
P4C
P4B
AN02
P4E
VSS
MD1
X0
AN01
VSS
X1
AN00
VCC
VSS
K
L
MD0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05652 Rev.*C
Page 14 of 108
MB9B320M Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
1
2
B1
C1
1
2
1
2
VCC
P50
-
INT00_0
AIN0_2
SIN3_1
AN22
F
N
N
P51
INT01_0
BIN0_2
3
4
C2
B3
3
4
3
4
F
F
SOT3_1
(SDA3_1)
AN23
P52
INT02_0
ZIN0_2
N
SCK3_1
(SCL3_1)
AN24
P53
SIN6_0
TIOA1_2
INT07_2
P54
5
6
D1
D2
-
-
-
-
E
E
L
L
SOT6_0
(SDA6_0)
TIOB1_2
INT18_1
P55
SCK6_0
(SCL6_0)
7
8
9
D3
E1
E2
-
-
-
-
E
E
F
L
L
N
ADTG_1
INT19_1
P56
-
INT08_2
P30
AIN0_0
TIOB0_1
INT03_2
AN25
5
Document Number: 002-05652 Rev.*C
Page 15 of 108
MB9B320M Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
P31
BIN0_0
TIOB1_1
10
11
E3
G1
6
-
-
F
N
SCK6_1
(SCL6_1)
INT04_2
AN26
P32
ZIN0_0
TIOB2_1
7
E
L
SOT6_1
(SDA6_1)
INT05_2
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
P39
12
13
G2
G3
8
9
-
E
E
L
L
DTTI0X_0
INT06_0
ADTG_2
P3A
5
RTO00_0
(PPG00_0)
TIOA0_1
INT07_0
SUBOUT_2
RTCCO_2
P3B
14
H1
10
6
G
L
RTO01_0
(PPG00_0)
15
16
17
H2
H3
J1
11
12
13
7
8
9
G
G
G
K
L
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
INT18_2
P3D
RTO03_0
(PPG02_0)
K
TIOA3_1
Document Number: 002-05652 Rev.*C
Page 16 of 108
MB9B320M Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
P3E
RTO04_0
(PPG04_0)
18
19
J2
J4
14
10
11
G
G
L
TIOA4_1
INT19_2
P3F
RTO05_0
(PPG04_0)
15
K
TIOA5_1
20
21
L1
L5
16
-
12
-
VSS
-
P44
TIOA4_0
INT10_0
P45
TIOA5_0
INT11_0
C
G
L
L
22
K5
-
-
G
23
24
25
L2
L4
K1
17
-
13
-
-
-
-
VSS
18
14
VCC
P46
26
L3
19
15
D
F
X0A
P47
27
28
K3
K4
20
21
16
17
D
B
G
C
X1A
INITX
P48
29
J5
-
-
INT14_1
SIN3_2
P49
E
L
TIOB0_0
INT20_1
DA0_0
18
-
30
K6
22
L
L
SOT3_2
(SDA3_2)
AIN0_1
P4A
TIOB1_0
INT21_1
DA1_0
19
-
31
J6
23
L
L
SCK3_2
(SCL3_2)
BIN0_1
Document Number: 002-05652 Rev.*C
Page 17 of 108
MB9B320M Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
P4B
TIOB2_0
INT22_1
IGTRG_0
ZIN0_1
P4C
32
33
L7
24
-
-
E
I*
L
L
TIOB3_0
SCK7_1
(SCL7_1)
K7
25
INT12_0
AIN1_2
P4D
TIOB4_0
SOT7_1
(SDA7_1)
34
35
J7
26
27
-
-
I*
I*
L
L
INT13_0
BIN1_2
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MD1
K8
36
37
38
K9
L8
L9
28
29
30
20
21
22
C
K
A
E
D
A
PE0
MD0
X0
PE2
X1
39
L10
L11
31
23
A
B
PE3
40
41
32
33
24
-
VSS
-
-
K11
VCC
P10
42
J11
34
25
F
M
N
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
WKUP1
P12
43
J10
35
26
F
AN02
44
J8
36
27
F
M
SOT1_1
(SDA1_1)
IC00_2
Document Number: 002-05652 Rev.*C
Page 18 of 108
MB9B320M Series
Pin No
37
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
H10
45
46
28
29
AVSS
P14
-
AN04
H9
38
INT03_1
IC02_2
SIN0_1
P15
F
N
N
AN05
IC03_2
47
G10
39
30
F
SOT0_1
(SDA0_1)
INT14_0
P16
AN06
48
49
G9
-
-
-
F
F
N
N
SCK0_1
(SCL0_1)
INT15_0
P17
AN07
F10
40
SIN2_2
INT04_1
AVCC
AVRH
AVRL
P18
50
51
52
H11
F11
G11
41
42
43
31
32
33
-
-
-
AN08
53
54
F9
44
45
-
-
F
F
M
M
SOT2_2
(SDA2_2)
P19
AN09
E11
SCK2_2
(SCL2_2)
P1A
AN10
55
E10
-
-
SIN4_1
INT05_1
IC00_1
F
N
Document Number: 002-05652 Rev.*C
Page 19 of 108
MB9B320M Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
P1B
AN11
SOT4_1
(SDA4_1)
56
57
58
E9
-
-
F
F
F
N
IC01_1
INT20_2
P23
SCK0_0
(SCL0_0)
D10
D9
46
34
M
M
TIOA7_1
AN12
P22
SOT0_0
(SDA0_0)
47
-
35
-
TIOB7_1
AN13
ZIN1_1
P21
SIN0_0
INT06_1
WKUP2
BIN1_1
AN14
59
60
C11
C10
48
36
F
E
N
N
P20
INT05_0
CROUT_0
AIN1_1
P00
-
-
61
62
63
64
A10
B9
49
50
51
52
37
38
39
40
E
E
E
E
J
J
J
J
TRSTX
P01
TCK
SWCLK
P02
B11
A9
TDI
P03
TMS
SWDIO
P04
65
66
B8
A8
53
-
41
-
TDO
E
E
J
SWO
P07
ADTG_0
INT23_1
L
Document Number: 002-05652 Rev.*C
Page 20 of 108
MB9B320M Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
P0A
SIN4_0
67
C8
C7
54
-
-
J*
N
N
INT00_2
AN15
P0B
SOT4_0
(SDA4_0)
68
55
56
J*
J*
TIOB6_1
AN16
INT18_0
P0C
SCK4_0
(SCL4_0)
69
B7
-
N
TIOA6_1
INT19_0
AN17
P0D
RTS4_0
TIOA3_2
INT20_0
P0E
70
71
B6
C6
-
-
-
-
E
E
L
L
CTS4_0
TIOB3_2
INT21_0
P0F
NMIX
SUBOUT_0
CROUT_1
RTCCO_0
WKUP0
AN18
72
A6
57
42
F
I
P63
73
74
B5
C5
-
-
-
E
F
L
INT03_0
P62
SCK5_0
(SCL5_0)
58
M
ADTG_3
AN19
P61
SOT5_0
(SDA5_0)
TIOB2_2
UHCONX
DTTI0X_2
AN20
75
B4
59
43
F
M
Document Number: 002-05652 Rev.*C
Page 21 of 108
MB9B320M Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
IGTRG_1
AN21
76
C4
60
44
J*
N
77
78
A4
A3
61
62
45
46
USBVCC
P80
-
UDM0
H
H
H
INT16_1
P81
79
80
A2
A1
63
64
47
48
UDP0
H
-
INT17_1
VSS
A5, A7, A11, B2,
B10, C3, C9, D11,
F1, F2, F3, J3, J9,
K2, K10, L6
-
-
-
VSS
-
*: 5 V tolerant I/O
Document Number: 002-05652 Rev.*C
Page 22 of 108
MB9B320M Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Pin function
Pin name
ADTG_0
Function description
LQFP-64 LQFP-48
QFN-64 QFN-48
LQFP-80 BGA-96
ADC
66
7
A8
-
-
9
58
8
34
35
36
38
39
-
40
44
45
-
-
-
5
-
-
25
26
27
29
30
-
ADTG_1
ADTG_2
ADTG_3
ADTG_6
AN00
AN01
AN02
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
D3
G3
C5
G2
J11
J10
J8
H9
G10
G9
F10
F9
E11
E10
E9
D10
D9
C11
C8
C7
B7
A/D converter external trigger input pin
13
74
12
42
43
44
46
47
48
49
53
54
55
56
57
58
59
67
68
69
72
74
75
76
2
-
-
-
-
-
-
46
47
48
54
55
56
57
58
59
60
2
34
35
36
-
-
-
42
-
43
44
2
A/D converter analog input pin.
ANxx describes ADC ch.xx.
A6
C5
B4
C4
C1
C2
B3
3
4
9
10
3
4
5
6
3
4
-
-
E2
E3
Document Number: 002-05652 Rev.*C
Page 23 of 108
MB9B320M Series
Pin No
Pin function
Pin name
TIOA0_1
Function description
Base timer ch.0 TIOA pin
LQFP-64 LQFP-48
QFN-64
LQFP-80
BGA-96
QFN-48
6
18
-
7
-
Base Timer
0
14
30
9
15
5
31
10
6
H1
10
22
5
11
-
23
6
TIOB0_0
TIOB0_1
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOB4_0
TIOA5_0
TIOA5_1
TIOB5_0
TIOA6_1
TIOB6_1
TIOA7_1
TIOB7_1
SWCLK
K6
E2
H2
D1
J6
E3
D2
H3
C4
L7
G1
B4
J1
B6
K7
G2
C6
L5
J2
J7
K5
J4
K8
B7
C7
D10
D9
B9
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base Timer
1
19
-
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
-
-
Base Timer
2
16
76
32
11
75
17
70
33
12
71
21
18
34
22
19
35
69
68
57
58
62
12
60
24
7
59
13
-
25
8
-
8
44
-
-
43
9
-
Base Timer
3
-
-
-
-
Base Timer
4
-
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
14
26
-
15
27
56
55
46
47
50
10
-
Base Timer
5
-
11
-
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input pin
Serial wire debug interface data input / output
pin
Base Timer
6
Base Timer
7
Debugger
-
-
34
35
38
SWDIO
64
A9
52
40
SWO
TCK
TDI
TDO
TMS
TRSTX
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
JTAG test reset input pin
65
62
63
65
64
61
B8
B9
B11
B8
A9
53
50
51
53
52
49
41
38
39
41
40
37
A10
Document Number: 002-05652 Rev.*C
Page 24 of 108
MB9B320M Series
Pin No
Pin function
Pin name
INT00_0
Function description
LQFP-64 LQFP-48
QFN-64
LQFP-80
BGA-96
QFN-48
External
Interrupt
2
C1
2
2
External interrupt request 00 input pin
INT00_2
INT01_0
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_2
INT08_2
INT10_0
INT11_0
INT12_0
INT13_0
INT14_0
INT14_1
INT15_0
INT15_1
INT16_1
INT17_1
INT18_0
INT18_1
INT18_2
INT19_0
INT19_1
INT19_2
67
3
4
43
73
46
9
12
49
10
60
55
11
13
59
35
14
5
C8
C2
B3
J10
B5
H9
E2
G2
F10
E3
P20
E10
G1
G3
C11
K8
H1
D1
E1
L5
K5
K7
J7
G10
J5
G9
C4
A3
A2
C7
D2
H3
C11
D3
J2
54
3
4
35
-
38
5
8
40
6
-
-
7
9
48
27
10
-
-
-
-
-
External interrupt request 01 input pin
External interrupt request 02 input pin
3
4
26
-
29
-
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
-
-
-
-
-
-
5
36
-
6
-
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
8
-
-
-
-
21
22
33
34
47
29
48
76
78
79
68
6
25
26
39
-
-
30
-
External interrupt request 14 input pin
External interrupt request 15 input pin
-
-
60
62
63
55
-
12
56
-
44
46
47
-
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
-
16
59
7
8
-
-
18
14
10
Document Number: 002-05652 Rev.*C
Page 25 of 108
MB9B320M Series
Pin No
Pin function
Pin name
INT20_0
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
-
18
-
-
19
-
LQFP-80
BGA-96
External
Interrupt
70
30
56
71
31
32
66
72
61
62
63
64
65
66
67
68
69
70
71
72
42
43
44
46
47
48
49
53
54
55
56
60
59
58
57
B6
K6
E9
C6
J6
L7
A8
A6
A10
B9
-
22
-
INT20_1
INT20_2
INT21_0
INT21_1
INT22_1
INT23_1
NMIX
P00
P01
P02
P03
P04
P07
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P14
P15
P16
P17
P18
P19
P1A
P1B
P20
P21
P22
P23
External interrupt request 20 input pin
External interrupt request 21 input pin
-
23
24
-
57
49
50
51
52
53
-
External interrupt request 22 input pin
External interrupt request 23 input pin
Non-Maskable Interrupt input pin
-
42
37
38
39
40
41
-
-
-
-
-
GPIO
B11
A9
B8
A8
General-purpose I/O port 0
C8
C7
B7
B6
C6
A6
54
55
56
-
-
-
57
34
35
36
38
39
-
40
44
45
-
-
-
48
47
46
42
25
26
27
29
30
-
-
-
-
-
-
-
36
35
34
J11
J10
J8
H9
G10
G9
F10
F9
E11
E10
E9
C10
C11
D9
D10
General-purpose I/O port 1
General-purpose I/O port 2
Document Number: 002-05652 Rev.*C
Page 26 of 108
MB9B320M Series
Pin No
Pin function
Pin name
P30
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-80
BGA-96
GPIO
9
E2
5
-
P31
P32
P33
P39
P3A
P3B
P3C
P3D
P3E
P3F
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
10
11
12
13
14
15
16
17
18
19
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
E3
G1
G2
G3
H1
H2
H3
J1
J2
J4
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
C4
B4
C5
B5
A3
A2
K9
L9
6
7
8
9
10
11
12
13
14
15
-
-
-
-
5
6
7
8
9
10
11
-
General-purpose I/O port 3
-
-
19
20
-
22
23
24
25
26
27
2
3
4
-
-
-
-
60
59
58
-
62
63
28
30
31
15
16
-
18
19
-
-
-
-
2
3
4
-
-
-
-
44
43
-
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
-
46
47
20
22
23
General-purpose I/O port 8
General-purpose I/O port E
L10
Document Number: 002-05652 Rev.*C
Page 27 of 108
MB9B320M Series
Pin No
Pin function
Pin name
SIN0_0
Function description
LQFP-64 LQFP-48
QFN-64
LQFP-80
BGA-96
QFN-48
36
Multi-
function Serial
0
59
46
C11
H9
48
Multi-function serial interface ch.0 input pin
SIN0_1
38
47
29
35
SOT0_0
(SDA0_0)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA0 when it is used in an I2C
(operation mode 4).
58
47
57
48
D9
SOT0_1
(SDA0_1)
G10
D10
G9
39
46
-
30
34
-
SCK0_0
(SCL0_0)
Multi-function serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used in
a CSIO (operation mode 2) and as SCL0
when it is used in an I2C (operation mode 4).
SCK0_1
(SCL0_1)
Multi-
function
Serial
1
SIN1_1
Multi-function serial interface ch.1 input pin
43
44
49
J10
J8
35
36
40
26
27
-
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in
a UART/LIN (operation modes 0,1,3) .
SOT1_1
(SDA1_1)
Multi-
function Serial
2
SIN2_2
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA2 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.2 clock I/O
pin.
This pin operates as SCK2 when it is used in
a CSIO (operation mode 2) and as SCL2
when it is used in an I2C (operation mode 4).
F10
SOT2_2
(SDA2_2)
53
54
F9
44
45
-
-
SCK2_2
(SCL2_2)
E11
Multi-
function Serial
3
SIN3_1
SIN3_2
2
C1
J5
2
-
2
-
Multi-function serial interface ch.3 input pin
29
SOT3_1
(SDA3_1)
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA3 when it is used in an I2C
(operation mode 4).
3
C2
K6
B3
J6
3
-
3
-
SOT3_2
(SDA3_2)
30
4
SCK3_1
(SCL3_1)
Multi-function serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in
a CSIO (operation mode 2) and as SCL3
when it is used in an I2C (operation mode 4).
4
-
4
-
SCK3_2
(SCL3_2)
31
Document Number: 002-05652 Rev.*C
Page 28 of 108
MB9B320M Series
Pin No
Pin function
Pin name
SIN4_0
Function description
LQFP-64 LQFP-48
QFN-64
LQFP-80 BGA-96
QFN-48
Multi-
function Serial
4
67
55
C8
54
-
-
Multi-function serial interface ch.4 input pin
SIN4_1
E10
-
SOT4_0
(SDA4_0)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA4 when it is used in an I2C (operation
mode 4).
68
56
C7
E9
55
-
-
SOT4_1
(SDA4_1)
-
Multi-function serial interface ch.4 clock I/O
pin.
This pin operates as SCK4 when it is used in a 69
CSIO (operation mode 2) and as SCL4 when it
is used in an I2C (operation mode 4).
SCK4_0
(SCL4_0)
B7
B6
56
-
-
Multi-function serial interface ch.4 RTS output
pin
Multi-function serial interface ch.4 CTS input
pin
RTS4_0
70
-
-
CTS4_0
SIN5_0
71
C6
C4
-
Multi-
function Serial
5
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA5 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.5 clock I/O
pin.
This pin operates as SCK5 when it is used in a 74
CSIO (operation mode 2) and as SCL5 when it
is used in an I2C (operation mode 4).
76
60
44
SOT5_0
(SDA5_0)
75
B4
C5
59
58
43
SCK5_0
(SCL5_0)
-
Multi-
function Serial
6
SIN6_0
SIN6_1
5
D1
G2
-
-
-
Multi-function serial interface ch.6 input pin
12
8
SOT6_0
(SDA6_0)
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA6 when it is used in an I2C (operation
mode 4).
6
D2
G1
D3
E3
-
-
-
-
-
SOT6_1
(SDA6_1)
11
7
7
-
SCK6_0
(SCL6_0)
Multi-function serial interface ch.6 clock I/O
pin.
This pin operates as SCK6 when it is used in a
CSIO (operation mode 2) and as SCL6 when it
is used in an I2C (operation mode 4).
SCK6_1
(SCL6_1)
10
6
Document Number: 002-05652 Rev.*C
Page 29 of 108
MB9B320M Series
Pin No
Pin function
Pin name
SIN7_1
Function description
LQFP-64 LQFP-48
QFN-64
LQFP-80 BGA-96
QFN-48
Multi-
function Serial
7
Multi-function serial interface ch.7 input pin
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA7 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
CSIO (operation mode 2) and as SCL7 when it
is used in an I2C (operation mode 4).
35
K8
27
-
SOT7_1
(SDA7_1)
34
J7
26
25
-
SCK7_1
(SCL7_1)
33
K7
-
Multi-
function Timer
0
Input signal of waveform generator to control
outputs RTO00 to RTO05 of Multi-function
timer 0
DTTI0X_0
DTTI0X_2
FRCK0_2
13
75
43
G3
B4
9
5
59
35
43
26
16-bit free-run timer ch.0 external clock input
pin
J10
IC00_1
IC00_2
IC01_1
IC02_2
IC03_2
55
44
56
46
47
E10
J8
-
-
36
-
27
-
16-bit input capture input pin of Multi-function
timer 0.
ICxx describes channel number.
E9
H9
38
39
29
30
G10
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output mode.
RTO00_0
(PPG00_0)
14
15
16
17
18
19
H1
H2
H3
J1
J2
J4
10
11
12
13
14
15
6
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output mode.
RTO01_0
(PPG00_0)
7
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output mode.
RTO02_0
(PPG02_0)
8
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output mode.
RTO03_0
(PPG02_0)
9
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output mode.
RTO04_0
(PPG04_0)
10
11
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output mode.
RTO05_0
(PPG04_0)
IGTRG_0
IGTRG_1
32
76
L7
24
60
-
PPG IGBT mode external trigger input pin
C4
44
Document Number: 002-05652 Rev.*C
Page 30 of 108
MB9B320M Series
Pin No
Pin function
Pin name
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
Function description
LQFP-64 LQFP-48
QFN-64
LQFP-80 BGA-96
QFN-48
Quadrature Position/
Revolution Counter 0
9
30
2
10
31
3
11
32
4
60
33
59
34
58
35
78
79
75
72
14
72
14
E2
K6
C1
E3
J6
C2
G1
L7
B3
C10
K7
C11
J7
D9
K8
A3
A2
B4
A6
H1
A6
H1
5
22
2
6
23
3
7
24
4
-
25
-
-
-
QPRC ch.0 AIN input pin
2
-
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
-
3
-
ZIN0_1
ZIN0_2
-
4
-
Quadrature Position/
Revolution Counter 1
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
UDM0
UDP0
UHCONX
RTCCO_0
RTCCO_2
SUBOUT_0
SUBOUT_2
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
-
-
-
-
26
-
27
62
63
59
57
10
57
10
-
USB
USB device/host D – pin
USB device/host D + pin
USB external pull-up control pin
0.5 seconds pulse output pin of
Real-time clock
46
47
43
42
6
42
6
Real-time clock
Sub clock output pin
Low-Power
Consumption
Mode
Deep standby mode return signal input
pin 0
Deep standby mode return signal input
pin 1
Deep standby mode return signal input
pin 2
Deep standby mode return signal input
pin 3
WKUP0
WKUP1
WKUP2
WKUP3
72
43
59
76
A6
57
35
48
60
42
26
36
44
J10
C11
C4
DAC
DA0
DA1
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
External Reset Input pin.
A reset is valid when INITX="L".
30
31
K6
J6
22
23
18
19
Reset
INITX
28
K4
21
17
Document Number: 002-05652 Rev.*C
Page 31 of 108
MB9B320M Series
Pin No
Pin function
Pin name
Function description
Mode 0 pin.
LQFP-64
LQFP-48
QFN-48
LQFP-80 BGA-96
QFN-64
Mode
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
Mode 1 pin.
MD0
37
36
L8
29
21
MD1
During serial programming to Flash memory,
K9
28
20
MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
3.3V Power supply port for USB I/O
GND Pin
Power
GND
VCC
VCC
VCC
USBVCC
VSS
1
B1
K1
K11
A4
F1
1
1
14
-
45
-
25
41
77
-
18
33
61
-
VSS
GND Pin
-
F2
-
-
VSS
GND Pin
-
F3
-
-
VSS
VSS
VSS
VSS
GND Pin
GND Pin
GND Pin
GND Pin
-
20
-
B2
L1
K2
J3
-
16
-
-
12
-
-
-
-
VSS
GND Pin
-
L6
-
-
VSS
VSS
VSS
VSS
GND Pin
GND Pin
GND Pin
GND Pin
24
40
-
L4
-
32
-
-
24
-
L11
K10
J9
-
-
-
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_0
CROUT_1
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
-
-
-
-
-
-
-
80
38
26
39
27
60
72
B10
C9
D11
A11
A7
C3
A5
A1
L9
-
-
-
-
-
-
-
64
30
19
31
20
-
-
-
-
-
-
-
-
48
22
15
23
16
-
Clock
L3
L10
K3
C10
A6
Built-in high-speed CR-osc clock output port
57
42
Analog
Power
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference voltage input
pin
A/D converter and D/A converter
GND pin
AVCC
AVRH
AVSS
50
51
45
H11
F11
H10
41
42
37
31
32
28
Analog
GND
A/D converter analog reference voltage input
pin
Power supply stabilization capacity pin
AVRL
C
52
23
G11
L2
43
17
33
13
C pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05652 Rev.*C
Page 32 of 108
MB9B320M Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is selected.
• Oscillation feedback resistor
P-ch
P-ch
: Approximately 1 MΩ
• With Standby mode control
Digital output
Digital output
X1A
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
N-ch
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-05652 Rev.*C
Page 33 of 108
MB9B320M Series
Type
Circuit
Remarks
C
• Open drain output
• CMOS level hysteresis input
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 5 MΩ
P-ch
P-ch
Digital output
• With Standby mode control
X1A
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
N-ch
Digital output
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
P-ch
N-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05652 Rev.*C
Page 34 of 108
MB9B320M Series
Type
Circuit
Remarks
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
P-ch
P-ch
Digital output
Digital output
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
Digital output
Digital output
P-ch
P-ch
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
N-ch
P-ch transistor is always off
• +B input is available
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
Document Number: 002-05652 Rev.*C
Page 35 of 108
MB9B320M Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -12 mA, IOL= 12 mA
• +B input is available
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
H
It is possible to select the USB I/O /
GPIO function.
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
When the USB I/O is selected.
• Full-speed, Low-speed control
GPIO Digital input circuit control
When the GPIO is selected.
UDP output
• CMOS level output
UDP0/P81
USB Full-speed/Low-speed control
UDP input
• CMOS level hysteresis input
• With standby mode control
Differential
UDM0/P80
Differential input
USB/GPIO select
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-05652 Rev.*C
Page 36 of 108
MB9B320M Series
Type
Circuit
Remarks
I
• CMOS level output
• CMOS level hysteresis input
• 5 V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
P-ch
P-ch
Digital output
Digital output
• Available to control PZR registers.
• When this pin is used as an I2C pin,
the digital output
N-ch
P-ch transistor is always off
R
Pull-up resistor control
Digital input
Standby mode control
J
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• 5 V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
Digital output
Digital output
P-ch
P-ch
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
N-ch
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
K
CMOS level hysteresis input
Mode input
Document Number: 002-05652 Rev.*C
Page 37 of 108
MB9B320M Series
Type
Circuit
Remarks
L
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
P-ch
P-ch
N-ch
Digital output
Digital output
• IOH = -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
R
Standby mode Control
Analog output
Document Number: 002-05652 Rev.*C
Page 38 of 108
MB9B320M Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
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Page 39 of 108
MB9B320M Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
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Page 40 of 108
MB9B320M Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05652 Rev.*C
Page 41 of 108
MB9B320M Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin, between AVRH pin and AVRL pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size:
Load capacitance:
More than 3.2 mm × 1.5 mm
Approximately 6 pF to 7 pF
Lead type
Load capacitance:
Approximately 6 pF to 7 pF
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as
Can be used as
general-purpose
I/O ports.
External clock
input
X1(PE3),
X1A (P47)
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Page 42 of 108
MB9B320M Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC →USBVCC
VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
USBVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05652 Rev.*C
Page 43 of 108
MB9B320M Series
8. Block Diagram
MB9BF321K/L/M, F322K/L/M, F324K/L/M
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
8/16 Kbytes
SWJ-DP
ROM Table
Cortex-M3ꢀCore
@72MHz(Max)
I
SRAM1
8/16 Kbytes
D
Sys
NVIC
On-Chip Flash
64+32 Kbytes/
128+32 Kbytes/
256+32 Kbytes
Flash I/F
Security
Dual-Timer
WatchDog Timer
(Software)
USBVCC
USB2.0
(Host/
Device)
PHY
UDP0/UDM0
Clock Reset
Generator
UHCONX
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
Main
Source Clock
X0
X1
PLL
Osc
Sub
Osc
CR
4MHz
CR
100kHz
X0A
X1A
CROUT
AVCC,
AVSS,
AVRH,
AVRL
12-bit A/D Converter
Unit 0
ANxx
Unit 1
Power-On
Reset
USB Clock Ctrl
LVD Ctrl
PLL
ADTGx
10-bit D/A Converter
2units
LVD
DAx
C
Regulator
IRQ-Monitor
Base Timer
16-bit 8ch./
32-bit 4ch.
TIOAx
TIOBx
CRC
Accelerator
AINx
BINx
ZINx
RTCCO_x,
SUBOUT_x
QPRC
2ch.
Real-Time Colck
Watch Counter
A/D Activation
Compare 2ch.
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
16-bit Input Capture
4ch.
IC0x
MD0,
MD1
MODE-Ctrl
16-bit Free-run Timer
3ch.
FRCKx
WKUPx
Deep Standby Ctrl
16-bit Output
Compare 6ch.
P0x,
P1x,
・
・
・
GPIO
PIN-Function-Ctrl
DTTI0X
RTO0x
Waveform Generator
3ch.
PFx
SCKx
Multi-Function Serial I/F
8ch.
(with FIFO ch.0/1/3/4)
HW flow control(ch.4)
SINx
16-bit PPG
3ch.
IGTRG_x
SOTx
CTS4
RTS4
Multi-function Timer
Document Number: 002-05652 Rev.*C
Page 44 of 108
MB9B320M Series
9. Memory Size
See “Memory size” in “Product Lineup” to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
Cortex-M3 Private
Peripherals
0xE000_0000
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
DMAC
Reserved
USB ch.0
Reserved
RTC
Reserved
Watch Counter
CRC
0x7000_0000
0x6000_0000
External DeviceArea
Reserved
MFS
Reserved
USB Clock Ctrl
LVD/DS mode
Reserved
GPIO
0x4400_0000
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
32Mbyte
Bit band alias
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
Reserved
CR Trim
Reserved
D/AC
32Mbyte
Bit band alias
Reserved
A/DC
0x2008_0000
0x2000_0000
0x1FF8_0000
SRAM1
SRAM0
QPRC
Base Timer
PPG
Reserved
0x0020_8000
0x0020_0000
0x0010_4000
0x0010_0000
Reserved
Flash(Work area)
Reserved
0x4002_1000
0x4002_0000
See " Memory Map (2)"
for the memory size
details.
Security/CR Trim
MFT unit0
Reserved
Dual Timer
Reserved
0x4001_6000
0x4001_5000
Flash(Main area)
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
0x0000_0000
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-05652 Rev.*C
Page 45 of 108
MB9B320M Series
Memory Map (2)
MB9BF324K/L/M
MB9BF322K/L/M
MB9BF321K/L/M
0x2008_0000
0x2008_0000
0x2008_0000
Reserved
Reserved
Reserved
0x2000_4000
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
0x2000_0000
0x1FFF_E000
SRAM1
16Kbytes
SRAM1
8Kbytes
SRAM1
8Kbytes
0x2000_0000
0x1FFF_C000
0x0020_8000
SRAM0
8Kbytes
SRAM0
8Kbytes
SRAM0
16Kbytes
Reserved
Reserved
Reserved
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
0x0020_0000
Reserved
Reserved
Reserved
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
0x0004_0000
Reserved
SA11(64KB)
SA10(64KB)
Reserved
0x0002_0000
SA9(64KB)
SA8(48KB)
SA9(64KB)
SA8(48KB)
0x0001_0000
0x0000_0000
SA8(48KB)
SA3(8KB)
SA2(8KB)
SA3(8KB)
SA2(8KB)
SA3(8KB)
SA2(8KB)
0x0000_0000
0x0000_0000
Refer to the programming manual for the detail of Flash main area.
MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
Document Number: 002-05652 Rev.*C
Page 46 of 108
MB9B320M Series
Peripheral Address Map
Start address
End address
Bus
AHB
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
0x4000_FFFF
Flash Memory I/F register
Reserved
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_8FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
APB1
D/A Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
Reserved
Low-Voltage Detector
Deep standby mode Controller
USB clock generator
Reserved
APB2
Multi-function serial Interface
CRC
Watch Counter
Real-time clock
Reserved
USB ch.0
Reserved
AHB
DMAC register
Reserved
Document Number: 002-05652 Rev.*C
Page 47 of 108
MB9B320M Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
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MB9B320M Series
List of Pin Status
Power-on
reset or
low-
voltage
detection
state
Return
from
Deep
standby
mode
Run
mode or
SLEEP
mode
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
INITX
input
state
Timer mode,
RTC mode, or
STOP mode state
state
state
state
Function group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply stable
INITX = 0 INITX = 1
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 1
-
INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
A
Main crystal
oscillator input pin/
External main
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z /
Hi-Z /
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Internal
input
fixed at
"0"
Maintain
previous
state
Internal
input
fixed at
"0"
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
B
Maintain
previous
state/Whe state/Wh
n en
Maintain
previous
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Whe
n
oscillation
stops*1,
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Internal
input fixed
at "0"/
or Input
enable
Main crystal
oscillator output
pin
oscillation oscillation oscillation oscillation oscillation
stops*1,
Hi-Z /
Internal
input
stops*1,
Hi-Z /
Internal
input
stops*1,
Hi-Z /
Internal
input
stops*1,
Hi-Z /
Internal
input
stops*1,
Hi-Z /
Internal
input
Internal
input fixed
at "0"
fixed at
"0"
fixed at
"0"
fixed at
"0"
fixed at
"0"
fixed at
"0"
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
INITX
C
input pin
Mode
D
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
input pin
Document Number: 002-05652 Rev.*C
Page 49 of 108
MB9B320M Series
Power-on
reset or
low-
voltage
detection
state
Return
from
Deep
standby
mode
Run
mode or
SLEEP
mode
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
INITX
input
state
Timer mode,
RTC mode, or
STOP mode state
state
state
state
Function group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply stable
INITX = 0 INITX = 1
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 1
-
INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
F
Sub crystal
oscillator input pin
/
External sub clock
input selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z/
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
External sub clock
input selected
Setting
disabled
Setting
disabled
Setting
disabled
G
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Whe
n
oscillation
stops*2,
Hi-Z/
Hi-Z /
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Internal
input fixed
at "0"/
or Input
enable
Sub crystal
oscillator output
pin
Maintain
previous
state
oscillation oscillation oscillation oscillation
stops*2,
Hi-Z /
Internal
input
stops*2,
Hi-Z /
Internal
input
stops*2,
Hi-Z/
Internal
input
stops*2,
Hi-Z/
Internal
input
Internal
input fixed
at "0"
fixed at
"0"
fixed at
"0"
fixed at
"0"
fixed at
"0"
Document Number: 002-05652 Rev.*C
Page 50 of 108
MB9B320M Series
Power-on
reset or
low-
voltage
detection
state
Return
from
Deep
standby
mode
Run
mode or
SLEEP
mode
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
INITX
input
state
Timer mode,
RTC mode, or
STOP mode state
state
state
state
Function group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply stable
INITX = 0 INITX = 1
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 1
-
INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Maintain
previous
state
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z
Maintain
previous
state
H
Hi-Z at
trans-
Hi-Z at
trans-
mission/
Input
enabled/
Internal
input
mission/
Input
enabled/
Internal
input
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
USB I/O pin
fixed at
"0" at
fixed at
"0" at
reception
reception
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Analog input
selected
Hi-Z
disabled
enabled
enabled
enabled
enabled
enabled
disabled
disabled
I
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
NMIX selected
GPIO
selected
Hi-Z /
WKUP
input
Resource other
than above
selected
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
enabled
Hi-Z
Hi-Z
Maintain
previous
state
GPIO
selected
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input
fixed at
"0"
J
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Document Number: 002-05652 Rev.*C
Page 51 of 108
MB9B320M Series
Power-on
reset or
low-
voltage
detection
state
Return
from
Deep
standby
mode
Run
mode or
SLEEP
mode
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
INITX
input
state
Timer mode,
RTC mode, or
STOP mode state
state
state
state
Function group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply stable
INITX = 0 INITX = 1
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 1
-
INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Resource selected
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
K
Hi-Z
GPIO
selected
Analog output
selected
*3
*4
Setting
Setting
Setting
Maintain
previous
state
disabled
disabled
disabled
GPIO
selected
Internal
input
fixed at
"0"
External interrupt
enabled selected
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
GPIO
selected
L
Maintain
previous
state
Resource other
than above
selected
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
GPIO
selected
Internal
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Analog input
selected
enabled
M
enabled
enabled
enabled
enabled
enabled
enabled
Resource other
than above
selected
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
fixed at
"0"
Document Number: 002-05652 Rev.*C
Page 52 of 108
MB9B320M Series
Power-on
reset or
low-
voltage
detection
state
Return
from
Deep
standby
mode
Run
mode or
SLEEP
mode
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
INITX
input
state
Timer mode,
RTC mode, or
STOP mode state
state
state
state
Function group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply stable
INITX = 0 INITX = 1
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 1
-
INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Analog input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
N
Maintain
previous
state
External interrupt
enabled selected
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and
Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
*3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at "0" at RTC mode, Stop mode.
*4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, Stop mode.
Document Number: 002-05652 Rev.*C
Page 53 of 108
MB9B320M Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
VCC
Unit
Remarks
Min
Max
Power supply voltage*1, *2
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5 V)
USBVCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
+2
V
V
V
V
Power supply voltage (for USB)*1, * 3
Analog power supply voltage*1, *4
Analog reference voltage*1, *4
USBVCC
AVCC
AVRH
VSS - 0.5
V
Except for USB pin
Input voltage*1
VI
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
USB pin
5 V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
-2
V
Clamp maximum current
Clamp total maximum current
ICLAMP
mA
mA
mA
*8
*8
Σ[ICLAMP
]
+20
10
20
4 mA type
L level maximum output current*5
L level average output current*6
IOL
-
mA
12 mA type
The pin doubled as USB
39
mA
I/O
4
12
mA
mA
4 mA type
12 mA type
The pin doubled as USB
I/O
IOLAV
-
16.5
mA
L level total maximum output current
L level total average output current*7
∑IOL
∑IOLAV
-
-
100
50
- 10
mA
mA
mA
4 mA type
H level maximum output current*5
H level average output current*6
IOH
-
-
- 20
mA
12 mA type
The pin doubled as USB
I/O
4 mA type
12 mA type
The pin doubled as USB
I/O
- 39
mA
- 4
- 12
mA
mA
IOHAV
- 18
mA
H level total maximum output current
H level total average output current*7
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
- 100
- 50
300
mA
mA
mW
°C
Storage temperature
TSTG
- 55
+ 150
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100
ms period.
*7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
Document Number: 002-05652 Rev.*C
Page 54 of 108
MB9B320M Series
*8:
• See “List of Pin Functions” and “I/O Circuit Type” about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
Digital output
Digital input
+B input (0V to 16V)
N-ch
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-05652 Rev.*C
Page 55 of 108
MB9B320M Series
12.2 Recommended Operating Conditions
(VSS = AVSS = AVRL = 0.0V)
Value
Parameter
Power supply voltage
Symbol
Conditions
Unit
Remarks
Min
2.7*4
Max
VCC
-
-
5.5
V
3.6
3.0
2.7
*1
*2
(≤ VCC
)
Power supply voltage (3V power supply) for
USB
USBVCC
V
5.5
(≤ VCC
)
Analog power supply voltage
Analog reference voltage
AVCC
AVRH
AVRL
CS
-
-
-
-
-
2.7
2.7
AVSS
1
5.5
AVCC
AVSS
10
V
V
AVCC = VCC
V
Smoothing capacitor
μF
°C
For Regulator*3
Operating temperature
TA
- 40
+ 105
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: See “C Pin” in “Handling Devices” for the connection of the smoothing capacitor.
*4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-05652 Rev.*C
Page 56 of 108
MB9B320M Series
12.3 DC Characteristics
12.3.1 Current Rating
(VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
CPU: 72 MHz,
Peripheral: 36 MHz
32.5
41
mA *1, *5
mA *1, *5
mA *1
PLL
Run mode
CPU:72 MHz,
Peripheral clock stops
NOP operation
18
2.5
110
23
3.4
980
High-speed
CR
Run
mode
CPU/ Peripheral: 4 MHz*2
ICC
Run mode
current
Sub
Run mode
CPU/ Peripheral: 32 kHz
µA
µA
*1, *6
*1
VCC
Low-speed
CR
CPU/ Peripheral: 100 kHz
130
1030
Run mode
PLL
Peripheral: 36 MHz
Peripheral: 4 MHz*2
Peripheral: 32 kHz
Peripheral: 100 kHz
22
1.6
96
28
2.6
mA *1, *5
mA *1
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep
mode
current
ICCS
955
975
µA
µA
*1, *6
*1
115
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA = +25°C, VCC = 5.5 V
*4: TA = +105°C, VCC = 5.5 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05652 Rev.*C
Page 57 of 108
MB9B320M Series
(VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
TA = + 25°C,
Unit
Remarks
Typ*2
Max*2
4.1
4.8
mA *1, *4
mA *1, *4
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
Main
Timer mode
ICCT
-
17
-
5.4
66
Timer
mode
current
μA
μA
μA
μA
μA
μA
*1, *5
*1, *5
*1, *5
*1, *5
*1
Sub
Timer mode
ICCT
ICCR
ICCH
835
61
15
-
RTC
mode
current
RTC mode
Stop mode
680
53
14
-
Stop
mode
current
600
*1
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 105°C,
When LVD is off,
When RAM is off
TA = + 105°C,
When LVD is off,
When RAM is on
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 105°C,
When LVD is off,
When RAM is off
TA = + 105°C,
When LVD is off,
When RAM is on
2.2
6.2
11
23
μA
μA
μA
μA
μA
μA
μA
μA
*1, *3, *5
*1, *3, *5
*1, *3, *5
*1, *3, *5
*1, *3
VCC
Deep Standby
RTC mode
ICCRD
155
215
9.6
22
-
Deep Standby
mode
current
1.6
5.6
*1, *3
Deep Standby
Stop mode
ICCHD
150
210
*1, *3
-
*1, *3
*1: When all ports are fixed.
*2: VCC = 5.5 V
*3: RAM on/off setting is on-chip SRAM only.
*4: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*5: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05652 Rev.*C
Page 58 of 108
MB9B320M Series
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
At operation
for reset
0.13
0.3
μA
At not detect
Vcc = 5.5 V
Low-voltage detection
circuit (LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
Vcc = 5.5 V
0.13
0.3
μA
At not detect
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
9.5
11.2
mA
*
*: The current at which to write or erase Flash memory, "ICCFLASH" is added to "ICC".
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
At 1unit operation
At stop
Unit
mA
μA
Remarks
Typ
Max
0.69
0.90
Power supply current
ICCAD
AVCC
0.25
1.1
25.84
1.97
3.4
At 1unit operation
AVRH=5.5 V
mA
Reference power
supply current
ICCAVRH
AVRH
At stop
0.2
μA
D/A Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
At 1unit operation
AVCC=3.3 V
250
315
380
μA
2
IDDA
*
Power supply
At 1unit operation
AVCC=5.0 V
AVCC
current*1
380
-
475
-
580
16
μA
μA
IDSA
At stop
*1: No-load
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05652 Rev.*C
Page 59 of 108
MB9B320M Series
12.3.2 Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
CMOS
Conditions
Unit
Remarks
Min
Typ
Max
hysteresis
input pin, MD0,
MD1
5 V tolerant
input pin
H level input
-
-
-
-
VCC × 0.8
VCC × 0.8
VSS - 0.3
VSS - 0.3
-
-
-
-
VCC + 0.3
VSS + 5.5
VCC × 0.2
VCC × 0.2
V
V
V
V
voltage
(hysteresis
input)
VIHS
CMOS
hysteresis
input pin, MD0,
MD1
5 V tolerant
input pin
L level input
voltage
(hysteresis
input)
VILS
VCC ≥ 4.5 V,
IOH = - 4 mA
4 mA type
VCC - 0.5
-
VCC
V
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
H level
output voltage
VOH
12 mA type
VCC - 0.5
USBVCC - 0.4
VSS
-
-
-
-
-
VCC
USBVCC
0.4
V
V
V
V
V
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
IOH = - 18.0 mA
USBVCC < 4.5 V,
IOH = - 12.0 mA
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
USBVCC ≥ 4.5 V,
IOL = 16.5 mA
USBVCC < 4.5 V,
IOL = 10.5 mA
-
The pin
doubled as
USB I/O
4 mA type
L level
output voltage
VOL
12 mA type
VSS
0.4
The pin
doubled as
USB I/O
VSS
0.4
Input leak current
IIL
-
- 5
33
-
+ 5
90
μA
kΩ
VCC ≥ 4.5 V
50
Pull-up resistance
value
RPU
Pull-up pin
VCC < 4.5 V
-
-
180
Other than
VCC,
USBVCC,
VSS,
Input capacitance
CIN
-
-
5
15
pF
AVCC,
AVSS, AVRH,
AVRL
Document Number: 002-05652 Rev.*C
Page 60 of 108
MB9B320M Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
4
4
4
48
20
48
20
250
250
When crystal oscillator is
connected
MHz
MHz
ns
Input frequency
fCH
When using external
Clock
4
X0,
X1
20.83
50
When using external
Clock
Input clock cycle
tCYLH
-
VCC < 4.5 V
PWH/tCYLH,
PWL/tCYLH
When using external
Clock
When using external
Clock
Input clock pulse width
45
-
55
5
%
Input clock rising time and tCF,
falling time
-
ns
tCR
fCM
-
-
-
-
-
-
72
72
MHz
MHz
Master clock
fCC
Base clock (HCLK/FCLK)
Internal operating
clock frequency*1
fCP0
fCP1
fCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz
MHz
MHz
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
-
-
-
-
-
-
-
-
13.8
25
-
-
-
-
ns
ns
ns
ns
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
tCYCC
tCYCP0
tCYCP1
tCYCP2
Internal operating
clock cycle time*1
25
25
APB2 bus clock*2
*1: For more information about each internal operating clock, see “Chapter 2-1: Clock” in “FM3 Family Peripheral Manual”.
*2: For about each APB bus which each peripheral is connected to, see “Block Diagram” in this data sheet.
X0
Document Number: 002-05652 Rev.*C
Page 61 of 108
MB9B320M Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
When crystal oscillator is
connected
-
-
32.768
-
kHz
Input frequency
1/ tCYLL
-
-
32
10
-
-
100
kHz
When using external clock
When using external clock
X0A,
X1A
Input clock cycle
tCYLL
-
31.25
μs
PWH/tCYLL,
PWL/tCYLL
Input clock pulse width
45
-
55
%
When using external clock
*: See “Sub crystal oscillator” in “Handling Devices” for the crystal oscillator used.
X0A
Document Number: 002-05652 Rev.*C
Page 62 of 108
MB9B320M Series
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
TA = + 25°C
3.92
4
4.08
TA = 0°C to + 85°C
3.9
3.88
3.94
3.92
3.9
2.8
-
4
4
4
4
4
4
-
4.1
4.12
4.06
4.08
4.1
TA = -40°C to + 105°C
When trimming*1
TA = + 25°C
VCC ≤ 3.6 V
Clock frequency
fCRH
MHz
TA = - 20°C to + 85°C
VCC ≤ 3.6 V
TA = - 20°C to + 105°C
VCC ≤ 3.6 V
TA = - 40°C to + 105°C
-
5.2
When not trimming
Frequency stabilization
time
2
tCRWT
30
μs
*
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.
This period is able to use high-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
Clock frequency
fCRL
-
50
100
150
kHz
Document Number: 002-05652 Rev.*C
Page 63 of 108
MB9B320M Series
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
4
5
75
-
-
-
-
-
-
16
37
150
72
MHz
multiplier
MHz
MHz
MHz
-
PLL macro oscillation clock frequency
Main PLL clock frequency*2
USB clock frequency*3
fPLLO
fCLKPLL
fCLKSPLL
-
48
After the M frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see “Chapter: Clock” in “FM3 Family Peripheral Manual”.
*3: For more information about USB clock, see “Chapter 2-2: USB Clock Generation” in “FM3 Family Peripheral Manual
Communication Macro Part”.
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
3.8
19
72
-
4
-
-
4.2
35
150
72
MHz
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
-
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see “Chapter 2-1: Clock” in “FM3 Family Peripheral Manual”.
Note:
−
Make sure to input to the Main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been
trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
PLL input
clock
PLL macro
clock
oscillation clock
(CLKPLL)
K
M
Main
PLL
divider
divider
N
divider
Document Number: 002-05652 Rev.*C
Page 64 of 108
MB9B320M Series
USB PLL connection
PLL input
clock
PLL macro
USB
Main clock (CLKMO)
oscillation clock
clock
K
M
USB PLL
divider
divider
N
divider
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Reset input time
Symbol
tINITX
Pin name
Conditions
Unit
Remarks
Min
Max
INITX
-
500
-
ns
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
*1
name
Min
Typ
Max
-
Power supply shut down time
Power ramp rate
tOFF
-
1
-
-
-
ms
dV/dt
tPRT
VCC
VCC: 0.2 V to 2.70 V
-
0.3
1.34
1000
18.6
mV/µs *2
ms
Time until releasing Power-on reset
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12.4.6.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
• VDH: detection voltage (when SVHR=00000) of Low-Voltage detection reset. See "12.8. Low-Voltage Detection
Characteristics".
Document Number: 002-05652 Rev.*C
Page 65 of 108
MB9B320M Series
12.4.8 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as ECK,
TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see “Block Diagram” in this data sheet.
Document Number: 002-05652 Rev.*C
Page 66 of 108
MB9B320M Series
12.4.9 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Baud rate
-
-
-
-
8
-
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
tSLOVI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Master mode
tIVSHI
tSHIXI
-
-
-
-
Serial clock L pulse width
Serial clock H pulse width
SCK ↓ → SOT delay time
tSLSH
tSHSL
tSLOVE
SCKx
2tCYCP - 10
tCYCP + 10
-
-
-
2tCYCP - 10
tCYCP + 10
-
-
-
ns
ns
ns
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
50
30
Slave mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHE
tSHIXE
10
20
-
-
10
20
-
-
ns
ns
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
−
−
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05652 Rev.*C
Page 67 of 108
MB9B320M Series
tSCYC
VOH
SCK
SOT
VOL
VOL
tSLOVI
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
SIN
Master mode
tSLSH
tSHSL
VIH
tR
VIH
tF
VIH
SCK
VIL
VIL
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05652 Rev.*C
Page 68 of 108
MB9B320M Series
CSIO (SPI = 0, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
VCC ≥ 4.5 V
Pin
name
Symbol
Conditions
Unit
Min
Max
Min
Max
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
tSHOVI
tIVSLI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
- 30
+ 30
- 20
+ 20
ns
Master mode
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
50
0
-
-
30
0
-
-
ns
ns
tSLIXI
tSLSH
tSHSL
Serial clock L pulse width
Serial clock H pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05652 Rev.*C
Page 69 of 108
MB9B320M Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05652 Rev.*C
Page 70 of 108
MB9B320M Series
CSIO (SPI = 1, SCINV = 0)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
VCC ≥ 4.5 V
Pin
name
Symbol
Conditions
Unit
Min
Max
Min
Max
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
tIVSLI
tSLIXI
tSOVLI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
Master mode
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05652 Rev.*C
Page 71 of 108
MB9B320M Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05652 Rev.*C
Page 72 of 108
MB9B320M Series
CSIO (SPI = 1, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
VCC ≥ 4.5 V
Pin
name
Symbol
Conditions
Unit
Min
Max
Min
Max
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05652 Rev.*C
Page 73 of 108
MB9B320M Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Min
Max
Unit
Remarks
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tSHSL
tF
tCYCP + 10
tCYCP + 10
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
-
-
SCK rising time
tR
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
Document Number: 002-05652 Rev.*C
Page 74 of 108
MB9B320M Series
12.4.10 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
ADTG
Conditions
Unit
Remarks
Min
2tCYCP
2tCYCP
Max
A/D converter trigger input
1
-
-
*
*
-
ns
FRCKx
ICxx
Free-run timer input clock
Input capture
tINH,
tINL
Input pulse width
1
DTTIxX
-
-
-
-
ns
ns
ns
ns
Waveform generator
*2
*3
*4
2tCYCP + 100*1
INTxx,
NMIX
External interrupt
NMI
500
500
WKUPx
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see
“Block Diagram” in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in RTL mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05652 Rev.*C
Page 75 of 108
MB9B320M Series
12.4.11 Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Parameter
AIN pin H width
AIN pin L width
BIN pin H width
Symbol
tAHL
tALL
tBHL
tBLL
Conditions
Min
Max
-
-
-
-
BIN pin L width
BIN rising time from
AIN pin H level
AIN falling time from
BIN pin H level
BIN falling time from
AIN pin L level
AIN rising time from
BIN pin L level
AIN rising time from
BIN pin H level
BIN falling time from
AIN pin H level
AIN falling time from
BIN pin L level
BIN rising time from
AIN pin L level
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
2tCYCP
*
-
ns
ZIN pin H width
ZIN pin L width
tZHL
tZLL
QCR:CGSC=0
QCR:CGSC=0
AIN/BIN rising and falling time from
determined ZIN level
Determined ZIN level from AIN/BIN
rising and falling time
tZABE
tABEZ
QCR:CGSC=1
QCR:CGSC=1
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see “Block Diagram” in this
data sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
Document Number: 002-05652 Rev.*C
Page 76 of 108
MB9B320M Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05652 Rev.*C
Page 77 of 108
MB9B320M Series
12.4.12 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Standard-
mode
Min
Fast-
mode
Min
Parameter
Symbol
Conditions
Unit
Remarks
Max
Max
SCL clock frequency
(Repeated) START condition hold time
SDA ↓ → SCL ↓
fSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SCL clock L width
SCL clock H width
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
(Repeated) START condition setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTA
tHDDAT
tSUDAT
tSUSTO
4.7
0
-
0.6
0
-
μs
μs
ns
μs
CL = 30 pF,
3.45*2
0.9*3
R = (VP/IOL)*1
250
4.0
-
-
100
0.6
-
-
Bus free time between
STOP condition and
START condition
tBUF
tSP
4.7
-
-
1.3
-
-
μs
4
4
Noise filter
-
2 tCYCP
*
2 tCYCP
*
ns
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast mode I2C bus device can be used on a Standard mode I2C bus system as long as the device satisfies the requirement of
“tSUDAT ≥ 250 ns”.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see “Block Diagram” in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05652 Rev.*C
Page 78 of 108
MB9B320M Series
12.4.13 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
TMS, TDI setup time
TMS, TDI hold time
Symbol
tJTAGS
Pin name
TCK,
Conditions
VCC ≥ 4.5 V
Unit
ns
Remarks
Min
Max
15
-
TMS, TDI
VCC < 4.5 V
VCC ≥ 4.5 V
TCK,
TMS, TDI
tJTAGH
15
-
ns
VCC < 4.5 V
VCC ≥ 4.5 V
-
-
25
45
TCK,
TDO
TDO delay time
tJTAGD
ns
VCC < 4.5 V
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05652 Rev.*C
Page 79 of 108
MB9B320M Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
Parameter
Symbol
Unit
Remarks
name
Min
Max
12
Resolution
-
-
-
-
-
-
-
-
-
bit
Integral Nonlinearity
± 1.5
± 4.5
LSB
LSB
mV
mV
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
-
-
± 1.7
± 2.5
AVRH = 2.7 V to
5.5 V
VZT
ANxx
ANxx
± 10
± 15
VFST
-
AVRH ± 5
AVRH ± 15
0.8*1
1.0*1
0.24
0.3
40
-
-
-
-
-
-
-
-
AVCC ≥ 4.5 V
AVCC < 4.5 V
Conversion time
-
-
-
-
μs
μs
ns
AVCC ≥ 4.5 V
AVCC < 4.5 V
Sampling time*2
tS
10
AVCC ≥ 4.5 V
AVCC < 4.5 V
Compare clock cycle*3
tCCK
1000
50
State transition time to operation
permission
tSTT
-
-
-
-
-
-
1.0
9.7
μs
Analog input capacity
Analog input resistor
CAIN
pF
1.7
2.4
4
AVCC ≥ 4.5 V
RAIN
-
-
-
kΩ
AVCC < 4.5 V
Interchannel disparity
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
Analog port input leak current
Analog input voltage
ANxx
ANxx
5
AVSS
AVRH
AVRH
AVRL
2.7
-
-
AVCC
AVSS
V
V
Reference voltage
-
AVSS
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=50 MHz
AVCC < 4.5 V, HCLK=40 MHz
sampling time: 240 ns, compare time: 560 ns.
sampling time: 300 ns, compare time: 700 ns
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and compare clock cycle, see “Chapter 1-1: A/D Converter” in “FM3 Family Peripheral Manual
Analog Macro Part”.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see “Block Diagram”.
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05652 Rev.*C
Page 80 of 108
MB9B320M Series
Comparator
ANxx
REXT
RAIN
Analog input pin
Analog signal
source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time
RAIN
:
Input resistor of A/D = 1.5 kΩ at 4.5 V < AVCC < 5.5 V ch.0 to ch.7
Input resistor of A/D = 1.6 kΩ at 4.5 V < AVCC < 5.5 V ch.8 to ch.15
Input resistor of A/D = 1.7 kΩ at 4.5 V < AVCC < 5.5 V ch.16 to ch.26
Input resistor of A/D = 2.2 kΩ at 2.7 V < AVCC < 4.5 V ch.0 to ch.7
Input resistor of A/D = 2.3 kΩ at 2.7 V < AVCC < 4.5 V ch.8 to ch.15
Input resistor of A/D = 2.4 kΩ at 2.7 V < AVCC < 4.5 V ch.16 to ch.26
Input capacity of A/D = 9.7 pF at 2.7 V < AVCC < 5.5 V
CAIN
:
REXT
:
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
Compare clock cycle
tCCK
:
Document Number: 002-05652 Rev.*C
Page 81 of 108
MB9B320M Series
Definition of 12-bit A/D Converter Terms
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
Resolution:
Integral Nonlinearity:
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Differential Nonlinearity:
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVRL
AVRH
AVRL
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-05652 Rev.*C
Page 82 of 108
MB9B320M Series
12.6 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Resolution
Symbol
Pin name
Unit
Remarks
Min
-
Max
10
-
-
bit
μs
tC20
0.47
2.37
- 4.0
- 0.9
-
0.58
0.69
3.43
+ 4.0
+ 0.9
10.0
+ 5.4
4.50
-
Load 20 pF
Conversion time
tC100
INL
DNL
2.90
μs
Load 100 pF
Integral Nonlinearity*1
Differential Nonlinearity*1,*2
-
LSB
LSB
mV
mV
kΩ
-
DAx
-
Code is 0x000
Code is 0x3FF
D/A operation
D/A stop
Output Voltage offset
VOFF
- 20.0
3.10
2.0
-
3.80
Analog output impedance
RO
tR
-
-
MΩ
ns
Output undefined period
*1: No-load
-
70
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05652 Rev.*C
Page 83 of 108
MB9B320M Series
12.7 USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
VIH
Conditions
Unit Remarks
Min
Max
Input H level voltage
-
-
-
-
2.0
USBVCC + 0.3
V
V
V
V
*1
*1
*2
*2
Input
charact-eris
tics
Input L level voltage
VIL
VSS - 0.3
0.2
0.8
-
Differential input sensitivity
VDI
VCM
Different common mode range
0.8
2.5
External
Output H level voltage
VOH
pull-down resistor
= 15 kΩ
2.8
3.6
V
*3
UDP0,
UDM0
External pull-up
resistor = 1.5 kΩ
-
Output L level voltage
VOL
0.0
0.3
V
V
*3
*4
ns *5
Crossover voltage
Rising time
VCRS
tFR
1.3
4
2.0
20
Output
charact-eris
tics
Full-Speed
Falling time
tFF
Full-Speed
Full-Speed
Full-Speed
Low-Speed
Low-Speed
Low-Speed
4
20
111.11
44
300
300
125
ns *5
Rising/ falling time matching
Output impedance
Rising time
Falling time
Rising/ falling time matching
tFRFM
ZDRV
tLR
tLF
tLRFM
90
28
75
75
80
%
Ω
*5
*6
ns *7
ns *7
%
*7
*1: The switching threshold voltage of the Single-End-Receiver of USB I/O buffer is set as within VIL
(Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use the differential-Receiver to receive the USB differential data signal.
The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the
local ground reference level.
The voltage range above is said to be the common mode input voltage range.
Common mode input voltage [V]
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to
ground and 15 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
Document Number: 002-05652 Rev.*C
Page 84 of 108
MB9B320M Series
*5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
Falling time
Document Number: 002-05652 Rev.*C
Page 85 of 108
MB9B320M Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential
Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor
(Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistor.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See “Low-Speed Load (Compliance Load)” for conditions of the external load.
Document Number: 002-05652 Rev.*C
Page 86 of 108
MB9B320M Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL = 200pF to
600pF
CL = 200pF to
600pF
Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-05652 Rev.*C
Page 87 of 108
MB9B320M Series
12.8 Low-Voltage Detection Characteristics
12.8.1 Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Value
Typ
2.45
2.50
2.60
Parameter
Detected voltage
Symbol
Conditions
Unit
Remarks
Min
2.25
2.30
2.39
Max
2.65
2.70
2.81
SVHR*1=
00000
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
SVHR*1=
00001
Same as SVHR = 00000 value
2.48 2.70 2.92
Same as SVHR = 00000 value
2.58 2.80 3.02
Same as SVHR = 00000 value
2.76 3.00 3.24
Same as SVHR = 00000 value
2.94 3.20 3.46
Same as SVHR = 00000 value
3.31 3.60 3.89
Same as SVHR = 00000 value
3.40 3.70 4.00
Same as SVHR = 00000 value
3.68 4.00 4.32
Same as SVHR = 00000 value
3.77 4.10 4.43
Same as SVHR = 00000 value
3.86 4.20 4.54
Same as SVHR = 00000 value
SVHR*1=
00010
SVHR*1=
00011
SVHR*1=
00100
SVHR*1=
00101
SVHR*1=
00110
SVHR*1=
00111
SVHR*1=
01000
SVHR*1=
01001
SVHR*1=
01010
2
LVD stabilization wait time
LVD detection delay time
tLVDW
-
-
-
-
-
-
8160 × tCYCP
*
μs
μs
tLVDDL
200
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to "00000" by Low-Voltage Detection
Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05652 Rev.*C
Page 88 of 108
MB9B320M Series
12.8.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Conditions
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
Unit
Remarks
Min
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
Max
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
LVD stabilization wait time
LVD detection delay time
tLVDW
-
-
-
-
-
-
8160 × tCYCP
*
μs
μs
tLVDDL
200
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05652 Rev.*C
Page 89 of 108
MB9B320M Series
12.9 Flash Memory Write/Erase Characteristics
12.9.1 Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Large Sector
Small Sector
Unit
Remarks
Typ
Max
1.1
2.7
Sector erase time
s
Includes write time prior to internal erase
0.3
16
0.9
310
18
Half word (16-bit)
write time
μs
Not including system-level overhead time
Includes write time prior to internal erase
Chip erase time
6.8
s
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
12.9.2 Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
Remarks
1,000
20*
10*
10,000
*: At average + 85°C
Document Number: 002-05652 Rev.*C
Page 90 of 108
MB9B320M Series
12.10Return Time from Low-Power Consumption Mode
12.10.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
tCYCC
μs
High-speed CR Timer mode,
Main Timer mode,
40
80
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
340
680
268
680
860
503
μs
μs
μs
tICNT
RTC mode,
Stop mode
308
268
583
503
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05652 Rev.*C
Page 91 of 108
MB9B320M Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
The return factor is different in each Low-Power consumption modes.
See “Chapter 6: Low Power Consumption Mode” and “Operations of Standby Modes” in FM3 Family Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See “Chapter 6: Low Power Consumption Mode” in “FM3 Family Peripheral Manual”.
Document Number: 002-05652 Rev.*C
Page 92 of 108
MB9B320M Series
12.10.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
148
263
μs
High-speed CR Timer mode,
Main Timer mode,
148
263
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
248
312
268
463
496
503
μs
μs
μs
tRCNT
RTC mode,
Stop mode
308
268
583
503
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
Document Number: 002-05652 Rev.*C
Page 93 of 108
MB9B320M Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
The return factor is different in each Low-Power consumption modes.
See “Chapter 6: Low Power Consumption Mode” and “Operations of Standby Modes” in FM3 Family Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See “Chapter 6: Low Power Consumption Mode” in “FM3 Family Peripheral Manual”.
−
The time during the power-on reset/low-voltage detection reset is excluded. See “12.4.7. Power-on Reset Timing in
12.4. AC Characteristics in 12.Electrical Characteristics” for the detail on the time during the power-on reset/low -voltage
detection reset.
−
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05652 Rev.*C
Page 94 of 108
MB9B320M Series
13.Ordering Information
On-chip
SRAM
On-chip Flash
memory
Part number
MB9BF321KQN-G-AVE2
MB9BF322KQN-G-AVE2
MB9BF324KQN-G-AVE2
MB9BF321KPMC-G-JNE2
MB9BF322KPMC-G-JNE2
MB9BF324KPMC-G-JNE2
MB9BF321LQN-G-AVE2
MB9BF322LQN-G-AVE2
MB9BF324LQN-G-AVE2
MB9BF321LPMC1-G-JNE2
MB9BF322LPMC1-G-JNE2
MB9BF324LPMC1-G-JNE2
MB9BF321LPMC-G-JNE2
MB9BF322LPMC-G-JNE2
MB9BF324LPMC-G-JNE2
MB9BF321MPMC-G-JNE2
MB9BF322MPMC-G-JNE2
MB9BF324MPMC-G-JNE2
MB9BF321MPMC1-G-JNE2
MB9BF322MPMC1-G-JNE2
MB9BF324MPMC1-G-JNE2
MB9BF321MBGL-GE1
Package
Packing
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
Plastic・QFN
(0.5 mm pitch), 48-pin
(VNA048)
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic・LQFP
(0.5 mm pitch), 48-pin
(LQA048)
Main: 128 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic・QFN
(0.5 mm pitch), 64-pin
(VNC064)
Main: 128 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic・LQFP
(0.5 mm pitch), 64-pin
(LQD064)
Main: 128 Kbyte
Work: 32 Kbyte
Tray
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic・LQFP
(0.65 mm pitch), 64-pin
(LQG064)
Main: 128 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic・LQFP
(0.5 mm pitch), 80-pin
(LQH080)
Main: 128 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic・LQFP
(0.65 mm pitch), 80-pin
(LQJ080)
Main: 128 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic・PFBGA
(0.5 mm pitch), 96-pin
(FDG096)
Main: 128 Kbyte
Work: 32 Kbyte
MB9BF322MBGL-GE1
Tray
Main: 256 Kbyte
Work: 32 Kbyte
MB9BF324MBGL-GE1
Document Number: 002-05652 Rev.*C
Page 95 of 108
MB9B320M Series
14.Package Dimensions
Package Type
Package Code
LQFP 80
LQH080
4
D
5
7
D1
60
41
41
60
61
40
40
61
5
7
E1
E
4
3
6
80
21
21
80
1
20
20
1
2
5
8
7
D
3
0.10
C
C
A-B D
BOTTOM VIEW
e
0.08
A-B
D
b
0.20
C A-B D
TOP VIEW
2
A
A
SEATING
PLANE
9
c
A'
L1
0.25
0.08
C
A1
b
L
10
SIDE VIEW
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
c
D
D1
e
14.00 BSC.
12.00 BSC.
0.50 BSC
E
14.00 BSC.
12.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
002-11501 **
Document Number: 002-05652 Rev.*C
Page 96 of 108
MB9B320M Series
Package Type
Package Code
LQFP 80
LQJ080
4
5
D
7
D1
60
41
41
60
61
40
40
61
E1
E
5
7
4
3
6
80
21
21
80
1
20
b
20
1
2
A-B
5
7
D
0.10
C
C
e
3
0.20
C A-B D
ddd
A-B
D
8
2
A
9
A
SEATING
PLANE
c
A'
A1
b
0.10
C
0.2 5
L
L1
10
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.16 0.32 0.38
0.09 0.20
0.20
c
D
D1
e
16.00 BSC
14.00 BSC
0.65 BSC
E
16.00 BSC
14.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
0
8
002-14043 **
PACKAGE OUTLINE, 80 LEAD LQFP
14.0X14.0X1.7 MM LQJ080 REV**
Document Number: 002-05652 Rev.*C
Page 97 of 108
MB9B320M Series
Package Type
Package Code
LQFP 64
LQD064
4
5
D
D1
7
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
5
7
e
A-B D
3
0.10
0.08
C A-B D
BOTTOM VIEW
0.20
C
C
A-B
D
b
8
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A'
A1
10
SECTION A-A'
L1
0.08
C
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
c
0.20
D
D1
e
12.00 BSC.
10.00 BSC.
0.50 BSC
E
12.00 BSC.
10.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
002-11499 **
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
Document Number: 002-05652 Rev.*C
Page 98 of 108
MB9B320M Series
Package Type
Package Code
LQFP 64
LQG064
4
D
5
7
D1
48
33
33
48
49
32
32
49
E1
E
5
7
4
3
64
17
17
64
1
16
16
1
2
5
7
BOTTOM VIEW
e
3
0.10
C A-B D
0.20
C A-B D
0.13
C
A-B
D
b
8
TOP VIEW
2
A
A
9
SEATI NG
PLA NE
A1
10
0.2 5
L
c
A'
L1
b
0.10
C
SECTION A -A'
SIDE VIEW
DIMENSION
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.27 0.32 0.37
0.09 0.20
0.20
c
D
D1
e
14.00 BSC
12.00 BSC
0.65 BSC
E
14.00 BSC
12.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
0
L1
002-13881 **
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
Document Number: 002-05652 Rev.*C
Page 99 of 108
MB9B320M Series
Package Type
Package Code
QFN 64
VNC064
0.10
C
A B
D2
A
D
48
33
33
48
0.10
2X
C
32
32
49
49
0.10
C A B
5
(ND-1)
e
E
E2
17
64
64
17
1
16
16
1
4
INDEXMARK
8
9
e
B
b
L
0.10
0.05
C A B
0.10
2X
C
C
TOP VIEW
SIDE VIEW
BOTTOMVIEW
0.10
C
A
SEATINGPLANE
0.05
C
C
A1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
0.90
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
A
0.00
9.00 BSC
9.00 BSC
0.05
1
4
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL,
D
E
b
THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
0.20 0.25 0.30
6.00 BSC
5
D
2
6.
7.
8
E
2
e
6.00 BSC
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
0.50 BSC
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
R
L
N
0.20 REF
0.40 0.45
0.35
64
16
ND
002-13234 **
PACKAGE OUTLINE, 64 LEAD QFN
9.0X9.0X0.9 MM VNC064 6.0X6.0 MM EPAD (SAWN) Rev*.*
Document Number: 002-05652 Rev.*C
Page 100 of 108
MB9B320M Series
Package Type
Package Code
LQFP 48
LQA048
4
5
D
7
D1
36
36
25
25
37
24
24
37
E1
E
5
7
4
3
6
48
13
13
48
1
1
12
12
2
A-B
5
D
7
e
0.10
C
3
0.20
C A-B D
0.80
C
A-B
D
b
8
2
A
9
A
SEATING
PLANE
c
A'
0.25
A1
10
b
0.80
C
L1
L
SECTION A-A'
DIMENSIONS
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.15
0.09
0.20
0.27
0.20
c
D
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0
0.75
0.70
8
L1
0.50
002-13731 **
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
Document Number: 002-05652 Rev.*C
Page 101 of 108
MB9B320M Series
Package Type
Package Code
QFN 48
VNA048
0.10
C
A
B
D
D2
A
25
36
0.10
2X
C
0.10
C A B
24
37
(ND-1)
e
E
E2
5
13
48
12
1
R
9
INDEX MARK
8
L
0.10
0.05
C
A
B
B
e
b
TOP VIEW
C
4
0.10
2X
C
BOTTOM VIEW
0.10
C
A
SEATING PLANE
C
0.05
A1
9
C
SIDE VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
MIN. NOM. MAX.
0.90
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINALHAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL.THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
A
0.00
0.05
1
D
E
7.00 BSC
7.00 BSC
0.25
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
6. MAX. PACKAGE WARPAGE IS 0.05mm.
0.20
0.30
b
D
5.50 BSC
5.50 BSC
0.50 BSC
0.20 REF
0.40
2
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.
E
e
2
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT
SINK SLUG AS WELL AS THE TERMINALS.
R
L
0.35
0.45
10. JEDEC SPEC IFICATIONNO . REF: N/A
002-15528 **
PACKAGE OUTLINE, 48 LEADQFN
7.0X7.0X0.9 MMVNA048 5.5X5.5 MMEPAD(SAWN) REV**
Document Number: 002-05652 Rev.*C
Page 102 of 108
MB9B320M Series
Package Type
Package Code
FBGA 96
FDG096
A
0.20
2X
C
11
10
9
6
8
7
6
5
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
7
PIN A1
CORNER
6
B
0.20
2X
C
TOP VIEW
BOTTOM VIEW
DETAIL A
0.20
C
C
5
0.08
C
96xφb
SIDE VIEW
DETAIL A
0.05
C
A B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. SOLDER BALL POSITION DESIGNATIO
DIMENSIONS
NOM.
SYMBOL
N PER JEP95, SECTION 3, SPP-020.
MIN.
MAX.
1.30
0.35
3. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A
A1
D
-
-
0.25
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.15
6.00 BSC
E
6.00 BSC
5.00 BSC
5.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
11
96
WHEN THERE IS AN ODD NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
0.30
b
0.20
0.40
eD
eE
SD
SE
0.50 BSC
0.50 BSC
0.00
WHEN THERE IS AN EVEN NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
7.
0.00
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
002-13224 **
PACKAGE OUTLINE, 96 BALL FBGA
6.0X6.0X1.3 MM FDG096 REV**
Document Number: 002-05652 Rev.*C
Page 103 of 108
MB9B320M Series
15.Major Changes
Spansion Publication Number: DS706-00049
Page
Section
Change Results
Revision 1.0
-
-
Preliminary → Data Sheet
Features
A/D Converter (Max 26channels)
Uniqueid
Revised the conversion time:
1.0μs → 0.8μs
Added the "Unique ID".
3
6
7
Product Lineup
Function
Added the "Unique ID".
List Of Pin Functions
List Of Pin Numbers
List Of Pin Functions
Corrected the I/O circuit type.
Corrected the Pin state type.
Corrected the Pin function.
16 to 18
33
39
I/O Circuit Type
Block Diagram
Added the "Type: L".
Corrected the figure.
46
- TIOA: input → input/output
- TIOB: output → input
Revised the value of "TBD".
Electrical Characteristics
1. Absolute Maximum Ratings
2. Recommended Operating Conditions
55
Revised the Condition of "Operating temperature".
57
3. Dc Characteristics
(1) Current Rating
4. Ac Characteristics
(3) Built-In Cr Oscillation Characteristics
(4-2) Operating Conditions Of Main PLL (In The
Case Of Using Built-In High-Speed CR For Input
Clock Of Main PLL)
Revised the value of "TBD".
Added "Flash memory write/erase current".
Revised the Condition.
Revised the footnote.
Revised the value of "TBD".
58, 59
62
63
5. 12-Bit A/D Converter
Electrical Characteristics For The A/D Converter
Deleted "(Preliminary value)".
Revised the conversion time.
Min: 1.0μs → 0.8μs
79
Revised the value of "Compare clock cycle (AVCC ≥ 4.5V)".
Min: 50ns → 40ns
Revised the footnote.
6. 10-Bit D/A Converter
Deleted "(Preliminary value)".
82
87
8. Low-Voltage Detection Characteristics
9. Mainflash Memory Write/Erase Characteristics
Revised the value of "TBD".
Revised the value of "TBD".
Revised the value of "Sector erase time".
- Large Sector Typ: 1.065s → 1.1s
- Small Sector Typ: 0.606s → 0.3s
Revised the value of "Chip erase time".
Typ: 9.11s → 6.8s
88
Deleted "(targeted value)".
Revision 1.1
-
-
Company name and layout design change
Revision 2.0
Features
On-Chip Memories [Flash Memory]
USB Interface [USB Function]
Revised the features of Dual operation Flash memory
2
3
4
Added the size of each endpoint.
Corrected the mode.
High speed mode → Fast mode
Revised the features of 5V tolerant I/O.
Corrected the number of A/D activating compare channels.
3ch. → 2ch.
Multi-Function Serial Interface [I2C]
General-Purpose I/O Port
Multi-Function Timer
Document Number: 002-05652 Rev.*C
Page 104 of 108
MB9B320M Series
Page
Section
Change Results
Corrected the number of A/D activating compare channels.
3ch. → 2ch.
7
Revised Built-in CR .
Product Lineup
Function
High-speed: 4MHz(± 2%) → 4MHz
Low-speed: 100kHz(Typ) → 100kHz
Revised the footnote.
8
List Of Pin Functions
List Of Pin Numbers
21
Corrected the pin number of ZIN1_1.
24
29
31
Corrected the pin number of ADTG_2.
Corrected pin numbers of SIN0_1 and SOT0_1.
Corrected the pin number of DTTI0X_2.
Corrected the I/O circuit figure.
List Of Pin Functions
37
44
47
I/O Circuit Type
TYPE H : GPIO Digital input → GPIO Digital output
Handling Devices
Sub Crystal Oscillator
Added the descriptions.
Corrected the figure.
-A/D Activation Compare: 3ch → 2ch
Block Diagram
Memory Map
Memory Map (2)
49
54
55
Added the explanatory note.
Added the pin function of selected Analog output about type L.
Corrected the footnote.
Sub CR timer→ Low-speed CR tim
Added the note and footnote.
Corrected the value of Analog reference voltage “AVRH”.
Min.: AVss → 2.7
Added notes and footnotes.
Pin Status In Each Cpu State
List Of Pin Status
Electrical Characteristics
2. Recommended Operating Conditions
58
59
3. Dc Characteristics
(1) Current Rating
Added the remarks of Icc.
Added the frequency of main clock crystal oscillator in remarks
4. Ac Characteristics
63
64
66
Added the footnote.
(2) Sub Clock Input Characteristics
(3) Built-In CR Oscillation Characteristics
Built-In High-Speed CR
Added "Frequency stabilization time"
Added notes and footnotes.
Added "Timing until releasing Power-on reset"
Added the timing chart
(6) Power-On Reset Timing
Corrected the title.
UART Timing → CSIO Timing
Corrected the notefoot.
UART → Multi-function serial
Corrected the notefoot.
UART → Multi-function serial
Revised the Condition.
Revised the footnote.
68
(8) Csio Timing
70,72,74
79
(11) I2c Timing
Changed the name of parameter.
•Non Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
Changed the Symbol. Of Zero transition voltage.
V0T → VZT
81
5. 12-Bit A/D Converter
Electrical Characteristics For The A/D Converter
Changed the pin name.
AN00 to AN26 → ANxx
Corrected the value of V0T, VFST, Ts, Tstt, and reference voltage.
Revises footnotes.
Change the figure.
AN00 to AN26 → ANxx
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
V0T → VZT
82
83
Difinition Of 12-Bit A/D Converter Terms
•Revised the remark of IDDA.
D/A operation → D/A 1unit operation
Changed the name of parameter.
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
6. 10-Bit D/A Converter
Electrical Characteristics For The D/A Converter
84
Document Number: 002-05652 Rev.*C
Page 105 of 108
MB9B320M Series
Page
Section
Change Results
Corrected the condition and the value.
Added the note and the footnote.
Added “LVD detection delay time”.
Corrected the condition and the value.
Added “LVD detection delay time”.
Changed the title of Chapter.
8. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
89
90
(2) Interrupt Of Low-Voltage Detection
91
92
9. Flash Memory Write/Erase Characteristics
10. Return Time Low-Power Consumption Mode
Main Flash Memory Write/Erase Characteristics →
Flash Memory Write/Erase Characteristics
Added the Chapter “Return Time from Low-Power Consumption mode”.
Revision 3.0
Features
Usb Interface
I/O Circuit Type
Memory Map
2
Added the description of Pll For USB
Added about +B Input
36, 37
49
Added the summary of Flash Memory Sector and the note
· Memory Map(2)
PIN STATUS IN EACH CPU STAE
· List Of Pin Status
Electrical Characteristics
1. Absolute Maximum Ratings
54
Changed the Pin Status of I-type
· Added the clamp maximum current
· Added about +B Input
56, 57
· Changed the table format
Electrical Characteristics
3. DC Characteristics
(1) Current Rating
· Added Main TIMER mode current
· Moved A/D converter current
· Moved D/A converter current
59-61
66
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions Of Main And USB PLL
(4-2) Operating Conditions Of Main PLL
Electrical Characteristics
4. Ac Characteristics
(7) Csio/Uart Timing
Electrical Characteristics
4. Ac Characteristics
· Added the figure of Main PLL connection and USB PLL connection
· Modified from UART timing to Csio/UART timing
· Changed from Internal Shift Clock Operation to Master mode
· Changed from External Shift Clock Operation to Slave mode
69-76
77
Added Input Pulse Width of Wkupx Pin
(9) External Input Timing
· Added the typical value of Integral nonlinearity, Differential nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Added conversion time at Avcc < 4.5V
Electrical Characteristics
5. 12bit A/D Converter
82
97, 98
Ordering Information
Change to full part number
Note: Please see “Document History” about later revised information.
Document Number: 002-05652 Rev.*C
Page 106 of 108
MB9B320M Series
Document History
Document Title: MB9B320M Series 32-bit ARM® Cortex®-M3, FM3 Microcontroller
Document Number: 002-05652
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-05652.
No change to document contents or format.
**
TOYO
TOYO
09/13/2012
–
*A
5166569
03/08/2016 Updated to Cypress format.
・ Modified RTC description in“Features, Real-Time Clock(RTC)”. Changed starting
count value from 01 to 00. Deleted “second , or day of the week” in the Interrupt
function. (Page 3)
・ Updated Package code and dimensions as follows (Page 8-14, 95-103)
-
-
-
-
-
-
-
-
FPT-48P-M49 -> LQA048
LCC-48P-M73 -> VNA048
FPT-64P-M38 -> LQD064
FPT-64P-M39 -> LQG064
LCC-64P-M24 -> VNC064
FPT-80P-M37 -> LQH080
FPT-80P-M40 -> LQJ080
BGA-96P-M07 -> FDG096
*B
5653470
HTER
03/09/2017
・ Added Notes for JTAG. (Page 32)
・ Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power
Supply rise time(Tr) [ms]” to “Power ramp rate(dV/dt) [mV/us]” and add some
comments. (Page 65)
・ Added the Baud rate spec in “12.4.9 CSIO/UART Timing”.(Page 67-73)
・ Corrected the erroneous descriptions as follows.
-
-
“USB Function” -> “USB Device” (Page 1, 7, 31, 44)
“J-TAG” -> “JTAG” (Page 24)
“Analog port input current” -> “Analog port input leak current” (Page 80)
*C
5787206
YSAT
06/28/2017 Adapted new Cypress logo
Document Number: 002-05652 Rev.*C
Page 107 of 108
MB9B320M Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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Document Number: 002-05652 Rev.*C
June 28, 2017
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