MBM29QM12DH70PCN_技术文档

TM

SPANSION Flash Memory

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20909-1E

PAGE MODE FLASH MEMORY

CMOS

128M (8M× 16) BIT

MBM29QM12DH^-60

■ DESCRIPTION

The MBM29QM12DH is 128 M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M

words of 16 bits each. The device is offered in 56-pin TSOP and 80-ball FBGA package. This device is designed

to be programmed in-system with the standard system 3.0 V Vcc supply. 12.0 V Vpp and 5.0 V Vcc are not

required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.

(Continued)

■ PRODUCT LINE UP

Part No.

MBM29QM12DH60

+0.6 V

–0.3 V

V^CC= 3.0 V

VCCQ = 2.7 V to 3.6 V

VCCQ = 1.65 V to 1.95 V

Max Random Address Access Time (ns)

Max Page Address Access Time (ns)

Max CE Access Time (ns)

60

20

60

20

70

30

70

30

Max OE Access Time (ns)

■ PACKAGES

56-pin plastic TSOP (1)

80-pin plastic FBGA

(FPT-56P-M01)

(BGA-80P-M04)

MBM29QM12DH-60

(Continued)

The device provides truly high performance non-volatile Flash memory solution. The device offers fast page

access times of 20 ns with random access times of 60 ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE),

and output enable (OE) controls. The page size is 8 words.

The dual operation function provides simultaneous operation by dividing the memory space into four banks. The

device can improve overall system performance by allowing a host system to program or erase in one bank,

then immediately and simultaneously read from the other bank with zero latency. This releases the system from

waiting for the completion of program or erase operations.

The device is command set compatible with JEDEC standard E²PROMs. Commands are written to the command

register using standard microprocessor write timings. Register contents serve as input to an internal state-

machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and

data needed for the programming and erase operations. Reading data out of the device is similar to reading

from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the device automatically times the erase pulse widths and

verifies proper cell margins.

Any individual sector is typically erased and verified in 0.5 second. (If already preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been completed,

the device internally resets to the read mode.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector

simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM

programming mechanism of hot electron injection.

2

MBM29QM12DH-60

■ FEATURES

• 0.13 µm Process Technology

• Single 3.0 V read, program and erase

Minimized system level power requirements

• Simultaneous Read/Write operations (Dual Bank)

1

• FlexBank^TM

*

Bank A: 16 Mbit (4 KW × 8 and 32 KW × 31)

Bank B: 48 Mbit (32 KW × 96)

Bank C: 48 Mbit (32 KW × 96)

Bank D: 16 Mbit (4 KW × 8 and 32 KW × 31)

• Enhanced V^I/O(V^CCQ) Feature

Input / Output voltage generated on the device is determined based on the V^I/Olevel

V^I/O(V^CCQ) range : 2.7 V to 3.6 V or 1.65 V to 1.95 V

• High Performance Page Mode

20 ns maximum page access time (60 ns random access time) (3 V V^I/O)

• 8 words Page ( × 16)

• Compatible with JEDEC-standard commands

Uses same software commands as E²PROMs

• Minimum 100,000 program/erase cycles

• Sector erase architecture

Eight 4K words, two hundred fifty-four 32K words, eight 8K words sectors.

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Dual Boot Block

164K words boot block sectors, 8 at the top of the address range and 8 at the bottom of the address range

• HiddenROM region

64wordsforfactoryand64wordsforcustomerofHiddenROM, accessiblethroughanew“HiddenROMEnable”

command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At V^IL, allows protection of “outermost” 2×4K words on both ends of boot sectors, regardless of sector

protection/unprotection status

At VIH, allows removal of boot sector protection

At VACC, increases program performance

• Embedded Erase^TM*²Algorithms

Automatically preprograms and erases the chip or any sector

• Embedded Program^TM*²Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, the device automatically switches itself to low power mode.

• Low V^CCwrite inhibit ≤ 2.5 V

(Continued)

3

MBM29QM12DH-60

(Continued)

• Program Suspend/Resume

Suspends the program operation to allow a read in another byte

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• In accordance with CFI (Common Flash Memory Interface)

• Hardware Reset Pin (RESET)

Hardware method to reset the device for reading array data

• New Sector Protection

Persistent Sector Protection

Password Sector Protection

*1 : FlexBank^TMis a trademark of Fujitsu Limited, Japan.

*2 : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

4

MBM29QM12DH-60

■ PIN ASSIGNMENT

TSOP (1)

(Top View)

RESET

RY/BY

A⁰

WP/ACC

56

1

2

3

4

5

6

7

8

(Marking Side)

WE

55

N.C.

54

A1

A2

A3

A4

A²²

A21

A20

53

52

51

OE

50

A5

N.C.

49

VCC

DQ0

DQ1

DQ2

DQ3

VSSQ

VCCQ

DQ4

DQ5

DQ6

DQ7

VSS

N.C.

A6

A7

A8

A9

A10

A11

A12

CE

48

9

V^SS

DQ15

DQ14

DQ13

DQ12

VSSQ

VCCQ

DQ11

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

47

46

45

44

43

42

41

40

DQ10

DQ9

39

38

DQ8

37

VCC

A19

A18

A17

A16

A15

A14

A13

36

35

34

33

32

31

30

29

(FPT-56P-M01)

(Continued)

5

MBM29QM12DH-60

(Continued)

FBGA

(Top View)

(Marking Side)

A8

N.C. N.C.

A7 B7

N.C. N.C.

B8

L8

N.C. N.C.

L7 M7

N.C. N.C.

M8

C8

D8

E8

F8

G8

H8

J8

K8

A22

N.C.

V

CCQ

VSSQ N.C. N.C.

N.C.

C7

D7

E7

F7

G7

H7

J7

K7

A13

A

12

A

14

A15

A16

DQ15

VSS

N.C.

C6

D6

E6

F6

G6

H6

J6

K6

A9

A

8

A

10

A11

DQ

7

DQ14 DQ13 DQ6

C5

WE RESET

C4 D4

RY/BYWP/ACC A¹⁸

C3 D3 E3

D5

E5

F5

G5

H5

J5

K5

DQ

K4

A

21

A19

DQ

5

DQ12

V

CC

4

E4

F4

G4

H4

J4

A20

DQ

2

DQ10 DQ11 DQ3

F3

G3

H3

J3

K3

DQ

K2

A7

A

17

A

6

A

5

DQ

0

DQ

8

DQ

9

1

A2

N.C. N.C.

A1 B1

N.C. N.C. N.C.

B2

C2

D2

E2

F2

G2

H2

CE

J2

L2

N.C. N.C.

L1 M1

N.C. N.C.

M2

A3

A

4

A

2

A

1

A0

OE

V

SS

C1

D1

E1

F1

G1

H1

J1

K1

VCC

N.C.

V

CCQ

VSSQ N.C.

N.C.

(BGA-80P-M04)

■ PIN DESCRIPTIONS

MBM29QM12DH Pin Configuration Table

A²²to A0

DQ15 to DQ0

CE

Function

Address Inputs

Data Inputs/Outputs

Chip Enable

OE

Output Enable

Write Enable

WE

RESET

WP/ACC

RY/BY

N.C.

Hardware Reset

Hardware Write Protection/ Program Acceleration

Ready/Busy output

Pin Not Connected Internally

Device Ground

VSS

VCC

Device Power Supply

VSSQ

Input & Output Buffer Ground

Input & Output Buffer Power Supply

VCCQ

6

MBM29QM12DH-60

■ BLOCK DIAGRAM

VCC

VSS

Bank A

address

Cell Matrix

16 Mbit

Cell Matrix

48 Mbit

A22 to A0

(Bank A)

(Bank B)

X-Decoder

Bank B Address

State

Control

&

Command

Register

RESET

WE

CE

OE

WP/ACC

DQ15 to DQ0

RY/BY

DQ15

to

DQ0

Status

Control

Bank C Address

X-Decoder

Cell Matrix

16 Mbit

Cell Matrix

48 Mbit

(Bank D)

(Bank C)

Bank D

address

■ LOGIC SYMBOL

23

A²²to A0

16

DQ15 to DQ0

RESET

CE

OE

WE

RY/BY

WP/ACC

7

MBM29QM12DH-60

■ DEVICE BUS OPERATION

MBM29QM12DH User Bus Operations Table

DQ¹⁵to

DQ⁰

WP/

ACC

Operation

CE OE WE A⁰A¹A²A³A⁴A⁵A⁶A⁷A⁹

RESET

Auto-SelectManufacturer

Code*¹

L

H

L

X

L

VID Code

H

X

Auto-Select Device

Code*¹

H

L

H

L

H

X

H

L

H

X

L

VID Code

V^IDCode

H

X

Extended Auto-Select

Device Code*²

Read*³

L

A0

X

A1

X

A2

X

A3

X

A4

X

A5

X

A6

X

A7

X

A9

X

DOUT

High-Z

DIN

Standby

X

H

Output Disable

Write (Program/Erase)

X

A⁰

A1

A2

A3

A4

A5

A6

A7

A9

Enable Sector Group

Protection*^3,*⁴

L

VID

L

X

H

X

L

X

L

VID

X

H

X

H

L

Verify Sector Group

Protection*^3,*⁴

H

X

VID Code

Boot Block Sector Write

Protection*⁶

X

Temporary Sector Group

Unprotection*⁵

X

VID

X

Reset

High-Z

L

Legend: L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See DC Characteristics for voltage levels.

*1 : Manufacturer and device codes may also be accessed via a command register write sequence.

See “MBM29QM12DH Command Definitions Table” in “■ DEVICE BUS OPERATION”.

*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*3 : Refer to section on Sector Protection.

*4 : VCCQ = 2.7 V to 3.6 V for 60 ns

V^CCQ= 1.65 V to 1.95 V for 70 ns.

*5 : Also used for the extended sector group protection.

*6 : Protect “outermost” 2 × 4K words on both ends of the boot block sectors (SA0, SA1, SA268, SA269) .

8

MBM29QM12DH-60

MBM29QM12DH Command Definitions Table

Second

Bus

Write

Cycle

Seventh

Bus

Write

Cycle

Bus

Write

Cy-

First Bus

Write

Cycle

Third Bus Fourth Bus

Sixth Bus

Write

Cycle

Fifth Bus

Write Cycle

Write

Cycle

Read/Write

Cycle

Command

Sequence

cles

Req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

XXXh

Read/Reset

1

3

F0h RA RD

—

555h AAh 2AAh 55h 555h F0h RA

(BA)

RD

Autoselect

3

555h AAh 2AAh 55h

90h

—

555h

555h AAh 2AAh 55h 555h A0h PA

Program

4

6

PD

—

Chip Erase

Sector Erase

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h

Program/Erase

Suspend

1

BA B0h

BA 30h

—

Program/Erase

Resume

Set to Fast

Mode

3

2

555h AAh 2AAh 55h 555h 20h

—

XXXh A0h PA PD

—

Fast Program

4

Reset from Fast

Mode *¹

*

BA 90h XXXh

F0h

Extended

Sector Group

Protection *²

SGA+

WPH

SGA+

WPH

SGA+

WPH

XXXh

4

60h

98h

60h

—

40h

—

SD

—

(BA)

55h

Query

1

3

4

6

—

HiddenROM

Entry

555h AAh 2AAh 55h 555h 88h

HiddenROM

Program *³

(HRA)

PA

555h AAh 2AAh 55h 555h A0h

(HRBA)

PD

—

HiddenROM

Exit *³

555h AAh 2AAh 55h

90h XXXh 00h

—

555h

HiddenROM

Protect *³

RD

(0)

XXXh

555h AAh 2AAh 55h 555h 60h OPBP 68h OPBP 48h

555h AAh 2AAh 55h 555h 38h XX0h PD0

555h AAh 2AAh 55h 555h 38h XX1h PD1

Password

Program

4

—

555h AAh 2AAh 55h 555h 38h XX2h PD2

555h AAh 2AAh 55h 555h 38h XX3h PD3

Password

Unlock

XX2h

—

XX3h

—

7

4

555h AAh 2AAh 55h 555h 28h XX0h PD0 XX1h PD1

PWD

PD2

—

PD3

—

Password

Verify

555h AAh 2AAh 55h 555h C8h PWA

—

(Continued)

9

MBM29QM12DH-60

(Continued)

Bus

Write

Cy-

cles

Req’

d

Second

Seventh

Bus

Write

Cycle

First Bus

Write

Cycle

Third Bus Fourth Bus

Sixth Bus

Write

Cycle

Bus

Write

Cycle

Fifth Bus

Write Cycle

Write

Cycle

Read/Write

Cycle

Command

Sequence

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Password

Mode Locking

Bit Program

RD

(0)

XXXh

6

555h AAh 2AAh 55h 555h 60h

PL

68h

PL

48h

—

Persistent

Protection

Mode Locking

Bit Program

RD

(0)

6

555h AAh 2AAh 55h 555h 60h SPML 68h SPML 48h

SGA+

WP

SGA+

WP

RD

(0)

XXXh

—

PPB Program

PPB Verify

6

4

3

4

555h AAh 2AAh 55h 555h 60h

(BA)

68h

48h

—

SGA+ RD

WP

555h AAh 2AAh 55h

90h

—

555h

(0)

SGA+

WP

RD

(0)

XXXh

—

All PPB Erase

555h AAh 2AAh 55h 555h 60h WP

60h

40h

—

PPB Lock Bit

Set

555h AAh 2AAh 55h 555h 78h

(BA)

—

PPB Lock Bit

Verify

RD

(1)

555h AAh 2AAh 55h

58h

SA

—

555h

DPB Write

DPB Erase

4

555h AAh 2AAh 55h 555h 48h

(BA)

SA

X1h

X0h

—

RD

(0)

DPB Verify

4

555h AAh 2AAh 55h

58h

SA

—

555h

Legend:

RA

PA

= Address of the memory location to be read

= Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA

= Address of the sector to be erased. The combination of A²², A21, A20, A19, A18, A17, A16, A15, A14, A13 and

A12 will uniquely select any sector.

BA

RD

= Bank Address. Address setted by A22, A21, A20 will select Bank A, Bank B, Bank C and Bank D.

= Data read from location RA during read operation.

PD

= Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

= Sector group address to be protected.

= (A⁷, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)

= Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

SGA

WPH

SD

HRA

= Address of the HiddenROM area Word Mode : 000000h to 00007Fh

= Bank Address of the HiddenROM area (A²²= A21 = A20 = VIL)

= Read Data bit. If programmed, DQ0 = 1, if erase, DQ0 = 0

= Read Data bit. If programmed, DQ1 = 1, if erase, DQ1 = 0

= (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0)

HRBA

RD (0)

RD (1)

OPBP

PWA/PWD = Password Address/Password Data

PL

SPML

WP

= (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 1, 0, 1, 0)

= (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 0, 0, 1, 0)

= (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)

10

MBM29QM12DH-60

*1 : This command is valid during Fast Mode.

*2 : This command is valid while RESET = VID.

*3 : This command is valid during HiddenROM mode.

*4 : The data “00h” is also acceptable.

*5 : Command combinations not described in “MBM29QM12DH Command Definitions Table” in “■ DEVICE BUS

OPERATION” are illegal.

Notes : • Address bits A²²to A11 = X = “H” or “L” for all address commands except for

PA, SA, BA, SGA, OPBP, PWA, PL, SPML, WP, WPH.

• Bus operations are defined in “MBM29QM12DH User Bus Operations Table” and “MBM29QM12DH

Command Definitions Table” in “■ DEVICE BUS OPERATION”.

• The system should generate the following address patterns:

Word Mode : 555h or 2AAh to addresses A10 to A0

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

MBM29QM12DH Sector Group Protection Verify Autoselect Codes Table

Type

Manufacture’s Code

Device Code

A²²to A¹²

BA*²

A⁷

VIL

V^IL

A⁶

VIL

A⁵

X

A⁴

X

A³

VIL

A²

VIL

A¹

A⁰

Code (HEX)

04h

VIL

BA*²

X

VIL VIH

227Eh

2220h

X

VIH VIH VIH VIL

VIH VIH VIH VIH

Extended Device Code*³

Sector Group Protection

BA*²

X

2200h

Sector Group

Addresses

V^IL

VIL

VIL VIH VIL

01h*¹

DQ7 - Factory Lock Bit

Extended Device Code

(Indicator Bits)

1 = Locked, 0 = Not Locked

DQ6 - Customer Lock Bit

1 = Locked, 0 = Not Locked

BA*²

VIL

VIL VIH VIH

*1 : Sector Group can be protected by "Sector Group Protection", "Extended Sector Group Protection", and "New

Sector Protection(PPB Protection). Outputs 01h at protected sector group addresses and outputs 00h at

unprotected sector group addresses.

*2 : When V^IDis applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous

operation unable to be executed. Consequently, specifying the bank address is not required. However, the

bank address needs to be indicated when Autoselect mode is read out at command mode, because then it

becomes possible to activate simultaneous operation.

*3 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional

codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these

Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.

Extended Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰

DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ

9

8

7

6

5

4

3

2

1

0

Type

Code

04h

Manufacturer’s Code

Device Code

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

227Eh

2220h

2200h

01h

Extended Device

Code

PPB Protection

PPB Unprotection

00h

11

MBM29QM12DH-60

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

Sector Address Table (Bank A)

Sector Address

Sector Bank Address

A²²A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector Size

(Kwords)

( × 16)

Bank

Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

006000h to 006FFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

X

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank A

12

MBM29QM12DH-60

Sector Address Table (Bank B)

Sector Address

Bank Address

A²²A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector

( × 16)

Size

Bank

Sector

Address Range

(Kwords)

32

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1FFFFFh

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

(Continued)

Bank B

13

MBM29QM12DH-60

Sector Address

Bank Address

A²²A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector

Size

( × 16)

Bank

Sector

Address Range

(Kwords)

32

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

250000h to 257FFFh

258000h to 25FFFFh

260000h to 267FFFh

268000h to 26FFFFh

270000h to 277FFFh

278000h to 27FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

2A0000h to 2A7FFFh

2A8000h to 2AFFFFh

2B0000h to 2B7FFFh

2B8000h to 2BFFFFh

2C0000h to 2C7FFFh

2C8000h to 2CFFFFh

2D0000h to 2D7FFFh

2D8000h to 2DFFFFh

2E0000h to 2E7FFFh

2E8000h to 2EFFFFh

2F0000h to 2F7FFFh

2F8000h to 2FFFFFh

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

350000h to 357FFFh

358000h to 35FFFFh

360000h to 367FFFh

368000h to 36FFFFh

(Continued)

SA95

SA96

SA97

SA98

Bank B

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

14

MBM29QM12DH-60

(Continued)

Sector Address

Bank Address

A²²A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector

(× 16)

Size

Bank

Sector

Address Range

(Kwords)

32

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

370000h to 377FFFh

378000h to 37FFFFh

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

3A0000h to 3A7FFFh

3A8000h to 3AFFFFh

3B0000h to 3B7FFFh

3B8000h to 3BFFFFh

3C0000h to 3C7FFFh

3C8000h to 3CFFFFh

3D0000h to 3D7FFFh

3D8000h to 3DFFFFh

3E0000h to 3E7FFFh

3E8000h to 3EFFFFh

3F0000h to 3F7FFFh

3F8000h to 3FFFFFh

32

Bank B

32

15

MBM29QM12DH-60

Sector Address Table (Bank C)

Sector Address

Sector Bank Address

A²²A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector Size

(Kwords)

(× 16)

Bank

Address Range

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

32

400000h to 407FFFh

408000h to 40FFFFh

410000h to 417FFFh

418000h to 41FFFFh

420000h to 427FFFh

428000h to 42FFFFh

430000h to 437FFFh

438000h to 43FFFFh

440000h to 447FFFh

448000h to 44FFFFh

450000h to 457FFFh

458000h to 45FFFFh

460000h to 467FFFh

468000h to 46FFFFh

470000h to 477FFFh

478000h to 47FFFFh

480000h to 487FFFh

488000h to 48FFFFh

490000h to 497FFFh

498000h to 49FFFFh

4A0000h to 4A7FFFh

4A8000h to 4AFFFFh

4B0000h to 4B7FFFh

4B8000h to 4BFFFFh

4C0000h to 4C7FFFh

4C8000h to 4CFFFFh

4D0000h to 4D7FFFh

4D8000h to 4DFFFFh

4E0000h to 4E7FFFh

4E8000h to 4EFFFFh

4F0000h to 4F7FFFh

4F8000h to 4FFFFFh

500000h to 507FFFh

508000h to 50FFFFh

510000h to 517FFFh

518000h to 51FFFFh

520000h to 527FFFh

528000h to 52FFFFh

530000h to 537FFFh

(Continued)

Bank C

16

MBM29QM12DH-60

Sector Address

Sector Bank Address

A²²A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector Size

(Kwords)

(× 16)

Bank

Address Range

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

32

538000h to 53FFFFh

540000h to 547FFFh

548000h to 54FFFFh

550000h to 557FFFh

558000h to 55FFFFh

560000h to 567FFFh

568000h to 56FFFFh

570000h to 577FFFh

578000h to 57FFFFh

580000h to 587FFFh

588000h to 58FFFFh

590000h to 597FFFh

598000h to 59FFFFh

5A0000h to 5A7FFFh

5A8000h to 5AFFFFh

5B0000h to 5B7FFFh

5B8000h to 5BFFFFh

5C0000h to 5C7FFFh

5C8000h to 5CFFFFh

5D0000h to 5D7FFFh

5D8000h to 5DFFFFh

5E0000h to 5E7FFFh

5E8000h to 5EFFFFh

5F0000h to 5F7FFFh

5F8000h to 5FFFFFh

600000h to 607FFFh

608000h to 60FFFFh

610000h to 617FFFh

618000h to 61FFFFh

620000h to 627FFFh

628000h to 62FFFFh

630000h to 637FFFh

638000h to 63FFFFh

640000h to 647FFFh

648000h to 64FFFFh

650000h to 657FFFh

658000h to 65FFFFh

660000h to 667FFFh

668000h to 66FFFFh

(Continued)

Bank C

17

MBM29QM12DH-60

(Continued)

Sector Address

Bank Address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector

Size

(× 16)

Bank

Sector

Address Range

A²²

1

A²¹

1

(Kwords)

32

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

670000h to 677FFFh

678000h to 67FFFFh

680000h to 687FFFh

688000h to 68FFFFh

690000h to 697FFFh

698000h to 69FFFFh

6A0000h to 6A7FFFh

6A8000h to 6AFFFFh

6B0000h to 6B7FFFh

6B8000h to 6BFFFFh

6C0000h to 6C7FFFh

6C8000h to 6CFFFFh

6D0000h to 6D7FFFh

6D8000h to 6DFFFFh

6E0000h to 6E7FFFh

6E8000h to 6EFFFFh

6F0000h to 6F7FFFh

6F8000h to 6FFFFFh

32

Bank C

32

18

MBM29QM12DH-60

Sector Address Table (Bank D)

Sector Address

Sector Bank Address

A²²A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

Sector Size

(Kwords)

(× 16)

Bank

Address Range

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

32

4

700000h to 707FFFh

708000h to 70FFFFh

710000h to 717FFFh

718000h to 71FFFFh

720000h to 727FFFh

728000h to 72FFFFh

730000h to 737FFFh

738000h to 73FFFFh

740000h to 747FFFh

748000h to 74FFFFh

750000h to 757FFFh

758000h to 75FFFFh

760000h to 767FFFh

768000h to 76FFFFh

770000h to 777FFFh

778000h to 77FFFFh

780000h to 787FFFh

788000h to 78FFFFh

790000h to 797FFFh

798000h to 79FFFFh

7A0000h to 7A7FFFh

7A8000h to 7AFFFFh

7B0000h to 7B7FFFh

7B8000h to 7BFFFFh

7C0000h to 7C7FFFh

7C8000h to 7CFFFFh

7D0000h to 7D7FFFh

7D8000h to 7DFFFFh

7E0000h to 7E7FFFh

7E8000h to 7EFFFFh

7F0000h to 7F7FFFh

7F8000h to 7F8FFFh

7F9000h to 7F9FFFh

7FA000h to 7FAFFFh

7FB000h to 7FBFFFh

7FC000h to 7FCFFFh

7FD000h to 7FDFFFh

7FE000h to 7FEFFFh

7FF000h to 7FFFFFh

Bank D

0

1

0

1

0

1

0

1

0

1

0

1

4

19

MBM29QM12DH-60

Sector Group Address Table

Sector Group A²²

A²¹

0

1

A²⁰

0

1

0

A¹⁹

0

1

0

1

0

A¹⁸

0

1

0

1

0

1

0

1

0

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

SGA8

0

1

X

SA8

SGA9

1

0

SA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

1

SA10

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

SA71 to SA74

SA75 to SA78

(Continued)

20

MBM29QM12DH-60

Sector Group A²²

A²¹

1

0

A²⁰

0

1

0

1

A¹⁹

0

1

0

1

0

1

0

A¹⁸

1

0

1

0

1

0

1

0

1

0

1

0

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

X

A¹⁵

X

A¹⁴

X

A¹³

X

A¹²

X

Sectors

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

SGA39

SGA40

SGA41

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

SGA48

SGA49

SGA50

SGA51

0

1

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

SA131 to SA134

SA135 to SA138

SA139 to SA142

SA143 to SA146

SA147 to SA150

SA151 to SA154

SA155 to SA158

SA159 to SA162

SA163 to SA166

SA167 to SA170

SA171 to SA174

(Continued)

21

MBM29QM12DH-60

(Continued)

Sector Group A²²

A²¹

0

1

A²⁰

1

0

1

A¹⁹

0

1

0

1

0

1

A¹⁸

1

0

1

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

X

0

A¹⁵

X

0

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

Sectors

SA175 to SA178

SA179 to SA182

SA183 to SA186

SA187 to SA190

SA191 to SA194

SA195 to SA198

SA199 to SA202

SA203 to SA206

SA207 to SA210

SA211 to SA214

SA215 to SA218

SA219 to SA222

SA223 to SA226

SA227 to SA230

SA231 to SA234

SA235 to SA238

SA239 to SA242

SA243 to SA246

SA247 to SA250

SA251 to SA254

SA255 to SA258

SA259

SGA52

SGA53

SGA54

SGA55

SGA56

SGA57

SGA58

SGA59

SGA60

SGA61

SGA62

SGA63

SGA64

SGA65

SGA66

SGA67

SGA68

SGA69

SGA70

SGA71

SGA72

SGA73

SGA74

SGA75

SGA76

SGA77

SGA78

SGA79

SGA80

SGA81

SGA82

SGA83

1

0

1

SA260

1

0

SA261

1

SA262

1

0

1

SA263

1

0

1

0

SA264

1

0

1

SA265

1

0

SA266

1

0

1

SA267

1

0

SA268

1

SA269

22

MBM29QM12DH-60

Common Flash Memory Interface Code Table

Description

A⁶to A⁰DQ¹⁵to DQ⁰

DQ¹⁵to DQ⁰

Description

A⁶to A⁰

10h

11h

12h

0051h

0052h

0059h

39h

3Ah

3Bh

3Ch

0000h

Query-unique ASCII string “QRY”

Erase Block Region 4 Information

Primary OEM Command Set

02h: AMD/FJ standard type

13h

14h

0002h

0000h

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

Address for Primary

Extended Table

15h

16h

0040h

0000h

Major version number, ASCII

Minor version number, ASCII

43h

44h

0031h

0033h

Alternate OEM Command Set

(00h = not applicable)

17h

18h

0000h

Address for Alternate OEM

Extended Table

19h

1Ah

0000h

Address Sensitive Unlock

Ch = Required and 0.13 µm

technology

Dh = Not Required and 0.13 µm

technology

45h

000Ch

V^CCMin voltage (write/erase)

DQ⁷to DQ4: 1 V, DQ3 to DQ0: 100 mV

1Bh

1Ch

0027h

0036h

V^CCMax voltage (write/erase)

DQ⁷to DQ4: 1 V, DQ3 to DQ0: 100 mV

Erase Suspend

46h

47h

0002h

0001h

02h = To Read & Write

V^PPMin voltage

V^PPMax voltage

1Dh

1Eh

0000h

Sector Protection

00h = Not Supported

X = Number of sectors in per group

Typical timeout per single byte/word

write 2^Nµs

1Fh

20h

21h

22h

23h

24h

25h

0004h

0000h

0009h

0000h

0005h

0000h

0004h

Sector Temporary Unprotection

01h = Supported

Typical timeout for Min size buffer

write 2^Nµs

48h

49h

0001h

0007h

Sector Protection Algorithm

Typical timeout per individual block

erase 2^Nms

Typical timeout for full chip erase 2^N

Simultaneous Operation

00h = Not Supported,

X = Total number of sectors in all

Banks except Bank A

4Ah

00E7h

ms

Max timeout for byte/word write 2^N

times typical

Max timeout for buffer write 2^Ntimes

Burst Mode Type

00h = Not Supported

4Bh

4Ch

0000h

0002h

Page Mode Type

00h = Not Supported

typical

Max timeout per individual block

erase 2^Ntimes typical

Max timeout for full chip erase 2^N

times typical

Device Size = 2^Nbyte

V^ACC(Acceleration) Supply Minimum

00h = Not Supported,

DQ⁷to DQ4: 1 V, DQ3 to DQ0: 100 mV

4Dh

4Eh

0085h

0095h

26h

27h

0000h

0018h

V^ACC(Acceleration) Supply Maximum

00h = Not Supported,

DQ⁷to DQ4: 1 V, DQ3 to DQ0: 100 mV

Flash Device Interface description

01h : × 16

28h

29h

0001h

0000h

Boot Type

4Fh

50h

0001h

Max number of byte in

multi-byte write = 2^N

2Ah

2Bh

0000h

Program Suspend

01h = Supported

Number of Erase Block

Regions within device

Bank Organization

57h

58h

59h

5Ah

5Bh

0004h

0027h

0060h

0027h

2Ch

0003h

Bank A Region Information

Bank B Region Information

Bank C Region Information

Bank D Region Information

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

Erase Block Region 2 Information

Erase Block Region 3 Information

31h

32h

33h

34h

00FDh

0000h

0001h

35h

36h

37h

38h

0007h

0000h

0020h

0000h

23

MBM29QM12DH-60

■ FUNCTIONAL DESCRIPTION

Simultaneous Operation

The device features functions that enable reading of data from one memory bank while a program or erase

operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features

(read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank

address (A²², A21, A20) with zero latency. The device consists of the following four banks :

Bank A : 8 × 4 KW and 31 × 32 KW; Bank B : 96 × 32 KW; Bank C : 96 × 32 KW; Bank D : 8 × 4 KW and 31 × 32 KW.

The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks,

and Bank 2, a bank consisting of the three remaining banks. (See “FlexBank^TMArchitecture Table” in “■ FUNC-

TIONAL DESCRIPTION”.) This is what we call a “FlexBank”, for example, the rest of banks B, C and D to let

the system read while Bank A is in the process of program (or erase) operation. However, the different types of

operations for the three banks are impossible, e.g. Bank A writing, Bank B erasing, and Bank C reading out.

With this “FlexBank”, as described in “Example of Virtual Banks Combination Table” in “■ FUNCTIONAL DE-

SCRIPTION”, the system gets to select from four combinations of data volume for Bank 1 and Bank 2, which

works well to meet the system requirement. The simultaneous operation cannot execute multi-function mode in

the same bank. “Simultaneous Operation Table” in “■ FUNCTIONAL DESCRIPTION” shows the possible com-

binations for simultaneous operation. (Refer to “Bank-to-Bank Read/Write Timing Diagram” in “■ TIMING DIA-

GRAM”.)

FlexBank^TMArchitecture Table

Bank 1

Combination

Bank 2

Combination

Bank

Splits

Volume

16 Mbit

48 Mbit

16 Mbit

Volume

112 Mbit

80 Mbit

112 Mbit

1

2

3

4

Bank A

Bank B

Bank C

Bank D

Remainder (Bank B, C, D)

Remainder (Bank A, C, D)

Remainder (Bank A, B, D)

Remainder (Bank A, B, C)

Example of Virtual Banks Combination Table

Bank 1

Bank 2

Bank

Splits

Volume Combination

Sector Size

Volume Combination

Sector Size

Bank B

+

Bank C

+

8 × 4 Kwords

+

31 × 32 Kwords

8 × 4 Kwords

+

223 × 32 Kwords

112

Mbits

1

2

3

4

16 Mbit

32 Mbit

48 Mbit

64 Mbit

Bank A

Bank D

Bank A

+

Bank D

16 × 4 Kwords

+

62 × 32 Kwords

Bank B

+

Bank C

96

Mbits

192 × 32 Kwords

Bank A

+

Bank C

+

16 × 4 Kwords

+

158 × 32 Kwords

80

Mbits

Bank B

96 × 32 Kwords

Bank D

Bank A

+

Bank B

8 × 4 Kwords

+

127 × 32 Kwords

Bank C

+

Bank D

8 × 4 Kwords

+

127 × 32 Kwords

64

Mbits

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which

a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,

neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)

Meanwhile the system would get to read from either Bank C or Bank D.

24

MBM29QM12DH-60

Simultaneous Operation Table

Bank 1 Status

Read mode

Case

Bank 2 Status

Read mode

1

2

3

4

5

6

7

Read mode

Autoselect mode

Program mode

Erase mode

Read mode

Autoselect mode

Program mode

Erase mode

Read mode

Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank

consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the

Banks.

Read Mode

The device has two control functions which are required in order to obtain data at the outputs. CE is the power

control and should be used for a device selection. OE is the output control and should be used to gate data to

the output pins.

Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access

time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable

access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses

have been stable for at least tACC − tOE time) . When reading out data without changing addresses after power-

up, it is necessary to input hardware reset or to change CE pin from “H” or “L”

Page Mode Read

The device is capable of fast page mode read. This mode provides faster read access speed by sequential

access within a page. The Page size of the device is 8 words, within the appropriate Page being selected by the

higher address bits A²²to A3 and the LSB bits A2 to A0 determining the specific word within that page. This is

an asynchronous operation with the microprocessor supplying the specific word location.

The random or initial page access is equal to t^ACCand subsequent page read access (as long as the locations

specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device

and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast

page mode accesses are obtained by keeping A22 to A3 constant and changing A2 to A0 within that page.

Standby Mode

There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and

the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET input held at VCC ± 0.3 V. Under

this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active

current (ICC2) is required even if CE = “H”. The device can be read with standard access time (tCE) from either of

these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE

= “H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high,

the device requires tRH as a wake-up time for output to be valid for read access.

During standby mode, the output is in the high impedance state, regardless of OE input.

25

MBM29QM12DH-60

Automatic Sleep Mode

Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in

applications such as handy terminal, which requires low power consumption.

To activate this mode, the device automatically switches itself to low power mode when the device addresses

remain stable during access time of 150 ns. It is not necessary to control CE, WE and OE in this mode. In this

mode the current consumed is typically 1 µA (CMOS Level) .

During simultaneous operation, V^CCactive current (ICC2) is required.

Since the data are latched during this mode, the data are continuously read out. When the addresses are

changed, the mode is automatically canceled and the device reads the data for changed addresses.

Output Disable

With the OE input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The Autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.It is intended

for use by programming equipment for the purpose of automatically matching the device to be programmed with

itscorrespondingprogrammingalgorithm. Thismodeisfunctionalovertheentiretemperaturerangeofthedevice.

To activate this mode, the programming equipment must force V^IDon address pin A9. Three identifier bytes may

then be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A7,

A6, A5, A4, A3, A2, A1 and A0. (See “MBM29QM12DH User Bus Operations Table” and “MBM29QM12DH Com-

mand Definitions Table” in “■ DEVICE BUS OPERATION”.)

The manufacturer and device codes may also be read via the command register, for instances when the device

is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is

illustrated in “MBM29QM12DH Command Definitions Table” in “■ DEVICE BUS OPERATION”. (Refer to Au-

toselect Command section.)

In the command Autoselect mode, the bank addresses BA;(A²², A21, A20) must point to a specific bank during

the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while

array data can be read from the other bank.

In WORD mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle

at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended

Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes

at addresses of 0Eh and 0Fh. (Refer to “MBM29QM12DH Sector Group Protection Verify Autoselect Codes

Table” and “Extended Autoselect Code Table” in “■ DEVICE BUS OPERATION” )

In the case of applying V^IDon A9, since both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation

cannot be executed.

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as input to the internal state machine. The state machine output dictates the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

fallingedgeofWE or CE, whicheverhappens later, whiledataislatchedontherisingedgeof WEor CE, whichever

happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Accelerated Program Operation

The device offers accelerated program operation which enables the programming in high speed. If the system

asserts V^ACCto the WP/ACC pin, the device automatically enters the acceleration mode and the time required

26

MBM29QM12DH-60

for program operation will reduce to about 60%. This function is primarily intended to allow high speed program,

so caution is needed as the sector group will temporarily be unprotected.

The system would use a fast program command sequence when programming during acceleration mode.

Set command to fast mode and reset command from fast mode are not necessary. When the device enters the

acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the WP/ACC pin returns the device to normal operation. Do not remove V^ACCfrom WP/

ACC pin while programming. See “Accelerated Program Timing Diagram” in “■ TIMING DIAGRAM”.

RESET

Hardware Reset

The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to

be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process

of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after

the RESET pin is driven low. Furthermore, once the RESET pin goes high the device requires an additional “tRH”

before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the

duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program

or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal

should be ignored during the RESET pulse. See “RESET, RY/BY Timing Diagram” in “■ TIMING DIAGRAM” for

the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality.

Boot Block Sector Protection

The write protection function provides a hardware method of protecting certain boot sectors without using V^ID.

This function is one of two provided by the WP/ACC pin.

If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two

outermost 8K bytes on both ends of boot sectors (SA0, SA1, SA268, SA269) independently of whether those

sectors are protected or unprotected using the method described in “Sector Group Protection”.

If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte on both

ends of boot sectors ware last set to be protected or unprotected. Sector group protection or unprotection for

these four sectors depends on whether they ware last protected or unprotected using the method described in

“Sector Group Protection”.

HiddenROM Region

The HiddenROM feature provides a Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the HiddenROM region is protected, any further

modification of that region becomes impossible. This ensures the security of the ESN once the product is shipped

to the field. ONLY Program is possible in this area until it is protected. Once it is protected, it is impossible to

unprotect, so please use this with caution.

HiddenROM area is 128 words (64 words for factory and 64 words for customer) in length and is stored at the

same address of the "outermost" 4 Kwords boot sector. The device occupies the address of the 000000h to

00007Fh. After the system has written the Enter HiddenROM command sequence, the system may read the

HiddenROM region by using the addresses normally occupied by the boot sector (particular area of SA0). That

is, the device sends all commands that would normally be sent to the boot sector to the HiddenROM region.

This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until

power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending

commands to the boot sector.

HiddenROM area is devided into two regions, which are Factory Locked area and Customer Locked area. The

Factory Locked area is 64 words (address: 000000h to 00003Fh) that is programmed and locked at Fujitsu. The

Customer Locked area is also 64 words (address: 000040h to 00007Fh) that is programmed and locked at user.

The Factory indicator Bit (DQ⁷) is used to indicate whether or not the Factory Locked area is locked when shipped

from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Locked area

is locked. The Factory Locked area can be programmed and protected at Fujitsu ONLY and is always protected

27

MBM29QM12DH-60

when shipped from the factory regardless of the conditon whether or not this area is programmed. Therefore

this area has the Factory Indicator Bit (DQ⁷) permanently set to a "1". The Factory Locked area cannot be

modified in any way. The Customer Locked area is shipped unprotected, allowing users to utilize that area in

any manner they choose. The Customer Indicator Bit set to "0". Once the Customer Locked area is protected,

the Customer Indicator Bit will be permanently set to "1".

(3) Extended Sector Group Protection [Software Protection]

In addition to normal sector group protection, the device has Extended Sector Group Protection as extended

function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command

sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins.

The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection

requires VID on RESET pin. With this condition the operation is initiated by writing the set-up command (60h) in

the command register. Then the sector group addresses pins (A22, A21, A20, A19, A18, A17, A16, A15, A14, A13 and

A12) and (A7, A6, A5, A4, A3, A2, A1, A0) = (0, 0, 0, 0, 0, 0, 1, 0) should be set to the sector group to be protected

(setting VIL for the other addresses pins is recommended) , and an extended sector group protection command

(60h) should be written. A sector group is typically protected in 250 µs. To verify programming of the protection

circuitry, the sector group addresses pins (A²², A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A7, A6, A5,

A4, A3, A2, A1, A0) = (0, 0, 0, 0, 0, 0, 1, 0) should be set a command (40h) should be written. Following the

command write, a logical “1” at device output DQ0 will produce a protected sector in the read operation. If the

output is logical “0”, write the extended sector group protection command (60h) again. To terminate the operation,

it is necessary to set RESET pin to VIH. (Refer to “Extended Sector Gropup Protection Timing Diagram” in

“■ TIMING DIAGRAM” and “Extended Sector Group Protection Algorithm” in “■ FLOW CHART”.)

If Persistent Protection Bit Lock is set to "1", this mode is disabled.

(4) New Sector Protection [Software Protection]

A command sector protection method that replaces the old V^IDcontrolled protection method in future. However

MBM29QM12DH support both VID protection and Persistent Sector Protection. Both Protect supported as a shift

period.

The persistent Sector Protection and the old VID controlled protection can go back each other until Persistent

Protection Lock Bit is settled.

a) Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address

tables for specific sector protection groupings). All 4 K words boot-block sectors have individual sector Persistent

ProtectionBits(PPBs)forgreaterflexibility. EachPPBisindividuallymodifiablethroughthePPBWriteCommand.

Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All

PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of

the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential

of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure.

b) Dynamic Protection Bit (DPB)

A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DPBs

is “0”. Each DPB is individually modifiable through the DPB Write Command.

When the parts are first shipped, the PPBs are cleared, the DPBs are cleared, and PPB Lock is defaulted to

power up in the cleared state - meaning the PPBs are changeable.

When the device is first powered on the DPBs power up cleared (sectors not protected). The Protection State

for each sector is determined by the logical OR of the PPB and the DPB related to that sector. For the sectors

that have the PPBs cleared, the DPBs control whether or not the sector is protected or unprotected. By issuing

the DPB Write/Erase command sequences, the DPBs will be set or cleared, thus placing each sector in the

protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called

dynamicstatesbecauseitisveryeasytoswitchbackandforthbetweentheprotectedandunprotectedconditions.

This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal

of protection when changes are needed. The DPBs maybe set or cleared as often as needed.

28

MBM29QM12DH-60

PPB vs DPB

The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across

power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared

as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100

erase cycles.

The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings,

the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-

Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB

Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed

e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PBB

Lock to disable any further changes to the PBBs during system operation.

The WP/ACC write protect pin adds a final level of hardware protection to the two outermost 4 Kwords sectors.

When this pin is low it is not possible to change the contents of these two sectors. These sectors generally hold

system boot code. So, the WP/ACC pin can prevent any changes to the boot code that could override the choices

made while setting up sector protection during system initialization.

It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state.

The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DPB

Write command sequence is all that is necessary. The DPB write/erase command for the dynamic sectors switch

the DPBs to signify protected and unprotected, respectively. If there is a need to change the status of the

persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either

putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the

desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again.

Note: To achieve the best protection, it’s recommended to execute the PPB lock bit set command early in the

boot code, and protect the boot code by holding WP/ACC = VIL.

DPB

PPB

PPB Lock

Sector State

0

1

0

1

0

1

0

Unprotected—PPB and DPB are changeable

Protected—PPB and DPB are changeable

Unprotected—PPB is not changeable, DPB is

changeable

0

1

0

1

0

1

Protected—PPB is not changeable, DPB is changeable

The above table contains all possible combinations of the DPB, PPB, and PPB lock relating to the status of the

sector.

In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be

removed until the next power cycle clears the PBB lock. If the PPB is cleared, the sector can be dynamically

locked or unlocked. The DPB then controls whether or not the sector is protected or unprotected.

If the user attempts to program or erase a protected sector, the device ignores the command and returns to read

mode. A program command to a protected sector enables status polling for approximately 1 µs before the device

returns to read mode without having modified the contents of the protected sector. An erase command to a

protected sector enables status polling for approximately 50 µs after which the device returns to read mode

without having erased the protected sector.

The programming of the DPB, PPB, and PPB lock for a given sector can be verified by writing a DPB/PPB lock

verify command to the device.

29

MBM29QM12DH-60

–DPB Status

The programming of the DPB for a given sector can be verified by writing a DPB status verify command to the

device.

–PPB Status

The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the

device.

–PPB Lock Bit Status

The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify

command to the device.

c) Persistent Protection Bit Lock (PPB Lock)

• PPB Locked

• PPB Locked with Password

A highly sophisticated protection method that requires a password before changes to certain sectors or sector

groups are permitted.

All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the

Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile

bits that define which sector protection method will be used. If the customer decides to continue using the

Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will

permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the

password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate

only using password sector protection.

It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password

Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods

once a locking bit has been set. It is important that one mode is explicitly selected when the device is first

programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program

or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default

Persistent Sector Protection Mode into the Password Protection Mode.

The WP/ACC Hardware Protection feature is always available, independent of the software managed protection

method chosen.

A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.

There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is

no command sequence to unlock the PPB Lock.

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking

Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates the device is in Password

Protection Mode, the PPB Lock Bit is also set after a hardware reset (RESET asserted) or a power-up reset.

The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock

command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector

PPBs modifications. Asserting RESET, taking the device through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit back to a “1”.

If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command.

Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password

Unlock command is ignored in Persistent Sector Protection Mode.

30

MBM29QM12DH-60

-Password and Password Mode Locking Bit

In order to select the Password sector protection scheme, the customer must first program the password. Fujitsu

recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the

particular flash device. Each ESN is different for every flash device; therefore each password should be different

for every flash device. While programming in the password region, the customer may perform Password Verify

operations.

Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This

operation achieves two objectives:

(1) It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse

this function.

(2) It also disables all further commands to the password region. All program, and read operations are ignored.

Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The

user must be sure that the Password Protection method is desired when setting the Password Mode Locking

Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit

is set. Due to the fact that read operations are disabled, there is no means to verify what the password is

afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the

PPB Lock bit.

The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is

programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no

changes to the protection scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory space and is accessible through the use of the Password

Program and Verify commands (see “Password Verify Command”). The password function works in conjunction

with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the

contents of the password on the pins of the device.

-Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the

device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents

programming of the password protection mode locking bit. This guarantees that a hacker could not place the

device in password protection mode.

(5) Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sectors of the device in order to change data.

The Sector Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode,

formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once

the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again.

While PPB Lock is set, this device cannot enter the Temporary Sector Unprotection mode.

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MBM29QM12DH-60

■ COMMAND DEFINITION

Device operations are selected by writing specific address and data sequences into the command register. Some

commands require Bank Address (BA) input. When command sequences are input into a bank reading, the

commands have priority over the reading. “MBM29QM12DH Command Definitions Table” in “■ DEVICE BUS

OPERATION” shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase

Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program

Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress.

Moreover, Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please

note that commands are always written at DQ⁷to DQ0 and DQ15 to DQ8 bits are ignored. Writing incorrect address

and data values or writing them in the improper sequence will take the device into unknow state.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-

processor read cycles retrieve array data from the memory. The device remains enabled for reads until the

command register contents are altered.

The device will automatically power-up in the Read/Reset state. In this case a command sequence is not required

in order to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs during the power transition. Refer to AC Read Char-

acteristics and Timing Diagram for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,

manufacture and device codes must be accessible while the device resides in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a higher voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write

cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device

codes can be read from the bank, and actual data from the memory cell can be read from another bank. The

higher order address (A²², A21, A20) required for reading out the manufacture and device codes demands the

bank address (BA) set at the third write cycle.

Following the command write, in WORD mode, a read cycle from address (BA) 00h returns the manufacturer’s

code (Fujitsu = 04h) . And a read cycle at address (BA) 01h outputs device code. When 227Eh was output, this

indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may

continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Notice

that the above applies to WORD mode. (Refer to “MBM29QM12DH Sector Group Protection Verify Autoselect

Codes Table” and “Extended Autoselect Code Table” in “■ DEVICE BUS OPERATION” )

The sector state (PPB protection or PPB unprotection) will be informed by address (BA) XX02h for × 16 . Scanning

the sector group addresses (A²², A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12) while(A7, A6, A5, A4, A3, A2,

A1,A0) = (0, 0, 0, 0, 0, 0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The

programming verification should be performed by verifying sector group protection on the protected sector. (See

“MBM29QM12DHUserBusOperationsTable”and“MBM29QM12DHCommandDefinitionsTable”in“■DEVICE

BUS OPERATION”.)

The manufacture and device codes can be read from the selected bank. To read the manufacture and device

codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command

sequence into the register. Autoselect command should then be written into the bank to be read.

If the software (program code) for Autoselect command is stored in the Flash memory, the device and manu-

facture codes should be read from the other bank, which does not contain the software.

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MBM29QM12DH-60

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To

execute the Autoselect command during the operation, Read/Reset command sequence must be written before

the Autoselect command.

Word Programming Command

The device is programmed on a word-by-word basis. Programming is a four bus cycle operation. There are two

“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are

latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the rising edge of

CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts programming.

Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide

further controls or timings. The device will automatically provide adequate internally generated program pulses

and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit)

or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

The automatic programming operation is completed when the data on DQ⁷is equivalent to data written to this

bit at which time the device returns to the read mode and addresses are no longer latched (see “Hardware

Sequence Flags Table” in “■ COMMAND DEFINITION”). Therefore, the device requires that a valid address to

the device be supplied by the system in this particular instance. Hence, Data Polling must be performed at the

memory location which is being programmed.

If hardware reset occurs during the programming operation, the data being written is not guaranteed.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert from “0”s to “1”s.

“Embedded Erase^TMAlgorithm” in “■FLOW CHART” illustrates the Embedded Program^TMAlgorithm using typical

command strings and bus operations.

Program Suspend/Resume Command

The Program Suspend command allows the system to interrupt a program operation so that data can be read

from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation

immediately suspends the programming. The Program Suspend command may also be issued during a pro-

gramming operation while an erase is suspended. The bank addresses of sector being programmed should be

set when writing the Program Suspend command.

When the Program Suspend command is written during a programming process, the device halts the program

operation within 1 µs and updates the status bits.

After the program operation has been suspended, the system can read data from any address. The data at

program-suspended address is not valid. Normal read timing and command definitions apply.

After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses

of sectors being suspended should be set when writing the Program Resume command. The system can

determine the status of the program operation using the DQ⁷or DQ6 status bits, just as in the standard program

operation. See “Write Operation Status” for more information.

The system may also write the Autoselect command sequence when the device in the Program Suspend mode.

The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are

not stored in the memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information.

The system must write the Program Resume command (address bits are “Bank Address”) to exit from the

Program Suspend mode and continue the programming operation. Further writes of the Resume command are

ignored. Another Program Suspend command can be written after the device has resumed programming.

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MBM29QM12DH-60

Chip Erase Command

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence, the device will automatically program and verify the entire memory for an all-

zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) or

RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence, and terminates when the data on DQ7 is “1” (see Write Operation Status section), at which time the

device returns to the read mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

“Embedded Erase^TMAlgorithm” in “■ FLOW CHART” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

Sector Erase Command

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever

happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE, whichever happens

first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation

begins.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29QM12DH Com-

mand Definitions Table” in “■ DEVICE BUS OPERATION”. This sequence is followed by writes of the Sector

Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must

be less than “t^TOW”. Otherwise, that command will not be accepted and erasure will not start. It is recommended

that processor interrupts be disabled during this time to guarantee such a condition. The interrupts can reoccur

after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE,

whichever happens first, will initiate the execution of the Sector Erase command (s) . If another falling edge of

CE or WE, whichever happens first occurs within the “tTOW” time-out window, the timer is reset (monitor DQ3 to

determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer). Resetting the

device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those

sectors and allow them to complete (refer to Write Operation Status section for Sector Erase Timer operation).

Loading the sector erase buffer may be done in any sequence and with any number of sectors.

Sector erase does not require the user to program the device before erase. The device automatically programs

all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing

a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these

operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) or

RY/BY.

The sector erase begins after the “t^TOW” time-out from the rising edge of CE or WE, whichever happens first, for

the last sector erase command pulse and terminates when the data on DQ7 is “1” (see Write Operation Status

section), at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at

an address within any of the sectors being erased.

Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of

Sector Erase

In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which

sectors being erased belong cannot be performed.

“Embedded Erase^TMAlgorithm” in “■ FLOW CHART” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

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MBM29QM12DH-60

Erase Suspend/Resume Command

The Erase Suspend command allows the user to interrupt Sector Erase operation and then reads data from or

programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation

which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector

Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.

Writing the Erase Resume command (30h) resumes the erase operation. The bank address of sector being

erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum

of “t^SPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the

RY/BY output pin will be at High-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must

use the address of the erasing sector for reading DQ⁶and DQ7 to determine if the erase operation has been

suspended. Further writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode, except that the data must be read from

sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle (see the section on DQ2).

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, it is

the same as programming in the regular Program mode, except that the data must be programmed to sectors

that are not erase-suspended. Reading successively from the erase-suspended sector while the device is in the

erase-suspend-program mode will cause DQ²to toggle. The end of the erase-suspended Program operation is

detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6), which is the same as the

regular Program operation. Note that DQ⁷must be read from the Program address while DQ6 can be read from

any address within bank being erase-suspended.

To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase

suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend

command can be written after the chip has resumed erasing.

Extended Command

(1) Fast Mode

The device has a Fast Mode function. It dispenses with the initial two unclock cycles required in the standard

program command sequence by writing the Fast Mode command into the command register. In this mode, the

required bus cycle for programming consists of two bus cycles instead of four in standard program command.

During the Fast mode, do not write any commands other than the Fast program/Fast mode reset command. The

read operation is also executed after exiting from the fast mode. To exit from this mode, it is necessary to write

Fast Mode Reset command into the command register. The first cycle must contain the bank address (see

“Embedded Program Algorithm fot Fast Mode” in “■ FLOW CHART”) .The V^CCactive current is required even if

CE = VIH during Fast Mode.

(2) Fast Programming

During the Fast Mode, programming can be executed with two bus cycle operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) (see “Embedded

Program Algorithm fot Fast Mode” in “■ FLOW CHART”) .

(3) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and the host system software interro-

gation handshake, which allows specific vendor-specified software algorithms to be used for entire families of

devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible soft-

ware support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. The bank address

should be set when writing this command. Then the device information can be read from the bank, and data

from the memory cell can be read from the another bank. The higher order address (A²², A21, A20) required for

reading out the CFI Codes requires that the bank address (BA) be set at the write cycle. Following the command

write, a read cycle from specific address retrieves device information. Please note that output data of upper byte

(DQ15 to DQ8) is “0” . Refer to CFI code table (“Common Flash Memory Interface Code Table” ) in “■ FLEXIBLE

35

MBM29QM12DH-60

SECTOR-ERASE ARCHITECTURE”. To terminate operation, it is necessary to write the read/reset command

sequence into the register.

HiddenROM Entry Command

The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and

to unable the change of the code once set. Programming is allowed in this area until it is protected. However,

once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required.

The HiddenROM area is 128 words (64 words for factory and 64 words for customer). This area is normally the

“outermost” 4 Kwords boot block area. Therefore, write the HiddenROM entry command sequence to enter the

HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears.

Sectors other than the boot block area (SA0) can be read during HiddenROM mode. Read/program of the

HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit

the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset

command sequence.

In HiddenROM mode, the simultaneous operation cannot be executed multi-function mode between the

HiddenROM area and the Bank A.

The following commands are unavailable when the HiddenROM is enabled. Issuing the following commands

while the HiddenROM is enabled results in the command being ignored.

1. CFI

2. Set to Fast Mode

3. Fast Program

4. Reset from Fast Mode

5. Program and Sector Erase Suspend

6. Program and Sector Erase Resume

The HiddenROM Entry command is allowed when the device is in either program or erase suspend modes. If

the HiddenROM is enabled, the program or erase suspend command is ignored. This prevents resuming either

programming or erasure on the HiddenROM if the overlayed sector was undergoing programming or erasure. It

is the responsibility of the software to resume the program or erasure of a suspended program or erase after

exiting the HiddenROM.

HiddenROM Program Command

To program the data to the HiddenROM area, write the HiddenROM program command sequence during

HiddenROM mode. This command is the same as the program command in usual except to write the command

during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the

DQ⁷data polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address

other than the HiddenROM area is selected to program, data of the address will be changed.

HiddenROM Protect Command

The method to protect the HiddenROM is to apply high voltage (V^ID) to A9 and OE, set the sector address in the

HiddenROM area and (A7, A6, A5, A4, A3, A2, A1, A0) = (0, 0, 0, 1, 1, 0, 1, 0), and apply the write pulse during the

HiddenROM mode. To verify the protect circuit, apply high voltage (V^ID) to A9, specify (A7, A6, A5, A4, A3, A2, A1,

A0) = (0, 0, 0, 1, 1, 0, 1, 0) and the sector address in the HiddenROM area, and read. When “1” appears on DQ0,

the protect setting is completed. “0” will appear on DQ0 if it is not protected. Please apply write pulse agian.

And the device has also HiddenROM protect command wirhout V^ID. See “MBM29QM12DH Command Definitions

Table” in “ ■ DEVICE BUS OPERATION”.

Other sector will be effected if the address other than those for HiddenROM area is selected for the sector

address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest

attention.

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MBM29QM12DH-60

Password Program Command

The Password Program Command permits programming the password that is used as part of the hardware

protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program

the password. The user must enter the unlock cycle, password program command (38h) and the program

address/data for each portion of the password when programming. There are no provisions for entering the 2-

cycle unlock cycle, the password program command, and all the password data. There is no special addressing

order required for programming the password. Also, when the password is undergoing programming, Simulta-

neous Operation is disabled. Read operations to any memory location will return the programming status. Once

the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification.

The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is

programmed as a “0” results in a time-out by the Embedded Program Algorithm with the cell remaining as a “0”.

The password is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password.

Writing the HiddenROM Exit command returns the device back to normal operation.

Password Verify Command

ThePasswordVerifyCommandisusedtoverifythePassword. ThePasswordisverifiableonlywhenthePassword

Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts

to verify the Password, the device will always drive all F’s onto the DQ data bus.

Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed.

Only the password is returned regardless of the bank address. The lower two address bits (A¹:A0) are valid during

the Password Verify. Writing the HiddenROM Exit command returns the device back to normal operation.

Password Protection Mode Locking Bit Program Command

ThePasswordProtectionModeLockingBitProgramCommandprogramsthePasswordProtectionModeLocking

Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection

Mode Locking Bit cannot be erased. Once the Password Protection Mode Locking Bit is programmed, the

Presistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in

the Password Protection mode. After issuing "PL/68h" at 4th bus cycle, the device requires approximately 150 µs

time out period for programming the Password Protection Mode Locking Bit. Then by writing "PL/48h" at 5th bus

cycle, thedeviceoutputsverifydataatDQ⁰. If DQ0 = 1 then Password Protection Mode Locking Bit is programmed.

If not, then the user needs to repeat this program sequence from the 4th cycle of "PL/68h". Exiting the Password

Protection Mode Locking Bit Program command is accomplished by writing the HiddenROM Exit command.

Persistent Sector Protection Mode Locking Bit Program Command

ThePersistentSectorProtectionModeLockingBitProgramCommandprogramsthePersistentSectorProtection

Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. By disabling

the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector

Protection mode of operation, once this bit is set. After issuing "SPML/68h" at 4th bus cycle, the device requires

approximately 150 µs time out period for programming the Persistent Protection Mode Locking Bit. Then by

writing "SPML/48h" at 5th bus cycle, the device outputs verify data at DQ⁰. If DQ0 = 1 then Persistent Protection

Mode Locking Bit is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle

of "SPML/68h". Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing

the HiddenROM Exit command.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password

Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock

Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock

command is executed. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even

after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the HiddenROM

Exit command.

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MBM29QM12DH-60

DPB Write(Erase) Command

The DPB Write command is used to set or clear a DPB for a given sector. The high order address bits (A²²to

A12) are issued at the same time as the code 01h or 00h on DQ7 to DQ0. All other DQ data bus pins are ignored

during the data write cycle. The DPBs are modifiable at any time, regardless of the state of the PPB or PPB

Lock Bit. The DPBs are cleared at power-up or hardware reset.Exiting the DPB Write command is accomplished

by writing the HiddenROM Exit command.

DPB verify command

DPB verify command is uesed to verify the status of a DPB for given sector.Scanning the sector addresses (SA)

will produce a logical "1" at the device output DQ0 for a protected sector. Otherwise the device will produce "0"

at DQ0 for the sector which is not protected. Writing the HiddenROM Exit Command returns the device back to

normal operation.

PPB Lock Bit verify command

PPB Lock Bit verify command is used to verify the status of a PPB Lock Bit. A logical "1" at the device output

DQ¹indicates that the PPB Lock Bit is set. If PPB Lock Bit is not set, DQ1 will output "0". Writing the HiddenROM

Exit Command returns the device back to normal operation.

Password Unlock Command

The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for

modification, thereby allowing the PPBs to become accessible for modification. The exact password must be

entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a

time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a

password. Ifthecommandisissuedbeforethe2µsexecutionwindowforeachportionoftheunlock, thecommand

will be ignored.

The Password Unlock function is accomplished by writing Password Unlock command and data to the device to

perform the clearing of the PPB Lock Bit. A⁰and A1 are used to determine the 16 bit data quantity is used to

match separated 16 bits. Writing the Password Unlock command is address order specific. In other words, the

lowers address A1:A0 = 00, the next cycle command is to A1:A0 = 01, then to A1:A0 = 10, and finally to A1:A0 = 11.

Writing out of sequence results in the Password Unlock not returning a match with the password and the PPB

Lock Bit remains set.

Once the Password Unlock command is entered, the RY/BY pin goes LOW indicating that the device is busy.

Also, reading the Bank A results in the DQ6 pin toggling, indicating that the Password Unlock function is in

progress. Reading the other bank returns actual array data. Approximately 2 µs is required for each portion of

the unlock. Once the first portion of the password unlock completes (RY/BY is not driven and DQ6 does not

toggle when read), the next cycle is issued, only this time with the next part of the password. Seven cycles

Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password

Unlock command, the RY/BY signal goes LOW and reading the device results in the DQ6 pin toggling on

successive read operations until complete. It is the responsibility of the microprocessor to keep track of the

number of Password Unlock cycles, the order, and when to read the PPB Lock bit to confirm successful password

unlock. Writing the HiddenROM Exit Command returns the device back to normal operation.

PPB Program Command

The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed

(but is bulk erased with the other PPBs). The specific sector address (A²²to A12) are written at the same time

as the program command 60h. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the

PPB Program command will not execute and the command will time-out without programming the PPB. After

issuing "SGA + WP/68h" at 4th bus cycle, the device requires approximately 150 µs time out period for program-

ming the PPB. Then by writing "SGA + WP/48h" at 5th bus cycle, the device outputs verify data at DQ⁰. If

DQ0 = 1 then PPB is programmed. If not, then the user needs to repeat this program sequence from the 4th

cycle of "SGA + WP/68h".

The PPB Program command does not follow the Embedded Program algorithm. Writing the HiddenROM Exit

Command returns the device back to normal operation.

38

MBM29QM12DH-60

All PPB Erase Command

The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a

specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase

command is written (60h), all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase

command will not execute and the command will time-out without erasing the PPBs. After issuing "WP/60h" at

4th bus cycle, the device requires approximately 1.5 ms time out period for programming the PPB. Then by

writing "SGA + WP/40h" at 5th bus cycle, the device outputs verify data at DQ⁰. If DQ0 = 0 then PPB is successfully

erased. If not, then the user needs to repeat this program sequence from the 4th cycle of "WP/60h".

It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user

attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time.

Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond

100 cycles is not guaranteed. Writing the HiddenROM Exit Command returns the device back to normal operation.

Write Operation Status

Detailed in “Hardware Sequence Flags Table” in “■ COMMAND DEFINITION” are all the status flags which can

determine the status of the bank for the current mode operation. The read operation from the bank which doesn’t

operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether

an Embedded Algorithm is properly completed. The information on DQ²is address-sensitive. This means that

if an address from an erasing sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle

if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are

in erase and which are not.

The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For

example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank

>, [2] < non-busy bank >, [3] < busy bank >, the DQ⁶toggles in the case of [1] and [3]. In case of [2], the data of

memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled

in [1] and [3].

In the erase suspend read mode, DQ2 is toggled in [1] and [3]. In case of [2], the data of memory cell is output.

Hardware Sequence Flags Table

Status

DQ⁷

0

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Toggle*¹

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

1

Program Suspend Read

(Program Suspended Sector)

Data

1

Data

1

Data Data

Data

Toggle

Data

1*²

Program

Suspended Mode

Program Suspend Read

(Non-Program Suspended Sector)

In Progress

Erase Suspend Read

(Erase Suspended Sector)

0

Erase

Erase Suspend Read

Suspended Mode (Non-Erase Suspended Sector)

Data

DQ⁷

Data

Toggle

Data Data

Erase Suspend Program

(Non-Erase Suspended Sector)

0

Embedded Program Algorithm

DQ⁷

0

Toggle

1

0

1

Exceeded Embedded Erase Algorithm

Time Limits

N/A

Erase

Erase Suspend Program

DQ⁷

Toggle

1

0

N/A

Suspended Mode (Non-Erase Suspended Sector)

*1 : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle.

*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ²bit.

39

MBM29QM12DH-60

DQ⁷

Data Polling

The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in

progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a

complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to

read the device will produce true data last written to DQ7. For programming, the Data Polling is valid after the

rising edge of the fourth write pulse in the four write pulse sequences. During the Embedded Erase Algorithm,

an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase

Algorithm, an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown

in “Temporary Sector Group Unprotection Algorithm” in “■ FLOW CHART”.

Data polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase Suspend

mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase

Suspend Mode.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not pro-

tected sectors. Otherwise the status may become invalid.

If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for

erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.

Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ⁷) may change

asynchronously while the output enable (OE) is asserted low. This means that device is driving status information

on DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples

the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm

operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to

DQ7 will be read on successive read attempts.

TheDataPollingfeatureisactiveonlyduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm

or sector erase time-out. (See “Hardware Sequence Flags Table” in “■ COMMAND DEFINITION”.)

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the Data

Polling timing specifications and diagrams.

DQ⁶

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the

busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse

sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse

in the six write pulse sequences. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop

toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If

all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into

read mode, having data kept remained.

Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause

DQ6 to toggle.

The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank

is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the

Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6

to toggle.

40

MBM29QM12DH-60

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the

Toggle Bit I timing specifications and diagrams.

DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under

these conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle was

not successfully completed. Data Polling is only operating function of the device under this condition. The CE

circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins

will control the output disable functions as described in “MBM29QM12DH User Bus Operations Table” in “■

DEVICE BUS OPERATION”.

The DQ⁵failure condition may also appear if a user tries to program a non-blank location without pre-erase. In

this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.

If this occurs, reset device with the command sequence.

DQ³

Sector Erase Timer

After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain

low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command

sequence.

If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to

determine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase

cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the

command has been accepted, the system software should check the status of DQ³prior to and following each

subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have

been accepted.

See “Hardware Sequence Flags Table” in “■ COMMAND DEFINITION” : Hardware Sequence Flags.

DQ²

Toggle Bit II

This toggle bit II, along with DQ⁶, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase

suspended sector will indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows :

For example, DQ²and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status Table” in “■ COMMAND DEFINITION” and “DQ2

vs. DQ6” in “■ TIMING DIAGRAM”.

Furthermore DQ²can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles

if this bit is read from an erasing sector.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

41

MBM29QM12DH-60

Reading Toggle Bits 3DQ⁶/DQ²

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit

after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ7 to DQ0 on the following read cycle.

However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system

also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then

determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5

went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ⁵has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, deter-

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the

status of the operation. (Refer to “Toggle Bit Algorithm” in “■ FLOW CHART”.)

Toggle Bit Status Table

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Toggle*

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

1*

Erase-Suspend Program

DQ⁷

Toggle

* : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle. Reading from the non

erase suspend sector address will indicate logic “1” at the DQ2 bit.

RY/BY

Ready/Busy

The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded

Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program

or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device

is placed in an Erase Suspend mode, RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate

a busy condition during RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation Timing

Diagram” in “■ TIMING DIAGRAM” and “RESET, RY/BY Timing Diagram” in “■ TIMING DIAGRAM” for a detailed

timing diagram. The RY/BY pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

Data Protection

The device is designed to offer protection against accidental erasure or programming caused by spurious system

level signals that may exist during power transitions. During power-up, the device automatically resets the internal

state machine in Read mode. Also, with its control register architecture, alteration of memory contents only

occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting from V^CCpower-up

and power-down transitions or system noise.

42

MBM29QM12DH-60

Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for VCC less

than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until

the VCC level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when VCC is above VLKO (Min) .

If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

43

MBM29QM12DH-60

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min

−55

−40

Max

+125

+85

Storage Temperature

Tstg

°C

Ambient Temperature with Power Applied

TA

Voltage with Respect to Ground All pins except A⁹,

OE, and RESET *^1,*²

VIN, VOUT

−0.5

VCC + 0.5

V

Power Supply Voltage *¹

A9, OE, and RESET *^1,*³

WP/ACC *^1,*⁴

VCC

VIN

−0.5

+4.0

+13.0

+10.5

V

VACC

*1 : Voltage is defined on the basis of VSS = GND = 0 V.

*2 : Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may

undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is

VCC+0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC+2.0 V for periods of up to

20 ns.

*3 : Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and

RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input

and supply voltage (VIN − VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET

pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.

*4 : Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may

undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is

+10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Part No.

Unit

Min

−40

Max

+85

Ambient Temperature

Power Supply Voltage

T^A

MBM29QM12DH 60/70

MBM29QM12DH 60

MBM29QM12DH 70

°C

V

V^CC

+2.7

+1.65

+3.6

+VCC

+1.95

V

V^CCQSupply Voltage*

VCCQ

V

* : Voltage is defined on the basis of VSS = GND = 0 V.

Note : Operating ranges define those limits between which the proper device function is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating conditionranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

44

MBM29QM12DH-60

■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

VCC +2.0 V

V^CC+0.5 V

+2.0 V

20 ns

Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

VCC +0.5 V

20 ns

Note: This waveform is applicable for A⁹, OE, and RESET.

Maximum Overshoot Waveform 2

45

MBM29QM12DH-60

■ DC CHARACTERISTICS

1. DC Characteristics (V^CCQ= 2.7 V to 3.6 V or 1.65 V to 1.95 V)

Value

Typ

Sym

bol

Un

it

Parameter

Conditions

Min

−1.0

Max

+1.0

Input Leakage Current

Output Leakage Current

ILI

V^IN= VSSQ to VCCQ, V^CC= VCC Max

V^OUT= VSSQ to VCCQ, V^CC= VCC Max

µA

I^LO

A⁹, OE, RESET Inputs

Leakage Current

V^CC= VCC Max,

A⁹, OE, RESET = 12.5 V

I^LIT

+35

µA

WP/ACC Accelerated

Program Current

V^CC= VCC Max,

WP/ACC = VACC Max

ILIA

20

mA

V^CC= 2.7 V to 3.1 V

45

60

25

30

25

CE = VIL, OE = VIH,

f = 10 MHz

mA

V^CC= 2.7 V to 3.6 V

V^CC= 2.7 V to 3.1 V

V^CC= 2.7 V to 3.6 V

VCC Active Current *¹

ICC1

CE = VIL, OE = VIH,

f = 5 MHz

V^CCActive Current *²

ICC2 CE = VIL, OE = VIH

mA

µA

V^CC= VCC Max, CE = VCCQ ± 0.3 V,

RESET = VCCQ ± 0.3 V,WP/ACC = VCCQ ± 0.3 V

V^CCCurrent (Standby)

V^CCCurrent (Standby, Reset)

ICC3

1

5

ICC4 V^CC= VCC Max, RESET = VSSQ ± 0.3 V

V^CC= VCC Max, CE = VSSQ ± 0.3 V,

ICC5 RESET = VCCQ ± 0.3 V,

V^CCPower Supply Current

(Automatic Sleep Mode) *³

1

5

µA

V^IN= VCCQ ± 0.3 V or VSSQ ± 0.3 V

V^CCActive Current *⁵

(Read-While-Program)

V^CCActive Current *⁵

(Read-While-Erase)

ICC6 CE = VIL, OE = VIH

I^CC7CE = VIL, OE = VIH

I^CC8CE = VIL, OE = VIH

45

25

mA

V^CCActive Current

(Erase-Suspend-Program)

V^CC= 2.7 V to 3.1 V

V^CC= 2.7 V to 3.6 V

10

V^CCActive Current

(Page Mode Read)

CE = VIL, OE = VIH,

8 Words Read

I^CC9

mA

15

Input Low Level

Input High Level

V^IL

V^IH

−0.5

V^CCQ× 0.3

V^CCQ+0.3

V

0.7 × V^CCQ

Voltage for Autoselect and

Sector Protection

VID

11.5

8.5

12

12.5

9.5

V

(A⁹, OE, RESET) *⁴

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration *⁴

VACC

9.0

V

0.15 ×

VCCQ

Output Low Voltage Level

V^OLI^OL= 100 µA, V^CC= VCC Min

0.85 ×

V^CCQ

Output High Voltage Level

Low V^CCLock-Out Voltage

V^OH2I^OH= −100 µA

V

VLKO

2.3

2.4

2.5

*1: The ICC current listed includes both the DC operating current and the frequency dependent component.

*2: ICC active while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

*4: Applicable for only V^CC.

*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)

46

MBM29QM12DH-60

■ AC CHARACTERISTICS

• Read Only Operations Characteristics

Value

Symbol

V^CCQ= 2.7 V to V^CCQ= 1.65 V to

Test

Setup

Parameter

Unit

3.6 V *¹

1.95 V *²

JEDEC Standard

Min

Max

Min

Max

Read Cycle Time

t^AVAV

t^AVQV

tRC

tACC

t^PRC

t^PACC

60

20

70

30

ns

CE = VIL

OE = VIL

Address to Output Delay

Page Read Cycle Time

60

70

CE = VIL

OE = VIL

Page Address to Output Delay

20

30

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

60

20

70

30

ns

Output Hold Time From Address,

CE or OE, Whichever Occurs First

tAXQX

tOH

5

ns

*1 : Test Conditions:

Output Load:

*2 : Test Conditions:

Output Load:

1 TTL gate and 30 pF (Figure 4.1)

CL = 30 pF (Figure 4.2)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V or V^CCQ

Timing measurement reference level

Input: 0.5 × VCCQ

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V or V^CCQ

Timing measurement reference level

Input: 0.5 × VCCQ

Output:0.5 × VCCQ

3.3 V

Diode = 1N3064

or equivalent

2.7 kΩ

Device

Under

Test

Device

Under

Test

6.2 kΩ

CL

Diode = 1N3064

or equivalent

Figure 4.1 Test Conditions

Figure 4.2 Test Conditions

47

MBM29QM12DH-60

• Write (Erase/Program) Operations

Parameter

Value

Symbol

V^CCQ= 2.7 V to

3.6 V *¹

V^CCQ= 1.65 V to

Unit

1.95 V *²

JEDEC Standard Min Typ Max Min Typ Max

Write Cycle Time

t^AVAV

t^AVWL

tWC

tAS

60

0

70

0

ns

Address Setup Time

Address Setup Time to OE Low during

Toggle Bit Polling

tASO

tAH

15

30

0

15

35

0

ns

Address Hold Time

t^WLAX

Address Hold Time from CE or OE High

during Toggle Bit Polling

tAHT

Data Setup Time

t^DVWH

t^WHDX

tDS

tDH

25

0

30

0

ns

Data Hold Time

Output Enable Setup Time

t^OES

0

Output

Read

0

Enable Hold

Time

t^OEH

Toggle and Data Polling

10

0

10

0

ns

Read Recover Time Before Write

t^GHWL

tGHWL

tGHEL

Read Recover Time Before Write

(OE High to CE Low)

tGHEL

0

ns

CE Setup Time

tELWL

tWLEL

tCS

tWS

0

ns

WE Setup Time

ns

CE Hold Time

tWHEH

tEHWH

t^WLWH

tELEH

tCH

0

ns

WE Hold Time

tWH

0

ns

Write Pulse Width

tWP

35

20

40

25

ns

CE Pulse Width

tCP

ns

Write Pulse Width High

CE Pulse Width High

Word Programming Operation

Sector Erase Operation*¹

V^CCSetup Time

t^WHWL

tEHEL

tWPH

tCPH

tWHWH1

tWHWH2

tVCS

ns

t^WHWH1

tWHWH2

6

µs

0.5

s

50

500

4

50

500

4

µs

Rise Time to V^ID*²

tVIDR

tVACCR

tVLHT

tWPP

tOESP

tCSP

ns

Rise Time to V^ACC*³

Voltage Transition Time*²

Write Pulse Width*²

OE Setup Time to WE Active*²

CE Setup Time to WE Active*²

ns

µs

100

4

100

4

µs

4

µs

(Continued)

48

MBM29QM12DH-60

(Continued)

Value

Symbol

V^CCQ= 2.7 V to V^CCQ= 1.65 V to

Parameter

Unit

3.6 V *¹

1.95 V *²

JEDEC Standard Min Typ Max Min Typ Max

Recover Time from RY/BY

RESET Pulse Width

—

tRB

tRP

tRH

0

—

0

—

ns

500

50

500

50

RESET High Level Period Before Read

Program/Erase Valid to RY/BY

Delay

—

t^BUSY

—

90

—

90

ns

Delay Time from Embedded Output Enable

Sector Erase Time-out Period

—

t^EOE

t^TOW

t^SPD

—

50

—

60

—

20

—

50

—

70

—

20

ns

µs

Erase Suspend Transition Time

*1: This does not include the preprogramming time.

*2: This timing is for Sector Protection operation.

*3: This timing is for Accelerated Program operation.

49

MBM29QM12DH-60

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

0.5

2

s

Word Programming Time

Chip Programming Time

Erase/Program Cycle

6.0

100

200

µs

s

Excludes system-level overhead

50.3

100,000

cycle

Note : Typical Erase conditions TA = +25°C, VCC = 2.9 V

Typical Program conditions TA = +25°C, VCC = 2.9 V, Data = checker

■ TSOP(1) PIN CAPACITANCE

(TA = +25°C, f = 1.0 MHz)

Value

Unit

Parameter

Symbol

C^IN

Test Setup

Typ

Max

Input Pin Capacitance

Output Pin Capacitance

Control Pin Capacitance

VIN = 0

7

8

10

pF

C^OUT

C^IN2

VOUT = 0

VIN = 0

12

8

11

Control Pin Capacitance (WP/ACC) CIN3

11

12

■ FBGA PIN CAPACITANCE

Value

Parameter

Symbol

Test Setup

Unit

Typ

Max

Input Pin Capacitance

Output Pin Capacitance

Control Pin Capacitance

C^IN

VIN = 0

VOUT = 0

VIN = 0

7

8

10

12

11

12

pF

C^OUT

C^IN2

8

ControlPin Capacitance (WP/ACC) CIN3

11

50

MBM29QM12DH-60

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will

Change

from H to L

May

Change

from L to H

Will

Change

from L to H

"H" or "L":

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

"Off" State

tRC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tOH

tCE

High-Z

Outputs Valid

Outputs

Read Operation Timing Diagram

51

MBM29QM12DH-60

Same page Address

A22 to A3

Aa

Ab

Ac

Ad

Ae

Af

Ag

Ah

A2 to A0

tRC

t^PRC

tPRC

tACC

tCE

CE

tOEH

tOE

OE

WE

t^DF

tPACC

tOH

tPACC

tOH

tPACC

tOH

tPACC

tOH

tPACC

tOH

tPACC

tOH

t^OH

Da

tOH

High-Z

Db

Dc

Dd

De

Df

Dg

Dh

Output

Page Read Operation Timing Diagram

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

Hardware Reset/Read Operation Timing Diagram

52

MBM29QM12DH-60

3rd Bus Cycle

555h

Data Polling

PA

Address

CE

tWC

tRC

tAS

tAH

tCS

tCH

tCE

OE

tOE

tWP

tWPH

tWHWH1

tGHWL

WE

tOH

tDF

tDH

tDS

A0h

PD

DOUT

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

Alternate WE Controlled Program Operation Timing Diagram

53

MBM29QM12DH-60

3rd Bus Cycle

Data Polling

PA

555h

tWC

PA

Address

WE

tAS

tAH

tWS

tWH

OE

CE

tCPH

tCP

tWHWH1

tGHEL

tDS

tDH

A0h

PD

DOUT

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

Alternate CE Controlled Program Operation Timing Diagram

54

MBM29QM12DH-60

555h

2AAh

555h

2AAh

SA*

Address

t

WC

t

AS

t

AH

CE

t

CS

t

CH

OE

t

WP

tWPH

t

GHWL

WE

DS

tDH

10h for Chip Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

VCC

t

VCS

* : SA is the sector address for Sector Erase. Addresses = 555h (at word mode) for Chip Erase.

Chip/Sector Erase Operation Timing Diagram

55

MBM29QM12DH-60

CE

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

Data

tEOE

tBUSY

* : DQ7 = Valid Data (The device has completed the Embedded operation) .

Data Polling during Embedded Algorithm Operation Timing Diagram

56

MBM29QM12DH-60

Address

CE

tAHT tASO

tAHT tAS

tCEPH

WE

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

Note : DQ6: Addresses are "Bank Address" where Embedded Algorithm is in progress.

DQ2: Addresses are "Sector Address" where Embedded Algorithm (Erase) is in progress.

* : DQ6 stops toggling (The device has completed the Embedded operation).

AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

57

MBM29QM12DH-60

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CE

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDH

tDS

tDF

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0h)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

Bank-to-Bank Read/Write Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase Suspend

Read

Erase Suspend

Read

WE

Erase

Suspend

Program

Erase

Complete

DQ6

DQ2*

Toggle

DQ2 and DQ6

with OE or CE

* : DQ2 is read from the erase-suspended sector.

DQ2 vs. DQ6

58

MBM29QM12DH-60

CE

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

WE

RESET

tRP

tRB

RY/BY

tREADY

RESET, RY/BY Timing Diagram

59

MBM29QM12DH-60

A22, A21, A20

A19, A18, A17

SGAX

SGAY

A16, A15, A14

A13, A11

A7, A6, A5

A4, A3, A2

A0

A1

VID

VIH

A9

tVLHT

VID

VIH

OE

tVLHT

tWPP

WE

tOESP

tCSP

CE

01h

Data

tOE

tVCS

VCC

SGAX : Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

Sector Group Protection Timing Diagram

60

MBM29QM12DH-60

VCC

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

RY/BY

Unprotection period

Temporary Sector Group Unprotection Timing Diagram

61

MBM29QM12DH-60

VCC

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SGAX

SGAY

A7, A6, A5

A4, A3, A2

A0

A1

CE

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

SGAX : Sector Group Address to be protected

SGAY : Next Sector Group Address

TIME-OUT : Time-Out window = 250 µs (Min)

Extended Sector Group Protection Timing Diagram

62

MBM29QM12DH-60

VCC

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CE

WE

tVLHT

Program Command Sequence

RY/BY

Acceleration period

Accelerated Program Timing Diagram

63

MBM29QM12DH-60

■ FLOW CHART

Embedded Algorithm^TM

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in program

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Embedded Program^TMAlgorithm

64

MBM29QM12DH-60

Embedded Algorithm^TM

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Embedded Erase^TMAlgorithm

65

MBM29QM12DH-60

VA = Address for programming

= Any of the sector addresses

within the sector being erased

during sector erase or multiple

erases operation.

Start

= Any of the sector addresses

within the sector not being

protected during sector erase or

multiple sector erases

operation.

Read

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data?

*

No

Fail

Pass

* : DQ⁷is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Data Polling Algorithm

66

MBM29QM12DH-60

Start

*1

Read DQ7 to DQ0

Addr. = VA

VA = Bank address being executed

Read DQ7 to DQ0

Addr. = VA

Embedded Algorithm.

No

DQ6 =

Toggle?

Yes

No

DQ5 = 1?

Yes

*1, 2

Read DQ7 to DQ0

Addr. = VA

Read DQ7 to DQ0

Addr. = VA

No

DQ6 =

Toggle?

Yes

Program/Erase

Operation Not

Complete.Write

Reset Command

Program/Erase

Operation

Complete

*1 : Read toggle bit twice to determine whether it is toggling.

*2 : Recheck toggle bit because it may stop toggling as DQ⁵changes to “1”.

Toggle Bit Algorithm

67

MBM29QM12DH-60

Start

555h/AAh

2AAh/55h

Set Fast Mode

555h/20h

XXXh/A0h

In Fast Program

Program Address/Program Data

Data Polling

No

Verify Data?

Yes

No

Last Address?

Yes

Increment Address

Programming Completed

(BA)XXXh/90h

XXXh/F0h

Reset Fast Mode

Embedded Programming Algorithm for Fast Mode

68

MBM29QM12DH-60

Start

Setup Sector Group Addr.

(A22, A21, A20, A19, A18, A17,

A16, A15, A14, A13, A12)

PLSCNT = 1

OE

CE

=

VID, A9

=

VID,

VIH

=

VIL, RESET

=

A7 = A6 = A5 = A4 =

A3 = A2 = A0 = VIL, A1 = VIH

Activate WE Pulse

Time out 100 µs

Increment PLSCNT

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector

(Addr. = SGA,

A⁷= A6 = A5 = A4 =

A3 = A2 = A0 = VIL, A1 = VIH)

No

PLSCNT = 25?

Yes

Data = 01h?

Yes

Remove VID from A9

Write Reset Command

Protect Another Sector

Group?

No

Device Failed

Remove VID from A9

Write Reset Command

Sector Group Protection

Completed

Sector Group Protection Algorithm

69

MBM29QM12DH-60

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*2

*1 : All protected sector groups are unprotected.

*2 : All previously protected sector groups are reprotected.

Temporary Sector Group Unprotection Algorithm

70

MBM29QM12DH-60

Start

RESET = VID

Wait 4 µs

Device is Operating in

Temporary Sector Group

Unprotection Mode

No

First Write Cycle

= 60h?

Yes

To Setup Sector Group Protection

Write XXXh/60h

PLSCNT = 1

To Protect Sector Group

Write 60h to Sector Address

A⁷= A6 = A5 = A4 =

(

)

A³= A2 = A0 = VIL, A1 = VIH

Time out 250 µs

To Verify Sector Group Protection

Write 40h to Sector Address

A⁷= A6 = A5 = A4 =

Increment PLSCNT

(

)

A3 = A2 = A0 = VIL, A1 = VIH

Read from Sector Group Address

(Addr. = SGA,

A⁷= A6 = A5 = A4 =

No

A³= A2 = A0 = VIL, A1 = VIH)

Setup Next Sector Group Address

No

Data = 01h?

PLSCNT = 25?

Yes

Protect Other Sector

Group?

Remove VID from RESET

Write Reset Command

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Group Protection

Completed

Extended Sector Group Protection Algorithm

71

MBM29QM12DH-60

Password Mode Choice Method

Start

Password Program

Password Verify

Password Protection

Mode

DQ⁰= 1?

Reset Command

Yes

Bit Program

No

No (Time out)

Reset Command

DQ⁰= 0?

Yes

Reset Command

Sector Protection

Completed

Password Sector Protect Algorithm

72

MBM29QM12DH-60

PPB Lock Clear in Password Mode

Start

Password Unlock

No (Time out)

RY/BY = H?

Yes

No

DPB/PPB/PPB Lock

Bit Status

DQ⁰= 1?

Yes

Reset Command

Password/Unlock

Complete

All PPB Erase

Reset Command

No (Time out)

DQ⁰= 0?

Yes

PPB Lock Bit

Clear Completed

PPB Lock Bit Clear in Password Mode

73

MBM29QM12DH-60

■ ORDERING INFORMATION

Part No.

Package

Access Time (ns)

Remarks

56-pin plastic TSOP (1)

(FPT-56P-M01)

MBM29QM12DH60PCN

60

Normal Bend

80-pin plastic FBGA

(BGA-80P-M04)

MBM29QM12DH60PBT

60

MBM29QM12D

H

60 PCN

PACKAGE TYPE

PCN = 56-Pin Thin Small Outline Package

(TSOP (1) Normal Bend)

PBT = 80-Pin Fine Pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

DEVICE NUMBER/DESCRIPTION

MBM29QM12D

128 Mbit (8M × 16-Bit) Page Mode Flash Memory

3.0 V-only, Page Mode and Dual Operation Flash Memory

74

MBM29QM12DH-60

■ PACKAGE DIMENSIONS

Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) .

Note 2) *2 : These dimensions do not include resin protrusion.

Note 3) Pins width and pins thickness include plating thickness.

Note 4) Pins width do not include tie bar cutting remainder.

56-pin plastic TSOP(1)

(FPT-56P-M01)

0.10±0.05

(.004±.002)

(Stand off)

LEAD No.

1

56

INDEX

0.22±0.05

(.009±.002)

M

0.10(.004)

¹14.00±0.10

*

(.551±.004)

0.50(.020)

28

29

Details of "A" part

1.10 –⁺0⁰.^.0¹5⁰

20.00±0.20(.787±.008)

²18.40±0.10(.724±.004)

.043 ⁺^–.^.⁰⁰⁰⁰²⁴

(Mounting height)

0˚~8˚

*

0.17±0.03

.007±.001

0.60±0.15

(.024±.006)

0.25(.010)

"A"

0.08(.003)

C

2002 FUJITSU LIMITED F56001S-c-4-5

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

(Continued)

75

MBM29QM12DH-60

(Continued)

80-pin plastic FBGA

(BGA-80P-M04)

11.00±0.10(.433±.004)

1.08 –⁺0⁰.^.1¹3²

.043 –⁺.^.0⁰0⁰5⁵

B

(Mounting height)

(Stand off)

0.40(.016)

REF

0.80(.031)

REF

0.38±0.10

(.015±.004)

8

7

6

5

4

3

2

1

A

8.00±0.10

(.315±.004)

0.10(.004)

S

(INDEX AREA)

M

L K J H G F E D C B A

S

(INDEX AREA)

80-ø0.45±0.05

(80-ø.018±.002)

M

0.08(.003)

S A B

C

2003 FUJITSU LIMITED B80004S-c-1-1

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

76

MBM29QM12DH-60

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0407

FUJITSU LIMITED Printed in Japan


型号：	MBM29QM12DH70PCN
厂家：	CYPRESS
描述：	Flash, 8MX16, 70ns, PDSO56, 光电二极管内存集成电路闪存
文件：	总78页 (文件大小：1064K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29QM12DH70PCN [CYPRESS]

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