MT54V512H36EF-10_技术文档

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E

MT54V512H36E

18Mb QDR^™SRAM

4-WORD BURST

Features

•

Separate independent read and write data ports with

concurrent transactions

100 percent bus utilization DDR READ and WRITE

operation

Figure 1: 165-Ball FBGA

•

Fast clock to valid data times

High frequency operation with future migration to

higher clock frequencies

•

Full data coherency, providing most current data

Four-tick burst counter for reduced-address frequency

Double data rate operation on read and write ports

Two input clocks (K and K#) for precise DDR timing at

clock rising edges only

•

Two output clocks (C and C#) for precise flight time

and clock skew matching—clock and data delivered

together to receiving device

Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

Table 1:

Valid Part Numbers

•

Single address bus

PART NUMBER

DESCRIPTION

Simple control logic for easy depth expansion

Internally self-timed, registered writes

2.5V core and 1.5 to 1.8V ( 0.1V) HSTL I/O

Clock-stop capability

13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA package

User-programmable impedance output

JTAG boundary scan

MT54V1MH18EF-xx

MT54V512H36EF-xx

1 Meg x 18, QDRb4 FBGA

512K x 36, QDRb4 FBGA

General Description

The Micron^®QDR™ (Quad Data Rate™) synchro-

nous, pipelined burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS

process.

Options

•

Marking¹

Clock Cycle Timing

5ns (200 MHz)

6ns (167 MHz)

The QDR architecture consists of two separate DDR

(double data rate) ports to access the memory array.

The read port has dedicated data outputs to support

READ operations. The write port has dedicated data

inputs to support WRITE operations. This architecture

eliminates the need for high-speed bus turnaround.

Access to each port is accomplished using a common

address bus. Addresses for reads and writes are latched

on alternate rising edges of the K clock. Each address

location is associated with four words that burst

sequentially into or out of the device. Since data can be

transferred into and out of the device on every rising

edge of both clocks (K, and K# and C and C#) memory

bandwidth is maximized and system design is simpli-

fied by eliminating bus turnarounds.

-5

-6

7.5ns (133 MHz)

10ns (100 MHz)

-7.5

-10

•

Configurations

1 Meg x 18

512K x 36

MT54V1MH18E

MT54V512H36E

•

Package

165-ball, 13mm x 15mm FBGA

Operating Temperature Range

Commercial (0°C ? T_A? +70°C)

F

None

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

1

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Depth expansion is accomplished with port selects

for each port (read R#, write W#) which are received at

K rising edge. Port selects permit independent port

operation.

READ cycles are pipelined. The request is initiated

by asserting R# LOW at K rising edge. Data is delivered

after the next rising edge of K, using C and C# as the

output timing references, or using K and K# if C and C#

are tied HIGH. If C and C# are tied HIGH, they may not

be toggled during device operation. Output tri-stating

is automatically controlled such that the bus is

released if no data is being delivered. This permits

banked SRAM systems with no complex output enable

(OE) timing generation. Back-to-back READ cycles are

initiated every second K rising edge. Any command in

between is ignored, since the burst sequence may not

be interrupted and requires two full clock cycles.

WRITE cycles are initiated by W# LOW at K rising

edge. Data is expected at both rising edges of K and K#,

beginning one clock period later. Write registers are

incorporated to facilitate pipelined self-timed WRITE

cycles and provide fully coherent data for all combina-

tions of reads and writes. A read can immediately fol-

low a write even if they are to the same address.

Although the write data has not been written to the

memory array, the SRAM will deliver the data from the

write register instead of using the older data from the

memory array. The latest data is always utilized for all

bus transactions. WRITE cycles are initiated every sec-

ond K rising edge. Any command is ignored, since the

burst sequence may not be interrupted.

All synchronous inputs pass through registers con-

trolled by the K or K# input clock rising edges. Active

LOW byte writes (BWx#) permit byte write or nibble

write selection. Write data and byte writes are regis-

tered on the rising edges of both K and K#. The

addressing within each burst of four is fixed and

sequential, beginning with the lowest and ending with

the highest address. All synchronous data outputs pass

through output registers controlled by the rising edges

of the output clocks (C and C# if provided, otherwise K

and K#).

Four balls are used to implement JTAG test capabili-

ties: test mode select (TMS), test data-in (TDI), test

clock (TCK), and test data-out (TDO). JTAG circuitry is

used to serially shift data to and from the SRAM. JTAG

inputs use JEDEC-standard 2.5V I/O levels to shift data

during this testing mode of operation.

The SRAM operates from a 2.5V power supply, and

all inputs and outputs are HSTL-compatible. The

device is ideally suited for applications that benefit

from a high-speed, fully-utilized DDR data bus.

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

READ/WRITE Operations

BYTE WRITE Operations

All bus transactions operate on an uninterruptable

burst of four data, requiring two full clock cycles of bus

utilization. Any request that attempts to interrupt a

burst-in-progress is ignored. The resulting benefit is

that the address rate is kept down to the clock fre-

quency even when both buses are 100 percent utilized.

BYTE WRITE operations are supported. The active

LOW byte write controls are registered coincident with

their corresponding data. This feature can eliminate

the need for some READ-MODIFY-WRITE cycles, col-

lapsing it to a single BYTE WRITE operation in some

instances.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

It is strontly recommended that the clocks operate for

a number of cycles prior to initiating commands to the

SRAM. This delay permits transmission line charging

effects to be overcome and allows the clock timing to

be nearer to its steady-state value.

Programmable Impedance Output

Buffer

The QDR SRAM is equipped with programmable

impedance output buffers. This allows a user to match

the driver impedance to the system. To adjust the

impedance, an external precision resistor (RQ) is con-

nected between the ZQ ball and VSS. The value of the

resistor must be five times the desired impedance. For

example, a 350ꢀ resistor is required for an output

impedance of 70ꢀ. To ensure that output impedance

is one-fifth the value of RQ (within 15 percent), the

range of RQ is 175ꢀ to 350ꢀ. Alternately, the ZQ ball

can be connected directly to VDDQ, which will place

the device in a minimum impedance mode.

Single Clock Mode

The SRAM can be used with the single K, K# clock

pair by tying C and C# HIGH. In this mode, the SRAM

will use K and K# in place of C and C#. This mode pro-

vides the most rapid data output but does not com-

pensate for system clock skew and flight times.

The output echo clocks are precise references to

output data. CQ and CQ# are both rising edge and fall-

ing edge accurate and are 180° out of phase. Either or

both may be used for output data capture. K or C rising

edge triggers CQ rising and CQ# falling edge. CQ rising

edge indicates first data response for QDRI and DDRI

(version 1, non-DLL) SRAM, while CQ# rising edge

indicates first data response for QDRII and DDRII (ver-

sion 2, DLL) SRAM.

Output impedance updates may be required

because over time variations may occur in supply volt-

age and temperature. The device samples the value of

RQ. Impedance updates are transparent to the system;

they do not affect device operation, and all data sheet

timing and current specifications are met during an

update.

The device will power up with an output impedance

set at 50ꢀ. To guarantee optimum output driver

impedance after power-up, the SRAM needs 1,024

cycles to update the impedance. The user can operate

the part with fewer than 1,024 clock cycles, but optimal

output impedance is not guaranteed.

Depth Expansion

Port select inputs are provided for the read and

write ports. This allows for easy depth expansion. Both

port selects are sampled on the rising edge of K only.

Each port can be independently selected and dese-

lected and does not affect the operation of the oppo-

site port. All pending transactions are completed prior

to a port deselect.

Clock Considerations

This device does not utilize internal phase-locked

loops and can therefore be placed into a stopped-clock

state to minimize power without lengthy restart times.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Figure 2: Functional Block Diagram

1 Meg x 18; 512K x 36

n

ADDRESS

R#

ADDRESS

REGISTRY

& LOGIC

W#

K

W#

MUX

2a

BW0#

BW1#

2a

O

U

T

B

U

F

D

R

I

V

E

R

O

U

T

O

U

T

S

E

L

E

C

T

W R

R E

I G

T

W

R

I

T

E

S

E

N

S

R

E

n

A

M

P

DATA

REGISTRY

& LOGIC

3a

a

2

x a

a

G

Q

MEMORY

ARRAY

P

F

D (Data In)

P

U

T

E

R

(Data Out)

2

U

T

U

T

R#

A

S

E 2

E

K

C

K

K#

MUX

CQ, CQ#

C,C#

or

K,K#

(Echo Clock Out)

NOTE:

1. Figure 2 illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed

information.

2. For 1 Meg x 18, n = 18, a = 18.

For 512K x 36, n = 17, a = 36.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Figure 3: Application Example

R = 250Ω

SRAM 1

B

SRAM 2

B

ZQ

Q

ZQ

Q

Vt

CQ

CQ#

K#

CQ

CQ#

K#

D

SA

R W W

R

# # #

SA

C

C#

K

#

C C# K

DATA IN

DATA OUT

Address

Read#

Vt

R

Write#

BW#

BUS

MASTER

(CPU

or

ASIC)

SRAM 1 Input CQ

SRAM 1 Input CQ#

SRAM 2 Input CQ

SRAM 2 Input CQ#

Source K

Source K#

Delayed K

Delayed K#

R

R = 50Ω

Vt = VREF

NOTE:

1. Consult Micron Technical Notes for more thorough discussions of clocking schemes.

2. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.

3. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended

over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Table 2:

1 Meg x 18 Ball Layout (Top View)

165-Ball FBGA

1

CQ#

NC

TDO

2

3

NC/SA¹

D9

4

5

BW1#

NC

6

7

NC

8

9

SA

10

VSS

NC

Q7

NC

D6

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

VSS

Q9

W#

K#

K

R#

B

SA

BW0#

SA

NC

VDDQ

NC

SA

C

NC

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

SA

VSS

SA

NC

VSS

SA

C

VSS

D

D11

NC

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

VSS

E

VDDQ

VSS

VDDQ

VSS

F

Q12

D13

VREF

NC

VREF

Q4

D3

G

H

J

K

NC

L

Q15

NC

Q1

NC

D0

M

N

P

D17

NC

VSS

SA

R

TCK

SA

C#

SA

TMS

NOTE:

1. Expansion address: 3A for 36Mb

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Table 3:

512K x 36 Ball Layout (Top View)

165-Ball FBGA

1

2

3

4

5

BW2#¹

BW3#⁴

SA

6

7

BW1#²

BW0#⁵

SA

8

9

VSS/SA³

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q9

10

VSS

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

CQ#

Q27

D27

D28

Q29

Q30

D30

NC

VSS

NC

W#

K#

K

R#

B

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

SA

Q17

Q7

C

VSS

NC

VSS

SA

C

VSS

D

VSS

D15

D6

E

VDDQ

VSS

VDDQ

VSS

F

VDD

VSS

VDD

VSS

Q14

D13

VREF

Q4

G

H

J

D31

Q32

Q33

D33

D34

Q35

TDO

K

D3

L

Q11

Q1

M

VSS

N

P

VSS

SA

VSS

D9

SA

D0

R

SA

C#

SA

TMS

NOTE:

1. BW2# controls writes to D18:D26

2. BW1# controls writes to D9:D17

3. Expansion address: 9A for 36Mb

4. BW3# controls writes to D27:D35

5. BW0# controls writes to D0:D8

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Table 4:

Ball Descriptions

SYMBOL TYPE

DESCRIPTION

BW_#

Input Synchronous Byte Writes: When LOW, these inputs cause their respective bytes to be registered and

written if W# had initiated a WRITE cycle. These signals must meet setup and hold times around the

rising edges of K and K# for each of the four rising edges comprising the WRITE cycle. See Ball Layout

figures for signal to data relationships.

C

C#

Input Output Clock: This clock pair provides a user-controlled means of tuning device output data. The rising

edge of C# is used as the output timing reference for first output data. The rising edge of C is used as

the output reference for second output data. Ideally, C# is 180 degrees out of phase with C. C and C#

may be tied HIGH to force the use of K and K# as the output reference clocks instead of having to

provide C and C# clocks. If tied HIGH, these inputs may not be allowed to toggle during device

operation.

D_

Input

Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and

K# during WRITE operations. See Ball Layout figures for ball site location of individual signals. The x18

device uses D0:D17, and the x36 device uses D0:D35.

K

K#

Input

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and

registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase

with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

R#

SA

Input Synchronous Read: When LOW, this input causes the address inputs to be registered and a READ cycle

to be initiated. This input must meet setup and hold times around the rising edge of K and is ignored

on the subsequent rising edge of K.

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times

around the rising edge of K. See Ball Layout figures for address expansion inputs. All transactions

operate on a burst of four words (two clock periods of bus activity). These inputs are ignored when

both ports are deselected.

TCK

Input

IEEE 1149.1 Clock Input: 2.5V I/O levels. This ball must be tied to VSS if the JTAG function is not used in

the circuit.

TMS

TDI

Input IEEE 1149.1 Test Inputs: 2.5V I/O levels. These balls may be left as No Connects if the JTAG function is

not used in the circuit.

VREF

Input

HSTL Input Reference Voltage: Nominally VDDQ/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffer trip point.

W#

Input

Synchronous Write: When LOW, this input causes the address inputs to be registered and a WRITE

cycle to be initiated. This input must meet setup and hold times around the rising edge of K and is

ignored on the subsequent rising edge of K. This input is also ignored if a READ cycle is being initiated.

ZQ

Input

Output Impedance Matching Input: This input is used to tune the device outputs to the system data

bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball to

ground. Alternately, this ball can be connected directly to VDDQ to enable the minimum impedance

mode. This ball cannot be connected directly to GND or left unconnected.

CQ#, CQ Output

Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the synchronous

data outputs and can be used as data valid indication. These signals run freely and do not stop when Q

tri-states.

Q_

Output Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K#

rising edges if C and C# are tied HIGH. This bus operates in response to R# commands. See Ball Layout

figures for ball site location of individual signals. The x18 device uses Q0:Q17, and the x36 device uses

Q0:35.

TDO

VDD

Output IEEE 1149.1 Test Output: 2.5V I/0 level.

Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range.

VDDQ

Supply Power Supply: Isolated Output Buffer Supply. Nominally, 1.5V. 1.8V is also permissible. See DC Electrical

Characteristics and Operating Conditions for range.

VSS

NC

Supply

–

Power Supply: GND.

No Connect: These balls are internally connected to the die, but have no function and may be left not

connected to the board to minimize ball count.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Figure 4:

Bus Cycle State Diagram

RD

RD & R_Count=4

always

LOAD NEW

READ ADDRESS;

R_Count=0;

R_Init=1

always

INCREMENT READ

ADDRESS BY TWO

R_Init=0

READ DOUBLE;

R_Count=R_Count+2

READ PORT NOP

R_Init=0

/RD

1

R_Count=2

Supply

voltage

/RD & R_Count=4

provided

POWER-UP

WT & R_Init=0

Supply

voltage

provided

WT & W_Count=4

always

LOAD NEW

WRITE ADDRESS;

W_Count=0

always

INCREMENT WRITE

ADDRESS BY TWO

WRITE DOUBLE;

W_Count=W_Count+2

/WT

1

WRITE PORT NOP

W_Count=2

/WT & W_Count=4

NOTE:

1. The address is concatenated with two additional internal LSBs to facilitate BURST operation. The address order is

always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. Bus cycle is terminated at the end of this sequence

(burst count = 4).

2. State transitions: RD = (R# = LOW); WT = (W# = LOW).

3. Read and write state machines can be simultaneously active. Read and write cannot be simultaneously initiated;

read takes precendence.

4. State machine, control timing sequence is controlled by K.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Table 5:

Notes 1–8

Truth Table

OPERATION

K

R#

W#

D or Q

LJH

X

L

DA(A0)

at

K(t)I

DA(A0 + 1)

at

K#(t + 1)I

DA(A0 + 2)

at

K(t+ 2)I

DA(A0 + 3)

at

K#(t + 3)I

WRITE Cycle:

Load address, input write data on

two consecutive K and K# rising

edges

LJH

L

X

QA(A0)

at

C#(t)I

QA(A0 + 1)

at

C(t + 1)I

QA(A0 + 2)

at

C#(t + 2)I

QA(A0 + 3)

at

C(t + 3)I

READ Cycle:

Load address, output data on two

consecutive C and C# rising edges

LJH

H

X

H

X

D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

NOP: No operation

Stopped

STANDBY: Clock stopped

Table 6:

Notes 9, 10

BYTE WRITE Operation

OPERATION

K

K#

BW0#

BW1#

LJH

0

1

0

1

0

1

WRITE D0–17 at K rising edge

WRITE D0–17 at K# rising edge

WRITE D0–8 at K rising edge

WRITE D0–8 at K# rising edge

WRITE D9–17 at K rising edge

WRITE D9–17 at K# rising edge

WRITE nothing at K rising edge

WRITE nothing at K# rising edge

LJH

NOTE:

1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. Iꢀmeans rising edge; Kꢀmeans falling edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C

and C# are HIGH, then data outputs are delivered at K and K# rising edges.

3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the ris-

ing edge of K.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

5. Refer to state diagram and timing diagrams for clarification. A0 refers to the initial address input during a WRITE or

READ cycle. A0+1 refers to the next internal burst address in accordance with the burst sequence.

6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by

overcoming transmission line charging symmetrically.

7. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation; however,

it is strongly recommended that this signal is brought HIGH, as shown in the truth table.

8. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecu-

tive K clock rising edges is not permitted. The device will ignore the second request.

9. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation,

provided that the setup and hold requirements are satisfied.

10.This table illustrates operation for x18 devices. The x36 device operation is similar except for the addition of BW2#

(controls D18:D26) and BW3# (controls D27:D35).

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Stresses greater than those listed under Absolute

Maximum Ratings may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other condi-

tions above those indicated in the operational sections

of this specification is not implied. Exposure to abso-

lute maximum rating conditions for extended periods

may affect reliability.

Absolute Maximum Ratings

Voltage on VDD Supply Relative to VSS.....-0.5V to +3.4V

Voltage on VDDQ Supply

Relative to VSS ....................................... -0.5V to +VDD

VIN ...................................................... -0.5V to VDD +0.5V

Storage Temperature..............................-55ºC to +125ºC

Junction Temperature .......................................... +125ºC

Short Circuit Output Current .............................. 70mA

Maximum Junction Temperature depends upon

package type, cycle time, loading, ambient tempera-

ture, and airflow.

Table 7:

DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 14; 0°C ? T_A? +70°C; VDD = 2.5V 0.1V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

VIH(DC)

VIL(DC)

VIN

MIN

VREF + 0.1

-0.3

MAX

VDDQ + 0.3

VREF - 0.1

VDDQ + 0.3

5

UNITS NOTES

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Clock Input Signal Voltage

Input Leakage Current

Output Leakage Current

V

3, 4

-0.3

V

0V ? VIN ? VDDQ

ILI

-5

µA

Output(s) disabled,

ILO

-5

5

0V ? VIN ? VDDQ (Q)

Output High Voltage

Output Low Voltage

|IOH| ? 0.1mA

Note 1

VOH (LOW)

VOH

VDDQ - 0.2

VDDQ

V

3, 5, 6

3

VDDQ/2 - 0.12 VDDQ/2 + 0.12

VSS 0.2

VDDQ/2 - 0.12 VDDQ/2 + 0.12

IOL ? 0.1mA

Note 2

VOL (LOW)

VOL

VDD

2.4

1.4

2.6

1.9

Supply Voltage

VDDQ

VREF

3, 7

Isolated Output Buffer Supply

Reference Voltage

0.68

0.95

3

Table 8:

AC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 14; 0°C ? T_A? +70°C; VDD = 2.5V 0.1V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

VIH(AC)

MIN

VREF + 0.2

-

MAX

-

UNITS NOTES

V

3, 4, 8

Input High (Logic 1) Voltage

Input Low (Logic 1) Voltage

VIL(AC)

VREF - 0.2

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

.

Table 9:

IDD Operating Conditions and Maximum Limits

Notes appear following parameter tables on page 14; 0°C ? T_A? +70°C; VDD = 2.5V 0.1V unless otherwise noted

MAX

DESCRIPTION

CONDITIONS

SYM

TYP

-5

-6

-7.5

-10

UNITS NOTES

Operating Supply

Current: DDR

All inputs ? VIL or O VIH; Cycle time

t

Oꢀ KHKH (MIN); Outputs open;

TBD

mA

8, 10

100% bus utilization; 50% address

and data bits toggling on each

clock cycle

IDD

x18

x36

300

410

250

350

230

300

200

260

^tKHKH = ^tKHKH (MIN);

Device in NOP state;

All addresses/data static

ISB1

x18

x36

Standby Supply

Current: NOP

TBD

mA

10, 11

10

170

180

145

155

125

135

110

120

Cycle time = 0;

Input Static

Stop Clock Current

ISB

75

Output Supply

Current: DDR

(Information only)

IDDQ

x18

x36

C_L= 15pF

25

57

21

47

17

38

13

19

12

Table 10: Capacitance

Note 13; notes appear following parameter tables on page 14

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

CI

4.5

6

5.5

7

pF

Address/Control Input Capacitance

Output Capacitance (Q)

Clock Capacitance

T_A= 25ºC; f = 1 MHz

CO

CCK

5.5

6.5

Table 11: Thermal Resistance

Note 13; notes appear following parameter tables on page 14

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

NOTES

Junction to Ambient

(Airflow of 1m/s)

ꢁ_JA

19.4

ºC/W

14

Soldered on a 4.25 x 1.125 inch,

4-layer printed circuit board

ꢁ_JC

1.0

9.6

ºC/W

Junction to Case (Top)

Junction to Balls (Bottom)

ꢁ

15

JB

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Table 12: AC Electrical Characteristics and Recommended Operating Conditions

Notes 13, 16–19, notes appear following paramater tables on page 14; °C ? T_A? +70°C; T_J? +95°C; VDD = 2.5V 0.1V

-5

-6

-7.5

-10

DESCRIPTION

SYM

MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES

Clock

^tKHKH

^tKHKL

^tKLKH

Clock cycle time (K, K#, C, C#)

5.0

2.0

6.0

2.4

7.5

3.0

10

3.5

ns

Clock HIGH time (K, K#, C, C#)

Clock LOW time (K, K#, C, C#)

Clock to clock# (KIJK#I,

CIJC#I)

Clock# to clock (K#IJKI,

C#IJCI)

Clock to data clock (KIJCI,

K#IJC#I)

^tKHK#H

^tK#HKH

^tKHCH

2.4

0.0

2.7

0.0

3.4

4.6

0.0

ns

1.5

2.00

0.04

2.5

3.0

Output Times

^tCHQV

^tCHQX

^tCHQZ

^tCHQX1

^tCHCQH

^tCQHQV

^tCQHQX

^tCQHQZ

^tCQHQX1

C, C# HIGH to output valid

2.2

2.5

3.0

ns

C, C# HIGH to output hold

C HIGH to output High-Z

C HIGH to output Low-Z

1.2

20

1.2

C, C# HIGH to CQ, CQ# HIGH

CQ, CQ# HIGH to output valid

CQ, CQ# HIGH to output hold

CQ HIGH to output High-Z

CQ HIGH to output Low-Z

2.3

2.6

3.2

0.35

0.40

0.45

0.50

-0.35

-0.40

-0.45

-0.50

0.35

0.40

0.45

0.50

20

Setup Times

^tAVKH

^tIVKH

Address valid to K rising edge

0.6

0.7

0.8

1.0

ns

16

Control inputs valid to K rising

edge

Data-in valid to K, K# rising

edge

^tDVKH

0.6

0.7

0.8

1.0

ns

Hold Times

^tKHAX

^tKHIX

K rising edge to address hold

0.6

0.7

0.8

1.0

ns

16

K rising edge to control inputs

hold

K, K# rising edge to data-in

hold

^tKHDX

0.6

0.7

0.8

1.0

ns

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Notes

1. Outputs are impedance-controlled. |IOH|

=

10. Typical values are measured at VDD =2.5V, VDDQ =

1.5V, and temperature = 25°C.

11. NOP currents are valid when entering NOP after

all pending READ and WRITE cycles are com-

pleted.

12. Average I/O current and power is provided for

informational purposes only and is not tested.

Calculation assumes that all outputs are loaded

with CL (in farads), f = input clock frequency, half

of outputs toggle at each transition (n = 18 for the

x36), CO = 6pF, VDDQ = 1.5V and uses the equa-

tions: Average I/O Power as dissipated by the

SRAM is: P = 0.5 × n × f × VDDQ²x (CL + 2CO).

Average IDDQ = n × f × VDDQ x (CL + CO).

13. This parameter is sampled.

14. Average thermal resistance between the die and

the case top surface per MIL SPEC 883 Method

1012.1.

15. Junction temperature is a function of total device

power dissipation and device mounting environ-

ment. Measured per SEMI G38-87.8.

16. This is a synchronous device. All addresses, data,

and control lines must meet the specified setup

and hold times for all latching clock edges.

17. Test conditons specified with the output loading,

as shown in Figure 5 unless otherwise noted.

18. Control input signals may not be operated with

(VDDQ/2)/(RQ/5) for values of 175ꢀ ? RQ ? 350ꢀꢁ.

2. Outputs are impedance-controlled. IOL = (VDDQ/

2)/(RQ/5) for values of 175ꢀ ? RQ ? 350ꢀꢁ.

3. All voltages referenced to Vss (GND).

t

4. Overshoot: VIH(AC) ? VDD + 0.7V for t ? KHKH/2

t

Undershoot:VIL(AC) O -0.5V for t ? KHKH/2

Power-up: VIH ? VDDQ + 0.3V and VDD ? 2.4V

and VDDQ ? 1.4V for t ? 200ms

During normal operation, VDDQ must not exceed

VDD. R#, W#, and address signals may not have

t

pulse widths less than KHKL (MIN) or operate at

cycle rates less than ^tKHKH (MIN).

5. AC load current is higher than the shown DC val-

ues. AC I/O curves are available upon request.

6. HSTL outputs meet JEDEC HSTL Class I and Class

II standards.

7. The nominal value of VDDQ may be set within the

range of 1.5V to 1.8V DC, and the variation of

VDDQ must be limited to 0.1V DC.

8. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current AC

level through the target AC level, VIL(AC) or

VIH(AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to

maintain at least the target DC level, VIL(DC) or

VIH(DC).

pulse widths less than ^tKHKL (MIN).

19. If C and C# are tied HIGH, then K and K# become

the references for C and C# timing parameters.

9. IDD is specified with no output current and

increases with faster cycle times. IDD increases

with faster cycle times and greater output loading.

Typical value is measured at 6ns cycle time.

t

20. ^tCHQX1 is greater than CHQZ at any given volt-

age and temperature.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

AC Test Conditions

Figure 5:

Output Load Equivalent

Input pulse levels ................................ 0.25V to 1.25V

Input rise and fall times...................................... 0.7ns

Input timing reference levels .............................0.75V

Output reference levels...................................VDDQ/2

ZQ for 50ꢀ impedance...........................................250ꢀ

Output load ..............................................See Figure 5

0.75V

VDDQ/2

VREF

50Ω

Z_O= 50Ω

SRAM

250Ω

ZQ

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Figure 6:

READ/WRITE Timing

NOP

READ

WRITE

READ

WRITE

NOP

1

7

2

3

4

5

6

K

t

KHKL KLKH

KHKH

KHK#H

K#

R#

t

IVKH

KHIX

IVKH KHIX

W#

A

A0

A1

A2

A3

t

KHDX

t

AVKH KHAX

t

DVKH

D

Q

D30

D31

D32

Q23

D33

D10

Q01

D11

Q02

D12

D13

Qx2

Q00

Q03

Q20

Q21

Q22

t

KHCH

t

CHQV

CHQX

CHQZ

t

CQHQV

t

CHQX1

CHQX

CHQZ

t

CHQV

CQHQX

C

t

KHCH

KHKH

KHKL KLKH

t

KHK#H

C#

t

CHCQV

t

CHCQX

CQ

t

CHCQV

t

CHCQX

CQ#

t

CQHQX1

DON’T CARE

UNDEFINED

NOTE:

1. Q00 refers to output from address A0 + 1. Q01 refers to output from the next internal burst address following

A0, i.e., A0 + 1.

2. Outputs are disabled (High-Z) one clock cycle after a NOP.

3. In this example, if address A2 ꢂ A1, then data Q20 = D10, Q21 = D11, Q22 = D12, Q23 = D13. Write data is forwarded

immediately as read results. (This note applies to whole diagram.)

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

IEEE 1149.1 Serial Boundary Scan

(JTAG)

Figure 7:

TAP Controller State Diagram

The SRAM incorporates a serial boundary scan test

access port (TAP). This port operates in accordance

with IEEE Standard 1149.1-1990 but does not have the

set of functions required for full 1149.1 compliance.

These functions from the IEEE specification are

excluded because their inclusion places an added

delay in the critical speed path of the SRAM. Note that

the TAP controller functions in a manner that does not

conflict with the operation of other devices using

1149.1 fully-compliant TAPs. The TAP operates using

JEDEC-standard 2.5V I/O logic levels.

TEST-LOGIC

RESET

1

0

1

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

CAPTURE-IR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

EXIT1-IR

The SRAM contains a TAP controller, instruction

register, boundary scan register, bypass register, and

ID register.

0

PAUSE-DR

1

0

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

Disabling the JTAG Feature

It is possible to operate the SRAM without using the

JTAG feature. To disable the TAP controller, TCK must

be tied LOW (VSS) to prevent clocking of the device.

TDI and TMS are internally pulled up and may be

unconnected. Alternately, they may be connected to

VDD through a pull-up resistor. TDO should be left

unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the opera-

tion of the device.

UPDATE-DR

UPDATE-IR

1

0

1

0

NOTE:

The 0/1 next to each state represents the value

of TMS at the rising edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It

is allowable to leave this ball unconnected if the TAP is

not used. The ball is pulled up internally, resulting in a

logic HIGH level.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller.

All inputs are captured on the rising edge of TCK. All

outputs are driven from the falling edge of TCK.

Test Data-In (TDI)

The TDI ball is used to serially input information

into the registers and can be connected to the input of

any of the registers. The register between TDI and TDO

is chosen by the instruction that is loaded into the TAP

instruction register. For information on loading the

instruction register, see Figure 7. TDI is pulled up

internally and can be unconnected if the TAP is

unused in an application. TDI is connected to the most

significant bit (MSB) of any register, as illustrated in

Figure 8.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-

out from the registers. The output is active depending

upon the current state of the TAP state machine, as

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

17

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

illustrated in Figure 7. The output changes on the fall-

ing edge of TCK. TDO is connected to the least signifi

cant bit (LSB) of any register, as depicted in Figure 8.

Figure 8:

TAP Controller Block Diagram

0

Performing a TAP RESET

Bypass Register

A RESET is performed by forcing TMS HIGH (VDD)

for five rising edges of TCK. This RESET does not affect

the operation of the SRAM and may be performed

while the SRAM is operating.

2

1 0

Selection

Circuitry

Selection

Circuitry

Instruction Register

31 30 29

Identification Register

TDI

TDO

.

. 2 1 0

At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

x

.

. 2 1 0

Boundary Scan Register

TAP Registers

TCK

TMS

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the

SRAM test circuitry. Only one register can be selected

at a time through the instruction register. Data is seri-

ally loaded into the TDI ball on the rising edge of TCK.

Data is output on the TDO ball on the falling edge of

TCK.

TAP CONTROLLER

NOTE:

X = 106.

Boundary Scan Register

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. The SRAM

has a 107-bit-long register.

Instruction Register

Three-bit instructions can be serially loaded into

the instruction register. This register is loaded when it

is placed between the TDI and TDO balls, as shown in

Figure 8. Upon power-up, the instruction register is

loaded with the IDCODE instruction. It is also loaded

with the IDCODE instruction if the controller is placed

in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state,

the two LSBs are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test

data path.

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in

the Capture-DR state and is then placed between the

TDI and TDO balls when the controller is moved to the

Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and

SAMPLE Z instructions can be used to capture the

contents of the I/O ring.

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to

one of the balls on the SRAM package. The MSB of the

register is connected to TDI, and the LSB is connected

to TDO.

Bypass Register

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain

chips. The bypass register is a single-bit register that

can be placed between the TDI and TDO balls. This

allows data to be shifted through the SRAM with mini-

mal delay. The bypass register is set LOW (Vss) when

the BYPASS instruction is executed.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the

IDCODE command is loaded in the instruction regis-

ter. The IDCODE is hardwired into the SRAM and can

be shifted out when the TAP controller is in the Shift-

DR state. The ID register has a vendor code and other

information described in the Identification Register

Definitions table.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

18

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

and TDO balls and allows the IDCODE to be shifted

out of the device when the TAP controller enters the

Shift-DR state. The IDCODE instruction is loaded into

the instruction register upon power-up or whenever

the TAP controller is given a test logic reset state.

TAP Instruction Set

Overview

Eight different instructions are possible with the

three-bit instruction register. All combinations are

listed in the Instruction Codes table. Three of these

instructions are listed as RESERVED and should not be

used. The other five instructions are described in detail

below.

SAMPLE Z

The SAMPLE Z instruction causes the boundary

scan register to be connected between the TDI and

TDO balls when the TAP controller is in a Shift-DR

state. It also places all SRAM outputs into a High-Z

state.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of

the mandatory 1149.1 instructions are not fully imple-

mented. The TAP controller cannot be used to load

address, data or control signals into the SRAM and

cannot preload the I/O buffers. The SRAM does not

implement the 1149.1 commands EXTEST or INTEST

or the PRELOAD portion of SAMPLE/PRELOAD;

rather, it performs a capture of the I/O ring when these

instructions are executed.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not

implemented, so the device TAP controller is not fully

1149.1-compliant.

Note that since the PRELOAD part of the command

is not implemented, putting the TAP into the Update-

DR state while performing a SAMPLE/PRELOAD

instruction will have the same effect as the Pause-DR

command.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is

to be executed whenever the instruction register is

loaded with all 0s. EXTEST is not implemented in this

SRAM TAP controller; therefore, this device is not

1149.1-compliant.

BYPASS

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the

instruction register, the SRAM responds as if a

SAMPLE/PRELOAD instruction has been loaded.

EXTEST does not place the SRAM outputs (including

CQ and CQ#) in a High-Z state.

When the BYPASS instruction is loaded in the

instruction register and the TAP is placed in a Shift-DR

state, the bypass register is placed between the TDI

and TDO balls. The advantage of the BYPASS instruc-

tion is that it shortens the boundary scan path when

multiple devices are connected together on a board.

IDCODE

Reserved

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It

also places the instruction register between the TDI

These instructions are not implemented but are

reserved for future use. Do not use these instructions.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

19

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Figure 9: TAP Timing

1

2

3

4

5

6

Test Clock

(TCK)

t

THTH

THTL

TLTH

t

MVTH

DVTH

THMX

Test Mode Select

(TMS)

t

THDX

Test Data-In

(TDI)

t

TLOV

t

TLOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

NOTE:

Timing for SRAM inputs and outputs is congruent with TDI and TDO, respectively, as shown in Figure 9.

Table 13: TAP DC Electrical Characteristics

Notes 1, 2; 0°C ? T_A? +70°C; VDD = 2.5V 0.1V

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock

^tTHTH

^fTF

^tTHTL

^tTLTH

Clock cycle time

100

ns

MHz

ns

10

Clock frequency

Clock HIGH time

Clock LOW time

40

ns

Output Times

^tTLOX

^tTLOV

^tDVTH

^tTHDX

0

ns

TCK LOW to TDO unknown

20

TCK LOW to TDO valid

TDI valid to TCK HIGH

TCK HIGH to TDI invalid

10

Setup Times

^tMVTH

^tCS

10

ns

TMS setup

Capture setup

Hold Times

^tTHMX

^tCH

10

ns

TMS hold

Capture hold

NOTE:

t

1. CS and ^tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the load in Figure 10.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

20

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

TAP AC Test Conditions

Figure 10:

TAP AC Output Load Equivalent

Input pulse levels........................................VSS to 1.8V

Input rise and fall times .........................................1ns

Input timing reference levels............................... 0.9V

Output reference levels........................................ 0.9V

Test load termination supply voltage ................. 0.9V

0.9V

50Ω

TDO

Z_O= 50Ω

20pF

Table 14: TAP DC Electrical Characteristics and Operating Conditions

Note 2; 0°C ? T_A? +70°C; VDD = 2.5V 0.1V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

VIH

VIL

1.7

VDD + 0.3

0.7

V

1, 2

Input High (Logic 1) Voltage

-0.3

Input Low (Logic 0) Voltage

Input Leakage Current

0V ? VIN ? VDD

ILI

-5.0

5.0

µA

2

Output(s) disabled,

ILO

Output Leakage Current

0V ? VIN ? VDD

IOLC = 100µA

IOLT = 2mA

VOL1

VOL2

VOH1

0.2

0.4

V

1, 2

Output Low Voltage

Output High Voltage

IOHC = -100µA

IOHT = -2mA

2.1

1.7

NOTE:

1. All voltages referenced to VSS (GND).

2. This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have

the DC values as defined in Table 7, “DC Electrical Characteristics and Operating Conditions,” on page 11.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

21

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Table 15: Identification Register Definitions

INSTRUCTION FIELD

ALL DEVICES

DESCRIPTION

REVISION NUMBER (31:28)

DEVICE ID (28:12)

000

Revision number.

00def0wx0t0q0b0s0 def = 010 for 36Mb density

def = 001 for 18Mb density

wx = 11 for x36 width

wx = 10 for x18 width

wx = 01 for x8 width

t = 1 for DLL version

t = 0 for non-DLL version

q = 1 for QDR

q = 0 for DDR

b = 1 for 4-word burst

b = 0 for 2-word burst

s = 1 for separate I/O

s = 0 for common I/O

MICRON JEDEC ID CODE

(11:1)

00000101100

1

Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

ID Register Presence

Indicator (0)

Table 16: Scan Register Sizes

REGISTER NAME

BIT SIZE

Instruction

Bypass

3

1

ID

32

107

Boundary Scan

Table 17: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

000

EXTEST

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This

instruction is not 1149.1-compliant.

001

010

IDCODE

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM output drivers to a High-Z state.

011

100

RESERVED

Do Not Use: This instruction is reserved for future use.

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This

instruction does not implement 1149.1 preload function and is therefore not 1149.1-

compliant.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

22

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Table 18: Boundary Scan (Exit) Order

BIT#

FBGA BALL

BIT#

FBGA BALL

BIT#

FBGA BALL

1

6R

6P

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

10D

9E

73

74

2C

3E

2D

2E

1E

2F

2

3

6N

10C

11D

9C

75

4

7P

76

5

7N

77

6

7R

9D

11B

11C

9B

78

7

8R

79

3F

8

8P

80

1G

1F

9

9R

81

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

11P

10P

10N

9P

10B

11A

10A

9A

8B

82

3G

2G

1J

83

84

85

2J

10M

11N

9M

9N

86

3K

3J

7C

87

6C

88

2K

1K

2L

8A

7A

7B

89

11L

11M

9L

90

91

3L

6B

92

1M

1L

10L

11K

10K

9J

6A

5B

93

94

3N

3M

1N

2M

3P

2N

2P

1P

3R

4R

4P

5P

5N

5R

5A

4A

5C

95

96

9K

97

10J

11J

11H

10G

9G

4B

98

3A

2A

1A

2B

99

100

101

102

103

104

105

106

107

11F

11G

9F

3B

1C

1B

10F

11E

10E

3D

3C

1D

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

23

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Figure 11:

165-Ball FBGA

0.85 0.075

0.12

C

SEATING PLANE

C

BALL A11

165X Ø 0.45

10.00

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION. THE

PRE-REFLOW DIAMETER IS Ø 0.40

BALL A1

PIN A1 ID

1.20 MAX

1.00

TYP

PIN A1 ID

7.50 0.05

14.00

15.00 0.10

7.00 0.05

1.00

TYP

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 0.05

5.00 0.05

13.00 0.10

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb

SOLDER BALL PAD: Ø .33mm

NOTE:

1. All dimensions are in millimeters.

2. Molding dimensions do not include protrusion; allowable mold protrusion is 0.25mm per side.

Data Sheet Designation

No Marking: This data sheet contains minimum and maximum limits specified over the complete power

supply and temperature range for production devices. Although considered final, these specifications are sub-

ject to change, as further product development and data characterization sometimes occur.

®

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.,

NEC, and Samsung.

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

24

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb4 SRAM

Document Revision History

Rev. F, Pub 3/03................................................................................................................................................................3/03

•

Updated JTAG Section

Removed Preliminary Status

Rev. E, Pub 2/03 ...............................................................................................................................................................2/03

•

Added definitive notes to Figure 3

Added definitive note to Table 9

Updated Truth Table for clarity

Added 1.5V references

Update READ/WRITE Timing Diagram

Updated JTAG section to reflect 1149.1 specification compliance with EXTEST features

Updated JTAG description to reflect 1149.1 specification compliance with EXTEST feature

Added definitive note concerning SRAM (DQ) I/O balls used for JTAG DC values and timing

Changed process information in header to die revision indicator

Updated Thermal Resistance Values to Table 12:

CI = 4.5 TYP; 5.5 MAX

CO = 6 TYP; 7 MAX

CCK = 5.5 TYP; 6.5 MAX

•

Updated Thermal Resistance values to Table 12:

JA = 19.4 TYP

JC = 1.0 TYP

JB = 9.6 TYP

Added T_J? +95°C to Table 13

•

Modified Figure 2 regarding depth, configuration, and byte controls

Added definitive notes regarding I/O behavior during JTAG operation

Added definitive notes regarding IDD test conditions for read to write ratio

Removed note regarding AC derating information for full I/O range

Remove references to JTAG scan chain logic levels being at logic zero for NC pins in Tables 5 and 19

Revised ball description for NC balls:

These balls are internally connected to the die, but have no function and may be left not connected to the

board to minimize ball count.

Rev. D, Pub 6/02...............................................................................................................................................................6/02

•

Removed ADVANCE designation

Added CQ, CQ# to Ball Description table on page 5

Added note 10 on page 8

Deleted note 6 on page 9

Revised note 5 on page 10

Added “t” and description to Device ID code

Deleted Boundary Scan (Exit) Order note on page 20

Rev. C, Pub. 5/02, ADVANCE...........................................................................................................................................5/02

Fixed voltage range error in AC Electrical Characteristics and Operating Conditions table

•

Rev. B, Pub. 5/02, ADVANCE...........................................................................................................................................8/02

•

Updated DC Electrical Characteristics and Operating Conditions table

Added AC Electrical Characteristics and Operating Conditions table

Rev. A, Pub. 4/02, ADVANCE...........................................................................................................................................4/02

New ADVANCE data sheet

•

18Mb: 2.5V VDD, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

25


型号：	MT54V512H36EF-10
厂家：	CYPRESS
描述：	QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 静态存储器
文件：	总25页 (文件大小：387K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT54V512H36EF-10 [CYPRESS]

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