MT58L256L18F1B-10 [CYPRESS]
Standard SRAM, 256KX18, 10ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119;型号: | MT58L256L18F1B-10 |
厂家: | CYPRESS |
描述: | Standard SRAM, 256KX18, 10ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119 静态存储器 |
文件: | 总31页 (文件大小:349K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
4Mb SYNCBURST™
SRAM
MT58L256L18F1, MT58L128L32F1,
MT58L128L36F1; MT58L256V18F1,
MT58L128V32F1, MT58L128V36F1
3.3V VDD, 3.3V o r 2.5V I/O, Flo w -Th ro u g h
FEATURES
1
• Fast clock an d OE# access tim es
• Sin gle +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
100-Pin TQFP
• SNOOZE MODE for reduced-power stan dby
• Com m on data in puts an d data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Th ree ch ip en ables for sim ple depth expan sion
an d address pipelin in g
• Clock-con trolled an d registered addresses, data
I/Os an d con trol sign als
• In tern ally self-tim ed WRITE cycle
• Burst con trol pin (in terleaved or lin ear burst)
• Autom atic power-down
• 165-pin FBGA package
• 100-pin TQFP package
• 119-pin BGA package
• Low capacitive bus loadin g
165-Pin FBGA
(Preliminary Package Data)
• x18, x32, an d x36 version s available
OPTIONS
MARKING
• Tim in g (Access/Cycle/MHz)
6.8n s/7.5n s/133 MHz
7.5n s/8.8n s/113 MHz
8.5n s/10n s/100 MHz
10n s/15n s/66 MHz
-6.8
-7.5
-8.5
-10
• Con figuration s
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
MT58L256L18F1
MT58L128L32F1
MT58L128L36F1
2
119-Pin BGA
256K x 18
128K x 32
128K x 36
MT58L256V18F1
MT58L128V32F1
MT58L128V36F1
• Packages
100-pin TQFP
165-pin FBGA
119-pin , 14m m x 22m m BGA
T
F*
B
• Operatin g Tem perature Ran ge
Com m ercial (0°C to +70°C)
In dustrial (-40°C to +85°C)**
Non e
IT
Part Number Example:
MT58L256L18F1T-8.5
* A Part Markin g Guide for th e FBGA devices can be foun d on Micron ’s
Web site—h ttp://www.m icron .com /support/in dex.h tm l.
** In dustrial tem perature ran ge offered in specific speed grades an d
con figuration s. Con tact factory for m ore in form ation .
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA(PBGA).
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
1
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 18
18
16
18
18
2
ADDRESS
REGISTER
SA0, SA1, SA
MODE
SA0-SA1
Q1
SA1'
SA0'
ADV#
CLK
BINARY
COUNTER AND
LOGIC
CLR
Q0
ADSC#
ADSP#
BYTE “b”
WRITE DRIVER
BYTE “b”
WRITE REGISTER
9
9
9
9
DQs
DQPa
DQPb
BWb#
256K x 9 x 2
MEMORY
ARRAY
OUTPUT
BUFFERS
SENSE
AMPS
18
18
18
BYTE “a”
WRITE DRIVER
BYTE “a”
WRITE REGISTER
BWa#
BWE#
INPUT
GW#
18
REGISTERS
ENABLE
REGISTER
CE#
CE2
CE2#
2
OE#
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
17
15
17
17
ADDRESS
SA0, SA1, SA
MODE
REGISTER
SA0-SA1
Q1
Q0
ADV#
CLK
BINARY
COUNTER
AND LOGIC
SA1'
SA0'
CLR
ADSC#
ADSP#
BYTE “d”
BYTE “d”
9
9
BWd#
9
9
WRITE DRIVER
WRITE REGISTER
128K x 8 x 4
(x32)
BYTE “c”
BYTE “c”
BWc#
DQs
WRITE DRIVER
WRITE REGISTER
DQPa
OUTPUT
BUFFERS
128K x 9 x 4
(x36)
SENSE 36
AMPS
36
36
BYTE “b”
MEMORY
ARRAY
9
9
BYTE “b”
9
9
BWb#
DQPd
WRITE DRIVER
WRITE REGISTER
BYTE “a”
BYTE “a”
BWa#
BWE#
WRITE DRIVER
WRITE REGISTER
INPUT
REGISTERS
GW#
36
ENABLE
REGISTER
CE#
CE2
CE2#
OE#
4
NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams
for detailed information.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
2
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
GENERALDESCRIPTION
Th e Micron ® Syn cBurst™ SRAM fam ily em ploys
h igh -speed, low-power CMOS design s th at are fabri-
cated usin g an advan ced CMOS process.
in tern ally gen erated as con trolled by th e burst advan ce
in put (ADV#).
Address an d write con trol are registered on -ch ip to
sim plify WRITE cycles. Th is allows self-tim ed WRITE
cycles. In dividual byte en ables allow in dividual bytes
to be written . Durin g WRITE cycles on th e x18 device,
BWa# con trols DQa pin s an d DQPa; BWb# con trols
DQb pin s an d DQPb. Durin g WRITE cycles on th e x32
an d x36 devices, BWa# con trols DQa pin s an d DQPa;
BWb# con trols DQb pin s an d DQPb; BWc# con trols
DQc pin s an d DQPc; BWd# con trols DQd pin s an d
DQPd. GW# LOW causes all bytes to be written . Parity
bits are on ly available on th e x18 an d x36 version s.
Micron ’s 4Mb Syn cBurst SRAMs operate from a
+3.3V VDD power supply, an d all in puts an d outputs are
TTL-com patible. Users can ch oose eith er a 2.5V or 3.3V
I/O version . Th e device is ideally suited for 486,
Pen tium ®, an d PowerPC system s an d th ose system s
th at ben efit from a wide syn ch ron ous data bus. Th e
device is also ideal in gen eric 16-, 18-, 32-, 36-, 64-, an d
72-bit-wide application s.
Micron ’s 4Mb Syn cBurst SRAMs in tegrate a 256K x
18, 128K x 32, or 128K x 36 SRAM core with advan ced
synchronousperipheralcircuitry and a 2-bit burst counter.
All syn ch ron ous in puts pass th rough registers con -
trolled by a positive-edge-triggered sin gle clock in put
(CLK). Th e syn ch ron ous in puts in clude all addresses, all
data in puts, active LOW ch ip en able (CE#), two addi-
tion al ch ip en ables for easy depth expan sion (CE2#,
CE2), burst con trol in puts (ADSC#, ADSP#, ADV#), byte
write en ables (BWx#) an d global write (GW#).
Asyn ch ron ous in puts in clude th e output en able
(OE#), clock (CLK) an d sn ooze en able (ZZ). Th ere is also
a burst m ode in put (MODE) th at selects between in ter-
leaved an d lin ear burst m odes. Th e data-out (Q), en -
abled by OE#, is also asyn ch ron ous. WRITE cycles can
be from on e to two bytes wide (x18) or from on e to four
bytes wide (x32/x36), as con trolled by th e write con trol
in puts.
Burst operation can be in itiated with eith er address
status processor (ADSP#) or address status con troller
(ADSC#) in puts. Subsequen t burst addresses can be
Please refer to Micron ’s Web site (www.m icron .com /
products/datash eets/syn cds.h tm l) for th e latest data
sh eet.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
x18
NC
NC
NC
x32/x36
NC/DQPc*
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
VSS
VDDQ
DQd
DQd
NC/DQPd*
MODE
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa*
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
VSS
VDDQ
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
DQc
NC
NC
NC
DQa
NC
NC
SA
VDDQ
VSS
VDDQ
VSS
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
SA
SA
SA
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
VDDQ
SA
SA1
SA0
DNU
DNU
VSS
VDD
NF**
NF**
SA
DQb
DQb
DQc
DQc
VSS
VDD
NC
VSS
VSS
VDD
CE2#
BWa#
BWb#
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
VDDQ
VSS
SA
SA
SA
SA
SA
SA
VDDQ
VSS
NC
NC
BWc#
BWd#
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
CE2
CE#
SA
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
3
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
SA
ADV#
ADSP#
ADSC#
OE#
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SA
SA
SA
SA
SA
BWE#
GW#
CLK
SA
NF**
NF**
V
SS
V
DD
V
DD
V
SS
x18
CE2#
BWa#
BWb#
NC
DNU
DNU
SA0
SA1
SA
NC
CE2
SA
CE#
SA
SA
SA
SA
100
1
MODE
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
ADV#
ADSP#
ADSC#
OE#
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SA
SA
SA
SA
SA
BWE#
GW#
SA
NF**
NF**
CLK
V
SS
V
DD
V
DD
V
SS
x32/x36
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
DNU
DNU
SA0
SA1
SA
SA
CE#
SA
SA
SA
SA
100
1
MODE
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
4
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
37
36
37
36
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
32-35, 44-50, 32-35, 44-50,
80-82, 99,
100
81, 82, 99,
100
93
94
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
–
87
88
89
87
88
89
BWE#
GW#
CLK
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
98
92
97
98
92
97
CE#
CE2#
CE2
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
86
83
86
83
OE#
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
ADV#
Input Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
84
84
ADSP#
Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
5
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (co n t in u e d )
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
85
85
ADSC#
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31
64
31
64
MODE
ZZ
Input Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
(a) 58, 59,
62, 63, 68, 69, 56-59, 62, 63
72, 73
(b) 8, 9, 12,
13, 18, 19,
22, 23
(a) 52, 53,
DQa
DQb
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
Input data must meet setup and hold times around the rising edge
of CLK.
(b) 68, 69,
72-75, 78, 79
(c) 2, 3, 6-9,
12, 13
(d) 18, 19,
22-25, 28, 29
DQc
DQd
74
24
–
51
80
1
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these pins are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
–
30
15, 41, 65, 91 15, 41, 65, 91
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27,
54, 61, 70, 77 54, 61, 70, 77
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
5, 10, 14, 17, 5, 10, 14, 17,
21, 26, 40, 55, 21, 26, 40, 55,
VSS
Supply Ground: GND.
60, 67, 71,
76, 90
60, 67, 71,
76, 90
38, 39
38, 39
DNU
NC
–
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7, 16,
25, 28-30,
16, 66
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
51-53, 56, 57,
66, 75, 78, 79,
95, 96
42, 43
42, 43
NF
–
No Function: These pins are internally connected to the die and will
have the capacitance of input pins. It is allowable to leave these
pins unconnected or driven by signals. Reserved for address
expansion, pin 43 becomes an SA at 8Mb density and pin 42
becomes an SA at 16Mb density.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
6
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
PIN LAYOUT (TOP VIEW)
165-PIN FBGA
x18
x32/x36
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
A
B
C
D
E
F
A
B
C
D
E
F
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
SA
SA
CE# BWb#
NC
CE2# BWE# ADSC# ADV#
SA
SA
SA
NC
NC
NC
SA
SA
CE# BWc# BWb# CE2# BWE# ADSC# ADV#
SA
SA
NC
NC
CE2
NC
BWa# CLK
GW# OE# (G#) ADSP#
CE2 BWd# BWa# CLK
GW# OE# (G#) ADSP#
NC
VDDQ
VSS
VSS
V
SS
V
SS
V
SS
V
DD
Q
Q
Q
Q
Q
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
SA
DQPa
DQa
DQa
DQa
DQa
ZZ
NF/DQPc NC
V
DD
Q
Q
Q
Q
Q
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
Q
Q
Q
Q
Q
NC NF/DQPb
DQb
DQb
DQb
DQb
V
DD
Q
Q
Q
Q
V
DD
VSS
VSS
VSS
VDD
VDD
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
VDD
VDD
VSS
VSS
VSS
VDD
VDD
DQb
DQb
DQb
DQb
NC
DQb
DQb
DQb
DQb
ZZ
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
G
H
J
G
H
J
G
H
J
G
H
J
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VSS
VSS
NC
VDD
VSS
VSS
VSS
VDD
NC
VSS
VSS
NC
VDD
VSS
VSS
VSS
VDD
NC
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
NC
NC
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
K
L
M
N
P
K
L
M
N
P
K
L
M
N
P
K
L
M
N
P
V
DD
Q
Q
Q
Q
V
DD
VSS
V
SS
V
SS
V
DD
V
DD
Q
Q
Q
Q
NC
V
DD
Q
Q
Q
Q
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
Q
Q
Q
Q
VDD
VDD
VSS
VSS
VSS
VDD
VDD
NC
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
NC
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
V
SS
NC
NC
SA1
SA0
VSS
V
SS
VDD
NC
NF/DQPd NC
VDD
V
SS
NC
NC
SA1
SA0
VSS
V
SS
VDD
NC NF/DQPa
SA
SA
SA
SA
DNU
DNU
DNU
DNU
SA
SA
SA
SA
SA
NC
NC
SA
SA
SA
SA
DNU
DNU
DNU
DNU
SA
SA
SA
SA
SA
SA
SA
SA
R
R
R
R
MODE NC
(LBO#)
SA
SA
MODE NC
(LBO#)
TOP VIEW
TOP VIEW
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
NOTE: Pins 11P, and 6N reserved for address pin expansion; 8Mb, and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
7
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
6R
6P
6R
6P
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
2A, 2B, 3P,
3R, 4P, 4R,
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P, 9R, 8P, 8R, 9P,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
5B
4A
–
5B
5A
4A
4B
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
–
7A
7B
6B
7A
7B
6B
BWE#
GW#
CLK
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
3A
6A
3A
6A
CE#
CE2#
ZZ
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
11H
11H
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
3B
3B
CE2
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
8B
9A
8B
9A
OE#(G#)
ADV#
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
Input Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
8
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (co n t in u e d )
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
9B
9B
ADSP#
Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
8A
8A
ADSC#
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
1R
1R
MODE
(LB0#)
Input Mode: This input selects the burst sequence. A LOW on this input
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b) 1J, 1K,
1L, 1M, 2D, 10F, 10G, 11D,
(a) 10J, 10K,
DQa
DQb
DQc
DQd
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;
Output Byte “b” is associated with DQbs. For the x32 and x36 versions,
Byte “a” is associated with DQas; Byte “b” is associated with DQbs;
Byte “c” is associated with DQcs; Byte “d” is associated with DQds.
Input data must meet setup and hold times around the rising edge
of CLK.
(b) 10D, 10E,
2E, 2F, 2G
11E, 11F, 11G
(c) 1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d) 1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
11C
1N
–
11N
11C
1C
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
–
1N
4D, 4E, 4F,
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
4D, 4E, 4F,
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
9
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (co n t in u e d )
x18
x32/x36
SYMBOL TYPE
Supply Ground: GND.
DESCRIPTION
1H, 2H, 4C, 4N, 1H, 2H, 4C, 4N,
5C, 5D, 5E 5F, 5C, 5D, 5E 5F,
5G, 5H, 5J, 5K, 5G, 5H, 5J, 5K,
5L, 5M, 6C, 6D, 5L, 5M, 6C, 6D,
6E, 6F, 6G, 6H, 6E, 6F, 6G, 6H,
6J, 6K, 6L, 6M, 6J, 6K, 6L, 6M,
7C, 7D, 7E, 7F, 7C, 7D, 7E, 7F,
VSS
7G, 7H, 7J,
7K, 7L, 7M,
7N, 8C, 8N
7G, 7H, 7J,
7K, 7J, 7M,
7N, 8C, 8N
5P, 5R, 7P, 7R 5P, 5R, 7P, 7R
DNU
NC
–
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1A, 1B, 1C,
1D, 1E, 1F,
1G, 1P, 2C,
2J, 2K,
1A, 1B, 1P,
2C, 2N,
2P, 2R, 3H,
5N, 6N,
No Connect: These signals are not internally connected and may
be connected to ground to improve package heat dissipation.
Pins 11P, and 6N reserved for address pin expansion; 8Mb, and
16Mb respectively.
2L, 2M, 2N,
2P, 2R, 3H,
4B, 5A, 5N,
6N, 9H, 10C,
10D, 10E, 10F,
10G, 10H,
10N, 11B,
9H, 10C,
10H, 10N,
11A, 11B,
11P
11J, 11K,
11L, 11M,
11N, 11P,
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
10
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
PIN LAYOUT (TOP VIEW)
119-PIN BGA
x18
x32/x36
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
F
A
B
C
D
E
F
V
DD
Q
SA
SA ADSP#
SA
SA
SA
VDDQ
V
DD
Q
SA
CE2**
SA
SA
SA
SA
ADSP#
ADSC#
SA
SA
SA
SA
SA
SA
VDDQ
NC CE2**
SA ADSC# SA
NC
NC
NC
NC
NC
NC
NC
DQb
NC
SA
NC
SA
VDD
SA
SA
VDD
V
SS
NC
CE#
OE#
VSS
DQPa
NC
NC
DQc NF/DQPc*
VSS
NC
CE#
OE#
VSS NF/DQPb* DQb
DQb
NC
VSS
VSS
DQa
DQc
DQc
DQc
VSS
VSS
DQb
DQb
DQb
VDD
Q
VSS
VSS
DQa
NC
V
DD
DQa
NC
Q
VDD
Q
VSS
VSS
VDDQ
G
H
J
G
H
J
NC
DQb BWb# ADV#
VSS
DQc
DQc
DQc BWc# ADV# BWb# DQb
DQb
DQb
DQb
NC
VSS
GW#
VSS
DQa
DQc
VSS
GW#
VSS
DQb
V
DD
Q
V
DD
DQb
NC
NC
V
DD
NC
V
DD
V
DD
DQa
NC
Q
V
DD
Q
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
L
M
N
P
K
L
M
N
P
NC
VSS
CLK
NC
VSS
NC
DQd
DQd
DQd
VSS
CLK
NC
VSS
DQa
DQa
DQa
DQb
VSS
BWa# DQa
DQd BWd#
BWa# DQa
V
DD
DQb
NC
Q
DQb
NC
VSS
BWE#
SA1
VSS
NC
DQa
NC
SA
V
DD
NC
DQa
NC
ZZ
Q
VDD
Q
DQd
DQd
VSS
BWE#
SA1
VSS
DQa
DQa
VDDQ
VSS
VSS
DQd
VSS
VSS
DQa
DQPb
VSS
SA0
VSS
DQd NF/DQPd*
VSS
SA0
VSS NF/DQPa* DQa
R
T
U
R
T
U
‡
VDD
‡
NC
SA MODE (LBO#)
VDD
NC
NC
SA MODE (LBO#)
VDD
VDD
SA
NC
NC
NC
ZZ
NC
SA
SA
NC
SA
SA
NC
SA
SA
SA
VDD
Q
DNU DNU DNU DNU
NC
VDDQ
VDD
Q
DNU DNU DNU DNU
VDDQ
TOP VIEW
TOP VIEW
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
NOTE: Pins 6B and 2B reserved for address pin expansion; 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
11
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
BGA PIN DESCRIPTIONS
x 1 8
x 3 2 /x 3 6
S Y M B O L TY P E
D ES CRIP TIO N
4 P
4 N
4 P
4 N
SA0
SA1
S A
In p u t Synchronous Address Inputs: These inputs are registered and
must meet the setup and hold times around the rising edge
of CLK.
2A, 3A, 5A,
6A, 3B, 5B,
2C, 3C, 5C,
6C, 2R, 6R,
2T, 3T, 5T, 6T
2A, 2C, 2R,
3A, 3B, 3C,
3T, 4T, 5A,
5B, 5C, 5T,
6A, 6C, 6R
5 L
3 G
–
5 L
5 G
3 G
3 L
BWa #
BWb #
BWc#
BWd #
In p u t Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa;
BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. Parity is only available on the x18
and x36 versions.
–
4 M
4 H
4K
4 M
4 H
4K
BWE#
GW#
CLK
In p u t Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
In p u t Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
In p u t Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
e d g e .
4 E
6 B
7 T
4 E
6 B
7 T
CE#
CE2#
ZZ
In p u t Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
In p u t Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loa de d.
In p u t Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ig n o re d .
2 B
2 B
CE2
In p u t Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loa de d.
4 F
4 F
OE#
In p u t Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
4 G
4 G
ADV#
In p u t Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
12
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
BGA PIN DESCRIPTIONS (co n t in u e d )
x 1 8
x 3 2 /x 3 6
S Y M B O L TY P E
D ES CRIP TIO N
4 A
4 A
ADSP#
In p u t Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to
be registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but
dependent upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is
HIGH. Power-down state is entered if CE2 is LOW or CE2# is
HIGH.
4 B
3 R
4 B
3 R
ADSC#
MODE
In p u t Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to
be registered. A READ or WRITE is performed using the new
address if CE# is LOW. ADSC# is also used to place the chip into
power-down state when CE# is HIGH.
In p u t Mode: This input selects the burst sequence. A LOW on this
input selects “linear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
o p e ra t in g .
(a) 6F, 6H, 6L, (a) 6K, 6L,
DQ a
DQ b
DQ c
DQ d
In p u t / SRAM Data I/Os: For the x18 version, Byte “a” is DQa’s; Byte “b”
Ou t p u t is DQb’s. For the x32 and x36 versions, Byte “a” is DQa’s;
Byte “b” is DQb’s; Byte “c” is DQc’s; Byte “d” is DQd’s. Input
data must meet setup and hold times around the rising edge of
CLK.
6N, 7E, 7G,
7K, 7P
6M, 6N, 7K,
7L, 7N, 7P
(b) 6E, 6F,
6G, 6H, 7D,
7E, 7G, 7H
(c) 1D, 1E,
1G, 1H, 2E,
2F, 2G, 2H
(d) 1K, 1L,
1N, 1P, 2K,
2L, 2M, 2N
(b) 1D, 1H,
1L, 1N, 2E,
2G, 2K, 2M
6 D
2P
–
6P
6 D
2 D
2P
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
NC/ No Connect/Parity Data I/Os: On the x32 version, these are No
I/O
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity
is DQPd.
–
2J, 4C, 4J,
4R, 5R, 6J
2J, 4C, 4J,
4R, 5R, 6J
VDD
Su p p ly Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
1A, 1F, 1J,
1A, 1F, 1J,
VDD
Q
Su p p ly Isolated Output Buffer Supply: See DC Electrical Characteristics
a n d
1M, 1U, 7A, 1M, 1U, 7A,
Operating Conditions for range.
7F, 7J, 7M,
7 U
7F, 7J, 7M,
7 U
3D, 3E, 3F,
3H, 3K, 3L,
3M, 3N, 3P,
5D, 5E, 5F,
5G, 5H, 5K,
5M, 5N, 5P
3D, 3E, 3F,
3H, 3K, 3M,
3N, 3P, 5D,
5E, 5F, 5H,
5K, 5M, 5N,
5P
V
SS
Su p p ly Gro u n d : GND.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
13
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
BGA PIN DESCRIPTIONS (co n t in u e d )
x 1 8
x 3 2 /x 3 6
S Y M B O L TY P E
D ES CRIP TIO N
2U, 3U, 4U,
5 U
2U, 3U, 4U,
5 U
DNU
–
Do Not Use: These signals may either be unconnected or wired
to GND to improve package heat dissipation.
1B, 1C, 1E,
1G, 1K, 1P,
1R, 1T, 2D,
2F, 2H, 2L,
2N, 3J, 4D,
4L, 4T, 5J,
6E, 6G, 6K,
6M, 6P, 6U,
7B, 7C, 7D,
7H, 7L, 7N,
7 R
1B, 1C, 1R,
1T, 2T, 3J,
4D, 4L, 5J,
6T, 6U, 7B,
7C, 7R
N C
–
No Connect: These signals are not internally connected and
may be connected to ground to improve package heat
d issip a t io n .
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
14
MT58L256L18F1_D.p65 – Rev. 10/01
©2001, Micron Technology, Inc.
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
FUNCTION
READ
GW#
H
BWE#
BWa #
BWb #
H
L
L
L
L
X
X
H
L
X
H
H
L
READ
H
WRITE Byte “a”
WRITE Byte “b”
WRITE All Bytes
WRITE All Bytes
H
H
H
L
H
L
L
X
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
READ
GW#
H
BWE#
BWa #
BWb #
BWc#
BWd #
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
READ
H
WRITE Byte “a”
WRITE All Bytes
WRITE All Bytes
H
H
L
L
X
X
X
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
15
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TRUTH TABLE
OPERATION
ADDRESS
USED
CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE#
CLK
DQ
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
X
L
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
High-Z
Q
External
External
External
External
External
Next
L-H
READ Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
L
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQas and DQPa. BWb# enables WRITEs to DQbs and DQPb. BWc# enables WRITEs to DQcs
and DQPc. BWd# enables WRITEs to DQds and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
16
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
*Stresses greater th an th ose listed un der “Absolute
Maxim um Ratin gs” m ay cause perm an en t dam age to
th e device. Th is is a stress ratin g on ly, an d fun ction al
operation of th e device at th ese or an y oth er con dition s
above th ose in dicated in th e operation al section s of
th is specification is n ot im plied. Exposure to absolute
m axim um ratin g con dition s for exten ded periods m ay
affect reliability.
**Maxim um jun ction tem perature depen ds upon pack-
age type, cycle tim e, loadin g, am bien t tem perature an d
airflow. See Micron Tech n ical Note TN-05-14 for m ore
in form ation .
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply
Relative to VSS ............................... -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS ............................... -0.5V to +4.6V
VIN -0.5V to VDDQ + 0.5V
Storage Tem perature (plastic) ............ -55°C to +150°C
Jun ction Tem perature** ................................... +150°C
Sh ort Circuit Output Curren t ........................... 100m A
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL MIN
MAX
VDD + 0.3
0.8
UNITS
V
NOTES
1, 2
1, 2
3
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
VIH
VIL
ILI
2.0
-0.3
-1.0
-1.0
V
0V ≤ VIN ≤ VDD
1.0
µA
µA
Output(s) disabled,
ILO
1.0
0V ≤ VIN ≤ VDD
Output High Voltage
Output Low Voltage
Supply Voltage
IOH = -4.0mA
IOL = 8.0mA
VOH
VOL
2.4
–
–
V
V
V
V
1, 4
1, 4
1
0.4
3.6
3.6
VDD
3.135
3.135
Isolated Output Buffer Supply
VDDQ
1, 5
NOTE: 1. All voltages referenced to VSS (GND).
t
2. Overshoot:
Undershoot: VIL ≥ -0.7V for t ≤ KC/2 for I ≤ 20mA
Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
VIH ≤ +4.6V for t ≤ KC/2 for I ≤ 20mA
t
4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the stated DC
values. AC I/O curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
17
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
TA = 25°C; f = 1 MHz;
VDD = 3.3V
SYMBOL
TYP
MAX
4
UNITS
p F
NOTES
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CI
CO
3
4
3
3
1
1
1
1
5
p F
CA
CCK
3.5
3.5
p F
p F
BGA CAPACITANCE
DESCRIPTION
CONDITIONS
TA = 25°C; f = 1 MHz
VDD = 3.3V
SYMBOL TYP
M AX
7
UNITS NOTES
Address/Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
CI
CO
4
4.5
4
p F
p F
p F
p F
1
1
1
1
5.5
7
CA
CCK
Clock Capacitance
4
5.5
FBGA CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL TYP
MAX
UNITS NOTES
Address/Control Input Capacitance
Output Capacitance (Q)
Clock Capacitance
CI
CO
2.5
4
3.5
5
p F
p F
p F
1, 2
1, 2
1, 2
TA = 25°C; f = 1 MHz
CCK
2.5
3.5
NOTE: 1. This parameter is sampled.
2. Preliminary package data.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
18
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
Data bus (DQx)
Inputs
VIHQ
VIH
1.7
1.7
VDDQ + 0.3
VDD + 0.3
V
V
1, 2
1, 2
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
VIL
ILI
-0.3
-1.0
-1.0
0.7
1.0
1.0
V
1, 2
3
0V ≤ VIN ≤ VDD
µA
µA
Output(s) disabled,
ILO
0V ≤ VIN ≤ VDDQ (DQx)
Output High Voltage
Output Low Voltage
IOH = -2.0mA
IOH = -1.0mA
VOH
VOH
1.7
2.0
–
–
V
V
1, 4
1, 4
IOL = 2.0mA
IOL = 1.0mA
VOL
VOL
–
–
0.7
0.4
V
V
1, 4
1, 4
Supply Voltage
VDD
3.135
2.375
3.6
2.9
V
V
1
1
Isolated Output Buffer Supply
VDDQ
NOTE: 1. All voltages referenced to VSS (GND).
t
2. Overshoot:
Undershoot: VIL ≥ -0.7V for t ≤ KC/2 for I ≤ 20mA
Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE has an internal pull-up, and input leakage = ±10µA.
VIH ≤ +4.6V for t ≤ KC/2 for I ≤ 20mA
t
4. The load used for VOH, VOL testing is shown in Figure 4 for 2.5V I/O. AC load current is higher than the shown DC
values. AC I/O curves are available upon request.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
19
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
46
°C/W
1
Thermal Resistance
θJC
2.8
°C/W
1
(Junction to Top of Case)
BGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL TYP
UNITS NOTES
Junction to Ambient
(Airflow of 1m/s)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
40
°C/W
1
Junction to Case (Top)
θJC
θJB
9
°C/W
°C/W
1
1
Junction to Bumps
(Bottom)
17
FBGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL TYP
UNITS NOTES
Junction to Ambient
(Airflow of 1m/s)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
40
°C/W
1, 2
Junction to Case (Top)
θJC
θJB
9
°C/W
°C/W
1, 2
1, 2
Junction to Pins
(Bottom)
17
NOTE: 1. This parameter is sampled.
2. Preliminary package data.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
20
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
MAX
-7.5 -8.5
DESCRIPTION
CONDITIONS
SYMBOL TYP
-6.8
-10 UNITS NOTES
Power Supply
Cu rre n t :
Op e ra t in g
Device selected; All inputs ≤ VIL
or ≥ VIH; Cycle time ≥ KC (MIN);
t
I
DD
155
35
425 375 325 250
m A
m A
2, 3, 4
2, 3, 4
VDD = MAX; Outputs open
Power Supply Device selected; VDD = MAX; ADSC#,
Current: Idle
CMOS Standby
TTL Standby
Clo ck Ru n n in g
ADSP#, ADV#, GW#, BWx# ≥ VIH
;
IDD
1
115 100
85
65
All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;
t
Cycle time ≥ KC (MIN); Outputs open
Device deselected; VDD = MAX;
All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;
All inputs static; CLK frequency = 0
ISB
2
0.4
8
10
25
10
25
10
25
85
10
25
65
m A
m A
m A
3, 4
3, 4
3, 4
Device deselected; VDD = MAX;
All inputs ≤ VIL or ≥ VIH
;
ISB3
All inputs static; CLK frequency = 0
Device deselected; VDD = MAX;
ADSP#, ADV#, GW#, BWx# ≥ VIH
;
ISB
4
35
115 100
All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;
t
Cycle time ≥ KC (MIN)
NOTE: 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means
device is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C, and 15ns cycle time.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
21
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
-6.8
-7.5
-8.5
-10
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Clo ck
t
Clock cycle time
KC
7.5
8.8
10
15
ns
MHz
ns
f
Clock frequency
KF
133
113
100
66
t
Clock HIGH time
KH
2.5
2.5
2.5
2.5
3.0
3.0
4.0
4.0
2
2
t
Clock LOW time
KL
ns
Ou t p u t Tim e s
t
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Se t u p Tim e s
KQ
6.8
7.5
8.5
10
ns
ns
ns
ns
ns
ns
ns
t
KQX
1.5
1.5
1.5
1.5
3.0
3.0
3.0
3.0
3
t
KQLZ
3, 4, 5, 6
3, 4, 5, 6
7
t
KQHZ
3.5
3.5
4.2
4.2
5.0
5.0
5.0
5.0
t
OEQ
t
OELZ
0
0
0
0
3, 4, 5, 6
3, 4, 5, 6
t
OEHZ
3.5
4.2
5.0
5.0
t
Address
AS
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
Address status (ADSC#, ADSP#)
Address advance (ADV#)
ADSS
t
AAS
t
Byte write enables
WS
(BWa#-BWd#, GW#, BWE#)
t
Data-in
DS
1.5
1.5
1.5
1.5
1.8
1.8
2.0
2.0
ns
ns
8, 9
8, 9
t
Chip enable (CE#)
Ho ld Tim e s
CES
t
Address
AH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
Address status (ADSC#, ADSP#)
Address advance (ADV#)
ADSH
t
AAH
t
Byte write enables
WH
(BWa#-BWd#, GW#, BWE#)
t
Data-in
DH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 9
8, 9
t
Chip enable (CE#)
CEH
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) and
Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V) unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW for the required setup and hold times. A WRITE
cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
22
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
3.3V I/O AC TEST CONDITIONS
2.5V I/O AC TEST CONDITIONS
Input pulse levels ................. VIH = (VDD/2.2) + 1.5V
Input pulse levels ............. VIH = (VDD/2.64) + 1.25V
.................... VIL = (VDD/2.2) - 1.5V
................ VIL = (VDD/2.64) - 1.25V
Input rise and fall times ..................................... 1ns
Input timing reference levels ..................... VDD/2.2
Output reference levels ............................ VDDQ/2.2
Output load ............................. See Figures 1 and 2
Input rise and fall times ..................................... 1ns
Input timing reference levels ................... VDD/2.64
Output reference levels ............................... VDDQ/2
Output load ............................. See Figures 3 and 4
3.3V I/O Ou t p u t Lo a d Eq u iva le n t s
2.5V I/O Ou t p u t Lo a d Eq u iva le n t s
Q
Q
ZO= 50
50
ZO= 50Ω
50Ω
VT = 1.5V
VT = 1.25V
Fig u re 1
Fig u re 3
+2.5V
225Ω
+3.3V
317
Q
Q
5pF
5pF
351
225Ω
Fig u re 4
Fig u re 2
LOAD DERATING CURVES
Micron 256K x 18, 128K x 32, an d 128K x 36
Syn cBurst SRAM tim in g is depen den t upon th e capaci-
tive loadin g on th e outputs.
Con sult th e factory for copies of I/O curren t versus
voltage curves.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
23
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
SNOOZE MODE
SNOOZE MODE is a low-curren t, “power-down ”
m ode in wh ich th e device is deselected an d curren t is
reduced to ISB2Z. Th e duration of SNOOZE MODE is
dictated by th e len gth of tim e ZZ is in a HIGH state.
After th e device en ters SNOOZE MODE, all in puts
except ZZ becom e gated in puts an d are ign ored.
ZZ is an asyn ch ron ous, active HIGH in put th at
causes th e device to en ter SNOOZE MODE. Wh en ZZ
becom es a logic HIGH, ISB2Z is guaran teed after th e
t
setup tim e ZZ is m et. An y READ or WRITE operation
pen din g wh en th e device en ters SNOOZE MODE is n ot
guaran teed to com plete successfully. Th erefore, SNOOZE
MODE m ust n ot be in itiated un til valid pen din g opera-
tion s are com pleted.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
ISB2Z
tZZ
tRZZ
tZZI
tRZZI
MIN
MAX
10
tKC
UNITS NOTES
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ ≥ VIH
m A
ns
ns
ns
ns
1
1
1
1
tKC
0
tKC
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
t
ZZ
t
RZZ
ZZ
t
ZZI
I
SUPPLY
I
ISB2Z
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
24
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
3
READ TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
ADSH
ADSS
Deselect Cycle
(Note 4)
t
t
AH
AS
A1
A2
ADDRESS
t
t
WH
WS
BWE#, GW#,
BWa#-BWd#
t
t
CEH
CES
CE#
(NOTE 2)
t
t
AAH
AAS
ADV#
OE#
ADV# suspends burst.
t
t
t
KQ
OEQ
OELZ
t
t
OEHZ
KQHZ
t
KQX
t
KQLZ
Q(A2)
Q(A2 + 1)
(NOTE 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q
High-Z
t
KQ
Burst wraps around
to its initial state.
Single READ
BURST
READ
DON’T CARE
UNDEFINED
READ TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
-6.8
-7.5
-8.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
KC
7.5
8.8
10
15
ns
MHz
ns
AS
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.8
1.8
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
t
KF
133
6.8
113
7.5
100
8.5
66
10
ADSS
t
t
KH
2.5
2.5
2.5
2.5
3.0
3.0
4.0
4.0
AAS
t
t
KL
ns
WS
t
t
KQ
ns
CES
t
t
KQX
1.5
1.5
1.5
1.5
3.0
3.0
3.0
3.0
ns
AH
t
t
KQLZ
ns
ADSH
t
t
KQHZ
3.5
3.5
4.2
4.2
5.0
5.0
5.0
5.0
ns
AAH
t
t
OEQ
ns
WH
t
t
OELZ
0
0
0
0
ns
CEH
t
OEHZ
3.5
4.2
5.0
5.0
ns
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
t
4. Outputs are disabled KQHZ after deselect.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
25
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC# extends burst.
t
t
t
t
ADSH
ADSS
ADSH
ADSS
ADSC#
t
t
AH
AS
A1
A2
A3
ADDRESS
BYTE WRITE signals are
ignored when ADSP# is LOW.
t
t
WH
WS
BWE#,
BWa#-BWd#
t
t
WH
(NOTE 5)
WS
GW#
t
t
CEH
CES
CE#
(NOTE 2)
t
t
AAH
AAS
ADV#
OE#
ADV# suspends burst.
(NOTE 4)
(NOTE 3)
t
t
DH
DS
D
Q
D(A2)
D(A2 + 1)
(NOTE 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
WRITE TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
-6.8
-7.5
-8.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
KC
7.5
8.8
10
15
ns
MHz
ns
DS
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1.8
1.8
0.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
f
t
KF
133
3.5
113
4.2
100
5.0
66
CES
t
t
KH
2.5
2.5
2.5
2.5
3.0
3.0
4.0
4.0
AH
t
t
KL
ns
ADSH
t
t
OEHZ
5.0
ns
AAH
t
t
AS
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
ns
WH
t
t
ADSS
ns
DH
t
t
AAS
ns
CEH
t
WS
ns
NOTE: 1. D(A2) refers to output from address A2. D(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or
GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
26
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
6
READ/WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WH
WS
BWE#,
BWa#-BWd#
(NOTE 4)
t
t
CEH
CES
CE#
(NOTE 2)
ADV#
OE#
t
t
DH
DS
t
OELZ
t
D
Q
High-Z
D(A3)
D(A5)
D(A6)
t
OEHZ
KQ
(NOTE 1)
Q(A4+1)
Q(A1)
Q(A2)
Q(A4)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
(NOTE 5)
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
READ/WRITE TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
-6.8
-7.5
-8.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
KC
7.5
8.8
10
15
ns
MHz
ns
WS
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
f
t
KF
133
113
100
66
DS
t
t
KH
2.5
2.5
2.5
2.5
3.0
3.0
4.0
4.0
CES
t
t
KL
ns
AH
t
t
KQ
6.8
3.5
7.5
4.2
8.5
5.0
10
ns
ADSH
t
t
OELZ
0
0
0
0
ns
WH
t
t
OEHZ
5.0
ns
DH
t
t
AS
1.5
1.5
1.5
1.5
1.8
1.8
2.0
2.0
ns
CEH
t
ADSS
ns
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
27
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
PIN #1 ID
+0.03
-0.02
0.15
0.32
+0.06
-0.10
+0.10
-0.15
0.65
22.10
20.10 ±0.10
DETAIL A
0.62
1.50 ±0.10
0.10
14.00 ±0.10
+0.20
16.00
+0.10
-0.05
0.25
-0.05
0.10
GAGE PLANE
1.00 (TYP)
1.40 ±0.05
0.60 ±0.15
DETAIL A
MAX
MIN
NOTE: 1. All dimensions in millimeters
or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
28
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
165-PIN FBGA
0.85 ±0.075
0.12
C
SEATING PLANE
C
BALL A11
165X Ø 0.45
10.00
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40
BALL A1
PIN A1 ID
1.20 MAX
1.00
TYP
PIN A1 ID
7.50 ±0.05
14.00
15.00 ±0.10
7.00 ±0.05
1.00
TYP
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
6.50 ±0.05
5.00 ±0.05
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: Ø .33mm
13.00 ±0.10
MAX
NOTE: 1. All dimensions in millimeters
or typical where noted.
MIN
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
29
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
119-PIN BGA
22.00 ±0.20
19.94 ±0.10
Substrate material:
BT resin laminate
0.60 ±0.10
0.90 ±0.10
14.00 ±0.10
11.94 ±0.10
0.15
2.40 MAX
SEATING PLANE
A1 CORNER
A1 CORNER
(dimension applies to a
noncollapsed solder ball)
0.75 ±0.15
Ø
1.27 (TYP)
7.62
1.27 (TYP)
20.32
MAX
NOTE: 1. All dimensions in millimeters
or typical where noted.
MIN
2. Solder ball land pad is 0.6mm.
8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900
E-m a il: p ro d m kt g @m icro n .co m , In t e rn e t : h t t p ://w w w .m icro n .co m , Cu st o m e r Co m m e n t Lin e : 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT,
and Micron Technology, Inc.
SyncBurst is a trademark of Micron Technology, Inc.
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc., and Motorola, Inc.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
30
4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
REVISION HISTORY
Rem oved n ote "Not Recom m en ded for New Design s," Rev. 6/01 ................................................................ Jun e 7/01
Added In dustrial Tem perature n ote an d referen ces, Rev. 3/01, FINAL..................................................... March 6/01
Added 119-pin PBGA package, Rev. 1/01, FINAL ................................................................................. Jan uary 10/01
Rem oved FBGA Part Markin g Guide, REV 8/00-A, FINAL ..................................................................... August 22/00
Ch an ged FBGA capacitan ce values, REV 8/00, FINAL .............................................................................. August 7/00
CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF
CO; TYP 4pF from 6pF; MAX. 5pF from 7pF
CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF
Added FBGA Part Markin g Guide, Rev. 7/00, Prelim in ary .......................................................................... July 17/00
Added revision h istory
Rem oved in dustrial tem perature referen ces
Added 165-pin FBGA package, Rev. 6/00, Prelim in ary ............................................................................... May 23/00
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
31
相关型号:
MT58L256L18F1B-6.8
Standard SRAM, 256KX18, 6.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119
CYPRESS
MT58L256L18F1B-7.5
Standard SRAM, 256KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119
CYPRESS
MT58L256L18F1B-8.5
Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119
CYPRESS
MT58L256L18F1B-8.5IT
Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119
CYPRESS
©2020 ICPDF网 联系我们和版权申明