S29AL004D90MAI023 [CYPRESS]
Flash, 256KX16, 90ns, PDSO44, SOP-44;
| 型号： | S29AL004D90MAI023 |
| 厂家： | 
CYPRESS |
| 描述： | Flash, 256KX16, 90ns, PDSO44, SOP-44 光电二极管 内存集成电路 |
| 文件： | 总46页 (文件大小：1163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29AL004D
4 Mbit (512 K x 8-Bit/256 K x 16-Bit), 3 V
Boot Sector Flash
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
Single Power Supply Operation
– 2.7 to 3.6 volt read and write operations for battery-powered
applications
High Performance
– Access times as fast as 55 ns
– Extended temperature range (-40°C to +125°C)
Ultra-low Power Consumption (typical values at 5 MHz)
– 200 nA Automatic Sleep mode current
– 200 nA standby mode current
Manufactured on 200 nm Process Technology
– Compatible with 0.32 µm Am29LV400B and MBM29LV400T/BC
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte
sectors (byte mode)
– 9 mA read current
– 20 mA program/erase current
– One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword
sectors (word mode)
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 yars typical
– Supports full chip erase
Unlock Bypass Program Command
Package Options
48-ball FBGA
48-pin TSOP
44in SO
– Reduces overall programming time when issuing multiple program
command sequences
Top or Bottom Boot Block Configurations Available
Embedded Algorithms
– Embedded Erase algorithm automatically preprograms and
erases the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically writes and verifies
data at specified addresses
oftware Features
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Compatibility with JEDEC Standards
Erase Suspend/Erase Resume
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Sector Protection Features
– A hardware method of locking a sector to preveany program or
erase operations within that sector
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
Cypress Semiconductor Corporation
Document Number: 002-01235 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 09, 2015
S29AL004D
General Description
The S29AL004D is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-
ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A
standard EPROM programmer can also be used to program and erase the device.
This device is manufactured using Spansion’s 200 nm process technology, and offers all the features and benefits of the
Am29LV400B and MBM29LV400T/BC, which were manufactured using 320 nm process technology.
The standard device offers access times of 70 and 90 ns, allowing high speed microprocessors to operate without wait states. To
eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation icomplete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any
sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the
automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
Document Number: 002-01235 Rev. *A
Page 2 of 46
S29AL004D
Contents
1.
2.
3.
Product Selector Guide............................................... 4
30.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15
x 6.15 mm .....................................................................40
30.3 SO 044—44-Pin Small Outline Package ...................... 41
Block Diagram.............................................................. 4
Connection Diagrams.................................................. 5
31. Revision Summary...................................................... 42
31.1 Revision A0 (November 12, 2004)................................ 42
31.2 Revision A1 (February 18, 2005).................................. 42
31.3 Revision A2 (June 1, 2005)........................................... 42
31.4 Revision A3 (June 21, 2005)......................................... 43
31.5 Revision A4 (May 22, 2006).......................................... 43
31.6 Revision A5 (June 22, 2006)......................................... 43
31.7 Revision A6 (February 27, 2009).................................. 43
3.1 Special Handling Instructions for FBGA Package.......... 6
4.
5.
6.
7.
Pin Configuration......................................................... 6
Logic Symbol ............................................................... 7
Ordering Information (Standard Products)................ 7
Device Bus Operations................................................ 9
8.1 Word/Byte Configuration................................................ 9
8.2 Requirements for Reading Array Data........................... 9
8.3 Writing Commands/Command Sequences.................. 10
8.4 Program and Erase Operation Status.......................... 10
8.5 Standby Mode.............................................................. 10
8.6 Automatic Sleep Mode................................................. 10
8.7 RESET#: Hardware Reset Pin..................................... 11
8.8 Output Disable Mode ................................................... 11
10.1 Autoselect Mode .......................................................... 12
11.1 Sector Protection/Unprotection.................................... 12
11.2 Temporary Sector Unprotect........................................ 13
11.3 Hardware Data Protection............................................ 15
12. Command Definitions................................................ 15
12.1 Reading Array Data ..................................................... 15
12.2 Reset Command.......................................................... 15
12.3 Autoselect Command Sequence ................................. 16
12.4 Word/Byte Program Command Sequence................... 16
12.5 Chip Erase Command Sequence ................................ 17
12.6 Sector Erase Command Sequence ............................. 18
12.7 Erase Suspend/Erase Resume Commands ................ 18
14. Write Operation Status ........................................... 20
14.1 DQ7: Data# Polling ...................................................... 20
14.2 RY/BY#: Ready/Busy#.............................................. 21
14.3 DQ6: Toggle Bit I ......................................................... 22
14.4 DQ2: Toggle Bit II ........................................................ 22
14.5 Reading Toggle Bits DQ6/DQ2.................................... 22
14.6 DQ5: Exceeded Timing Limits ..................................... 23
14.7 DQ3: Sector Erase Timer............................................. 23
16. Absolute Maximum Ratings...................................... 24
17. Operating Ranges...................................................... 25
18. DC Characteristics..................................................... 25
18.1 Zero Power Flash......................................................... 26
19. Test Conditions.......................................................... 27
21. Key to Switching Waveforms.................................... 28
22. AC Characteristics..................................................... 29
22.1 Read Operations.......................................................... 29
25.1 Erase/Program Operations .......................................... 32
28. Erase And Programming Performance.................... 37
30. Physical Dimensions................................................. 39
30.1 TS 048—48-Pin Standard TSOP................................. 39
Document Number: 002-01235 Rev. *A
Page 3 of 46
S29AL004D
1. Product Selector Guide
Family Part Number
S29AL004D
Speed Options
Full Voltage Range: V = 2.7–3.6 V
55
55
55
25
70
70
70
30
90
90
90
35
CC
Max access time, ns (t
)
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note
See AC Characteristics on page 29 for full specifications.
2. Block Diagram
DQ0–DQ15 (A-1)
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
WE#
Control
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
CC
Timer
Cell Matrix
X-Decoder
A0–A17
Document Number: 002-01235 Rev. *A
Page 4 of 46
S29AL004D
3. Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
VCC
Standard TSOP
WE#
RESET#
NC
NC
RY/BY#
NC
DQ11
DQ3
DQ10
DQ2
Q9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A17
A7
A6
A5
A4
A3
A2
A1
NC
RY/BY#
A17
A7
1
2
3
4
5
6
7
8
9
44 RESET#
43 WE#
42 A8
41 A9
A6
40 A10
A5
39 A11
A4
38 A12
A3
37 A13
A2
36 A14
A1 10
A0 11
35 A15
SO
34 A16
CE# 12
VSS 13
33 BYTE#
32 VSS
OE# 1
DQ0 1
DQ8 16
Q1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
Document Number: 002-01235 Rev. *A
Page 5 of 46
S29AL004D
FBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE# RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
NC
NC
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
D1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
VSS
3.1
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA pakages. Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods. The packagand/or data integrity may be compromised if the package body is
exposed to temperatures above 150C for prolonged periods oime.
4. Pin Configuration
A0–A17
DQ0–DQ14
DQ15/A-1
BYTE#
CE#
18 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
Chip enable
OE#
Output enable
WE#
Write enable
RESET#
RY/BY#
Hardware reset pin, active low
Ready/Busy# output
3.0 volt-only single power supply
V
CC
(see Product Selector Guide on page 4 for speed options and voltage supply tolerances)
V
Device ground
SS
NC
Pin not connected internally
Document Number: 002-01235 Rev. *A
Page 6 of 46
S29AL004D
5. Logic Symbol
18
A0–A17
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
6. Ordering Information (Standard Products)
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
S29AL004D
55
T
A
I
01
0
Packing Type
0
1
2
3
= Tray
= Tube
= 7” Tape and Reel
= 13” Tape and Reel
Model Number
01 = V = 2.7 - 3.6V, top boot sector device
CC
R1 = V = 3.0 - 3.6V, top boot sector device
CC
02 = V = 2.7 - 3.6V, bottom boot sector device
CC
R2 = V = 3.0 - 3.6V, bottom boot sector device
CC
Temperature Range
I
N
= Industrial (-40°C to +85°C)
= Extended (-40°C to +125°C)
Package Material Set
A
F
= Standard
= Pb-Free
Package Type
T
B
M
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Small Outline Package (SOP) Standard Pinout
Speed Option
55 = 55 ns Access Speed
70 = 70 ns Access Speed
90 = 90 ns Access Speed
Device Number/Description
S29AL004D
4 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase
Document Number: 002-01235 Rev. *A
Page 7 of 46
S29AL004D
S29AL004D Valid Combinations
Package Type,
Package Description
Speed
Model
Number
Device Number
Material, and
Packing Type
Option
Temperature Range
TAI, TFI
TAN, TFN
01, 02
R1, R2
01, 02
01, 02
R1, R2
01, 02
01, 02
R1, R2
01, 02
55
70, 90
55
0, 3 (Note 1)
TS048 (Note 3)
VBK048 (Note 4)
SO044 (Note 3)
TSOP
TAI, TFI, TAN, TFN
BAI, BFI
Fine-Pitch
BGA
S29AL004D
BAN, BFN
0, 2, 3 (Note 1)
0, 1, 3 (Note 2)
70, 90
55
BAI, BFI, BAN, BFN
MAI, MFI
MAN, MFN
SOP
70, 90
MAI, MFI, MAN, MFN
Notes
1. Type 0 is standard. Specify other options as required.
2. Type 1 is standard. Specify other options as required.
3. TSOP and SOP package markings omit packing type designator from ordering part number.
4. BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Document Number: 002-01235 Rev. *A
Page 8 of 46
S29AL004D
7. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command
register. The command register itself does not occupy any addressable memory location. The register is composed of latches that
store the commands, along with the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 8 lists the device
bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Table 8. S29AL004D Device Bus Operations
DQ8–DQ15
Addresses
(Note 1)
DQ0–
DQ7
Operation
CE#
OE# WE#
RESET#
BYTE#
BYTE# = V
IL
= V
IH
Read
L
L
L
H
X
H
X
H
L
H
H
A
A
D
D
OUT
IN
IN
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write
D
D
IN
IN
Standby
V
0.3V
X
H
X
V
0.3V
CC
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
CC
Output Disable
Reset
L
H
L
X
X
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
V
D
X
X
X
ID
IN
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
V
D
D
X
ID
ID
IN
IN
Temporary Sector Unprotect
X
X
V
A
D
High-Z
IN
IN
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
V
= 12.0 0.5 V
ID
X = Don’t Care
A
= Address In
= Data In
IN
D
D
IN
= Data Out
OUT
Notes
1. Addresses are A17:A0 in word mode (BYTE# = V ), A17:A-1 in byte mode (BYTE# = V ).
IH
IL
2. The sector protect and sector unprotect functions ay also be implemented via programming equipment. See Sector Protection/Unprotection on page 12.
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is
set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by
CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register contents are altered.
Document Number: 002-01235 Rev. *A
Page 9 of 46
S29AL004D
See Reading Array Data on page 15 for more information. Refer to the AC Read Operations on page 29 for timing specifications and
to Figure 23.1 on page 29 for the timing diagram. ICC1 in DC Characteristics on page 25 represents the active current specification
for reading array data.
8.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte
Configuration on page 9 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,
only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence
on page 16 has details on programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 9 on page 11 and Table 10 on page 11
indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a
sector. The Command Definitions on page 15 has details on erasing a sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to Autoselect Mode on page 12 and Autoselect Command Sequence on page 16 for more information.
ICC2 in DC Characteristics on page 25 represents the active current specification for the write mode. The AC Characteristics
on page 29 contains timing specification tables and timing diagrams for write operations.
8.4
Program and Erase Operation Status
During an erase or program operation, the system may check e status of the operation by reading the status bits on DQ7–DQ0.
Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 20 for more information, and
to AC Characteristics on page 29 for timing diagrams.
8.5
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the otputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device is in the standby mode,
but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
In the DC Characteristics on page 25 table, ICC3 and ICC4 represents the standby current specification.
8.6
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. ICC4 in DC Characteristics on page 25 represents the automatic sleep mode current specification.
Document Number: 002-01235 Rev. *A
Page 10 of 46
S29AL004D
8.7
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for
at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby
current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is
1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). Thsystem can read data tRH after
the RESET# pin returns to VIH.
Refer to the tables in AC Characteristics on page 29 for RESET# parameters and to Figure 24.1 on page 30 for the timing diagram.
8.8
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 9. S29AL004D Top Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector Size
(Kbytes/Kwords)
Sector
A17
A16
A15
A14
A13
A12
(x8) Address Range
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
78000h–79FFFh
7A000h–7BFFFh
7C000h–7FFFFh
(x16) Address Range
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–38FFFh
3C000h–3CFFFh
3D000h–3DFFFh
3E000h–3FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
1
0
1
8/4
1
1
X
16/8
Note
The address range is A17:A-1 in byte mode and A17:A0 in word mode. See Word/Byte Configuration on page 9.
Table 10. S29AL004D Bottom Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector Size
(Kbytes/
Kwords)
Sector
A17
A16
A15
A14
A13
A12
(x8)
(x16)
Address Range
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
X
0
16/8
8/4
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
0
1
1
8/4
1
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
X
X
X
X
Document Number: 002-01235 Rev. *A
Page 11 of 46
S29AL004D
Table 10. S29AL004D Bottom Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector Size
(Kbytes/
Kwords)
Sector
A17
A16
A15
A14
A13
A12
(x8)
(x16)
Address Range
Address Range
SA8
SA9
1
1
1
0
1
1
1
0
1
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
SA10
Note
The address range is A17:A-1 in byte mode and A17:A0 in word mode. See Word/Byte Configuration on page 9.
10.1 Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes
output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 on address pin A9. Address pins A6, A1,
and A0 must be as shown in Table 11. In addition, when verifying sector protection, the sector address must appear on the
appropriate highest order address bits (see Table 9 on page 11 and Table 10 on page 11). Table 11 on page 12 shows the
remaining address bits that are don’t care. When all necessary bits are set as reqired, the programming equipment may then read
the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown
in Table 12.2 on page 19. This method does not require VID. See Command Definitions on page 15 for details on using the
autoselect mode.
Table 11. S29AL004D Autoselect Code(High Voltage Method)
A11
to
A10
DQ8
to
DQ15
DQ7
to
DQ0
A17
to
A12
A8
to
A7
A4
to
A5
A3
to
A2
Description
Mode CE#
OE# WE#
A9
A6
L
A1
L
A0
L
Manufacturer ID: Spansion
L
L
L
L
H
H
X
X
V
V
X
X
L
X
01h
B9h
ID
ID
Device ID:
S29AL004D
(Top Boot Block)
Word
Byte
22h
X
X
X
L
X
L
L
H
L
L
L
L
H
H
X
B9h
BAh
Device ID:
S29AL004D
(Bottom Boot
Block)
Word
22h
X
X
X
V
V
X
X
L
L
X
X
L
L
L
H
L
ID
ID
Byte
L
L
H
X
BAh
01h
(protected)
X
X
Sector Protection
Verification
L
L
H
SA
H
00h
(unprotected)
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
SA = Sector Address
X = Don’t care.
11.1 Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previously protected sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory
prior to shipping the device through Spansion’s ExpressFlash™ Service. Contact an Spansion representative for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 12 for details.
Document Number: 002-01235 Rev. *A
Page 12 of 46
S29AL004D
Sector Protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment.
Figure 11.2 on page 14 shows the algorithms and Figure 26.2 on page 36 shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector
unprotect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is
compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices.
11.2 Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is
activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting
the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again.
Figure 11.1 shows the algorithm and Figure 26.1 on page 35 shows the timing diagrams, for this feature.
Figure 11.1 Temporary Sector Unprotect Operation
START
RESET# = VID (Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Document Number: 002-01235 Rev. *A
Page 13 of 46
S29AL004D
Figure 11.2 In-System Sector Protect/Sector Unprotect Algorithms
START
START
Protect all sectors:
PLSCNT = 1
PLSCNT = 1
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
RESET# = VID
RESET# = VID
Wait 1 μs
Wait 1 μs
unprotect address
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protecte?
Sector Protect:
Yes
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
up first sector
address
Sector Unprotect:
Write 60h to sector
address with
Wait 150 μs
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect other
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Unprotect
Algorithm
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Document Number: 002-01235 Rev. *A
Page 14 of 46
S29AL004D
11.3 Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to Table 12.2 on page 19 for command definitions). In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC
power-up and power-down transitions, or from system noise.
11.3.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is greater than VLKO
.
11.3.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
11.3.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
11.3.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to reading array data on power-up.
12. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Figure 12.2
on page 19 defines the valid register command sequences. Writing incorrect address and data values or writing them in the
improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of E# or CE#, whichever happens later. All data is latched on the rising edge of WE#
or CE#, whichever happens first. Refer to the appropriate timing diagrams in AC Characteristics on page 29.
12.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device
is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.
After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 18 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect
mode. See Reset Command on page 15.
See also Requirements for Reading Array Data on page 9 for more information. The Read Operations on page 29 provides the read
parameters, and Figure 23.1 on page 29 shows the timing diagram.
12.2 Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
Document Number: 002-01235 Rev. *A
Page 15 of 46
S29AL004D
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins.
This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also
applies during Erase Suspend).
12.3 Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether
or not a sector is protected. Table 12.2 on page 19 shows the address and data requirements. This method is an alternative to that
shown in Table 11 on page 12, which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by autoselect command. The device then
enters the autoselect mode, and the system may read at any address any number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode)
returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode)
returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 9 on page 11 and Table 10 on page 11 for valid
sector addresses.
The system must write the reset command to exit the autoselect moe and return to reading array data.
12.4 Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is
not required to provide further controls or timinThe device automatically provides internally generated program pulses and
verifies the programmed cell margin. Table 12.2 on page 19 shows the address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer
latched. The system can determinthe status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status
on page 20 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1.
Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
12.4.1
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the
unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. Table 12.2 on page 19 shows the requirements for the command sequence.
Document Number: 002-01235 Rev. *A
Page 16 of 46
S29AL004D
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h (F0h). Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 12.1 illustrates the algorithm for the program operation. See Table 25 on page 30 for parameters, and Figure 25.3
on page 32 for timing diagrams.
Figure 12.1 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
o
Increment Address
Last Address?
Yes
Programming
Completed
Note
See Table 13 on page 19 for program command sequence.
12.5 Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations. Table 12.2 on page 19 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip
erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device
has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status
on page 20 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Figure 12.2 on page 19 illustrates the algorithm for the erase operation. See Table 25 on page 30 for parameters and Figure 25.4
on page 33 for timing diagrams.
Document Number: 002-01235 Rev. *A
Page 17 of 46
S29AL004D
12.6 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector
erase command. Table 12.2 on page 19 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically
programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector
addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs,
otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system
need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the
device to reading array data. The system must rewrite the command sequence and any additional sector addresses and
commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See 3: Sector Erase Timer on page 23). The
time-out begins from the rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that
a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence
should be reinitiated once the device has returned to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to rading array data and addresses are no longer latched.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status
on page 20 for information on these status bits.
Figure 12.2 on page 19 illustrates the algorithm for the erase oeration. Refer to Table 25 on page 30 for parameters, and to
Figure 25.4 on page 33 for timing diagrams.
12.7 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,
any sector not selected for erasure. This commnd is valid only during the sector erase operation, including the 50 µs time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorhm. Writing the Erase Suspend command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend
the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure.
(The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 20 for
information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within non-suspended
sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See Write Operation Status on page 20 for more information.
The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows
reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 16 for more information.
Document Number: 002-01235 Rev. *A
Page 18 of 46
S29AL004D
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the
sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after
the device has resumed erasing.
Figure 12.2 Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes
1. See Sector Erase Command Sequence on page 18 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 23 for more information.
Table 13. S29AL004D Command Definitions
Bus Cycles (Notes 2-5)
Command
First
Second
Third
Fourth
Fifth
Addr Data
Sixth
Addr Data
Sequence
(Note 1)
Addr
Data
F0
Addr
Data
Addr
Data
Addr
Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
55
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
555
AAA
555
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90
90
90
X00
01
AAA
555
X01
X02
X01
X02
22B9
B9
Device ID,
Top Boot Block
AAA
555
AAA
555
22BA
BA
Device ID,
Bottom Boot Block
AAA
AAA
XX00
XX01
00
Word
Byte
555
2AA
555
555
(SA)X02
(SA)X04
PA
Sector Protect Verify
(Note 9)
4
AA
55
55
90
AAA
AAA
01
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
PA
555
AAA
555
Program
4
3
AA
AA
A0
20
PD
Unlock Bypass
55
AAA
XXX
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
(F0h)
XXX
XXX
Document Number: 002-01235 Rev. *A
Page 19 of 46
S29AL004D
Table 13. S29AL004D Command Definitions
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
10
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
AAA
Sector Erase
SA
30
AAA
XXX
XXX
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
Legend
X = Don’t care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation, and
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17–A12 uniquely select any sector.
Notes
1. See Table 8 on page 9 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A17–A11 are don’t cares for unlock and command cycles, unless PA or SA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is
providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence on page 16 for more
information.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program cmmand.
11. The Unlock Bypass Reset command is required to return to reading array dawhen the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation.
13. The Erase Resume command is valid only during the Erase Suspend mode.
14. Write Operation Status
The device provides several bits to determne the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 15
on page 24 and the following subsectins describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
14.1 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether
the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if
the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum
output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
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S29AL004D
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following
read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low.
Figure 25.6 on page 34 illustrates this.
Table 15 on page 24 shows the outputs for Data# Polling on DQ7. Figure 14.1 on page 21 shows the Data# Polling algorithm.
Figure 14.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Adr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
14.2 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.
Table 15 on page 24 shows the outputs for RY/BY#. Figure 23.1 on page 29, Figure 24.1 on page 30, Figure 25.3 on page 32, and
Figure 25.4 on page 33 shows RY/BY# for read, reset, program, and erase operations, respectively.
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14.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 20).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the pogram command sequence is
written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the mbedded Program algorithm is complete.
Table 15 on page 24 shows the outputs for Toggle Bit I on DQ6. Figure 14.2 on page 23 shows the toggle bit algorithm. Figure 25.7
on page 34 shows the toggle bit timing diagrams. Figure 25.8 on page 34 shows the differences between DQ2 and DQ6 in graphical
form. See also DQ2: Toggle Bit II on page 22.
14.4 DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that are selected for erasure. (The system may use either
OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 15 on page 24 to
compare outputs for DQ2 and DQ6.
Figure 14.2 on page 23 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II on page 22 explains the
algorithm. See also the DQ6: Toggle BI on page 22 subsection. Figure 25.7 on page 34 shows the toggle bit timing diagram.
Figure 25.8 on page 34 shows the differences between DQ2 and DQ6 in graphical form.
14.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 14.2 on page 23 for the following discussion. Whenever the system initially begins reading toggle bit status, it must
read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the
value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 23). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the
operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 14.2 on page 23)
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14.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the reset command to return the device to reading array data.
14.7 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has
begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire
time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The
system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands is always less than
50 µs. See also the Sector Erase Command Sequence on page 18.
Figure 14.2 Toggle Bit Algorithm
START
Read DQ7–DQ0
(Note 1)
Read DQ7DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes 1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Program/Erase
Complete, Write
Reset Command
Operation Complete
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
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After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle
has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the
device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the
status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. Table 15 shows the outputs for DQ3.
Table 15. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
Operation
DQ6
DQ3
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits
on page 23 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
16. Absolute Maximum Ratings
Storage Temperature Plastic Packages–65°C to +150°C
Ambient Temperature with Power Applied–65°C to +125°C
Voltage with Respect to Ground VCC (Note 1)–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2)–0.5 V to +12.5 V
All other pins (Note 1)
–0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3)200 mA
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot V to –2.0 V for periods of up to 20 ns. See
SS
Figure 17.1 on page 25. Maximum DC vage on input or I/O pins is V +0.5 V. During voltage transitions, input or I/O pins may overshoot to V +2.0 V for periods
CC
CC
up to 20 ns. See Figure 17.2 on page 25.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot V to –2.0 V for periods of up
SS
to 20 ns. See Figure 17.1 on page 25. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings on page 24 may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device reliability.
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17. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA)
-40°C to +85°C
Extended (N) Devices
Ambient Temperature (TA)
-40°C to +125°C
+2.7 V to +3.6 V
V
Supply Voltages
CC
VCC for full voltage range
Operating ranges define those limits between which the functionality of the device is guaranteed.
Figure 17.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 17.2 Maximum Posite Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
18. DC Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
1.0
35
Unit
µA
V
V
= V to V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
SS
,
OUT
CC
I
1.0
µA
LO
= V
CC
CC max
10 MHz
5 MHz
1 MHz
10 MHz
5 MHz
1 MHz
18
9
35
16
4
CE# = V OE#
IL,
Byte Mode
V
=
IH,
2
V
Active Read Current
CC
I
I
mA
mA
CC1
(Notes 1, 2)
15
9
30
16
4
CE# = V OE#
IL,
Word Mode
V
V
=
=
IH,
IH
2
V
Active Write Current
CC
CE# = V OE#
20
35
CC2
IL,
(Notes 2, 3, 6)
I
I
V
Standby Current (Notes 2, 4)
CE#, RESET# = V 0.3 V
0.2
0.2
5
5
µA
µA
CC3
CC
CC
CC
V
Reset Current (Notes 2, 4)
RESET# = V 0.3 V
CC4
SS
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S29AL004D
Parameter
Description
Test Conditions
Min
Typ
Max
5
Unit
Automatic Sleep Mode
(Notes 2, 4, 5)
V
V
= V 0.3 V;
CC
= V 0.3 V
IH
IL
I
0.2
µA
CC5
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
0.7 x V
V
+ 0.3
CC
IH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 3.3 V
11.5
2.4
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
V
V
= –2.0 mA, V = V
CC
OH1
OH2
LKO
CC min
CC min
Output High Voltage
= –100 µA, V = V
V
–0.4
CC
CC
Low V Lock-Out Voltage
2.3
2.5
V
CC
Notes
1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.
CC
IH
CC
2. Maximum I specifications are tested with V = V .
CCmax
CC
CC
3.
I
active while Embedded Erase or Embedded Program is in progress.
CC
4. At extended temperature range (>+85°C), typical current is 5µA and maximum current is 10µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t
6. Not 100% tested.
+ 30 ns.
ACC
18.1 Zero Power Flash
Figure 18.1 ICC1 Current vs. Time (Showing Acte and Automatic Sleep Currents)
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note
Addresses are switching at 1 MHz.
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S29AL004D
Figure 18.2 Typical ICC1 vs. Frequency
10
8
3.6 V
6
2.7 V
4
2
0
1
2
3
4
5
Frequeny in MHz
Note
T = 25 C
19. Test Conditions
Figure 19.1 Test Setup
3.3 V
2.7 k
Device
Under
Test
C
6.2 k
L
Note
Nodes are IN3064 or equivalent.
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S29AL004D
Table 20. Test Specifications
Test Condition
55
70
1 TTL gate
90
Unit
Output Load
Output Load Capacitance, C
(including jig capacitance)
L
30
30
100
pF
ns
Input Rise and Fall Times
Input Pulse Levels
5
0.0 or V
CC
Input timing measurement reference levels
Output timing measurement reference levels
0.5V
0.5V
V
CC
CC
21. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Figure 21.1 Input Waveforms and Measurement Levels
Measurement Level
V
CC
0.5V
Input
Output
0.5V
CC
CC
0.0 V
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S29AL004D
22. AC Characteristics
22.1 Read Operations
Parameter
Table 23. Read Operations
Speed Options
Description
JEDEC
Std
Test Setup
55
70
90
Unit
t
t
Read Cycle Time (Note 1)
Min
55
70
90
AVAV
RC
CE# = V
OE# = V
IL
IL
t
t
Address to Output Delay
Max
55
70
90
AVQV
ACC
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
Min
Min
55
25
70
30
16
16
2
0
90
35
ELQV
GLQV
EHQZ
CE
IL
t
t
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Latency Between Read and Write Operations
DF
DF
ns
t
GHQZ
t
SR/W
Read
Output Enable
t
OEH
Hold Time (Note 1)
Toggle and Data# Polling
10
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
t
t
Min
0
AXQX
OH
Notes
1. Not 100% tested.
2. See Figure 19.1 on page 27 and Table 20 on page 28 for test specifications.
Figure 23.1 Read Operations Timings
t
RC
Addresses Stable
Addresses
CE#
t
ACC
t
DF
t
OE
OE#
t
SR/W
t
OEH
WE#
t
CE
t
OH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
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S29AL004D
Table 24. Hardware Reset (RESET#)
Parameter
JEDEC Std
Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
t
20
µs
READY
READY
Max
Min
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
t
500
ns
t
RESET# Pulse Width
500
50
20
0
ns
ns
µs
ns
RP
t
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
RB
Note
Not 100% tested.
Figure 24.1 RESET# Timings
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
t
RH
tRP
Table 25. Word/Byte Configuration (BYTE#)
Parameter
Speed Options
Description
JEDEC
Std
55
70
90
Unit
t
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
5
ELFL/ ELFH
t
16
70
ns
FLQZ
t
55
90
FHQV
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Figure 25.1 BYTE# Timings for Read Operations
CE#
OE#
BYTE#
tELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
Switching
from word
to byte
DQ0–DQ14
DQ15/A-1
mode
Address
Input
DQ15
Output
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
Address
Input
DQ15
Output
tFHQV
Figure 25.2 BYTE# Timings for Write Operations
CE
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note
Refer to Erase/Program Operations on page 32 for t and t specifications.
AS
AH
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25.1 Erase/Program Operations
Parameter
Speed Options
Description
JEDEC
Std
55
70
70
0
90
Unit
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
55
90
AVAV
WC
t
t
AVWL
WLAX
AS
AH
DS
DH
t
t
45
35
0
t
t
t
35
45
DVWH
WHDX
t
Data Hold Time
t
Output Enable Setup Time
0
OES
Min
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
0
GHWL
GHWL
t
t
CE# Setup Time
0
0
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
t
CE# Hold Time
t
Write Pulse Width
35
30
20
5
t
t
Write Pulse Width High
Latency Between Read and Write Operations
WPH
t
Min
Typ
ns
µs
SR/W
Byte
t
t
t
t
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
WHWH1
WHWH2
WHWH1
Word
7
0.7
50
0
sec
µs
WHWH2
t
V
Setup Time (Note 1)
CC
Min
Min
Max
VCS
t
Recovery Time from RY/BY#
RB
ns
t
Program/Erase Valid to RY/BY# Delay
90
BUSY
Notes
1. Not 100% tested.
2. See the Sector Erase Command Sequence on page 18 section for more information.
Figure 25.3 Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
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S29AL004D
Figure 25.4 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
VA
VA
tAS
SA
tWC
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data e Write Operation Status on page 20).
2. Illustration shows device in word mode.
Figure 25.5 Back to Back Read/Write Cycle Timing
t
t
WC
RC
Addresses
PA
PA
PA
PA
t
t
ACC
t
AH
CPH
t
CE
CE#
OE#
t
CP
t
OE
t
GHWL
t
SR/W
t
WP
t
WE#
Data
DF
t
WDH
t
DS
t
OH
t
DH
Valid
In
Valid
Out
Valid In
Valid Out
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Page 33 of 46
S29AL004D
Figure 25.6 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tCH
tOE
OE#
tOEH
tDF
tOH
WE#
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Figure 25.7 Toggle Bit Timings (During Embedded Algorithms)
tRC
Addresses
VA
tACC
tCE
VA
VA
VA
CE#
tCH
tOE
OE#
tOEH
tDF
tOH
WE#
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 25.8 DQ2 vs. DQ6
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Document Number: 002-01235 Rev. *A
Page 34 of 46
S29AL004D
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Suspend
Program
Complete
Read
DQ6
DQ2
Table 26. Temporary Sector Unprotect
Parameter
All Speed Options
JEDEC
Std
Description
Unit
ns
t
V
Rise and Fall Time (See Note)
ID
Min
Min
500
4
VIDR
t
RESET# Setup Time for Temporary Sector Unprotect
µs
RSP
Note
Not 100% tested.
Figure 26.1 Temporary Sector Unprotect Timing Diagram
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Document Number: 002-01235 Rev. *A
Page 35 of 46
S29AL004D
Figure 26.2 Sector Protect/Unprotect Timing Diagram
V
V
ID
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Table 27. Alternate CE# Controlled Erase/Program Operation
Parameter
JEDEC Std
Speed Options
Description
Write Cycle Time (Note 1)
55
70
70
0
90
Unit
t
t
55
90
AVAV
AVEL
ELAX
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
AS
AH
DS
DH
t
t
45
35
0
t
t
t
35
45
DVEH
EHDX
t
Data Hold Time
t
Output Enable Setup Time
0
OES
Min
ns
Read Recovery Te Before Write
(OE# High to WE# Low)
t
t
t
0
GHEL
GHEL
t
WE# Setup Time
0
0
WLEL
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
30
20
5
ELEH
CP
t
t
CE# Pulse Width High
Latency Between Read and Write Operations
EHEL
CPH
t
Min
Typ
ns
µs
SR/W
Byte
Programming Operation
(Note 2)
t
t
t
t
WHWH1
WHWH1
Word
7
Sector Erase Operation (Note 2)
0.7
sec
WHWH2
WHWH2
Note
1. Not 100% tested.
2. See Erase And Programming Performance on page 37 for more information.
Document Number: 002-01235 Rev. *A
Page 36 of 46
S29AL004D
Figure 27.1 Alternate CE# Controlled Write Operation Timings
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
= data written to the device.
OUT
28. Erase And Programming Performance
Parameter
Sector Erase Time
yp (Note 1)
Max (Note 2)
Unit
s
Comments
0.7
11
7
10
Excludes 00h programming
prior to erasure
Chip Erase Time
s
Byte Programming Time
Word Programming Time
210
210
12.5
8.5
µs
µs
s
7
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
4.2
2.9
Chip Programming Time
(Note 3)
s
Notes
1. Typical program and erase times assume the following conditions: 25C, V = 3.0 V, 100,000 cycles, checkerboard data pattern.
CC
2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 on page 19 for further information
on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector
Document Number: 002-01235 Rev. *A
Page 37 of 46
S29AL004D
Table 29. TSOP, SO, And BGA Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
= 0
Package
TSOP, SO
BGA
Typ
6
Max
7.5
5.0
12
Unit
C
Input Capacitance
V
IN
IN
4.2
8.5
5.4
7.5
3.9
TSOP, SO
BGA
C
Output Capacitance
V
= 0
OUT
pF
OUT
6.5
9
TSOP, SO
BGA
C
Control Pin Capacitance
V
= 0
IN2
IN
4.7
Notes
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
Document Number: 002-01235 Rev. *A
Page 38 of 46
S29AL004D
30. Physical Dimensions
30.1 TS 048—48-Pin Standard TSOP
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
0.10
5
A2
1
N
REVERSE PIN OUT (TOP VIEW)
3
SEE DETAIL B
A
B
1
N
E
N
2
N
2
+1
e
9
5
D1
A1
N
N
2
4
+1
2
D
0.25
2X (N/2 TIPS)
C
B
SEATING
PLANE
A
B
SEE DETAIL A
0.08MM (0.0031")
M
C
6
A - B S
b
7
WITH PLATING
c1
(c)
7
b1
BASE METAL
SECTION B-B
R
(c)
e/2
GAUGE PLANE
0.25MM (0.0098") BSC
θ°
PARALLEL TO
SEATING PLANE
X
C
L
X = A OR B
DETAIL A
DETAIL B
NOTES:
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Jedec
MO-142 (D) DD
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
c1
c
D
D1
E
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
e
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
0.70
8˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3355 \ 16-038.10c
Note
For reference only. BSC is an ANSI standard for Basic Space Centering.
Document Number: 002-01235 Rev. *A
Page 39 of 46
S29AL004D
30.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm
0.10 (4X)
D1
A
D
6
5
4
3
2
1
7
e
SE
E1
E
H
G
F
E
D
C
B
A
INDEX MARK
10
6
B
A1 CORNER
PIN A1
CORNER
7
fb
SD
f 0.08
f 0.15
M
M
C
TOP VIEW
C A
B
BOTTVIEW
0.10 C
0.08 C
A2
A
SEATING PLANE
SIDE VIEW
C
A1
NOTES:
PACKAGE
JEDEC
VBK 048
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.15 mm x 6.15 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
MAX
1.00 OVERALL THICKNESS
--- BALL HEIGHT
NOTE
4.
e
REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
---
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.18
0.62
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.76 BODY CKNESS
BODY SIZE
8.15 BSC.
6.15 BSC.
5.60 BSC.
4.00 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
ODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
MD
ME
N
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
6
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
48
fb
0.35
---
0.43 BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
---
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25b
Document Number: 002-01235 Rev. *A
Page 40 of 46
S29AL004D
30.3 SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
Document Number: 002-01235 Rev. *A
Page 41 of 46
S29AL004D
31. Revision Summary
Spansion Publication Number: S29AL004D_00
31.1 Revision A0 (November 12, 2004)
Initial release
31.2 Revision A1 (February 18, 2005)
Added Cover Page
Ordering Information
Change package type from S to M.
Valid Combination Table
Package Type, Material, and Temperature Range from SAL and SFI to MAL and MFI.
Changed Package Description from SSOP to SOP
Erase and Programming Performance Table
Changed chip erase time in table.
31.3 Revision A2 (June 1, 2005)
Global
Updated status from Advance Information to Preliminary data eet.
Distinctive Characteristics
Updated High Performance access time to 55 ns.
Product Selector Guide
Added 55 ns speed column.
Ordering Information
Added tube packing type.
Added Extended Temperature rane.
Added 55 ns speed option.
Valid Combinations Table
Added two designators to packing types.
Added speed option along with speed option package type nomenclature.
Added Note for this table.
Operating Range
Added extended temperature range information.
Moved Figures 7 and 8 under Operating Range area.
Erase and Programming Performance
Changed Byte Programing Time values for Typical and Maximum.
Document Number: 002-01235 Rev. *A
Page 42 of 46
S29AL004D
31.4 Revision A3 (June 21, 2005)
Global
Update from Preliminary status to full Data Sheet.
Ordering Information
Added two Model Numbers.
Valid Combinations Table
Updated table with new Model Numbers and Package Types.
31.5 Revision A4 (May 22, 2006)
AC Characteristics
Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram.
Changed maximum value for tDF and tFLQZ
.
31.6 Revision A5 (June 22, 2006)
Connection Diagrams
Changed inputs on pins 1 and 2 of SO package.
Read Operations Timings figure
Connected end of tRC period to start of tOH period.
Erase/Program Operations table
Changed tBUSY to a maximum specification.
31.7 Revision A6 (February 27, 2009)
Global
Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information sections of data sheet.
Document Number: 002-01235 Rev. *A
Page 43 of 46
S29AL004D
Document History Page
Document Title:S29AL004D 4 Mbit (512 K x 8-Bit/256 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01235
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
11/12/2004 Initial release
02/18/2005
Added Cover Page
Ordering Information
Change package type from S to M.
Valid Combination Table
Package Type, Material, and Temperature Range from SAL and SFI to
MAL and MFI.
Changed Package Description from SSOP to SOP
Erase and Programming Performance Table
Changed chip erase time in table.
06/01/2005
Global
Updated status from Advance Information to Preliminary data sheet.
Distinctive Characteristics
Updated High Performance access time to 55 ns.
Product Selector Guide
Added 55 ns speed column.
Ordering Information
Added tube packing type.
Added Extded Temperature range.
Added 55 ns speed option.
**
-
BWHA
Valid Combinations Table
Added two designators to packing types.
Added speed option along with speed option package type nomenclature.
Added Note for this table.
Operating Range
Added extended temperature range information.
Moved Figures 7 and 8 under Operating Range area.
Erase and Programming Performance
Changed Byte Programing Time values for Typical and Maximum.
06/21/2005
05/22/2006
Global
Update from Preliminary status to full Data Sheet.
Ordering Information
Added two Model Numbers.
Valid Combinations Table
Updated table with new Model Numbers and Package Types.
AC Characteristics
Added tSR/W parameter to read and erase/program operations tables.
Added back-to-back read/write cycle
timing diagram. Changed maximum value for tDF and tFLQZ.
Document Number: 002-01235 Rev. *A
Page 44 of 46
S29AL004D
Document History Page (Continued)
Document Title:S29AL004D 4 Mbit (512 K x 8-Bit/256 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01235
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
BWHA
BWHA
Date
06/22/2006
Connection Diagrams
Changed inputs on pins 1 and 2 of SO package.
Read Operations Timings figure
Connected end of tRC period to start of tOH period.
Erase/Program Operations table
**
-
Changed tBUSY to a maximum specification.
02/27/2009
Global
Added obsolescence information to Cover Sheet, Distinctive
Characteristics, and Ordering Information
sections of data sheet.
*A
5043522
12/09/2015 Updated to Cypress template
Document Number: 002-01235 Rev. *A
Page 45 of 46
S29AL004D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
Automotive..................................cypress.com/go/automotive
Clocks & Buffers ................................ cypress.com/go/clocks
Interface......................................... cypress.com/go/interface
Lighting & Power Control............cypress.com/go/powerpsoc
Memory........................................... cypress.com/go/memory
PSoC ....................................................cypress.com/go/psoc
Touch Sensing.................................... cypress.com/go/touch
USB Controllers....................................cypress.com/go/USB
Wireless/RF.................................... cypress.com/go/wireless
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
© Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-01235 Rev. *A
Revised December 09, 2015
Page 46 of 46
Cypress®, Spansion®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress
Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.
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