S29JL032H60TAI2100 [CYPRESS]
Flash;
| 型号： | S29JL032H60TAI2100 |
| 厂家： | 
CYPRESS |
| 描述： | Flash 内存集成电路 |
| 文件： | 总58页 (文件大小：2180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29JL032H
32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V
Simultaneous Read/Write Flash
Distinctive Characteristics
– 200 nA in standby or automatic slp mode
Architectural Advantages
Cycling Endurance: 1 million cycles per sector typical
Simultaneous Read/Write Operations
Data Retention: 20 years typical
– Data can be continuously read from one bank while executing
erase/program functions in another bank.
Software Features
– Zero latency between read and write operations
Multiple Bank Architecture
Supports Common Flash Memory Inerface (CFI)
– Four bank architectures available (refer to Table on page 11).
Boot Sectors
Erase SuspendErse Resume
– Suspends erase operations to read data from, or program data to,
a sectot is not being ersed, then resumes the erase
operaion.
– Top and bottom boot sectors in the same device
– Any combination of sectors can be erased
Manufactured on 0.13 µm Process Technology
Data# Polling and Togge Bits
Provides a software method of detecting the status of program or
erase cycles
Secured Silicon Sector: Extra 256 Byte sector
– Customer lockable: One-time programmable only. Once locked,
data cannot be changed
Unlock BypProgram Command
– Reduces overall programming time when issuing multiple
program command sequences
Zero Power Operation
– Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
Hardware Features
Compatible with JEDEC standards
– Pinout and software compatible with single-power-supply flash
standard
eady/Busy# Output (RY/BY#)
– Hardware method for detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method of resetting the internal state machine to the
read mode
Package options
48-pin TSOP
WP#/ACC Input Pin
Performance Characteristics
– Write protect (WP#) function protects the two outermost boot
sectors regardless of sector protect status
High Performance
– Access time as fast as 60
– Acceleration (ACC) function accelerates program timing
– Program time: 4 µs/word tycal using accelerated programming
function
Sector Protection
– Hardware method to prevent any program or erase operation
within a sector
Ultra Low Power Consumption (typicvalues)
– 2 mA active read current at 1 MHz
– Temporary Sector Unprotect allows changing data in protected
sectors in-system
– 10 mA active read current at 5 MHz
General Descripion
The S29JL032H is a 2 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304
bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to
be programmed system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.
The device is available with an access time of 60, 70, or 90 ns and is offered in a 48-pin TSOP package. Standard control pins—
chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus
contention issues.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
Cypress Semiconductor Corporation
Document Number: 002-01186 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 08, 2015
S29JL032H
Contents
1.
Simultaneous Read/Write Operations with Zero
Latency ......................................................................... 3
1.1 S29JL032H Features..................................................... 3
14.1 CMOS Compatible........................................................ 38
14.2 Zero-Power Flash ......................................................... 39
15. Test Conditions........................................................... 40
16. Key To Switching Waveforms.................................... 41
2.
Product Selector Guide............................................... 3
3.
Block Diagram.............................................................. 4
17. AC Characteristics.................................................... 41
17.1 Read-Only Operations................................................. 41
17.2 Hardware Reset (RET#)........................................... 43
17.3 Word/Byte Configuration (BYTE#)................................ 44
17.4 Erase and Program Operatios.................................... 45
17.5 Temporary Sctor Unprotect......................................... 49
17.6 AlternCE# Controlled Erase and Program
3.1 4 Bank Device................................................................ 4
3.2 2 Bank Device................................................................ 5
4.
5.
6.
7.
8.
Connection Diagrams.................................................. 6
Pin Description............................................................. 6
Logic Symbol ............................................................... 7
Ordering Information................................................... 7
Device Bus Operations................................................ 8
Operations ....................................................................50
18. Erase and Programming Performance ..................... 51
19. TSOP Pin Capacitance................................................ 52
8.1 Word/Byte Configuration................................................ 9
8.2 Requirements for Reading Array Data........................... 9
8.3 Writing Commands/Command Sequences.................. 10
8.4 Simultaneous Read/Write Operations with
0. Physicamensions.................................................. 53
20.1 TS 048—48-Pin Standard TSOP.................................. 53
21. Revision History.......................................................... 54
211 Revision A0 (May 21, 2004).......................................... 54
21Revision A1 (August 5, 2004) ....................................... 54
1.3 Revision A2 (March 10, 2005) ...................................... 54
21.4 Revision B0 (September 21, 2005)............................... 54
21.5 Revision B1 (November 28, 2005)................................ 54
21.6 Revision B2 (March 13, 2006) ...................................... 55
21.7 Revision B3 (May 19, 2006).......................................... 55
21.8 Revision B4 (June 7, 2007)........................................... 55
21.9 Revision B5 (August 10, 2007)..................................... 55
21.10Revision B6 (March 7, 2008)........................................ 55
21.11Revision B7 (July 7, 2008)............................................ 55
21.12Revision B8 (August 31, 2009)..................................... 55
Zero Latency................................................................
8.5 Standby Mode........................................................10
8.6 Automatic Sleep Mode................................................. 11
8.7 RESET#: Hardware Reset Pin.................................. 11
8.8 Output Disable Mode ................................................... 11
8.9 Autoselect Mode ....................................................... 1
8.10 Sector/Sector Block Protection and Unprotection........ 17
8.11 Write Protect (WP#)..................................................... 19
8.12 Temporary Sector Unprotect..................................... 19
8.13 Secured Silicon Sector Flash Memory Region ............ 21
8.14 Hardware Data Protection........................................ 22
9.
Common Flash MemorInterface (CFI)................... 23
10. Command Definions............................................... 26
10.1 Reading Array Data ................................................... 26
10.2 Reset Comand.......................................................... 26
10.3 Autoselect Command Sequence ................................. 26
10.4 Enter Secured Silicon Sector/Exit Secured
Silicon Sector Commnd Sequence ............................ 27
10.5 Byte/Word Program Command Sequence................... 27
10.6 Chip Erase Command Sequence ................................ 28
10.7 Sector EraCommand Sequence ............................. 28
10.8 Erase Suspend/Erase Resume Commands ................ 30
11. Write Operation Status .............................................. 32
11.1 DQ7: Data# Polling ...................................................... 32
11.2 RY/BY#: Ready/Busy#................................................. 33
11.3 DQ6: Toggle Bit I ......................................................... 34
11.4 DQ2: Toggle Bit II ........................................................ 35
11.5 Reading Toggle Bits DQ6/DQ2.................................... 36
11.6 DQ5: Exceeded Timing Limits ..................................... 36
11.7 DQ3: Sector Erase Timer............................................. 37
12. Absolute Maximum Ratings...................................... 37
13. Operating Ranges...................................................... 38
14. DC Characteristics..................................................... 38
Document Number: 002-01186 Rev. *A
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S29JL032H
1. Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into separate banks
(see Table on page 11). Sector addresses are fixed, system software can be used to form user-defined bank groups.
During an Erase/Program operation, any of the non-busy banks may be read from. Note that only two banks can operate
simultaneously. The device can improve overall system performance by allowing a host system to progm or erase in one bank,
then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the
completion of program or erase operations.
The S29JL032H can be organized as both a top and bottom boot sector configuration.
1.1
S29JL032H Features
The Secured Silicon Sector is an extra 256 byte sector capable of being permanently locked by e customer. The Secured Silicon
Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been locked d is 0 if lockable.
Customers may utilize the Secured Silicon Sector as bonus space, reading and writing like ny other flash sector, or may
permanently lock their own code there.
DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous
read/write product line by allowing removal of EEPROM devices. S will also allthe system software to be simplified, as it will
perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a
particular piece of data (a phone number or configuration dafor example)he user only needs to state which piece of data is to be
updated, and where the updated data is located in the syste. This is an advantage compared to systems where user-written
software must keep track of the old data location, statusgical to phyal translation of the data onto the Flash memory device (or
memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead,
the user's software accesses the Flash memory by calling one of osix functions.
The device offers complete compatibility with te JEDEC 42.4 single-power-supply Flash command set standard. Commands
are written to the command register using standard microprocssor write timings. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or erae operation is complete by using the device status bits: RY/BY# pin, DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to
the read mode.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is lly erased wheshipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The ardware sector protection feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The device offers two powesaving features. When addresses have been stable for a specified amount of time, the device enters
the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both modes.
2. Product Selector Guide
Part Number
Standard Voltage Range: V = 3.0–3.6 V
S29JL032H
60
CC
Speed Option
Standard Voltage Range: V = 2.7–3.6 V
70
70
70
30
90
90
90
35
CC
Max Access Time (ns), t
60
60
25
ACC
CE# Access (ns), t
OE# Access (ns), t
CE
OE
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S29JL032H
3. Block Diagram
3.1
4 Bank Device
V
V
CC
OE# BYTE#
SS
Mux
Bank 1
Bank 1 Address
A20–A0
X-Decoder
Bank 2 Address
RY/BY#
Bank 2
X-Decoder
A20–A0
STATE
CONTROL
&
RESET#
WE#
Status
DQ15–DQ0
COMMAND
REGISTER
CE#
BYTE#
Control
Mux
WP#/ACC
DQ0–DQ15
X-Decoder
Bank 3
Bank 3 Address
X-Decoder
Bank 4
A20–A0
Bank 4 Address
Mux
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S29JL032H
3.2
2 Bank Device
OE# BYTE#
V
V
CC
SS
Upper Bank Address
A20–A0
Upper Bank
X-Decoder
RY/BY#
A20–A0
RESET#
WE#
STATE
CONTROL
&
COMMAND
REGISTER
Ss
DQ15–DQ0
CE#
BYTE#
WP#/ACC
Control
DQ15–DQ0
X-Decoder
Lower Bank
A20–A0
Lower Bank Add
OE# BYTE#
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S29JL032H
4. Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ151
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
48-Pin Standard TSOP
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
5. Pin Description
A20–A0
DQ14–DQ0
DQ15/A-1
CE#
21 Addresses
15 Data Inuts/Outputs (x1only devices)
DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode)
Chip Enable
OE#
Output Enable
WE#
Write Enable
WP#/ACC
RESET#
BYTE#
RY/BY#
Hardware Write Protect/Acceleration Pin
Hadware Reset Pin, Active Low
Selects 8-bit or 16-bit mode
Ready/Busy Output
3.0 volt-only single power supply (see Product Selector Guide on page 3 for
speed options and voltage supply tolerances)
VCC
VSS
NC
Device Ground
Pin Not Connected Internally
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S29JL032H
6. Logic Symbol
21
A20–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY
7. Ordering Information
The order number (Valid Combination) is formed by the following:
S29JL032H
60
T
A
I
00
0
Packing Type
0
= Tr
3
= 13-inch Tape and Reel
Moel Number
01 Top Boot DevicBanks: 4/12/12/4 Mb
02 = Bottom Boot Device, 4 Banks: 4/12/12/4 Mb
21 = Top BooDevice, 2 Banks: 4/28 Mb
22 = Bottom oot Device, 2 Banks: 4/28 Mb
31 = Top Boot Device, 2 Banks: 8/24 Mb
32 = Bottom Boot Device, 2 Banks: 8/24 Mb
41 = Top Boot Device, 2 Banks: 16/16 Mb
42 = Bottom Boot Device, 2 Banks: 16/16 Mb
Temperature Range
I
= Industrial (–40C to +85C)
Package Material Set
A
F
= Standard
= Pb-free
Package Type
= Thin Small Outline Package (TSOP) Standard Pinout
T
Speed Option
60 = 60 ns
70 = 70 ns
90 = 90 ns
Device Family
S29JL032H
3.0 Volt-only, 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) Simultaneous Read/Write Flash Memory
Manufactured on 130 nm process technology
Document Number: 002-01186 Rev. *A
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S29JL032H
S29JL032H Valid Combinations
Package, Material, Set and
Temperature Range
Model
Number
Device Family
Speed Option
Packing Type
Package Type
01
02
21
22
31
32
41
42
60
70
0
3
TAI
TFI
S29JL032H
TS048
TSOP
90
(Note 1)
(Note 2)
Note
1. Type 0 is standard. Specify others as required; TSOPs can be packed in Types 0 and 3.
2. Operating voltage V varies depending on speed option.
CC
Valid Combinations
Valid Combinations list configurations planned to be supported in vume for this device. Consult your local Spansion sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
8. Device Bus Operations
This section describes the requirements and use of the device bus opetions, which are initiated through the internal command
register. The command register itself does not occpy any addressae memory location. The register is a latch used to store the
commands, along with the address and data information needed to execute the command. The contents of the register serve as
inputs to the internal state machine. The state achine outpudictate the function of the device. Table lists the device bus
operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
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S29JL032H
S29JL032H Device Bus Operations
DQ15–DQ8
BYTE# = V
Addresses
(Note 1)
Operation
Read
CE#
L
OE# WE# RESET# WP#/ACC
BYTE# = V
DQ7–DQ0
IH
IL
L
H
L
H
H
L/H
A
D
D
OUT
IN
IN
OUT
DQ14–DQ8 = High-Z,
DQ15 = A-1
Write
L
H
(Note 3)
A
D
D
N
IN
V
0.3 V
V
0.3 V
CC
CC
Standby
X
X
L/H
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Sector Protect
(Note 2)
SA, A6 = L,
A1 = H, A0 = L
L
H
L
V
L/H
X
X
X
D
ID
IN
Sector Unprotect
(Note 2)
SA, A6 = H,
A1 = H, A0 = L
L
H
X
L
V
V
(Note 3)
(Note 3)
X
D
D
ID
ID
IN
IN
Temporary Sector
Unprotect
X
X
A
D
High-Z
IN
IN
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
V
V
= 8.5–12.5 V
ID
= 9.0 ± 0.5 V
HH
X = Don’t Care
SA = Sector Address
A
= Address In
= Data In
IN
D
D
IN
= Data Out
OUT
Notes
1. Addresses are A20:A0 in word mode (BYTE# = V ), A20:A-1 in byte mode (BYTE# = V ).
IH
IL
2. The sector protect and sector unprotect functions may also be impmented via programming equipment. See Sector/Sector Block Protection and Unprotection
on page 17.
3. If WP#/ACC = V , the two outermost bosectors remain protected. If WP#/ACC = V , protection on the two outermost boot sectors depends on whether they were
IL
IH
last protected or unprotected usinhe method described in Sector/Sector Block Protection and Unprotection on page 17. If WP#/ACC = V , all sectors will be
HH
unprotected.
8.1
Word/Byte Confguration
The BYTE# pin ontrols whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic
‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at lic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by
CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. Each bank remains enabled for read access until the command register contents are altered.
Refer to the Read-Only Operations on page 41 for timing specifications and to Figure 17.1 on page 42 for the timing diagram. ICC1 in
DC Characteristics on page 38 represents the active current specification for reading array data.
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S29JL032H
8.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte
Configuration on page 9 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only
two write cycles are required to program a word or byte, instead of four. Byte/Word Program Command Sequencon page 27 has
details on programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 12 and Table on page 14 indicate
the address space that each sector occupies. Similarly, a “sector address” is the address bits required uniquely select a sector.
Command Definitions on page 26 has details on erasing a sector or the entire chip, or spending/resuming the erase operation.
The device address space is divided into four banks. A “bank address” is the adss bits requireto uniquely select a bank.
ICC2 in the DC Characteristics table represents the active current specificatiofor the write ode. AC Characteristics on page 41
contains timing specification tables and timing diagrams for write operations.
8.3.1
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC
pin. This function is primarily intended to allow faster manufturing througut at the factory.
If the system asserts VHH on this pin, the device automally enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher voltage on the pto reduce the time required for program operations. The
system would use a two-cycle program command equence as requed by the Unlock Bypass mode. Removing VHH from the WP#/
ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than
accelerated programming, or device damage may result. In adition, the WP#/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result. See Write Protect (WP#) on page 19 for related information.
8.3.2
Autoselect Functions
If the system writes the autoseleccommand sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the inal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings
apply in this mode. Refer to Autoselect Mode on page 16 and Autoselect Command Sequence on page 26 for more information.
8.4
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An
erase operation may also be suspended to read from or program to another location within the same bank (except the sector being
erased). Figure 17.8 on pae 47 shows how read and write cycles may be initiated for simultaneous operation with zero latency.
ICC6 and ICC7 in DC Caracteristics on page 38 represent the current specifications for read-while-program and read-while-erase,
respectively.
8.5
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
ICC3 in DC Characteristics on page 38 represents the standby current specification.
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S29JL032H
8.6
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. ICC5 in DC Characteristics on page 38 represents the automatic sleep mode current specification.
8.7
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. en the RESET# pin is driven low for
at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state machito reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept other command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held VSS±0.3 V, the device draws CMOS standby
current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system ret would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RYY# pin remains a “0” (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is assewhen a proram or erase operation is not executing (RY/BY# pin is
“1”), the reset operation is completed within a time of tRY (not during Embedded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Refer to AC Characteristics on page 41 for RESET# parameters anto Figure 17.2 on page 43 for the timing diagram.
8.8
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
S29JL032H Bank Architecture
Device
Model
Number
Bank 1
Sector Size
Bank 2
Sector Size
Bank 3
Sector Size
Bank 4
Sector Size
Megabit
egabit
Megabit
Megabit
Eight
8 Kbyte/
4 Kword,
seven
64 te/
32 Kword
Twenty-four
64 Kbyte/
32 Kword
Twenty-four
64 Kbyte/
32 Kword
Eight 64 Kbyte/
32 Kword
01, 02
4 Mbit
12 Mbit
12 Mbit
4 Mbit
Device
Model
Bank 1
Bank 2
Number
Megabits
Sector Size
Megabit
Sector Size
Fifty-six
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
21, 22
4 Mbit
28 Mbit
64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
31, 32
41, 42
8 Mbit
24 Mbit
16 Mbit
Eight 8 Kbyte/4 Kword,
thirty-one 64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
16 Mbit
Document Number: 002-01186 Rev. *A
Page 11 of 58
S29JL032H
S29JL032H Sector Addresses - Top Boot Devices (Sheet 1 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA0
Address Range
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
10010xxx
010011xxx
010100xxx
010101xx
01110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/
64/32
64/32
64/32
64/32
64/32
62
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFF
040000h-04FFFF
050000h-05FFFh
06000-06FFFFh
070000h-07FFFFh
000h-08FFFFh
090000h-09FFFFh
0A0000h-0FFFFh
0B000h-0BFFFFh
0C00h-0CFFFFh
0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
00h-07FFFh
008000h-0FFFF
010000h-17FFFh
018000hFFFFh
020000h-027FFFh
02000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA2
SA22
SA23
SA24
SA25
SA26
S7
SA28
SA29
SA30
SA31
Document Number: 002-01186 Rev. *A
Page 12 of 58
S29JL032H
S29JL032H Sector Addresses - Top Boot Devices (Sheet 2 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA5
SA54
SA55
SA56
SA57
SA58
SA9
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Address Range
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
10011xxx
110100xxx
11010x
1110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/3
64/32
64/32
64/32
64/32
64/32
642
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFF
250000h-25FFh
260000h-26FFFFh
27000h-27FFFFh
000h-28FFFFh
290000h-29FFFFh
2A0000h-2FFFh
2B0000h-2BFFFFh
2C0-2CFFFFh
2000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3F1FFFh
3F2000h-3F3FFFh
3F4000h-3F5FFFh
3F6000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
3FC000h-3FDFFFh
3FE000h-3FFFFFh
10h-107FFFh
108000h-10FFFFh
110000h-117FFh
118000h-11FFFFh
120000h-127FFFh
1200h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1BFFFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1DFFFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1F8FFFh
1F9000h-1F9FFFh
1FA000h-1FAFFFh
1FB000h-1FBFFFh
1FC000h-1FCFFFh
1FD000h-1FDFFFh
1FE000h-1FEFFFh
1FF000h-1FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Document Number: 002-01186 Rev. *A
Page 13 of 58
S29JL032H
S29JL032H Sector Addresses - Bottom Boot Devices (Sheet 1 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA0
Address Range
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
01011xxx
001100xxx
001101xxx
001110xx
00111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
8/4
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFF
00A000h-00FFFh
00C00-00DFFFh
00E000h-00FFFFh
000h-01FFFFh
020000h-02FFFFh
030000h-0FFFFh
04000h-04FFFFh
05000h-05FFFFh
0000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
000-000FFFh
001000h-001FFF
002000h-002FFFh
003000h3FFFh
004000h-004FFFh
00000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
SA1
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/
64/32
64/32
64/32
64/32
64/32
62
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA2
SA22
SA23
SA24
SA25
SA26
S7
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Document Number: 002-01186 Rev. *A
Page 14 of 58
S29JL032H
S29JL032H Sector Addresses - Bottom Boot Devices (Sheet 2 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA6
SA61
SA62
SA63
SA64
SA65
SA6
SA67
SA68
SA69
SA70
Address Range
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
110111xxx
111000xxx
110001xxx
110010xxx
0011xxx
110100xxx
110101x
1110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/3
64/32
64/32
64/32
64/32
64/32
64
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFF
250000h-25FFh
260000h-26FFFFh
27000h-27FFFFh
000h-28FFFFh
290000h-29FFFFh
2A0000h-2FFFh
2B0000h-2BFFFFh
2C002CFFFFh
2D00h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3F1FFFh
100h-107FFFh
108000h-10FFFFh
110000h-117FFF
118000h-11FFFFh
120000h-127FFFh
1200h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
Document Number: 002-01186 Rev. *A
Page 15 of 58
S29JL032H
8.9
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes
output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in
Table . In addition, when verifying sector protection, the sector address must appear on the appropriate highest oer address bits.
Table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autlect codes can also be accessed in-
system through the command register, for instances when the S29JL032H is erased or programmed in a system without access to
high voltage on the A9 pin. The command sequence is illustrated in Table on page 31. Note that if a Bak Address (BA) on address
bits A20, A19 and A18 is asserted during the third write cycle of the autoselect comma, the host system can read autoselect data
from that bank and then immediately read array data from another bank, without xiting the autolect mode.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown
in Table on page 31. This method does not require VID. Refer to Autoselect Command Seqence on page 26 for more information.
S29JL032H Autoselect Codes (High Voltage Method)
DQ15 to DQ8
A11
to
DQ7
to
A20
to
A8
to
5
to
BYTE# BYTE#
Description
CE# OE# WE#
A12
A10
A9
A7
6
A4
A3
A2
A1
A0
= V
= V
DQ0
IH
IL
Manufacturer ID:
Spansion Products
L
L
H
BA
X
V
L
X
L
L
L
L
X
X
01h
ID
Read Cycle 1
Read Cycle 2
L
L
L
L
L
H
L
22h
22h
7Eh
0Ah
H
H
H
L
L
H
BA
X
V
X
X
X
ID
00h (bottom boot)
01h (top boot)
Read Cycle 3
L
H
H
H
H
22h
Device ID
56h (bottom boot)
55h (top boot)
L
L
L
L
H
H
BA
BA
X
X
V
V
X
X
L
L
X
X
H
H
X
X
X
X
L
L
22h
22h
X
X
ID
ID
(Models 21, 22)
Device ID
53h (bottom boot)
50h (top boot)
(Models 31, 32)
Device ID
5Fh (bottom boot)
5Ch (top boot)
L
L
L
L
H
H
A
SA
X
X
V
V
X
X
L
L
X
X
H
L
X
L
X
H
L
L
22h
X
X
X
ID
ID
(Models 41, 42)
Sector Protection
Verification
01h (protected),
00h (unprotected)
Secured Silicon
Indicator Bit (DQ6,
DQ7)
42h (customer locked),
82h (not customer
locked) (See Note)
L
H
BA
X
V
X
L
X
L
L
H
H
X
X
ID
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
BA = Bank Address
SA = Sector Address
X = Don’t care
.
Note
Some current and most future Spansion devices (including future revisions of this device) offer an option for programming and permanently locking
the Secured Silicon Sector at the factory. The Secured Silicon Indicator data changes to 82h if factory locked, 42h if customer locked, and 02h (not
82h) if non-factory/customer locked.
Document Number: 002-01186 Rev. *A
Page 16 of 58
S29JL032H
8.10 Sector/Sector Block Protection and Unprotection
Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more
adjacent sectors that are protected or unprotected at the same time (see Table ).
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previously protected sectors. Sector protectiounprotection can be
implemented via two methods.
S29JL032H Boot Sector/Sector Block Addresses for
Protection/Unprotection (Top Boot Devices)
Secor/
Sector
A20-A12
Sector Block Size
SA0
000000XXX
64 bytes
000001XXX
000010XXX
000011XXX
SA1-SA3
192 (3X64) Kes
SA4-SA7
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXX
1000XXXXX
101XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
256 (4X64) Kbytes
24X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
111100XXX
111101XXX
111110XXX
SA60-SA62
192 (3X64) Kbytes
S3
SA64
SA65
SA66
SA
SA
SA69
SA70
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
Document Number: 002-01186 Rev. *A
Page 17 of 58
S29JL032H
S29JL032H Sector/Sector Block Addresses for
Protection/Unprotection (Bottom Boot Devices)
Sector/
Sector
A20-A12
Sector Block Size
SA70
111111XXX
64 Kbytes
111110XXX
111101XXX
111100XXX
SA69-SA67
192 (3X64) Kbytes
SA66-SA63
SA62-SA59
SA58-SA55
SA54-SA51
SA50-SA47
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22-SA19
SA18-SA15
SA14-SA11
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXX
256 (4X64) Kbyte
256 (4X64) Kbytes
256 (4X64bytes
25(4X64) Kbytes
25X64) Kbytes
256 (4X64) Kbyts
256 (4X64) Kbytes
256 (4X64) Kbytes
256 4) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
256 (4X64) Kbytes
000011XXX
0000XXX
000001XXX
SA10-SA8
192 (3X64) Kbytes
SA7
SA6
SA5
SA4
SA3
SA2
SA
SA0
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
Sector protect/Sector Unprect requires VID on the RESET# pin only, and can be implemented either in-system or via programming
equipment. Figure 8.2 on page 20 shows the algorithms and Figure 17.13 on page 50 shows the timing diagram. For sector
unprotect, all unpoteed sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect
algorithm unprots all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in
protected sectors efficiently, the temporary sector unprotect function is available. See Temporary Sector Unprotect on page 49..
The device is shipped with all sectors unprotected. Optional Spansion programming service enable programming and protecting
sectors at the factory prior to shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 16 for details.
Document Number: 002-01186 Rev. *A
Page 18 of 58
S29JL032H
8.11 Write Protect (WP#)
The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of
two provided by the WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 8 Kbyte boot
sectors independently of whether those sectors were protected or unprotected using the method descrid in Sector/Sector Block
Protection and Unprotection on page 17. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest
addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-nfigured device.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8K Byte boot sectors were last set to
be protected or unprotected. That is, sector protection or unprotection for these two sectors ends on whether they were last
protected or unprotected using the method described in Sector/Sector Block Protection and Unprotection on page 17.
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behaor of the device may result.
WP#/ACC Modes
WP# Input Voltage
Device Mode
V
Disables programming and erasing in the two outermost boot ses
IL
Enables programming and erasing in the two outermost boot sectors, dependent on whether they were last
protected or unprotected
V
IH
V
Enables accelerated programming (ACC). See Accelerated Program Operation on page 10.
HH
8.12 Temporary Sector Unprotect
(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or
more adjacent sectors that are protected or unprotcted at the samtime (see Table on page 17 and Table on page 18).)
This feature allows temporary unprotection of reviously protected sectors to change data in-system. The Temporary Sector
Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are
protected again. Figure 8.1 shows the algorithm, and Fure 17.12 on page 49 shows the timing diagrams, for this feature. If the
WP#/ACC pin is at VIL, the two outermost boot sectors will remain protected during the Temporary sector Unprotect mode.
Figure 8.1 Temporary Sector Unprotect Operation
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes
1. All protected sectors unprotected (If WP#/ACC = V , the outermost two boot sectors will remain protected).
IL
2. All previously protected sectors are protected once again.
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Figure 8.2 In-System Sector Protect/Unprotect Algorithms
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
Wait 1 ms
Wait 1 ms
unprotect address
No
No
st Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6=0, A3=0, A2=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
Wait 150 µs
A6=1, A3=0, A2=0,
A1=1, A0=0
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A3=0,
A2=0, A1=1, A0=0
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6=1, A3=0, A2=0,
A1=1, A0=0
Read from
sector address with
A6=0, A=0, A2=0,
A1=1, A0=0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
Data = 01
Yes
sector address with
A6=1, A3=0, A2=0,
A1=1, A0=0
No
es
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Unprotect
Algorithm
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
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8.13 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic
Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and is shipped unprotected, allowing customers to utilize
that sector in any manner they choose. The Secured Silicon Customer Indicator Bit (DQ6) is permanently set to 1 if the part has
been customer locked and is 0 if customer lockable. DQ7, alternatively, is set to 0 if the part has been customer locked, and is 1 if
customer-lockable.
Some current and most future Spansion devices (including future revisions of this device) will offer an option for pgramming and
permanently locking the Secured Silicon Sector at the factory. DQ7 will become the Secured Silicon Factory Indicator bit, and as
such the Secured Silicon Indicator Bit data will change to 82h for factory locked, 42h for cuser locked, and 02h (no longer 82h)
for not factory/customer locked.
The system accesses the Secured Silicon through a command sequence (see Enter Secured Silicon Sctor/Exit Secured Silicon
Sector Command Sequence on page 27). After the system has written the Enter Securd Silicon Sector command sequence, it may
read the Secured Silicon Sector by using the addresses normally occupied by thboot sectors. Tis mode of operation continues
until the system issues the Exit Secured Silicon Sector command sequence, r until power is removed from the device. On power-
up, or following a hardware reset, the device reverts to sending commands to the first 256 btes of Sector 0. Note that the ACC
function and unlock bypass modes are not available when the Secured ilicon Sector is enabled.
8.13.1
Factory Locked: Secured Silicon Stor Programmed and Protected At the
Factory
In a factory locked device, the Secured Silicon Sector is protcted when the device is shipped from the factory. The Secured Silicon
Sector cannot be modified in any way. The device is preprammed wboth a random number and a secure ESN. The 8-word
random number is at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The secure ESN is
programmed in the next 8 words at addresses 00008h–00000Fh (000010h–00001Fh in byte mode). The device is available
preprogrammed with one of the following:
A random, secure ESN only
Customer code through Spansion programming servces
Both a random, secure ESN and customer code through Spansion programming services
Contact an your local sales office or details on using Spansion programming services.
8.13.2
Custmer Lockable: Secured Silicon Sector NOT Programmed or Protected At
the Factory
If the security feure is not required, the Secured Silicon Sector can be treated as an additional Flash memory space. The Secured
Silicon Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated
programming (ACC) and unock bypass functions are not available when programming the Secured Silicon Sector.
The Secured Silicon Sector area can be protected using one of the following procedures:
Write the threycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect
algorithm as shown in Figure 8.2 on page 20, except that RESET# may be at either VIH or VID. This allows in-system protection of
the Secured Silicon Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the
Secured Silicon Sector.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 8.3 on page 22.
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command
sequence to return to reading and writing the remainder of the array.
The Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the
Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.
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Figure 8.3 Secured Silicon Sector Protect Verify
START
If data = 00h,
RESET# =
Secure Silicon Sector
VIH or VID
is unprotected.
If data = 01h,
Secure Silicon Sector
Wait 1 ms
is protected.
Write 60h to
any address
Remove VIH or VID
from RESE#
Write 40h to Secure
Silicon Sector address
with A6 = 0,
Write reset
ommand
A1 = 1, A0 = 0
ecure Silicon Se
Protect Verify
coplete
Read from Secure
Silicon Sector address
with A6 = 0
A1 = 1, = 0
8.14 Hardware Data Protecton
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to Table on page 31 for command definitins). In addition, the following hardware data protection measures prevent
accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from stem noise.
8.14.1
Low VCC Write Inhibit
When VCC is less than VLKO, the dece does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO
.
8.14.2
Write Pulse “Glitch” Protection
Noise pulses of than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.14.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
8.14.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to the read mode on power-up.
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9. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows
specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-
independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or
address AAh in byte mode), any time the device is ready to read array data. The system can read CFI informatioat the addresses
given in Table . To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible
when the device is executing an Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The devce enters the CFI query
mode, and the system can read CFI data at the addresses given in Table . The system must write the reset command to reading
array data.
For further information, please refer to the CFI Specification and CFI Publication 0. Contact your local sales office for copies of
these documents.
CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
Query Unique I string “QRY”
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address r Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
System Interface String
Addresses
Addresss
(Word Mode)
(Byte Mode)
Dat
Description
V
Min. (write/erase)
CC
1Bh
1Ch
36h
38h
0027h
0036h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3A
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0003h
0000h
0009h
0000h
0005h
0000h
0004h
0000h
V
Min. voltage (00h = no V pin present)
PP
PP
V
Max. voltage (00h = no V pin present)
PP
PP
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
27h
4Eh
0016h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 10
31h
32h
33h
34h
62h
64h
66h
68h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI ublication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
(refer to the CFI specifior CFI publica00)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Re4 Information
(refer to thI specification r CFI publication 100)
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Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
000Ch
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = o Read & Write
46h
47h
48h
49h
8Ch
8Eh
90h
92h
0002h
0001h
0001h
0004h
Sector Protect
0 = Not Supported, X = Number of sors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Suprted
Sector Protect/Unprotect scheme
01 =29F040 mode, 02 016 mode, 03 = 400, 04 = 29LV800 mode
Number of sectors (excluding Bank 1)
XX = 38 (mode, 02, 21, 22)
XX = 30 (mels 31, 32)
4Ah
94h
00XXh
XX = 20 (mels 41, 42)
BuMode Type
00 = Not Supported, 01 = Supported
4Bh
4Ch
96h
98h
0000h
0000h
Page Mode Type
00 = Not Support01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleraion) Supply Minimum
4Dh
4Eh
4Fh
50h
9Ah
9Ch
9Eh
A0h
0085h
0095h
000Xh
0001h
00h = Noupported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
Program Suspend
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero
X = 4 (4 banks, models 01, 02)
X = 2 (2 banks, all other models)
57h
58h
AEh
B0h
000Xh
00XXh
Bank 1 Region Information - Number of sectors on Bank 1
XX = 0F (models 01, 02, 21, 22)
XX = 17 (models 31, 32)
XX = 27 (models 41, 42)
Bank 2 Region Information - Number of sectors in Bank 2
XX = 18 (models 01, 02)
59h
B2h
00XXh
XX = 38 (models 21, 22)
XX = 30 (models 31, 32)
XX = 20 (models 41, 42)
Bank 3 Region Information - Number of sectors in Bank 3
XX = 18 (models 01, 02)
5Ah
5Bh
B4h
B6h
00XXh
00XXh
XX = 00 (all other models)
Bank 4 Region Information - Number of sectors in Bank 4
XX = 08 (models 01, 02)
XX = 00 (all other models)
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10. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table on page 31
defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence
may place the device in an unknown state. A hardware reset may be required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latcheon the rising edge of WE#
or CE#, whichever happens first. Refer to AC Characteristics on page 41 for timing diagrams.
10.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank
is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-spend-read mode, after which
the system can read data from any non-erase-suspended sector within the samank. The system can read array data using the
standard read timing, except that if it reads at an address within erase-suspeded sectors, te device outputs status data. After
completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 30 or more information.
The system must issue the reset command to return a bank to the ad (or erase-pend-read) mode if DQ5 goes high during an
active program or erase operation, or if the bank is in the autoselecmode. See Reset Command on page 26, for more information.
See also Requirements for Reading Array Data on page 9 fmore informaon. Read-Only Operations on page 41 provides the
read parameters, and Figure 17.1 on page 42 shows the timg diagram.
10.2 Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be writtebetween the sequence cycles in a program command sequence before programming begins.
This resets the bank to whice system was writing to the read mode. If the program command sequence is written to a bank that
is in the Erase Suspend modewriting the reset command returns that bank to the erase-suspend-read mode. Once programming
begins, however, the dice ignores reet commands until the operation is complete.
The reset command may be written etween the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset mmand must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.
If DQ5 goes high during a pogram or erase operation, writing the reset command returns the banks to the read mode (or erase-
suspend-read mode if that bank was in Erase Suspend).
10.3 Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or
not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in
another bank.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains
the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of
autoselect codes without reinitiating the command sequence.
Table on page 31 shows the address and data requirements. To determine sector protection information, the system must write to
the appropriate bank address (BA) and sector address (SA). Table on page 12 and Table on page 14 show the address range and
bank number associated with each sector.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in
Erase Suspend).
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10.4 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command
Sequence
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command
sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured
Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the dece to normal operation.
The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm.
Table on page 31 shows the address and data requirements for both command sequences. See also Secured Silicn Sector
Flash Memory Region on page 21 for further information. Note that the ACC function and unlock bypass modes are not available
when the Secured Silicon Sector is enabled.
10.5 Byte/Word Program Command Sequence
The system may program the device by word or byte, depending on the state of e BYTE# pin. ogramming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock wricycles, followed by the program set-up
command. The program address and data are written next, which in turn initte the Embeded Program algorithm. The system is
not required to provide further controls or timings. The device automatically provides internally generated program pulses and
verifies the programmed cell margin. Table on page 31 shows the addess and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched.
The system can determine the status of the program operatin by using DQ, DQ6, or RY/BY#. Refer to Write Operation Status
on page 32 for information on these status bits.
Any commands written to the device during the Embedded Program Alithm are ignored. Note that a hardware reset immediately
terminates the program operation. The program comand sequencshould be reinitiated once that bank has returned to the read
mode, to ensure data integrity. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program
operation is in progress.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.”
Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was
successful. However, a succeeding read will show thahe data is still “0.” Only erase operations can convert a “0” to a “1.”
10.5.1
Unlock Bpass Command Sequence
The unlock bypass feature allows the syem to program bytes or words to a bank faster than using the standard program command
sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program
command sequece is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same
manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time. Table on page 31 shows the requirements for the command sequence.
During the unlock bypss mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, thystem must issue the two-cycle unlock bypass reset command sequence. (Table on page 31).
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin,
the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC
pin must not be at VHH for any operation other than accelerated programming, or device damage may result. In addition, the WP#/
ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
Figure 10.1 illustrates the algorithm for the program operation. Refer to Erase and Program Operations on page 45 for parameters,
and Figure 17.5 on page 46 for timing diagrams.
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Figure 10.1 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Addres
st Address?
Yes
Programming
Completed
Note
See Table on page 31 for program commasequence.
10.6 Chip Erase Commnd Sequence
Chip erase is a six bus cycle operatn. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up commandTwo additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any conols or timings during these operations. Table on page 31 shows the address and data requirements for
the chip erase command sequence.
When the Embeded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The
system can deterne the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status
on page 32 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an
erase operation is in progress.
Figure 10.2 on page 29 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 45 for
parameters, and Figure 17.7 on page 47 for timing diagrams.
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10.7 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command. Table on page 31 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm atomatically programs and
verifies the entire sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase time-out of 80 µs occurs. During the time-out period, additional sector
addresses and sector erase commands may be written. Loading the sector erase buffer may done in any sequence, and the
number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs,
otherwise erasure may begin. Any sector erase address and command following the exceeded time-oumay or may not be
accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written. Anommand other than Sector Erase or Erase
Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer hatimed out (See the section on DQ3: Sector Erase Timer.).
The time-out begins from the rising edge of the final WE# or CE# pulse (first rising edge) in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note
that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can
determine the status of the erase operation by reading DQ7Q6, DQ2, or RY/BY# in the erasing bank. Refer to Write Operation
Status on page 32 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However,
note that a hardware reset immediately terminates the erase operaon. If that occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured Silicon Sector,
autoselect, and CFI functions are unavailable hen an erase peration is in progress.
Figure 10.2 on page 29 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 45 for
parameters, and Figure 17.7 on page 47 for timing diaams.
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S29JL032H
Figure 10.2 Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Ebedded
Ease
algorithm
in progress
No
Data = FFh
Yes
Erasure Compled
Notes
1. See Table on page 31 for erase command sequence.
2. See the section on DQ3 for information on he sector erase timer.
10.8 Erase Suspend/Erase Resume Commands
The Erase Suspend commandB0h, allows the system to interrupt a sector erase operation and then read data from, or program
data to, any sector not lected for erare. The bank address is required when writing this command. This command is valid only
during the sector erase operation, inuding the 80 µs time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. The bank address must
contain one of thsectors currently selected for erase.
When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to
suspend the erase operati. However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase oration has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or
program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any
address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer to Write Operation Status on page 32 for
information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation.
Refer to Write Operation Status on page 32 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading
autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device
exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to
Autoselect Mode on page 16 and Autoselect Command Sequence on page 26 for details.
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S29JL032H
To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-
suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase
Suspend command can be written after the chip has resumed erasing.
S29JL032H Command Definitions
Bus Cycles (Notes 2–5)
Third Fourth
Addr Addr
Command
First
Addr
Second
Fifth
Addr
Sixth
Addr
Sequence
(Note 1)
Data
RD
F0
Addr
Data
Data
Da
Data
Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
AAA
555
Word
Byte
2AA
555
2AA
(BA)555
(BA)AAA
(BA)555
Manufacturer ID
4
6
AA
AA
55
55
90
9
BA)X00
01
Word
(BA)X01
(BA)X02
(BA)X0E
(BA)X1C
See
Table
(BA)X0F
(BA)X1E
See
Table
Se
Device ID (Note 9)
Table
Byte
AAA
555
(BA)AAA
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
XXX
XXX
55
AAA
555
AAA
BA
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2A
555
PA
(BA)555
(AA
(BA)555
(BA)AAA
555
(BA)X03
(06
(SA)X02
(SA)X04
Secured Silicon Sector
Factory Protect (Note 10)
4
4
3
4
4
3
AA
AA
AA
AA
AA
AA
55
55
55
55
55
55
90
90
88
90
A0
20
82/02
00/01
Sector/Sector Block
Protect Verify (Note 11)
Enter Secured Silicon Sector
Region
AAA
5
Exit Secured Silicon Sector
Region
XXX
PA
00
AAA
555
Program
PD
AAA
555
Unlock Bypass
AAA
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Byte
Word
Bye
AAA
Sector Erase
SA
AAA
AAA
Erase Suspend (Note 14)
Erase Resume (Note 15)
1
1
B0
30
BA
Word
Byte
55
CFI Query (Note 16)
1
98
AA
Legend
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector.
Refer to Table on page 12 and Table on page 14 for information on sector addresses.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A20–A18 uniquely select a bank.
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Notes
1. See Table on page 9 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A20–A11 are don’t cares for unlock and command cycles, unless SA or PA is required.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank n the autoselect
mode, or if DQ5 goes high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to ain the manufacturer ID, device ID, or Secured
Silicon Sector factory protect information. Data bits DQ15–DQ8 are don’t care. While reading the autoselect addressthe bank address must be the same until a
reset command is given. See Autoselect Command Sequence on page 26 for more information.
9. For models 01, 02, the device ID must be read across the fourth, fifth, and sixth cycles.
10. The data is 42h for customer locked, and 82h for not customer locked. Some current and most future Spansn devices (including future revisions of this device) will
offer an option for programming and permanently locking the Secured Silicon Sector at the factory. Secured Silicon Idicator data will change to 82h for factory
locked, 42h for customer locked, and 02h (no longer 82h) for not factory/customer locked.
11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector blk.
12. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the read mode when the bak is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or enter the autoselect ode, when in the se Suspend mode. The Erase Suspend command is valid
only during a sector erase operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase Suspend mode, and equires the bank address.
16. Command is valid when device is ready to read array data or when devicin autoselect me.
11. Write Operation Status
The device provides several bits to determine e status of a ogram or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table
on page 37 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining
whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/
BY#, to determine whether an Embedded Program or rase operation is in progress or has been completed.
11.1 DQ7: Data# olling
The Data# Polling bit, D7, indicates to he host system whether an Embedded Program or Erase algorithm is in progress or
completed, or whether a bank is in Ese Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command
sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to Q7. The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or
if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any
of the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at
an address within a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 (or DQ7–DQ0
for x8-only device) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may
change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-only device) while Output Enable (OE#) is asserted low. That is, the
device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid
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S29JL032H
data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on
successive read cycles.
Table on page 37 shows the outputs for Data# Polling on DQ7. Figure 11.1 on page 33 shows the Data# Polling algorithm.
Figure 17.9 on page 48 shows the Data# Polling timing diagram.
Figure 11.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
es
DQ7 = Data?
No
No
= 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid
address is any non-proted sector address.
2. DQ7 should be reked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
11.2 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read
mode.
Table on page 37 shows the outputs for RY/BY#.
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11.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cae DQ6 to toggle. The
system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for appoximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Erse algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is era-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 ggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine whicsectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on e 32).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs aftethe program command sequence is
written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
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Figure 11.2 Toggle Bit Algorithm
START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
No
Toggle Bit
= Toggle?
Yes
No
DQ5 1?
Yes
Read Byte Twice
(DQ7–D0)
Address = VA
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Program/Erase
Operation Complete
Complete, Write
Reset Command
Note
The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
11.4 DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use
either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-
suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table
on page 37 to compare outputs for DQ2 and DQ6.
Figure 11.2 on page 35 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 35 explains the algorithm.
See also DQ6: Toggle Bit I on page 34. Figure 17.10 on page 48 shows the toggle bit timing diagram. Figure 17.11 on page 49
shows the differences between DQ2 and DQ6 in graphical form.
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S29JL032H
11.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 11.2 on page 35 for the following discussion. Whenever the system initially begins reading toggle bit status, it must
read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycl.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system ao should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle s no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully,
and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggng and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, termining the satus as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this ase, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 11.2 on pag35).
11.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle wnot successly completed.
The device may output a “1” on DQ5 if the system tries rogram a “1” to a location that was previously programmed to “0.” Only
an erase operation can change a “0” back to a “1.” Under this condn, the device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read
mode if a bank was previously in the erase-suend-program ode).
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11.7 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The
sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less than 80 µs, the system need not
monitor DQ3. See also Sector Erase Command Sequence on page 28.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toge Bit I) to ensure
that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun;
all further commands (except Erase Suspend) are ignored until the erase operation is complIf DQ3 is “0,” the device will accept
additional sector erase commands. To ensure the command has been accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second statcheck, the last command
might not have been accepted.
Table shows the status of DQ3 relative to the other status bits.
Write Operation Status
DQ7
D5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No tgle
0
N/A
Toggle
1
Suspended Sector
Erase-Suspend-
Read
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Dta
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase opertion has exceeded the maximum timing limits. Refer to the section on DQ5 for more
information.
2. DQ7 and DQ2 require a valid address when reading status informan. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array
data if the system addresses a non-busank.
12. Absolute Mamum Ratings
Storage Temperature, Pltic Packages
Ambient Temperature with Power Applied
Voltage with Respct to Ground, VCC (Note 1)
A9, OE#, and RESET# (Note 2)
WP#/ACC
–65°C to +150°C
–65°C to +125°C
–0.5 V to +4.0 V
–0.5 V to +12.5 V
–0.5 V to +9.5 V
–0.5 V to VCC +0.5 V
200 mA
All other pins (Note 1
Output Short Circurrent (Note 3)
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V to –2.0 V for periods of up to 20 ns. Maximum DC
SS
voltage on input or I/O pins is V +0.5 V. See Figure 12.1 on page 37. During voltage transitions, input or I/O pins may overshoot to V +2.0 V for periods up to 20
CC
CC
ns. See Figure 12.2 on page 38.
2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V to –
SS
2.0 V for periods of up to 20 ns. See Figure 12.1 on page 37. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns.
Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
Figure 12.1 Maximum Negative Overshoot Waveform
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20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 12.2 Maximum Positive Overshoot Wavorm
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
2.0 V
ns
20 ns
13. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA)
–40°C to +85°C
V
Supply Voltages
CC
VCC for standard voltage rang2.7 V to 3.6 V
Operating ranges definthose limits between which the functionality of the device is guaranteed.
14. DC Characteristics
14.1 CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
Test Conditions
= V to V
Min
Typ
Max
Unit
V
V
,
CC
IN
SS
I
1.0
µA
LI
= V
CC
CC max
V
= V
, OE# = V ; A9 or
IH
CC
CC max
I
A9, OE# and RESET# Input Load Current
35
µA
LIT
OE# or RESET# = 12.5 V
V
V
= V to V
,
CC
OUT
SS
I
Output Leakage Current
Reset Leakage Current
1.0
µA
µA
LO
= V
, OE# = V
CC
CC max
IH
I
V
= V
; RESET# = 12.5 V
5 MHz
35
16
4
LR
CC
CC max
10
2
CE# = V , OE#
IL
Byte Mode
V ,
IH
=
1 MHz
5 MHz
1 MHz
V
Active Read Current
CC
I
I
mA
mA
CC1
CC2
(Notes 1, 2)
10
2
16
4
CE# = V , OE# = V
IL
Word Mode
,
IH
V
Active Write Current (Notes 2, 3)
CE# = V , OE# = V , WE# = V
IL
15
30
CC
IL
IH
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S29JL032H
Parameter
Symbol
Parameter Description
Standby Current (Note 2)
Reset Current (Note 2)
Test Conditions
Min
Typ
0.2
0.2
Max
10
Unit
µA
I
V
V
CE#, RESET# = V 0.3 V
CC3
CC
CC
I
RESET# = V 0.3 V
10
µA
CC4
CC
SS
V
V
= V 0.3 V;
IH
IL
CC
I
Automatic Sleep Mode (Notes 2, 4)
0.2
10
µA
CC5
CC6
= V 0.3 V
SS
Byte
Word
Byte
Word
21
21
21
21
45
45
45
45
V
Active Read-While-Program Current
CC
I
CE# = V , OE# = V
mA
IL
IH
(Notes 1, 2)
V
Active Read-While-Erase Current
CC
I
I
CE# = V , OE# = V
mA
mA
CC7
IL
IH
IH
(Notes 1, 2)
V
Active Program-While-Erase-
CC
CE# = V , OE# = V
17
35
CC8
IL
Suspended Current (Notes 2, 5)
V
Input Low Voltage
.5
.8
V
V
IL
V
Input High Voltage
0.7 x V
V
+ 0.3
IH
CC
CC
Voltage for WP#/ACC Sector Protect/
Unprotect and Program Acceleration
V
V
V
= 3.0 V ± 10%
8.5
8
9.5
V
V
HH
CC
CC
Voltage for Autoselect and Temporary Sector
Unprotect
V
= 3.0 V 10%
12.5
0.45
ID
V
Output Low Voltage
I
I
I
= 2.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
V
V
= –2.0 mA= V
0.85 x V
CC
OH1
OH2
LKO
C
CC min
Output High Voltage
= –10A, = V
V
–0.4
CC
CC
CC min
Low V Lock-Out Voltage (Note 5)
1.8
2.0
2.3
V
CC
Notes
1. The I current listed is typically less than 2 mA/MHz, with OE# at V
.
IH
CC
2. Maximum I specifications are tested with V = V mx.
CC
CC
CC
3.
I
active while Embedded Erase or Embedded Program is in progress.
CC
4. Automatic sleep mode enables the low power mode when addresses remain stable for t
5. Not 100% tested.
+ 30 ns. Typical sleep mode current is 200 nA.
ACC
14.2 Zero-Power lash
Figure 14.1 CC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note
Addresses are switching at 1 MHz
Document Number: 002-01186 Rev. *A
Page 39 of 58
S29JL032H
Figure 14.2 Typical ICC1 vs. Frequency
12
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note
T = 25 °C
15. Test Conditions
Figure 15.1 Test Setup
3.3 V
2.7 k
Device
Under
Test
C
6.2 k
L
Note
Diodes are IN3064 or equivalent.
Document Number: 002-01186 Rev. *A
Page 40 of 58
S29JL032H
Test Specifications
Test Condition
60
70, 90
1 TTL gate
Unit
Output Load
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0 or Vcc
0.5 Vcc
0.5 Vcc
Input timing measurement reference levels
Output timing measurement reference levels
V
V
16. Key To Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Cae, Any Change Permed
Does Not Aply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Figure 16.1 Input Waveforms and Measurement Levels
Vcc
0.5 Vcc
0.5 Vcc
Input
Measurement Level
Output
0.0 V
17. AC Characteristics
17.1 Read-Only Operations
Parameter
Speed Options
JEDEC
Std.
Description
Read Cycle Time (Note 1)
Test Setup
60
70
90
Unit
t
t
Min
60
70
90
ns
AVAV
RC
CE#,
OE# = V
t
t
Address to Output Delay
Max
60
70
90
ns
AVQV
ACC
IL
IL
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
60
25
70
30
16
16
90
35
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
t
t
t
Output Enable to Output Delay
OE
t
t
Chip Enable to Output High Z (Notes 1, 3)
Output Enable to Output High Z (Notes 1, 3)
DF
DF
t
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
0
0
ns
ns
ns
AXQX
OH
Read
Output Enable Hold Time
t
OEH
Toggle and
(Note 1)
5
10
Data# Polling
Document Number: 002-01186 Rev. *A
Page 41 of 58
S29JL032H
Notes
1. Not 100% tested.
2. See Figure 15.1 on page 40 and Table on page 41 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V /2. The time from OE# high to the data bus driven to V /2 is taken as t
DF.
CC
CC
Figure 17.1 Read Operation Timings
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
t
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Document Number: 002-01186 Rev. *A
Page 42 of 58
S29JL032H
17.2 Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to Read Mode
(See Note)
t
t
Max
Max
20
s
Ready
RESET# Pin Low (NOT During Embedded Algorithms) to Read
Mode (See Note)
500
ns
Ready
t
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RP
t
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
RB
Note
Not 100% tested.
Figure 17.2 Reset imings
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timgs NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/B
tRB
CE#, OE#
REET#
tRP
Document Number: 002-01186 Rev. *A
Page 43 of 58
S29JL032H
17.3 Word/Byte Configuration (BYTE#)
Parameter
Speed Options
JEDEC
Std.
Description
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
60
70
5
90
Unit
ns
t
t
Max
Max
Max
ELFL/ ELFH
t
16
70
ns
FLQZ
t
60
90
ns
FHQV
Figure 17.3 BYTE# Timings for Read Operations
CE#
OE#
BYTE#
tELFL
DOutput
DQ14–DQ0)
Data Output
(DQ7–DQ0)
BYTE#
DQ14–DQ0
DQ15/A-1
Switching
from word
to byte
mode
Address
Input
DQ15
Output
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data Output
(DQ7–DQ0)
Data Output
(DQ14–DQ0)
DQ14–DQ0
DQ15/A-1
Address
Input
DQ15
Output
tFHQV
Document Number: 002-01186 Rev. *A
Page 44 of 58
S29JL032H
Figure 17.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
tHOLD (tAH
)
)
Note
Refer to the Erase/Program Operations table for t and t specifications.
AS
AH
17.4 Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
60
70
70
0
90
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
60
90
AVAV
WC
t
t
ns
AVWL
AS
t
Address Setup Time to OE# low during toggle polling
Address Hold Time
12
40
ns
ASO
t
t
35
35
45
45
ns
WLAX
AH
Address Hold Time From CE# or Ohigh
during toggle bit polling
t
Min
0
ns
AHT
t
t
t
Data Setup Time
Min
Min
Min
40
0
ns
ns
ns
DVWH
DS
t
Data Hold Time
WHDX
DH
t
Output Enable High during toggle bit polling
20
OEPH
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup e
Min
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
ns
ELWL
WHEH
WLWH
CS
CH
WP
t
t
t
CE# HTime
t
ite Pulse Width
25
25
30
30
0
35
30
t
t
Write Pulse WiHigh
Latency Between Read and Write Operations
WHDL
WPH
t
W
Byte
4
t
t
Programming Operation (Note 2)
µs
µs
WHWH1
WHWH1
Word
6
Accelerated Programming Operation,
Byte or Word (Note 2)
t
t
t
t
Typ
4
WHWH1
WHWH2
WHWH1
Sector Erase Operation (Note 2)
Typ
Min
Min
Max
0.4
50
0
sec
µs
ns
W2
t
V
Setup Time (Note 1)
CC
VCS
t
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
RB
t
90
ns
BUSY
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 51 for more information.
Document Number: 002-01186 Rev. *A
Page 45 of 58
S29JL032H
Figure 17.5 Program Operation Timings
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
DOUT
A0h
Status
tBU
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 17.6 Accelerated Program Timing Diagram
VHH
VIL or VIH
WP#/ACC
VIL or VIH
tVHH
tVHH
Document Number: 002-01186 Rev. *A
Page 46 of 58
S29JL032H
Figure 17.7 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles) Read Status Data
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. SA = sector address (for Sector Erase), VA = Valid Addreor reading status a (see Write Operation Status on page 32.
2. These waveforms are for the word mode.
Figure 17.8 Back-to-back Read/Write Cycle Timings
tWC
Valid PA
tRC
tWC
Valid PA
tAH
Valid RA
Valid PA
Addresses
tCPH
tACC
tCE
CE#
OE#
tCP
tOE
tOEH
tGHWL
tWP
WE#
Data
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# or CE2# Controlled Write Cycles
Document Number: 002-01186 Rev. *A
Page 47 of 58
S29JL032H
Figure 17.9 Data# Polling Timings (During Embedded Algorithms)
Addresses
CE#
VA
tACC
tCE
VA
VA
tCH
tOE
OE
tOEH
WE#
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complem
Tru
DQ0–DQ6
Status
Tru
Valid Data
Status
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last statuead cycle, and array data read cycle.
Figure 17.10 Toggle Bit Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
DH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Document Number: 002-01186 Rev. *A
Page 48 of 58
S29JL032H
Figure 17.11 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erse
Erase Suspend
Read
DQ6
DQ2
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OEr CE# to toggle DQ2 and DQ6.
17.5 Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
Rise and Fall Time (See Note)
ID
All Speed Options
Unit
ns
t
V
Min
Mn
500
250
4
VIDR
t
V
Rise and Fall Time (See Note)
HH
ns
VHH
t
RESET# Setup Time for Temporary Sector Unprotect
µs
RSP
RESET# Hold Time from RY/BY# High for Temporary
Sector Unprotect
t
Min
4
µs
RRB
Note
Not 100% tested.
Figure 17.12 Temporary Sector Unprotect Timing Diagram
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Document Number: 002-01186 Rev. *A
Page 49 of 58
S29JL032H
Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect/Unprotect
Verify
4h
Data
60h
60h
1 µs
Sector Group Protect: 150 µs
Sector Group Unotect: 15 ms
CE#
WE#
OE#
Note
*For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0
17.6 Alternate CE# Controlled Erase and Program Operations
Parameter
JEDEC Std.
Speed Options
Description
60
70
70
0
90
Unit
ns
t
t
Write CTime (Note 1)
Address Setup Time
Address Hold Ti
Data Setup Time
Min
Min
Min
Min
Min
60
90
AVAV
WC
t
t
ns
AVWL
AS
AH
DH
t
t
35
35
40
40
0
45
45
ns
ELAX
DVEH
EHDX
t
t
t
ns
t
Data Hold Time
ns
Read Recovery Time Before Write
(OE# igh to WE# Low)
t
t
t
Min
0
ns
GHEL
GHEL
t
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
WLEL
WS
t
t
EHWH
W
t
t
CE# Pulse Width
CE# Pulse Width High
25
25
30
30
4
35
30
ELEH
CP
t
t
CPH
EHEL
Byte
Programming Operation
(Note 2)
t
t
µs
WHWH1
WHWH1
Word
6
Accelerated Programming Operation,
Byte or Word (Note 2)
t
t
t
t
Typ
Typ
4
µs
WHWH1
WHWH2
WHWH1
Sector Erase Operation (Note 2)
0.4
sec
WHWH2
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 51 for more information.
Document Number: 002-01186 Rev. *A
Page 50 of 58
S29JL032H
Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. Waveforms are for the word mode.
is e data written to the device.
OUT
18. Erase and Programming Performance
Paramer
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
Chip Erase Time
0.4
28
4
5
Excludes 00h programming
prior to erasure (Note 4)
Byte Program Time
Word Proram Time
80
100
70
6
µs
Accelerated Byte/Word Program me
yte Mode
4
µs
Excludes system level
overhead (Note 5)
12.6
12.0
10
50
Chip Program Time
(Note 3)
Word Mode
35
sec
Accelerated Mode
30
Notes
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0 V, 100,000 cycles; checkerboard data pattern.
CC
2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 31 for further information on
command definitions.
6. The device has a minimum cycling endurance of 100,000 cycles per sector.
Document Number: 002-01186 Rev. *A
Page 51 of 58
S29JL032H
19. TSOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
V
= 0
IN
TSOP
TSOP
TSOP
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
IN
9
pF
IN2
Notes
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
Document Number: 002-01186 Rev. *A
Page 52 of 58
S29JL032H
20. Physical Dimensions
20.1 TS 048—48-Pin Standard TSOP
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
0.10
5
A2
1
N
REVERSE N OUT (TOP VIEW)
3
SEE DETAIL B
A
B
1
N
E
N
2
N
2
+1
e
9
5
D1
A1
N
N
2
4
+1
2
D
0.25
2X (N/2 TIPS)
C
B
SEATING
PLANE
A
B
SEE DETAIL A
0.08MM (0.0031")
M
C
6
A - B S
b
7
WITH PLATING
c1
(c)
7
b1
BASE METAL
SECTION B-B
R
(c)
e/2
GAUGE PLANE
0.25MM (0.0098") BSC
θ°
PARALLEL TO
SEATING PLANE
X
C
L
X = A OR B
DETAIL A
DETAIL B
NOTES:
Packa
Jedec
TS/TSR 048
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (D) DD
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
c1
c
D
D1
E
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
0.16
0.21
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
e
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
0.70
8˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3355 \ 16-038.10c
Document Number: 002-01186 Rev. *A
Page 53 of 58
S29JL032H
21. Revision History
Spansion Publication Number: S29JL032H_00
21.1 Revision A0 (May 21, 2004)
Initial release.
21.2 Revision A1 (August 5, 2004)
Secured Silicon Sector Flash Memory Region
Reworded how the Secured Silicon Sector area can be protected.
Removed Secured Silicon Sector Protect Verify flowchart.
CMOS Compatible
Updated Output Low Voltage.
Erase and Programming Performance
Updated Word and Byte Mode for the Chip Program Time.
21.3 Revision A2 (March 10, 2005)
Deleted 55 ns speed option
Changed operating voltage (VCC) range for 60ns option
Changed standby current (ICC3, ICC4, ICC5
)
Deleted Secured Silicon sector protection functionality with RESET#=VIH method
21.4 Revision B0 (Sptember 21, 2005)
Changed data sheet status fAdvance to Preliminary.
21.5 Revision B1 (Noember 28, 2005)
Removed text ochanged text in the following sections.
Distinctive Characterisics
Eliminated sub-bullet under the Secured Silicon Sector information bullet.
General Descrtion
Eliminated text in e S29JL032H Features section.
Device Bus Operations
Added Note and made changes to the S29JL032H Autoselect Codes table.
Eliminated text from the Secured Silicon Sector Flash Memory Region section.
Command Definitions
Modified a note in the S29JL032H Command Definitions table.
DC Characteristics
Modified VOL Parameters.
Document Number: 002-01186 Rev. *A
Page 54 of 58
S29JL032H
21.6 Revision B2 (March 13, 2006)
Erase and Programming Performance
Changed chip program time for byte and word modes.
21.7 Revision B3 (May 19, 2006)
Changed document status from Preliminary to Full Production.
21.8 Revision B4 (June 7, 2007)
Removed the 7 inch Tape and Reel Packing Type option.
21.9 Revision B5 (August 10, 2007)
DC Characteristics
Changed VLKO minimum, typical, and maximum values.
21.10 Revision B6 (March 7, 2008)
Erase and Programming Performance
Changed the maximum sector erase time from 2 seconds to 5 seconds
Global
Corrected minor typos
21.11 Revision B7 (July 7, 2008)
Word/Byte Configuration (BTE#)
Changed tFHQV condition froMin. to Max.
21.12 Revision B8 (Auust 31, 2009)
Secured Silicon Sector Flash Memory Region
Modified Section
Section Added
Factory Locked: ecued Silicon Sector Programmed and Protected At the Factory
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected
At the Factory
In-System Sector Protect/Unprotect Algorithms
Updated table
Document Number: 002-01186 Rev. *A
Page 55 of 58
S29JL032H
Document History Page
Document Title:S29JL032H 32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V, Simultaneous Read/Write Flash
Document Number: 002-01186
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
05/21/2004 A0:Initial release
08/05/2004
A1:Secured Silicon Sector Flash Memy Region
Reworded how the Secured Silicon Sector area can be protected.
Removed Secured Silicon Sector Protect Verify flochart.
CMOS Compatible
Updated Output Low Voltag
Erase and Programming Pformance
Updated Word and Byte Mode for the Cip Program Time.
03/10/2005
A2:Deleted 55 ns seed option
Changed operating voltage (VCC) range for 60ns option
Changed stancurrent (ICCICC4, ICC5)
Deleted Secured Silicon sector protection functionality with RESET#=VIH
method
09/21/2005 B0:Canged data sheet status from Advance to Preliminary.
**
-
RYSU
11/28/2005
B1:Removed text or changed text in the following sections.
Distinctive Chracteristics
Eliminated sub-bullet under the Secured Silicon Sector information bullet.
General escription
Eliminated text in the S29JL032H Features section.
Dice Bus Operations
Added Note and made changes to the S29JL032H Autoselect Codes table.
Eliminated text from the Secured Silicon Sector Flash Memory Region
section.
Command Definitions
Modified a note in the S29JL032H Command Definitions table.
DC Characteristics
Modified VOL Parameters.
**
-
RYSU
03/13/2006
B2:Erase and Programming Performance
Changed chip program time for byte and word modes.
05/19/2006
06/07/2007
08/10/2007
B3:Changed document status from Preliminary to Full Production.
B4:Removed the 7 inch Tape and Reel Packing Type option.
B5:DC Characteristics
Changed VLKO minimum, typical, and maximum values.
03/07/2008
B6:Erase and Programming Performance
Changed the maximum sector erase time from 2 seconds to 5 seconds.
Global
Corrected minor typos
07/07/2008
B7:Word/Byte Configuration (BYTE#)
Changed tFHQV condition from Min. to Max.
Document Number: 002-01186 Rev. *A
Page 56 of 58
S29JL032H
Document History Page (Continued)
Document Title:S29JL032H 32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V, Simultaneous Read/Write Flash
Document Number: 002-01186
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
**
-
RYSU
08/31/2009
B8:Secured Silicon Sector Flash Memory Region
Modified Section
Section Added
Factory Locked: Secured Silicon Sector grammed and Protected At the
Factory
Customer Lockable: Secured SilicoSector NOT Programmed or
Protected
At the Factory
In-System Sector Prott/Unprotect gorithms
Updated table
*A
5038884
RYSU
12/08/2015
Updated to cypress template.
Document Number: 002-01186 Rev. *A
Page 57 of 58
S29JL032H
Sales, Solutions, and Legal Information
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any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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Document Number: 002-01186 Rev. *A
Revised December 08, 2015
Page 58 of 58
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