S29PL127J55BFI002_技术文档

PRELIMINARY

S29PL-J

128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory with Enhanced VersatileIO^TMControl

Data Sheet

Notice to Readers: This document indicates states the current technical

specifications regarding the Spansion product(s) described herein. The

Preliminary status of this document indicates that a product qualification has

been completed, and that initial production has begun. Due to the phases of

the manufacturing process that require maintaining efficiency and quality, this

document may be revised by subsequent versions or modifications due to

changes in technical specifications.

Publication Number S29PL-J_00 Revision A Amendment 7 Issue Date March 2, 2005

This page intentionally left blank.

S29PL-J

128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory with Enhanced VersatileIO^TMControl

PRELIMINARY

Data Sheet

Distinctive Characteristics

Bank 2B:

Architectural Advantages

PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)

128/128/64/32 Mbit Page Mode devices

— Page size of 8 words: Fast page read access from

random locations within the page

Enhanced VersatileI/O^TM(V_IO) Control

— Output voltage generated and input voltages

tolerated on all control inputs and I/Os is determined

by the voltage on the V_IOpin

Single power supply operation

— Full Voltage range: 2.7 to 3.6 volt read, erase, and

program operations for battery-powered applications

— V_IOoptions at 1.8 V and 3 V I/O for PL127J and

PL129J devices

Dual Chip Enable inputs (only in PL129J)

— Two CE# inputs control selection of each half of the

memory space

— 3V V_IOfor PL064J and PL032J devices

Secured Silicon Sector region

— Up to 128 words accessible through a command

sequence

Simultaneous Read/Write Operation

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Zero latency switching from write to read operations

— Up to 64 factory-locked words

— Up to 64 customer-lockable words

FlexBank Architecture (PL127J/PL064J/PL032J)

— 4 separate banks, with up to two simultaneous

operations per device

Both top and bottom boot blocks in one device

Manufactured on 110 nm process technology

Data Retention: 20 years typical

— Bank A:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

Cycling Endurance: 1 million cycles per sector

typical

— Bank B:

Performance Characteristics

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

High Performance

— Page access times as fast as 20 ns

— Random access times as fast as 55 ns

— Bank C:

Power consumption (typical values at 10 MHz)

— 45 mA active read current

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

— 17 mA program/erase current

— 0.2 µA typical standby mode current

— Bank D:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

Software Features

Software command-set compatible with JEDEC

42.4 standard

FlexBank Architecture (PL129J)

— 4 separate banks, with up to two simultaneous

operations per device

— Backward compatible with Am29F, Am29LV,

Am29DL, and AM29PDL families and MBM29QM/RM,

MBM29LV, MBM29DL, MBM29PDL families

— CE#1 controlled banks:

CFI (Common Flash Interface) compliant

— Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

Bank 1A:

PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)

Bank 1B:

PL129J - 48Mbit (32Kw x 96)

— CE#2 controlled banks:

Bank 2A:

Erase Suspend / Erase Resume

— Suspends an erase operation to allow read or

program operations in other sectors of same bank

PL129J - 48 Mbit (32Kw x 96)

Publication Number S29PL-J_00 Revision A Amendment 7 Issue Date March 2, 2005

This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that

product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and

quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.

P r e l i m i n a r y

Program Suspend / Program Resume

— Suspends a program operation to allow read

operation from sectors other than the one being

programmed

to prevent program or erase operations within that

sector

— Sectors can be locked and unlocked in-system at V_CC

level

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

Hardware Features

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or

erase cycle completion

Package options

— Standard discrete pinouts

11 x 8 mm, 80-ball Fine-pitch BGA (PL127J)

(VBG080)

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

8.15 x 6.15 mm, 48-ball Fine pitch BGA

(PL064J/PL032J)

(VBK048)

WP#/ ACC (Write Protect/Acceleration) input

— At V_IL, hardware level protection for the first and

last two 4K word sectors.

— At V_IH, allows removal of sector protection

— At V_HH, provides accelerated programming in a

factory setting

— MCP-compatible pinout

8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J)

7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and

PL032J)

Compatible with MCP pinout, allowing easy

integration of RAM into existing designs

— 20 x 14 mm, 56-pin TSOP (PL127J) (TS056)

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

2

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise

readers of product information or intended specifications throughout the product life cycle, in-

cluding development, qualification, initial production, and full production. In all cases, however,

readers are encouraged to verify that they have the latest information before finalizing their de-

sign. The following descriptions of Spansion data sheet designations are presented here to high-

light their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion LLC is developing one or more spe-

cific products, but has not committed any design to production. Information presented in a doc-

ument with this designation is likely to change, and in some cases, development on the product

may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-

tion content:

“This document contains information on one or more products under development at Spansion LLC. The

information is intended to help you evaluate this product. Do not design in this product without con-

tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a

commitment to production has taken place. This designation covers several aspects of the prod-

uct life cycle, including product qualification, initial production, and the subsequent phases in the

manufacturing process that occur before full production is achieved. Changes to the technical

specifications presented in a Preliminary document should be expected while keeping these as-

pects of production under consideration. Spansion places the following conditions upon Prelimi-

nary content:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. The Preliminary status of this document indicates that product qualification has been completed,

and that initial production has begun. Due to the phases of the manufacturing process that require

maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-

tions due to changes in technical specifications.”

Combination

Some data sheets will contain a combination of products with different designations (Advance In-

formation, Preliminary, or Full Production). This type of document will distinguish these products

and their designations wherever necessary, typically on the first page, the ordering information

page, and pages with DC Characteristics table and AC Erase and Program table (in the table

notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal

changes are expected, the Preliminary designation is removed from the data sheet. Nominal

changes may include those affecting the number of ordering part numbers available, such as the

addition or deletion of a speed option, temperature range, package type, or V_IOrange. Changes

may also include those needed to clarify a description or to correct a typographical error or incor-

rect specification. Spansion LLC applies the following conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-

sequent versions of this document are not expected to change. However, typographical or specification

corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu

sales office.

March 2, 2005 S29PL-J_00_A7

S29PL-J

3

P r e l i m i n a r y

General Description

The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page

Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2

Mwords. The devices are offered in the following packages:

11mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J)

8mm x 11.6mm, 64-ball Fine-pitch BGA multi-chip compatible (PL127J)

8.15mm x 6.15mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)

7mm x 9mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and

PL032J)

20mm x 14mm, 56-pin TSOP (PL127J)

The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-

grammed in-system or in standard EPROM programmers. A 12.0 V V_PPis not

required for write or erase operations.

The device offers fast page access times of 20 to 30 ns, with corresponding ran-

dom access times of 55 to 70 ns, respectively, allowing high speed

microprocessors to operate without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable (WE#) and output enable

(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).

Simultaneous Read/Write Operation with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation

by dividing the memory space into 4 banks, which can be considered to be four

separate memory arrays as far as certain operations are concerned. The device

can improve overall system performance by allowing a host system to program

or erase in one bank, then immediately and simultaneously read from another

bank with zero latency (with two simultaneous operations operating at any one

time). This releases the system from waiting for the completion of a program or

erase operation, greatly improving system performance.

The device can be organized in both top and bottom sector configurations. The

banks are organized as follows:

Bank

A

PL127J Sectors

PL064J Sectors

PL032J Sectors

16 Mbit (4 Kw x 8 and 32 Kw x 31)

48 Mbit (32 Kw x 96)

8 Mbit (4 Kw x 8 and 32 Kw x 15)

24 Mbit (32 Kw x 48)

4 Mbit (4 Kw x 8 and 32 Kw x 7)

12 Mbit (32 Kw x 24)

B

C

48 Mbit (32 Kw x 96)

24 Mbit (32 Kw x 48)

12 Mbit (32 Kw x 24)

D

16 Mbit (4 Kw x 8 and 32 Kw x 31)

8 Mbit (4 Kw x 8 and 32 Kw x 15)

4 Mbit (4 Kw x 8 and 32 Kw x 7)

Bank

1A

PL129J Sectors

CE# Control

CE1#

16 Mbit (4 Kw x 8 and 32 Kw x 31)

1B

48 Mbit (32 Kw x 96)

CE1#

2A

CE2#

2B

16 Mbit (4 Kw x 8 and 32 Kw x 31)

CE2#

4

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Page Mode Features

The page size is 8 words. After initial page access is accomplished, the page mode

operation provides fast read access speed of random locations within that page.

Standard Flash Memory Features

The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both

read and write functions. Internally generated and regulated voltages are pro-

vided for the program and erase operations.

The device is entirely command set compatible with the JEDEC 42.4 sin-

gle-power-supply Flash standard. Commands are written to the command

register using standard microprocessor write timing. Register contents serve as

inputs to an internal state-machine that controls the erase and programming cir-

cuitry. Write cycles also internally latch addresses and data needed for the

programming and erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. The

Unlock Bypass mode facilitates faster programming times by requiring only two

write cycles to program data instead of four. Device erasure occurs by executing

the erase command sequence.

The host system can detect whether a program or erase operation is complete by

reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready to read array data or ac-

cept another command.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low V_CCdetector that automat-

ically inhibits write operations during power transitions. The hardware sector

protection feature disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on

hold for any period of time to read data from, or program data to, any sector that

is not selected for erasure. True background erase can thus be achieved. If a read

is needed from the Secured Silicon Sector area (One Time Program area) after

an erase suspend, then the user must use the proper command sequence to

enter and exit this region.

The Program Suspend/Program Resume feature enables the user to hold the

program operation to read data from any sector that is not selected for program-

ming. If a read is needed from the Secured Silicon Sector area, Persistent

Protection area, Dynamic Protection area, or the CFI area, after a program sus-

pend, then the user must use the proper command sequence to enter and exit

this region.

The device offers two power-saving features. When addresses have been stable

for a specified amount of time, the device enters the automatic sleep mode.

The system can also place the device into the standby mode. Power consumption

is greatly reduced in both these modes.

The device electrically erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

March 2, 2005 S29PL-J_00_A7

S29PL-J

5

P r e l i m i n a r y

Table Of Contents

General Description . . . . . . . . . . . . . . . . . . . . . . . . 4

Simultaneous Read/Write Operation with Zero Latency ......... 4

Page Mode Features ................................................................................5

Standard Flash Memory Features .......................................................5

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 14

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Simultaneous Read/Write Block Diagram . . . . . 16

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 18

80-Ball Fine-pitch BGA ........................................................................18

Special Package Handling Instructions .............................................18

64-Ball Fine-pitch BGA—MCP Compatible ...................................19

Special Package Handling Instructions .............................................19

48-Ball Fine-pitch BGA ........................................................................20

Connection Diagram (PL064J and PL032J) . . . . . . 21

56-pin TSOP 20 x 14 mm Configuration (PL127J) ........................22

Special Package Handling Instructions ............................................22

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Selecting a Sector Protection Mode ............................................... 55

Persistent Sector Protection . . . . . . . . . . . . . . . . 56

Persistent Protection Bit (PPB) ........................................................ 56

Persistent Protection Bit Lock (PPB Lock) ................................... 56

Dynamic Protection Bit (DYB) ......................................................... 56

Persistent Sector Protection Mode Locking Bit ..........................58

Password Protection Mode . . . . . . . . . . . . . . . . . 59

Password and Password Mode Locking Bit .................................. 59

64-bit Password .....................................................................................60

Write Protect (WP#) ..........................................................................60

Persistent Protection Bit Lock .........................................................60

High Voltage Sector Protection .......................................................60

Figure 1. In-System Sector Protection/Sector

Unprotection Algorithms .................................................... 61

Temporary Sector Unprotect ..........................................................62

Figure 2. Temporary Sector Unprotect Operation................... 62

Secured Silicon Sector Flash Memory Region .............................62

Factory-Locked Area (64 words) .................................................... 63

Customer-Lockable Area (64 words) ............................................ 63

Secured Silicon Sector Protection Bits .......................................... 63

Figure 3. Secured Silicon Sector Protect Verify...................... 64

Hardware Data Protection ................................................................64

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .25

Table 1. PL127J Device Bus Operations ................................25

Table 2. PL129J Device Bus Operations ................................25

Low VCC Write Inhibit ......................................................................64

Write Pulse “Glitch” Protection ......................................................64

Logical Inhibit .........................................................................................64

Power-Up Write Inhibit .....................................................................64

Common Flash Memory Interface (CFI). . . . . . . 65

Table 17. CFI Query Identification String ............................. 65

Table 18. System Interface String ...................................... 66

Table 19. Device Geometry Definition ................................. 66

Table 20. Primary Vendor-Specific Extended Query ............... 67

Command Definitions . . . . . . . . . . . . . . . . . . . . . .69

Reading Array Data .............................................................................69

Reset Command ...................................................................................69

Autoselect Command Sequence ......................................................70

Enter Secured Silicon Sector/Exit Secured Silicon Sector Com-

mand Sequence ......................................................................................70

Word Program Command Sequence .............................................70

Unlock Bypass Command Sequence ................................................ 71

Figure 4. Program Operation .............................................. 72

Chip Erase Command Sequence ...................................................... 72

Requirements for Reading Array Data ..........................................26

Random Read (Non-Page Read) ......................................................26

Page Mode Read ....................................................................................26

Table 3. Page Select ..........................................................26

Simultaneous Read/Write Operation ............................................. 27

Table 4. Bank Select .........................................................27

Writing Commands/Command Sequences .................................. 27

Accelerated Program Operation .....................................................28

Autoselect Functions ...........................................................................28

Automatic Sleep Mode ........................................................................28

RESET#: Hardware Reset Pin ...........................................................29

Output Disable Mode ..........................................................................29

Table 5. PL127J Sector Architecture ....................................30

Table 6. PL064J Sector Architecture ....................................37

Table 7. PL032J Sector Architecture ....................................40

Table 8. S29PL129J Sector Architecture ...............................42

Table 9. Secured Silicon Sector Addresses ............................48

Autoselect Mode ..................................................................................48

Table 10. Autoselect Codes (High Voltage Method) ................49

Table 11. Autoselect Codes for PL129J .................................49

Table 12. PL127J Boot Sector/Sector Block Addresses

for Protection/Unprotection ................................................50

Table 13. PL129J Boot Sector/Sector Block Addresses

for Protection/Unprotection ................................................51

Table 14. PL064J Boot Sector/Sector Block Addresses

for Protection/Unprotection ................................................52

Table 15. PL032J Boot Sector/Sector Block Addresses

Sector Erase Command Sequence ...................................................73

Figure 5. Erase Operation .................................................. 74

Erase Suspend/Erase Resume Commands .................................... 74

Program Suspend/Program Resume Commands ........................ 75

Command Definitions Tables ........................................................... 76

Table 21. Memory Array Command Definitions ..................... 76

Table 22. Sector Protection Command Definitions ................. 78

for Protection/Unprotection ................................................53

Write Operation Status . . . . . . . . . . . . . . . . . . . . 80

Selecting a Sector Protection Mode ................................................53

Table 16. Sector Protection Schemes ...................................54

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 55

Persistent Sector Protection ............................................................. 55

Password Sector Protection ............................................................. 55

WP# Hardware Protection ............................................................... 55

DQ7: Data# Polling ..............................................................................80

Figure 6. Data# Polling Algorithm ....................................... 81

DQ6: Toggle Bit I ..................................................................................82

Figure 7. Toggle Bit Algorithm ............................................ 83

DQ2: Toggle Bit II ................................................................................83

Reading Toggle Bits DQ6/DQ2 ........................................................83

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S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Figure 17. Back-to-back Read/Write Cycle Timings ................ 96

Figure 18. Data# Polling Timings

(During Embedded Algorithms)........................................... 97

Figure 19. Toggle Bit Timings (During Embedded Algorithms) . 97

Figure 20. DQ2 vs. DQ6..................................................... 98

DQ5: Exceeded Timing Limits ..........................................................84

DQ3: Sector Erase Timer ..................................................................84

Table 23. Write Operation Status ........................................85

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .86

Figure 8. Maximum Overshoot Waveforms ........................... 86

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .87

Industrial (I) Devices ............................................................................87

Extended (E) Devices ..........................................................................87

Supply Voltages ......................................................................................87

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 24. CMOS Compatible ...............................................88

AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .89

Test Conditions .....................................................................................89

Figure 9. Test Setups ....................................................... 89

Table 25. Test Specifications ..............................................89

Protect/Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 30. Temporary Sector Unprotect ................................ 99

Figure 21. Temporary Sector Unprotect Timing Diagram......... 99

Figure 22. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................... 100

Controlled Erase Operations ...........................................................101

Table 31. Alternate CE# Controlled Erase and

Program Operations ........................................................101

Figure 23. Alternate CE# Controlled Write

(Erase/Program) Operation Timings................................... 102

Table 32. CE1#/CE2# Timing (S29PL129J only) ..................103

Figure 24. Timing Diagram for Alternating Between

Switching Waveforms ..........................................................................90

Table 26. Key To Switching Waveforms ................................90

Figure 10. Input Waveforms and Measurement Levels............ 90

CE1# and CE2# Control................................................... 103

Table 33. Erase And Programming Performance ..................103

BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 104

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 105

VBG080—80-Ball Fine-pitch Ball Grid Array 8 x 11 mm Package

(PL127J) ....................................................................................................105

VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm package

(PL127J) ...................................................................................................106

VBK048—48-Ball Fine-pitch Ball Grid Array 8.15 x 6.15 mm pack-

age (PL127J) ...........................................................................................107

VBU056—56-Ball Fine-pitch BGA 7 x 9mm package (PL064J and

PL032J) ................................................................................................... 108

TS056—20 x 14 mm, 56-pin TSOP (PL127J) ................................109

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 110

VCC RampRate .....................................................................................90

Read Operations ....................................................................................91

Table 27. Read-Only Operations ..........................................91

Figure 11. Read Operation Timings...................................... 92

Figure 12. Page Read Operation Timings.............................. 92

Reset ......................................................................................................... 93

Table 28. Hardware Reset (RESET#) ...................................93

Figure 13. Reset Timings ................................................... 93

Erase/Program Operations ................................................................94

Table 29. Erase and Program Operations ..............................94

Timing Diagrams ................................................................................... 95

Figure 14. Program Operation Timings................................. 95

Figure 15. Accelerated Program Timing Diagram ................... 95

Figure 16. Chip/Sector Erase Operation Timings.................... 96

March 2, 2005 S29PL-J_00_A7

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Ordering Information

The order number (Valid Combination) is formed by the following:

S29PL-J

55 BA 00

W

0

PACKING TYPE

0

1

2

3

=

Tray

Tube

7” Tape and Reel

13” Tape and Reel

MODEL NUMBER (ADDITIONAL ORDERING OPTIONS)

00

01

02

12

13

15

=

3.0V V_IO, 80-ball 11 x 8 mm FBGA (VBG080)

1.8V V_IO, 80-ball 11 x 8 mm FBGA (VBG080)

3.0V V_IO, 64-ball 8 x 11.6 mm FBGA (VBH064)

3.0V V_IO, 48-ball 8 x 6 mm FBGA (VBK048)

3.0V V_IO, 56-ball 20 x 14 mm TSOP (TS056)

3.0V V_IO, 56-ball 7 x 9 mm FBGA (VBU056)

TEMPERATURE RANGE

W

I

=

Wireless (–25

Industrial (–40

°

C to +85

°

C)

°

C to +85

°

PACKAGE TYPE

BA

BF

TA

TF

=

Fine-Pitch Grid Array (FBGA)

Lead (Pb)- free compliant

Fine-Pitch Grid Array (FBGA)

Lead (Pb)- free

Thin Small Outline Package (TSOP) Standard Pinout

Lead (Pb)- free compliant

Thin Small Outline Package (TSOP) Standard Pinout

Lead (Pb)- free

CLOCK SPEED

55

60

65

70

=

55 ns (Contact factory for availability)

60 ns

65 ns

70 ns

DEVICE NUMBER/DESCRIPTION

128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit), 32 Megabit (2 M x 16-Bit) CMOS Flash

Memory,

Simultaneous Read/Write, Page Mode Flash Memory, 3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combination configuration planned to be supported for this device.

8

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

128 Mb Products Based on 110 nm Floating Gate Technology

Valid FBGA Package

Combinations

CE#

Configuration

Package Marking

Temperature

Speed

V_IO

Package Type

S29PL127J55BAI00

S29PL127J55BFI00

S29PL127J55BAW00

S29PL127J55BFW00

S29PL127J60BAI00

S29PL127J60BFI00

S29PL127J60BAW00

S29PL127J60BFW00

S29PL127J65BAI00

S29PL127J65BFI00

S29PL127J65BAW00

S29PL127J65BFW00

S29PL127J70BAI00

S29PL127J70BFI00

S29PL127J70BAW00

S29PL127J70BFW00

S29PL127J65BAI01

S29PL127J65BFI01

S29PL127J65BAW01

S29PL127J65BFW01

S29PL127J70BAI01

S29PL127J70BFI01

S29PL127J70BAW01

S29PL127J70BFW01

PL127J55BAI00

PL127J55BFI00

PL127J55BAW00

PL127J55BFW00

PL127J60BAI00

PL127J60BFI00

PL127J60BAW00

PL127J60BFW00

PL127J65BAI00

PL127J65BFI00

PL127J65BAW00

PL127J65BFW00

PL127J70BAI00

PL127J70BFI00

PL127J70BAW00

PL127J70BFW00

PL127J60BAI01

PL127J60BFI01

PL127J60BAW01

PL127J60BFW01

PL127J70BAI01

PL127J70BFI01

PL127J70BAW01

PL127J70BFW01

(-40 - +85 º C)

55 ns

(Note)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

60 ns

65 ns

70 ns

65 ns

70 ns

3.0 V

Single CE#

11 x 8 mm

80 ball FBGA

Standalone Package

VBG080

1.8 V

Single CE#

March 2, 2005 S29PL-J_00_A7

S29PL-J

9

P r e l i m i n a r y

128 Mb Products Based on 110 nm Floating Gate Technology

Valid FBGA Package

Combinations

CE#

Configuration

Package Marking

Temperature

Speed

V_IO

Package Type

S29PL127J55BAI02

S29PL127J55BFI02

S29PL127J55BAW02

S29PL127J55BFW02

S29PL127J60BAI02

S29PL127J60BFI02

S29PL127J60BAW02

S29PL127J60BFW02

S29PL127J65BAI02

S29PL127J65BFI02

S29PL127J65BAW02

S29PL127J65BFW02

S29PL127J70BAI02

S29PL127J70BFI02

S29PL127J70BAW02

S29PL127J70BFW02

S29PL127J55TAI13

S29PL127J55TFI13

S29PL127J55TAW13

S29PL127J55TFW13

S29PL127J60TAI13

S29PL127J60TFI13

S29PL127J60TAW13

S29PL127J60TFW13

S29PL127J70TAI13

S29PL127J70TFI13

S29PL127J70TAW13

S29PL127J70TFW13

PL127J55BAI02

PL127J55BFI02

PL127J55BAW02

PL127J55BFW02

PL127J60BAI02

PL127J60BFI02

PL127J60BAW02

PL127J60BFW02

PL127J65BAI02

PL127J65BFI02

PL127J65BAW02

PL127J65BFW02

PL127J70BAI02

PL127J70BFI02

PL127J70BAW02

PL127J70BFW02

PL127J55TAI13

PL127J55TFI13

PL127J55TAW13

PL127J55TFW13

PL127J60TAI13

PL127J60TFI13

PL127J60TAW13

PL127J60TFW13

PL127J70TAI13

PL127J70TFI13

PL127J70TAW13

PL127J70TFW13

(-40 - +85 º C)

55 ns

(Note)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

60 ns

65 ns

70 ns

8 x 11.6 mm

64 ball FBGA

MCP-Compatible

VBH064

3.0 V

Single CE#

55

(Note)

60

70

20 x 14 mm

56-pin TSOP

TS056

3.0 V

Single CE#

(-25 - +85 º C)

(-40 - +85 º C)

55

(Note)

S29PL127J55TFI13

PL127J55TFI13

S29PL127J55TFW13

S29PL127J60TFI13

S29PL127J60TFW13

S29PL127J70TFI13

S29PL127J70TFW13

PL127J55TFW13

S29PL127J60TFI13

PL127J60TFW13

PL127J70TFI13

PL127J70TFW13

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

60

70

20 x 14 mm

56-pin TSOP

TS056

3.0 V

Single CE#

10

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

64 Mb Products Based on 110 nm Floating Gate Technology

Valid Combinations

BGA Packages

Package Marking

PL064J55BAI12

PL064J55BFI12

PL064J55BAW12

PL064J55BFW12

PL064J60BAI12

PL064J60BFI12

PL064J60BAW12

PL064J60BFW12

PL064J70BAI12

PL064J70BAFI12

PL064J70BAW12

PL064J70BFW12

PL064J55BAI15

PL064J55BFI15

PL064J55BAW15

PL064J55BFW15

PL064J60BAI15

PL064J60BFI15

PL064J60BAW15

PL064J60BFW15

PL064J70BAI15

PL064J70BFI15

PL064J70BAW15

PL064J70BFW15

Temperature

Speed

VIO

Package Type

S29PL064J55BAI12

S29PL064J55BFI12

S29PL064J55BAW12

S29PL064J55BFW12

S29PL064J60BAI12

S29PL064J60BFI12

S29PL064J60BAW12

S29PL064J60BFW12

S29PL064J70BAI12

S29PL064J70BFI12

S29PL064J70BAW12

S29PL064J70BFW12

S29PL064J55BAI15

S29PL064J55BFI15

S29PL064J55BAW15

S29PL064J55BFW15

S29PL064J60BAI15

S29PL064J60BFI15

S29PL064J60BAW15

S29PL064J60BFW15

S29PL064J70BAI15

S29PL064J70BFI15

S29PL064J70BAW15

S29PL064J70BFW15

(-40 - +85 º C)

55 ns

(Note)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

8 x 6 mm

48-ball

Standalone Package

60 ns

70 ns

3.0 V

VBK048

55 ns

(Note)

7 x 9 mm

56-ball

MCP-Compatible

60 ns

70 ns

3.0 V

VBU056

March 2, 2005 S29PL-J_00_A7

S29PL-J

11

P r e l i m i n a r y

32 Mb Products Based on 110 nm Floating Gate Technology

Valid Combinations

GA Packages

Package Marking

PL032J55BAI12

PL032J55BFI12

PL032J55BAW12

PL032J55BFW12

PL032J60BAI12

PL032J60BFI12

PL032J60BAW12

PL032J60BFW12

PL032J70BAI12

PL032J70BFI12

PL032J70BAW12

PL032J70BFW12

PL032J55BAI15

PL032J55BFI15

PL032J55BAW15

PL032J55BFW15

PL032J60BAI15

PL032J60BFI15

PL032J60BAW15

PL032J60BFW15

PL032J70BAI15

PL032J70BFI15

PL032J70BAW15

PL032J70BFW15

Temperature

Speed

VIO

Package Type

S29PL032J55BAI12

S29PL032J55BFI12

S29PL032J55BAW12

S29PL032J55BFW12

S29PL032J60BAI12

S29PL032J60BFI12

S29PL032J60BAW12

S29PL032J60BFW12

S29PL032J70BAI12

S29PL032J70BFI12

S29PL032J70BAW12

S29PL032J70BFW12

S29PL032J55BAI15

S29PL032J55BFI15

S29PL032J55BAW15

S29PL032J55BFW15

S29PL032J60BAI15

S29PL032J60BFI15

S29PL032J60BAW15

S29PL032J60BFW15

S29PL032J70BAI15

S29PL032J70BFI15

S29PL032J70BAW15

S29PL032J70BFW15

(-40 - +85 º C)

55 ns

(Note)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

(-40 - +85 º C)

(-25 - +85 º C)

8 x 6 mm

48-ball

Standalone Package

VBK048

60 ns

70 ns

3.0 V

55 ns

(Note)

7 x 9 mm

56-ball

MCP-Compatible

VBU056

60 ns

70 ns

3.0 V

12

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Valid Combinations for BGA Packages

Speed

Order Number (note 1)

V_IORange

PL129J, PL127J

PL064J, PL032J

55 (note 2)

PL129J, PL127J

PL064J, PL032J

60

65

70

2.7–3.6

PL129J, PL127J

PL064J, PL032J

PL129J, PL127J

PL064J, PL032J

PL129J, PL127J

65

70

1.65–1.95

Notes:

1. Please contact the factory for PL129J availability.

2. Please contact the factory for availability.

Valid Combinations for TSOP Packages

Order Number

Speed

55

V_IORange

PL127J

60

2.7–3.6

70

March 2, 2005 S29PL-J_00_A7

S29PL-J

13

P r e l i m i n a r y

Product Selector Guide

Part Number

S29PL032J/S29PL064J/S29PL-J/S29PL129J

V_CC,V_IO= 2.7–3.6 V

55 (Note)

60

65

70

V_CC= 2.7–3.6 V,

Speed Option

V_IO= 1.65–1.95 V (PL127J and

PL129J only)

65

70

Max Access Time, ns (t_ACC

Max CE# Access, ns (t_CE)

)

55 (Note)

20 (Note)

60

25

65

25

70

30

70

30

Max Page Access, ns (t_PACC

Max OE# Access, ns (t_OE)

)

Note: Contact factory for availability

14

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Block Diagram

DQ15–DQ0

RY/BY# (See Note)

V

CC

V

Sector

SS

Switches

V

IO

Input/Output

Buffers

RESET#

WE#

Erase Voltage

Generator

State

Control

Command

Register

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

CE#

OE#

Data Latch

Y-Gating

Y-Decoder

X-Decoder

V

Detector

Timer

CC

Amax–A3

Cell Matrix

A2–A0

Notes:

1. RY/BY# is an open drain output.

2. Amax = A22 (PL127J), A21 (PL129J and PL064J), A20 (PL032J)

3. For PL129J there are two CE# (CE1# and CE2#)

March 2, 2005 S29PL-J_00_A7

S29PL-J

15

P r e l i m i n a r y

Simultaneous Read/Write Block Diagram

V

CC

OE#

SS

Mux

Bank A

Bank A Address

Amax–A0

X-Decoder

Bank B Address

RY/BY#

Bank B

X-Decoder

Amax–A0

RESET#

STATE

CONTROL

&

COMMAND

REGISTER

Status

WE#

DQ15–DQ0

CE#

WP#/ACC

Control

Mux

X-Decoder

Bank C

DQ0–DQ15

Bank C Address

Bank D Address

X-Decoder

Bank D

Amax–A0

Mux

Note: Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J)

16

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Simultaneous Read/Write Block Diagram (PL129J)

V

CC

SS

OE#

CE1#=L

CE2#=H

Mux

Bank 1A

Bank 1A Address

Bank 1B Address

A21–A0

X-Decoder

RY/BY#

Bank 1B

X-Decoder

A21–A0

RESET#

STATE

CONTROL

&

Status

WE#

CE1#

DQ15–DQ0

CE2#

COMMAND

REGISTER

Control

Mux

WP#/ACC

CE1#=H

CE2#=L

X-Decoder

Bank 2A

DQ0–DQ15

Bank 2A Address

Bank 2B Address

X-Decoder

Bank 2B

A21–A0

Mux

Notes:

1. Amax = A21 (PL129J)

March 2, 2005 S29PL-J_00_A7

S29PL-J

17

P r e l i m i n a r y

Connection Diagrams

80-Ball Fine-pitch BGA

(PL127J)

Top View, Balls Facing Down

A8

NC

B8

NC

C8

NC

D8

E8

F8

G8

H8

NC

J8

K8

NC

L8

M8

NC

A22

NC

V

NC

IO

SS

A7

NC

B7

NC

C7

D7

E7

F7

G7

H7

NC

J7

K7

L7

M7

NC

A13

A12

A14

A15

A16

DQ15

V

NC

SS

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

WE#

RESET#

A21

A19

DQ5

DQ12

V

DQ4

CC

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

NC

B2

NC

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

NC

CE#

OE#

V

NC

SS

A1

NC

B1

NC

C1

NC

D1

NC

E1

F1

G1

NC

H1

J1

K1

NC

L1

M1

NC

V

NC

IO

Note: Pinout shown for PL127J.

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages

(TSOP, BGA, PDIP, SSOP, PLCC).

The package and/or data integrity may be compromised if the package body is

exposed to temperatures above 150°C for prolonged periods of time.

18

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

64-Ball Fine-pitch BGA—MCP Compatible

(PL127J)

Top View, Balls Facing Down

A1

NC

A10

NC

B5

B6

RFU

C3

A7

C4

C5

C6

C7

A8

C8

A11

RFU

WP#/ACC WE#

D2

A3

D3

A6

D4

D5

D6

D7

D8

D9

A12

A15

RFU

RESET# RFU

A19

E2

A2

E3

A5

E4

E5

E6

E7

A9

E8

E9

RY/BY # A20

A13

A21

A18

F2

A1

F3

A4

F4

F7

F8

F9

A17

A10

A14

CE2#

G2

A0

G3

G4

G7

G8

G9

VSS

DQ1

DQ6

RFU

A16

H2

H3

H4

H5

H6

H7

H8

H9

CE#f1

OE#

DQ9

DQ3

DQ4

DQ13

DQ15

RFU

J2

J3

J4

DQ10

K4

J5

VCCf

K5

J6

J7

DQ12

K7

J8

J9

RFU

DQ0

K3

RFU

K6

DQ7

K8

VSS

DQ8

DQ2

DQ11

RFU

DQ5

DQ14

L5

L6

VCCf

RFU

M1

NC

M10

NC

Note: Pinout shown for PL127J.

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages

(TSOP, BGA, PDIP, SSOP, PLCC).

The package and/or data integrity may be compromised if the package body is

exposed to temperatures above 150°C for prolonged periods of time.

March 2, 2005 S29PL-J_00_A7

S29PL-J

19

P r e l i m i n a r y

48-Ball Fine-pitch BGA

48-Ball Fine-pitch BGA (PL064J/PL032J)

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

V

A13

A12

A14

A15

A16

NC

DQ15

SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE#

RESET#

A21

A19

DQ5

DQ12

V

DQ4

CC

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY# WP#/ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V

SS

Note: Pinout shows for PL064J. For PL032J, C4(A21) = NC

20

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Connection Diagram (PL064J and PL032J)

56-ball Fine-Pitch Ball Grid Array

(Top View, Balls Facing Down)

A2

A7

A3

LB#

B3

A4

WP#/ACC

B4

A5

WE#

B5

A6

A8

A7

A11

B7

B1

A3

B2

B6

B8

A15

C8

A6

UB#

C3

RST#

C4

CE2s

C5

A19

C6

A12

C7

C1

C2

A2

A5

A18

D3

RY/BY#

A20

A9

A13

D7

A21

D8

D1

D2

D6

A1

A4

A17

E3

A10

E6

A14

E7

RFU

E8

E1

E2

A0

VSS

F2

DQ1

F3

DQ6

F6

RFU

F7

A16

F8

F1

F4

DQ3

G4

F5

DQ4

G5

CE1#f

G1

OE#

G2

DQ0

H2

DQ9

G3

DQ13

G6

DQ15

G7

RFU

G8

CE1#s

DQ10

H3

VCCf

H4

VCCs

H5

DQ12

H6

DQ7

H7

VSS

DQ8

DQ2

DQ11

RFU

DQ5

DQ14

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultra-

sonic cleaning methods. The package and/or data integrity may be compromised

if the package body is exposed to temperatures above 150°C for prolonged peri-

ods of time.

March 2, 2005 S29PL-J_00_A7

S29PL-J

21

P r e l i m i n a r y

56-pin TSOP 20 x 14 mm Configuration (PL127J)

RESET#

RY/BY#

A0

1

2

WP#/ACC

WE#

NC

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

3

A1

4

A22

A2

5

A21

A3

6

A20

A4

7

OE#

NC

A5

8

V_CC

9

CE#

V_SS

DQ0

DQ1

DQ2

DQ3

V_SSQ

V_CCQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DQ15

DQ14

DQ13

DQ12

V_SSQ

V_CCQ

DQ11

DQ10

DQ9

DQ8

V_CC

56-pin TSOP

DQ4

DQ5

DQ6

DQ7

V_SS

NC

A6

A19

A7

A18

A8

A17

A9

A16

A10

A11

A12

A15

A14

A13

For this family of products, a single multi-chip compatible package is offered for

each density to allow both standalone and multi-chip qualification using a single,

adaptable package. This new methodology allows package standardization

resulting in faster development. The multi-chip compatible package includes all

the pins required for standalone device operation and verification. In addition,

extra pins are included for insertion of common data storage or logic devices to

be used for multi-chip products. If a standalone device is required, the extra

multi-chip specific pins are not connected and the standalone device operates

normally. The multi-chip compatible package sizes were chosen to serve the

largest number of combinations possible. There are only a few cases where a

larger package size would be required to accommodate the multi-chip

combination. This multi-chip compatible package set does not allow for direct

package migration from the Am29BDS128H, Am29BDS128G, Am29BDS640G

products, which use legacy standalone packages.

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages

(TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be

compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

22

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Pin Description

Amax–A0

DQ15–DQ0

CE#

OE#

WE#

V_SS

NC

RY/BY#

=

Address bus

16-bit data inputs/outputs/float

Chip Enable Inputs

Output Enable Input

Write Enable

Device Ground

Pin Not Connected Internally

Ready/Busy output and open drain.

When RY/BY#= V_IH, the device is ready to accept

read operations and commands. When RY/BY#=

V_OL, the device is either executing an embedded

algorithm or the device is executing a hardware

reset operation.

WP#/ACC

=

Write Protect/Acceleration Input.

When WP#/ACC= V_IL, the highest and lowest two

4K-word sectors are write protected regardless of

other sector protection configurations. When

WP#/ACC= V_IH, these sector are unprotected unless

the DYB or PPB is programmed. When WP#/ACC=

12V, program and erase operations are accelerated.

V_IO

=

Input/Output Buffer Power Supply

(1.65 V to 1.95 V (for PL127J and PL129J) or 2.7 V

to 3.6 V (for all PLxxxJ devices))

Chip Power Supply

V_CC

(2.7 V to 3.6 V or 2.7 to 3.3 V)

RESET#

CE1#, CE2#

=

Hardware Reset Pin

Chip Enable Inputs.

CE1# controls the 64Mb in Banks 1A and 1B. CE2#

controls the 64 Mb in Banks 2A and 2B. (Only for

PL129J)

Notes:

1. Amax = A22 (PL127J), A21 (PL129J and PL064J), A20 (PL032J)

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P r e l i m i n a r y

Logic Symbol

max+1

Amax–A0

16

DQ15–DQ0

CE#

OE#

WE#

WP#/ACC

RESET#

RY/BY#

V_IO(V_CCQ

)

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S29PL-J_00_A7 March 2, 2005

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Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is a latch

used to store the commands, along with the address and data information

needed to execute the command. The contents of the register serve as inputs to

the internal state machine. The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the inputs and control levels they

require, and the resulting output. The following subsections describe each of

these operations in further detail.

Table 1. PL127J Device Bus Operations

Addresses

(Amax–A0)

DQ15–

DQ0

Operation

CE#

L

OE#

L

WE#

RESET#

WP#/ACC

X

Read

Write

H

L

H

A_IN

D_OUT

D_IN

L

H

X (Note 2)

V_IO

0.3 V

±

V_IO±

0.3 V

Standby

X

X (Note 2)

X

High-Z

Output Disable

Reset

L

X

H

X

H

X

H

X

High-Z

D_IN

L

Temporary Sector Unprotect (High Voltage)

V_ID

A_IN

Table 2. PL129J Device Bus Operations

Addresses

(A21–A0)

DQ15–

DQ0

Operation

CE1#

CE2#

OE#

WE#

RESET#

WP#/ACC

L

H

L

H

L

Read

L

H

X

A_IN

D_OUT

H

L

X

Write

H

X

L

H

A_IN

X

D_IN

(Note 2)

H

V_IO

0.3 V

±

V_IO

0.3 V

±

V_IO±

0.3 V

Standby

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Temporary Sector Unprotect

(High Voltage)

X

V_ID

X

A_IN

D_IN

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 8.5–9.5 V, X = Don’t Care, SA = Sector

Address, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the

"High Voltage Sector Protection" section section.

2. WP#/ACC must be high when writing to upper two and lower two sectors.

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Requirements for Reading Array Data

To read array data from the outputs, the system must drive the OE# and appro-

priate CE# pins (For PL129J - CE1#/CE2# pins) to V_IL. In PL129J, CE1# and

CE2# are the power control and select the lower (CE1#) or upper (CE2#) halves

of the device. CE# is the power control. OE# is the output control and gates array

data to the output pins. WE# should remain at V_IH.

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. Each bank remains enabled for read access until the command register

contents are altered.

Refer to Table 32 for timing specifications and to Figure 11 for the timing diagram.

I_CC1in the DC Characteristics table represents the active current specification for

reading array data.

Random Read (Non-Page Read)

Address access time (t_ACC) is equal to the delay from stable addresses to valid

output data. The chip enable access time (t_CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output inputs. The output enable

access time is the delay from the falling edge of the OE# to valid data at the out-

put inputs (assuming the addresses have been stable for at least t_ACC–t_OEtime).

Page Mode Read

The device is capable of fast page mode read and is compatible with the page

mode Mask ROM read operation. This mode provides faster read access speed for

random locations within a page. Address bits Amax–A3 select an 8 word page,

and address bits A2–A0 select a specific word within that page. This is an asyn-

chronous operation with the microprocessor supplying the specific word location.

The random or initial page access is t_ACCor t_CEand subsequent page read ac-

cesses (as long as the locations specified by the microprocessor falls within that

page) is equivalent to t_PACC. When CE# (CE1# and CE#2 in PL129J) is deasserted

(=V_IH), the reassertion of CE# (CE1# or CE#2 in PL129J) for subsequent access

has access time of t_ACCor t_CE. Here again, CE# (CE1# /CE#2 in PL129J)selects

the device and OE# is the output control and should be used to gate data to the

output inputs if the device is selected. Fast page mode accesses are obtained by

keeping Amax–A3 constant and changing A2–A0 to select the specific word within

that page.

Table 3. Page Select

Word

A2

0

A1

0

A0

0

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

0

1

0

1

0

1

0

1

0

1

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Table 3. Page Select (Continued)

Word 6

Word 7

1

0

1

Simultaneous Read/Write Operation

In addition to the conventional features (read, program, erase-suspend read,

erase-suspend program, and program-suspend read), the device is capable of

reading data from one bank of memory while a program or erase operation is in

progress in another bank of memory (simultaneous operation). The bank can be

selected by bank addresses (PL127J: A22–A20, PL129J and PL064J: A21–A19,

PL032J: A20–A18) with zero latency.

The simultaneous operation can execute multi-function mode in the same bank.

Table 4. Bank Select

PL127J: A22–A20

PL064J: A21–A19

PL032J: A20–A18

Bank

Bank A

Bank B

Bank C

Bank D

000

001, 010, 011

100, 101, 110

111

Bank

CE1#

CE2#

PL129J: A21–A20

00

Bank 1A

Bank 1B

Bank 2A

Bank 2B

0

1

0

01, 10, 11

00, 01, 10

11

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# (CE1# or CE#2 in PL129J) to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facilitate faster programming.

Once a bank enters the Unlock Bypass mode, only two write cycles are required

to program a word, instead of four. The “Word Program Command Sequence”

section has details on programming data to the device using both standard and

Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 4 indicates the set of address space that each sector occupies. A “bank ad-

dress” is the set of address bits required to uniquely select a bank. Similarly, a

“sector address” refers to the address bits required to uniquely select a sector.

The “Command Definitions” section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

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P r e l i m i n a r y

I_CC2in the DC Characteristics table represents the active current specification for

the write mode. See the timing specification tables and timing diagrams in the

"Reset" section for write operations.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This

function is primarily intended to allow faster manufacturing throughput at the

factory.

If the system asserts V_HHon this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the time required for program

operations. The system would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing V_HHfrom the WP#/ACC pin re-

turns the device to normal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin should be raised to V_CCwhen not in

use. That is, the WP#/ACC pin should not be left floating or unconnected; incon-

sistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

register (which is separate from the memory array) on DQ15–DQ0. Standard

read cycle timings apply in this mode. Refer to the "Secured Silicon Sector Ad-

dresses" section and "Autoselect Command Sequence" section for more

information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# (CE1#,CE#2 in

PL129J) and RESET# pins are both held at V_IO± 0.3 V. (Note that this is a more

restricted voltage range than V_IH.) If CE# (CE1#,CE#2 in PL129J) and RESET#

are held at V_IH, but not within V_IO± 0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device requires standard access time

(t_CE) for read access when the device is in either of these standby modes, before

it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

I_CC3in “DC Characteristics” represents the CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. Note that during automatic sleep mode, OE# must be at V_IHbefore

28

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P r e l i m i n a r y

the device reduces current to the stated sleep mode specification. I_CC5in “DC

Characteristics” represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at V_SS±0.3 V, the device draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a “0” (busy) until the internal reset operation is complete, which requires

a time of t_READY(during Embedded Algorithms). The system can thus monitor

RY/BY# to determine whether the reset operation is complete. If RESET# is as-

serted when a program or erase operation is not executing (RY/BY# pin is “1”),

the reset operation is completed within a time of t_READY(not during Embedded Al-

gorithms). The system can read data t_RHafter the RESET# pin returns to V_IH.

Refer to the "AC Characteristic" section tables for RESET# parameters and to 13

for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The output pins

(except for RY/BY#) are placed in the highest Impedance state

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Table 5. PL127J Sector Architecture

Bank

Sector

SA0

Sector Address (A22-A12)

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

00000100XXX

00000101XXX

00000110XXX

00000111XXX

00001000XXX

00001001XXX

00001010XXX

00001011XXX

00001100XXX

00001101XXX

00001110XXX

00001111XXX

00010000XXX

00010001XXX

00010010XXX

00010011XXX

00010100XXX

00010101XXX

00010110XXX

00010111XXX

00011000XXX

00011001XXX

00011010XXX

00011011XXX

00011100XXX

00011101XXX

00011110XXX

00011111XXX

Sector Size (Kwords)

Address Range (x16)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

4

SA1

4

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

30

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Table 5. PL127J Sector Architecture (Continued)

Bank

Sector

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

Sector Address (A22-A12)

00100000XXX

00100001XXX

00100010XXX

00100011XXX

00100100XXX

00100101XXX

00100110XXX

00100111XXX

00101000XXX

00101001XXX

00101010XXX

00101011XXX

00101100XXX

00101101XXX

00101110XXX

00101111XXX

00110000XXX

00110001XXX

00110010XXX

00110011XXX

00110100XXX

00110101XXX

00110110XXX

00110111XXX

00111000XXX

00111001XXX

00111010XXX

00111011XXX

00111100XXX

00111101XXX

00111110XXX

00111111XXX

01000000XXX

01000001XXX

01000010XXX

01000011XXX

01000100XXX

01000101XXX

01000110XXX

01000111XXX

Sector Size (Kwords)

Address Range (x16)

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

32

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Table 5. PL127J Sector Architecture (Continued)

Bank

Sector

SA79

Sector Address (A22-A12)

01001000XXX

01001001XXX

01001010XXX

01001011XXX

01001100XXX

01001101XXX

01001110XXX

01001111XXX

01010000XXX

01010001XXX

01010010XXX

01010011XXX

01010100XXX

01010101XXX

01010110XXX

01010111XXX

01011000XXX

01011001XXX

01011010XXX

01011011XXX

01011100XXX

01011101XXX

01011110XXX

01011111XXX

01100000XXX

01100001XXX

01100010XXX

01100011XXX

01100100XXX

01100101XXX

01100110XXX

01100111XXX

01101000XXX

01101001XXX

01101010XXX

01101011XXX

01101100XXX

01101101XXX

01101110XXX

01101111XXX

Sector Size (Kwords)

Address Range (x16)

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

32

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

32

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Table 5. PL127J Sector Architecture (Continued)

Bank

Sector

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

Sector Address (A22-A12)

01110000XXX

01110001XXX

01110010XXX

01110011XXX

01110100XXX

01110101XXX

01110110XXX

01110111XXX

01111000XXX

01111001XXX

01111010XXX

01111011XXX

01111100XXX

01111101XXX

01111110XXX

01111111XXX

10000000XXX

10000001XXX

10000010XXX

10000011XXX

10000100XXX

10000101XXX

10000110XXX

10000111XXX

10001000XXX

10001001XXX

10001010XXX

10001011XXX

10001100XXX

10001101XXX

10001110XXX

10001111XXX

10010000XXX

10010001XXX

10010010XXX

10010011XXX

10010100XXX

10010101XXX

10010110XXX

10010111XXX

Sector Size (Kwords)

Address Range (x16)

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

400000h–407FFFh

408000h–40FFFFh

410000h–417FFFh

418000h–41FFFFh

420000h–427FFFh

428000h–42FFFFh

430000h–437FFFh

438000h–43FFFFh

440000h–447FFFh

448000h–44FFFFh

450000h–457FFFh

458000h–45FFFFh

460000h–467FFFh

468000h–46FFFFh

470000h–477FFFh

478000h–47FFFFh

480000h–487FFFh

488000h–48FFFFh

490000h–497FFFh

498000h–49FFFFh

4A0000h–4A7FFFh

4A8000h–4AFFFFh

4B0000h–4B7FFFh

4B8000h–4BFFFFh

32

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P r e l i m i n a r y

Table 5. PL127J Sector Architecture (Continued)

Bank

Sector

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

Sector Address (A22-A12)

10011000XXX

10011001XXX

10011010XXX

10011011XXX

10011100XXX

10011101XXX

10011110XXX

10011111XXX

10100000XXX

10100001XXX

10100010XXX

10100011XXX

10100100XXX

10100101XXX

10100110XXX

10100111XXX

10101000XXX

10101001XXX

10101010XXX

10101011XXX

10101100XXX

10101101XXX

10101110XXX

10101111XXX

10110000XXX

10110001XXX

10110010XXX

10110011XXX

10110100XXX

10110101XXX

10110110XXX

10110111XXX

10111000XXX

10111001XXX

10111010XXX

10111011XXX

10111100XXX

10111101XXX

10111110XXX

10111111XXX

Sector Size (Kwords)

Address Range (x16)

4C0000h–4C7FFFh

4C8000h–4CFFFFh

4D0000h–4D7FFFh

4D8000h–4DFFFFh

4E0000h–4E7FFFh

4E8000h–4EFFFFh

4F0000h–4F7FFFh

4F8000h–4FFFFFh

500000h–507FFFh

508000h–50FFFFh

510000h–517FFFh

518000h–51FFFFh

520000h–527FFFh

528000h–52FFFFh

530000h–537FFFh

538000h–53FFFFh

540000h–547FFFh

548000h–54FFFFh

550000h–557FFFh

558000h–15FFFFh

560000h–567FFFh

568000h–56FFFFh

570000h–577FFFh

578000h–57FFFFh

580000h–587FFFh

588000h–58FFFFh

590000h–597FFFh

598000h–59FFFFh

5A0000h–5A7FFFh

5A8000h–5AFFFFh

5B0000h–5B7FFFh

5B8000h–5BFFFFh

5C0000h–5C7FFFh

5C8000h–5CFFFFh

5D0000h–5D7FFFh

5D8000h–5DFFFFh

5E0000h–5E7FFFh

5E8000h–5EFFFFh

5F0000h–5F7FFFh

5F8000h–5FFFFFh

32

34

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Table 5. PL127J Sector Architecture (Continued)

Bank

Sector

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

Sector Address (A22-A12)

11000000XXX

11000001XXX

11000010XXX

11000011XXX

11000100XXX

11000101XXX

11000110XXX

11000111XXX

11001000XXX

11001001XXX

11001010XXX

11001011XXX

11001100XXX

11001101XXX

11001110XXX

11001111XXX

11010000XXX

11010001XXX

11010010XXX

11010011XXX

11010100XXX

11010101XXX

11010110XXX

11010111XXX

11011000XXX

11011001XXX

11011010XXX

11011011XXX

11011100XXX

11011101XXX

11011110XXX

11011111XXX

Sector Size (Kwords)

Address Range (x16)

600000h–607FFFh

608000h–60FFFFh

610000h–617FFFh

618000h–61FFFFh

620000h–627FFFh

628000h–62FFFFh

630000h–637FFFh

638000h–63FFFFh

640000h–647FFFh

648000h–64FFFFh

650000h–657FFFh

658000h–65FFFFh

660000h–667FFFh

668000h–66FFFFh

670000h–677FFFh

678000h–67FFFFh

680000h–687FFFh

688000h–68FFFFh

690000h–697FFFh

698000h–69FFFFh

6A0000h–6A7FFFh

6A8000h–6AFFFFh

6B0000h–6B7FFFh

6B8000h–6BFFFFh

6C0000h–6C7FFFh

6C8000h–6CFFFFh

6D0000h–6D7FFFh

6D8000h–6DFFFFh

6E0000h–6E7FFFh

6E8000h–6EFFFFh

6F0000h–6F7FFFh

6F8000h–6FFFFFh

32

March 2, 2005 S29PL-J_00_A7

S29PL-J

35

P r e l i m i n a r y

Table 5. PL127J Sector Architecture (Continued)

Bank

Sector

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

Sector Address (A22-A12)

11100000XXX

11100001XXX

11100010XXX

11100011XXX

11100100XXX

11100101XXX

11100110XXX

11100111XXX

11101000XXX

11101001XXX

11101010XXX

11101011XXX

11101100XXX

11101101XXX

11101110XXX

11101111XXX

11110000XXX

11110001XXX

11110010XXX

11110011XXX

11110100XXX

11110101XXX

11110110XXX

11110111XXX

11111000XXX

11111001XXX

11111010XXX

11111011XXX

11111100XXX

11111101XXX

11111110XXX

11111111000

11111111001

11111111010

11111111011

11111111100

11111111101

11111111110

11111111111

Sector Size (Kwords)

Address Range (x16)

700000h–707FFFh

708000h–70FFFFh

710000h–717FFFh

718000h–71FFFFh

720000h–727FFFh

728000h–72FFFFh

730000h–737FFFh

738000h–73FFFFh

740000h–747FFFh

748000h–74FFFFh

750000h–757FFFh

758000h–75FFFFh

760000h–767FFFh

768000h–76FFFFh

770000h–777FFFh

778000h–77FFFFh

780000h–787FFFh

788000h–78FFFFh

790000h–797FFFh

798000h–79FFFFh

7A0000h–7A7FFFh

7A8000h–7AFFFFh

7B0000h–7B7FFFh

7B8000h–7BFFFFh

7C0000h–7C7FFFh

7C8000h–7CFFFFh

7D0000h–7D7FFFh

7D8000h–7DFFFFh

7E0000h–7E7FFFh

7E8000h–7EFFFFh

7F0000h–7F7FFFh

7F8000h–7F8FFFh

7F9000h–7F9FFFh

7FA000h–7FAFFFh

7FB000h–7FBFFFh

7FC000h–7FCFFFh

7FD000h–7FDFFFh

7FE000h–7FEFFFh

7FF000h–7FFFFFh

32

4

36

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Table 6. PL064J Sector Architecture

Bank

Sector

SA0

Sector Address (A22-A12)

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

0100000XXX

0100001XXX

0100010XXX

0100011XXX

0100100XXX

0100101XXX

0100110XXX

0100111XXX

0101000XXX

Sector Size (Kwords)

Address Range (x16)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

4

SA1

4

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

March 2, 2005 S29PL-J_00_A7

S29PL-J

37

P r e l i m i n a r y

Table 6. PL064J Sector Architecture (Continued)

Bank

Sector

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

Sector Address (A22-A12)

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

1001000XXX

1001001XXX

1001010XXX

1001011XXX

1001100XXX

1001101XXX

1001110XXX

1001111XXX

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

Sector Size (Kwords)

Address Range (x16)

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

32

38

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Table 6. PL064J Sector Architecture (Continued)

Bank

Sector

SA96

Sector Address (A22-A12)

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

1111000XXX

1111001XXX

1111010XXX

1111011XXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

Sector Size (Kwords)

Address Range (x16)

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

32

4

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

4

March 2, 2005 S29PL-J_00_A7

S29PL-J

39

P r e l i m i n a r y

Table 7. PL032J Sector Architecture

Bank

Sector

Sector Address (A22-A12)

Sector Size (Kwords)

Address Range (x16)

SA0

SA1

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001XXX

000010XXX

000011XXX

000100XXX

000101XXX

000110XXX

000111XXX

001000XXX

001001XXX

001010XXX

001011XXX

001100XXX

001101XXX

001110XXX

001111XXX

010000XXX

010001XXX

010010XXX

010011XXX

010100XXX

010101XXX

010110XXX

010111XXX

011000XXX

011001XXX

011010XXX

011011XXX

011100XXX

011101XXX

011110XXX

011111XXX

4

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

4

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

40

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Table 7. PL032J Sector Architecture (Continued)

Bank

Sector

Sector Address (A22-A12)

Sector Size (Kwords)

Address Range (x16)

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

100000XXX

100001XXX

100010XXX

100011XXX

100100XXX

100101XXX

100110XXX

100111XXX

101000XXX

101001XXX

101010XXX

101011XXX

101100XXX

101101XXX

101110XXX

101111XXX

110000XXX

110001XXX

110010XXX

110011XXX

110100XXX

110101XXX

110110XXX

110111XXX

111000XXX

111001XXX

111010XXX

111011XXX

111100XXX

111101XXX

111110XXX

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

32

4

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1F8FFFh

1F9000h–1F9FFFh

1FA000h–1FAFFFh

1FB000h–1FBFFFh

1FC000h–1FCFFFh

1FD000h–1FDFFFh

1FE000h–1FEFFFh

1FF000h–1FFFFFh

4

March 2, 2005 S29PL-J_00_A7

S29PL-J

41

P r e l i m i n a r y

Table 8. S29PL129J Sector Architecture

Sector Address

Sector Size

(Kwords)

Bank

Sector

SA1-0

CE1#

0

CE2#

1

(A21-A12)

Address Range (x16)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

4

SA1-1

4

SA1-2

4

SA1-3

4

SA1-4

4

SA1-5

4

SA1-6

4

SA1-7

4

SA1-8

32

SA1-9

SA1-10

SA1-11

SA1-12

SA1-13

SA1-14

SA1-15

SA1-16

SA1-17

SA1-18

SA1-19

SA1-20

SA1-21

SA1-22

SA1-23

SA1-24

SA1-25

SA1-26

SA1-27

SA1-28

SA1-29

SA1-30

SA1-31

SA1-32

SA1-33

SA1-34

SA1-35

SA1-36

SA1-37

SA1-38

42

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Table 8. S29PL129J Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

SA1-39

SA1-40

SA1-41

SA1-42

SA1-43

SA1-44

SA1-45

SA1-46

SA1-47

SA1-48

SA1-49

SA1-50

SA1-51

SA1-52

SA1-53

SA1-54

SA1-55

SA1-56

SA1-57

SA1-58

SA1-59

SA1-60

SA1-61

SA1-62

SA1-63

SA1-64

SA1-65

SA1-66

SA1-67

SA1-68

SA1-69

SA1-70

SA1-71

SA1-72

SA1-73

SA1-74

SA1-75

SA1-76

SA1-77

SA1-78

SA1-79

SA1-80

SA1-81

SA1-82

CE1#

0

CE2#

1

(Kwords)

32

Address Range (x16)

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

0100000XXX

0100001XXX

0100010XXX

0100011XXX

0100100XXX

0100101XXX

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

1001000XXX

1001001XXX

1001010XXX

1001011XXX

March 2, 2005 S29PL-J_00_A7

S29PL-J

43

P r e l i m i n a r y

Table 8. S29PL129J Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

SA1-83

CE1#

0

CE2#

1

(Kwords)

32

Address Range (x16)

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

1001100XXX

1001101XXX

1001110XXX

1001111XXX

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

SA1-84

SA1-85

SA1-86

SA1-87

SA1-88

SA1-89

SA1-90

SA1-91

SA1-92

SA1-93

SA1-94

SA1-95

SA1-96

SA1-97

SA1-98

SA1-99

SA1-100

SA1-101

SA1-102

SA1-103

SA1-104

SA1-105

SA1-106

SA1-107

SA1-108

SA1-109

SA1-110

SA1-111

SA1-112

SA1-113

SA1-114

SA1-115

SA1-116

SA1-117

SA1-118

SA1-119

SA1-120

SA1-121

SA1-122

SA1-123

SA1-124

SA1-125

SA1-126

44

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Table 8. S29PL129J Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

SA1-127

SA1-128

SA1-129

SA1-130

SA1-131

SA1-132

SA1-133

SA1-134

SA2-0

CE1#

0

1

CE2#

1

0

(Kwords)

32

Address Range (x16)

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

1111000XXX

1111001XXX

1111010XXX

1111011XXX

1111100XXX

1111101XXX

1111110XXX

1111111XXX

0000000XXX

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

0100000XXX

0100001XXX

0100010XXX

0100011XXX

SA2-1

SA2-2

SA2-3

SA2-4

SA2-5

SA2-6

SA2-7

SA2-8

SA2-9

SA2-10

SA2-11

SA2-12

SA2-13

SA2-14

SA2-15

SA2-16

SA2-17

SA2-18

SA2-19

SA2-20

SA2-21

SA2-22

SA2-23

SA2-24

SA2-25

SA2-26

SA2-27

SA2-28

SA2-29

SA2-30

SA2-31

SA2-32

SA2-33

SA2-34

SA2-35

March 2, 2005 S29PL-J_00_A7

S29PL-J

45

P r e l i m i n a r y

Table 8. S29PL129J Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

SA2-36

SA2-37

SA2-38

SA2-39

SA2-40

SA2-41

SA2-42

SA2-43

SA2-44

SA2-45

SA2-46

SA2-47

SA2-48

SA2-49

SA2-50

SA2-51

SA2-52

SA2-53

SA2-54

SA2-55

SA2-56

SA2-57

SA2-58

SA2-59

SA2-60

SA2-61

SA2-62

SA2-63

SA2-64

SA2-65

SA2-66

SA2-67

SA2-68

SA2-69

SA2-70

SA2-71

SA2-72

SA2-73

SA2-74

SA2-75

SA2-76

SA2-77

SA2-78

SA2-79

CE1#

1

CE2#

0

(Kwords)

32

Address Range (x16)

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

0100100XXX

0100101XXX

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

1001000XXX

1001001XXX

1001010XXX

1001011XXX

1001100XXX

1001101XXX

1001110XXX

1001111XXX

46

S29PL-J

S29PL-J_00_A7 March 2, 2005

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Table 8. S29PL129J Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

SA2-80

SA2-81

SA2-82

SA2-83

SA2-84

SA2-85

SA2-86

SA2-87

SA2-88

SA2-89

SA2-90

SA2-91

SA2-92

SA2-93

SA2-94

SA2-95

SA2-96

SA2-97

SA2-98

SA2-99

SA2-100

SA2-101

SA2-102

SA2-103

SA2-104

SA2-105

SA2-106

SA2-107

SA2-108

SA2-109

SA2-110

SA2-111

SA2-112

SA2-113

SA2-114

SA2-115

SA2-116

SA2-117

SA2-118

SA2-119

SA2-120

SA2-121

SA2-122

SA2-123

CE1#

1

CE2#

0

(Kwords)

32

Address Range (x16)

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

1111000XXX

1111001XXX

1111010XXX

1111011XXX

March 2, 2005 S29PL-J_00_A7

S29PL-J

47

P r e l i m i n a r y

Table 8. S29PL129J Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

(Kwords)

Bank

Sector

CE1#

1

CE2#

Address Range (x16)

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

SA2-124

SA2-125

SA2-126

SA2-127

SA2-128

SA2-129

SA2-130

SA2-131

SA2-132

SA2-133

SA2-134

0

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

32

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

Table 9. Secured Silicon Sector Addresses

Sector Size

64 words

Address Range

Factory-Locked Area

000000h-00003Fh

000040h-00007Fh

Customer-Lockable Area

64 words

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector

protection verification, through identifier codes output on DQ7–DQ0. This mode

is primarily intended for programming equipment to automatically match a device

to be programmed with its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V_IDon ad-

dress pin A9. Address pins must be as shown in Table 10 and Table 11. In

addition, when verifying sector protection, the sector address must appear on the

appropriate highest order address bits (see Table 4). Table 10 and Table 11 show

the remaining address bits that are don’t care. When all necessary bits have been

set as required, the programming equipment may then read the corresponding

identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed

in-system through the command register, for instances when the device is erased

or programmed in a system without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 21. Note that if a Bank Address (BA)

(on address bits PL127J: A22–A20, PL129J and PL064J: A21–A19, PL032J:

A20–A18) is asserted during the third write cycle of the autoselect command, the

host system can read autoselect data that bank and then immediately read array

data from the other bank, without exiting the autoselect mode.

To access the autoselect codes in-system, the host system can issue the autose-

lect command via the command register, as shown in Table 21. This method does

not require V_ID. Refer to the "Autoselect Command Sequence" section for more

information.

48

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Table 10. Autoselect Codes (High Voltage Method)

Amax

to

A5

to

DQ15

Description

CE#

OE# WE#

A12 A10 A9 A8

A7

A6

A4

A3 A2

A1 A0

to DQ0

Manufacturer

ID

products

:

Spansion

L

H

BA

X

V_ID

X

L

X

L

H

L

0001h

227Eh

Read

Cycle 1

L

2220h (PL127J)

2202h (PL064J)

220Ah (PL032J)

Read

Cycle 2

H

L

V_ID

L

2200h (PL127J)

2201h (PL064J)

2201h (PL032J)

Read

Cycle 3

L

H

L

H

L

H

L

Sector

0001h (protected),

0000h (unprotected)

Protection

Verification

L

H

SA

BA

X

V_ID

X

L

Secured

DQ7=1 (factory locked),

DQ6=1 (factory and

customer locked)

Silicon

L

V_ID

X

L

H

Indicator Bit

(DQ7, DQ6)

Table 11. Autoselect Codes for PL129J

A21

to

A5

to

DQ15

Description

CE1# CE2# OE# WE# A12

A10 A9 A8 A7 A6

A4

A3 A2 A1 A0

to DQ0

Manufacturer

L

H

L

V_I

ID:

Spansion

L

H

X

L

X

L

0001h

D

H

products

L

H

L

H

L

Read

Cycle 1

L

H

L

227Eh

2221h

2200h

H

L

Read

Cycle 2

V_I

L

H

D

H

L

H

L

Read

Cycle 3

H

L

Sector

Protection

Verification

H

V_I

0001h (protected),

0000h (unprotected)

L

H

SA

X

L

H

L

D

H

L

Secured

Silicon

Indicator Bit

(DQ7, DQ6)

H

DQ7=1 (factory locked),

DQ6=1 (factory and

customer locked)

V_I

X

H

D

H

L

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences

March 2, 2005 S29PL-J_00_A7

S29PL-J

49

P r e l i m i n a r y

Table 12. PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector/

Sector

SA0

A22-A12

Sector Block Size

Sector

A22-A12

Sector Block Size

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

000001XXXXX

000010XXXXX

000011XXXXX

000100XXXXX

000101XXXXX

000110XXXXX

000111XXXXX

001000XXXXX

001001XXXXX

001010XXXXX

001011XXXXX

001100XXXXX

001101XXXXX

001110XXXXX

001111XXXXX

010000XXXXX

010001XXXXX

010010XXXXX

010011XXXXX

010100XXXXX

010101XXXXX

010110XXXXX

010111XXXXX

011000XXXXX

011001XXXXX

011010XXXXX

011011XXXXX

011100XXXXX

011101XXXXX

011110XXXXX

4 Kwords

SA131-SA134

SA135-SA138

SA139-SA142

SA143-SA146

SA147-SA150

SA151-SA154

SA155-SA158

SA159-SA162

SA163-SA166

SA167-SA170

SA171-SA174

SA175-SA178

SA179-SA182

SA183-SA186

SA187-SA190

SA191-SA194

SA195-SA198

SA199-SA202

SA203-SA206

SA207-SA210

SA211-SA214

SA215-SA218

SA219-SA222

SA223-SA226

SA227-SA230

SA231-SA234

SA235-SA238

SA239-SA242

SA243-SA246

SA247-SA250

SA251-SA254

SA255-SA258

SA259

011111XXXXX

100000XXXXX

100001XXXXX

100010XXXXX

100011XXXXX

100100XXXXX

100101XXXXX

100110XXXXX

100111XXXXX

101000XXXXX

101001XXXXX

101010XXXXX

101011XXXXX

101100XXXXX

101101XXXXX

101110XXXXX

101111XXXXX

110000XXXXX

110001XXXXX

110010XXXXX

110011XXXXX

110100XXXXX

110101XXXXX

110110XXXXX

110111XXXXX

111000XXXXX

111001XXXXX

111010XXXXX

111011XXXXX

111100XXXXX

111101XXXXX

111110XXXXX

11111100XXX

11111101XXX

11111110XXX

11111111000

11111111001

11111111010

11111111011

128 (4x32) Kwords

32 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11-SA14

SA15-SA18

SA19-SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55-SA58

SA59-SA62

SA63-SA66

SA67-SA70

SA71-SA74

SA75-SA78

SA79-SA82

SA83-SA86

SA87-SA90

SA91-SA94

SA95-SA98

SA99-SA102

SA103-SA106

SA107-SA110

SA111-SA114

SA115-SA118

SA119-SA122

SA123-SA126

SA127-SA130

128 (4x32) Kwords

SA260

32 Kwords

SA261

32 Kwords

SA262

4 Kwords

SA263

4 Kwords

SA264

4 Kwords

SA265

4 Kwords

50

S29PL-J

S29PL-J_00_A7 March 2, 2005

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Table 13. PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection

CE1# Control

CE2# Control

Sector/Sector Block

Size

Sector/Sector Block

Size

Sector Group

SA1-0

A21-12

Sector Group

SA2-0–SA2-3

SA2-4–SA2-7

SA2-8–SA2-11

SA2-12–SA2-15

SA2-16–SA2-19

SA2-20–SA2-23

SA2-24–SA2-27

SA2-28–SA2-31

SA2-32–SA2-35

SA2-36–SA2-39

SA2-40–SA2-43

SA2-44–SA2-47

SA2-48–SA2-51

SA2-52–SA2-55

SA2-56–SA2-59

SA2-60–SA2-63

SA2-64–SA2-67

SA2-68–SA2-71

SA2-72–SA2-75

SA2-76–SA2-79

SA2-80–SA2-83

SA2-84–SA2-87

SA2-88–SA2-91

SA2-92–SA2-95

SA2-96–SA2-99

SA2-100–SA2-103

SA2-104–SA2-107

SA2-108–SA2-111

SA2-112–SA2-115

SA2-116–SA2-119

SA2-120–SA2-123

SA2-124

A21-12

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

11111XXXXX

4 Kwords

00000XXXXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

128 (4x32) Kwords

32 Kwords

SA1-1

4 Kwords

SA1-2

4 Kwords

SA1-3

4 Kwords

SA1-4

4 Kwords

SA1-5

4 Kwords

SA1-6

4 Kwords

SA1-7

4 Kwords

SA1-8

32 Kwords

SA1-9

32 Kwords

SA1-10

32 Kwords

SA1-11 - SA1-14

SA1-15 - SA1-18

SA1-19 - SA1-22

SA1-23 - SA1-26

SA1-27 - SA1-30

SA1-31 - SA1-34

SA1-35 - SA1-38

SA1-39 - SA1-42

SA1-43 - SA1-46

SA1-47 - SA1-50

SA1-51 - SA1-54

SA1-55 - SA1-58

SA1-59 - SA1-62

SA1-63 - SA1-66

SA1-67 - SA1-70

SA1-71 - SA1-74

SA1-75 - SA1-78

SA1-79 - SA1-82

SA1-83 - SA1-86

SA1-87 - SA1-90

SA1-91 - SA1-94

SA1-95 - SA1-98

SA1-99 - SA1-102

SA1-103 - SA1-106

SA1-107 - SA1-110

SA1-111 - SA1-114

SA1-115 - SA1-118

SA1-119 - SA1-122

SA1-123 - SA1-126

SA1-127 - SA1-130

SA1-131 - SA1-134

128 (4x32) Kwords

SA2-125

32 Kwords

SA2-126

32 Kwords

SA2-127

4 Kwords

SA2-128

4 Kwords

SA2-129

4 Kwords

SA2-130

4 Kwords

SA2-131

4 Kwords

SA2-132

4 Kwords

SA2-133

4 Kwords

SA2-134

4 Kwords

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Table 14. PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector

SA0

A21-A12

Sector/Sector Block Size

4 Kwords

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11-SA14

SA15-SA18

SA19-SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55-SA58

SA59-SA62

SA63-SA66

SA67-SA70

SA71-SA74

SA75-SA78

SA79-SA82

SA83-SA86

SA87-SA90

SA91-SA94

SA95-SA98

SA99-SA102

SA103-SA106

SA107-SA110

SA111-SA114

SA115-SA118

SA119-SA122

SA123-SA126

SA127-SA130

SA131

128 (4x32) Kwords

32 Kwords

SA132

32 Kwords

SA133

32 Kwords

SA134

4 Kwords

SA135

4 Kwords

SA136

4 Kwords

SA137

4 Kwords

SA138

4 Kwords

SA139

4 Kwords

SA140

4 Kwords

SA141

4 Kwords

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Table 15. PL032J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector

SA0

A21-A12

Sector/Sector Block Size

4 Kwords

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001XXX

000010XXX

000011XXX

0001XXXXX

0010XXXXX

0011XXXXX

0100XXXXX

0101XXXXX

0110XXXXX

0111XXXXX

1000XXXXX

1001XXXXX

1010XXXXX

1011XXXXX

1100XXXXX

1101XXXXX

1110XXXXX

111100XXX

111101XXX

111110XXX

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11-SA14

SA15-SA18

SA19-SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55-SA58

SA59-SA62

SA63-SA66

SA67

128 (4x32) Kwords

32 Kwords

SA68

32 Kwords

SA69

32 Kwords

SA70

4 Kwords

SA71

4 Kwords

SA72

4 Kwords

SA73

4 Kwords

SA74

4 Kwords

SA75

4 Kwords

SA76

4 Kwords

SA77

4 Kwords

Selecting a Sector Protection Mode

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See the

"Secured Silicon Sector Addresses" section for details.

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Table 16. Sector Protection Schemes

DYB

0

PPB

0

PPB Lock

Sector State

0

1

0

1

Unprotected—PPB and DYB are changeable

0

Unprotected—PPB not changeable, DYB is changeable

0

1

0

Protected—PPB and DYB are changeable

1

0

1

0

Protected—PPB not changeable, DYB is changeable

1

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Sector Protection

The PL127J, PL129J, PL064J, and PL032J features several levels of sector protec-

tion, which can disable both the program and erase operations in certain sectors

or sector groups:

Persistent Sector Protection

A command sector protection method that replaces the old 12 V controlled pro-

tection method.

Password Sector Protection

A highly sophisticated protection method that requires a password before

changes to certain sectors or sector groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase operations in sectors

SA1-133, SA1-134, SA2-0 and SA2-1.

The WP# Hardware Protection feature is always available, independent of the

software managed protection method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector Protection mode. The cus-

tomer must then choose if the Persistent or Password Protection method is most

desirable. There are two one-time programmable non-volatile bits that define

which sector protection method will be used. If the Persistent Sector Protection

method is desired, programming the Persistent Sector Protection Mode Locking

Bit permanently sets the device to the Persistent Sector Protection mode. If the

Password Sector Protection method is desired, programming the Password Mode

Locking Bit permanently sets the device to the Password Sector Protection mode.

It is not possible to switch between the two protection modes once a locking bit

has been set. One of the two modes must be selected when the device is first

programmed. This prevents a program or virus from later setting the Password

Mode Locking Bit, which would cause an unexpected shift from the default Per-

sistent Sector Protection Mode into the Password Protection Mode.

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See Au-

toselect Mode for details.

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Persistent Sector Protection

The Persistent Sector Protection method replaces the 12 V controlled protection

method in previous flash devices. This new method provides three different sec-

tor protection states:

Persistently Locked—The sector is protected and cannot be changed.

Dynamically Locked—The sector is protected and can be changed by a simple

command.

Unlocked—The sector is unprotected and can be changed by a simple com-

mand.

To achieve these states, three types of “bits” are used:

Persistent Protection Bit

Persistent Protection Bit Lock

Persistent Sector Protection Mode Locking Bit

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to a maximum four

sectors (see the sector address tables for specific sector protection groupings).

All 4 Kword boot-block sectors have individual sector Persistent Protection Bits

(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB

Write Command.

The device erases all PPBs in parallel. If any PPB requires erasure, the device

must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth-

erwise, a previously erased sector PPBs can potentially be over-erased. The flash

device does not have a built-in means of preventing sector PPBs over-erasure.

Persistent Protection Bit Lock (PPB Lock)

The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to

“1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.

There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up

or hardware reset. There is no command sequence to unlock the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware

reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through

the DYB Write Command.

When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and

PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are

changeable.

When the device is first powered on the DYBs power up cleared (sectors not pro-

tected). The Protection State for each sector is determined by the logical OR of

the PPB and the DYB related to that sector. For the sectors that have the PPBs

cleared, the DYBs control whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the DYBs will be set or cleared,

thus placing each sector in the protected or unprotected state. These are the

so-called Dynamic Locked or Unlocked states. They are called dynamic states be-

cause it is very easy to switch back and forth between the protected and

unprotected conditions. This allows software to easily protect sectors against in-

advertent changes yet does not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared as often as needed.

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The PPBs allow for a more static, and difficult to change, level of protection. The

PPBs retain their state across power cycles because they are non-volatile. Indi-

vidual PPBs are set with a command but must all be cleared as a group through

a complex sequence of program and erasing commands. The PPBs are also lim-

ited to 100 erase cycles.

The PPB Lock bit adds an additional level of protection. Once all PPBs are pro-

grammed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB

Lock disables all program and erase commands to the non-volatile PPBs. In ef-

fect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear

the PPB Lock is to go through a power cycle. System boot code can determine if

any changes to the PPB are needed; for example, to allow new system code to

be downloaded. If no changes are needed then the boot code can set the PPB

Lock to disable any further changes to the PPBs during system operation.

The WP#/ACC write protect pin adds a final level of hardware protection to sec-

tors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible

to change the contents of these sectors. These sectors generally hold system

boot code. The WP#/ACC pin can prevent any changes to the boot code that could

override the choices made while setting up sector protection during system

initialization.

For customers who are concerned about malicious viruses there is another level

of security - the persistently locked state. To persistently protect a given sector

or sector group, the PPBs associated with that sector need to be set to “1”. Once

all PPBs are programmed to the desired settings, the PPB Lock should be set to

“1”. Setting the PPB Lock automatically disables all program and erase commands

to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their cur-

rent state. The only way to clear the PPB Lock is to go through a power cycle.

It is possible to have sectors that have been persistently locked, and sectors that

are left in the dynamic state. The sectors in the dynamic state are all unprotected.

If there is a need to protect some of them, a simple DYB Write command se-

quence is all that is necessary. The DYB write command for the dynamic sectors

switch the DYBs to signify protected and unprotected, respectively. If there is a

need to change the status of the persistently locked sectors, a few more steps

are required. First, the PPB Lock bit must be disabled by either putting the device

through a power-cycle, or hardware reset. The PPBs can then be changed to re-

flect the desired settings. Setting the PPB lock bit once again will lock the PPBs,

and the device operates normally again.

The best protection is achieved by executing the PPB lock bit set command early

in the boot code, and protect the boot code by holding WP#/ACC = VIL.

Table 17 contains all possible combinations of the DYB, PPB, and PPB lock relating

to the status of the sector.

In summary, if the PPB is set, and the PPB lock is set, the sector is protected and

the protection can not be removed until the next power cycle clears the PPB lock.

If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB

then controls whether or not the sector is protected or unprotected.

If the user attempts to program or erase a protected sector, the device ignores

the command and returns to read mode. A program command to a protected sec-

tor enables status polling for approximately 1 µs before the device returns to read

mode without having modified the contents of the protected sector. An erase

command to a protected sector enables status polling for approximately 50 µs

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after which the device returns to read mode without having erased the protected

sector.

The programming of the DYB, PPB, and PPB lock for a given sector can be verified

by writing a DYB/PPB/PPB lock verify command to the device. There is an alter-

native means of reading the protection status. Take RESET# to VIL and hold WE#

at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of

the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) will

produce a logical ‘1” code at device output DQ0 for a protected sector or a “0” for

an unprotected sector. In this mode, the other addresses are don’t cares. Address

location with A1 = VIL are reserved for autoselect manufacturer and device

codes.

Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sector Protection mode locking

bit exists to guarantee that the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit prevents programming of the

password protection mode locking bit. This guarantees that a hacker could not

place the device in password protection mode.

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Password Protection Mode

The Password Sector Protection Mode method allows an even higher level of se-

curity than the Persistent Sector Protection Mode. There are two main differences

between the Persistent Sector Protection and the Password Sector Protection

Mode:

When the device is first powered on, or comes out of a reset cycle, the PPB Lock

bit set to the locked state, rather than cleared to the unlocked state.

The only means to clear the PPB Lock bit is by writing a unique 64-bit Password

to the device.

The Password Sector Protection method is otherwise identical to the Persistent

Sector Protection method.

A 64-bit password is the only additional tool utilized in this method.

Once the Password Mode Locking Bit is set, the password is permanently set with

no means to read, program, or erase it. The password is used to clear the PPB

Lock bit. The Password Unlock command must be written to the flash, along with

a password. The flash device internally compares the given password with the

pre-programmed password. If they match, the PPB Lock bit is cleared, and the

PPBs can be altered. If they do not match, the flash device does nothing. There

is a built-in 2 µs delay for each “password check.” This delay is intended to thwart

any efforts to run a program that tries all possible combinations in order to crack

the password.

Password and Password Mode Locking Bit

In order to select the Password sector protection scheme, the customer must first

program the password. The password may be correlated to the unique Electronic

Serial Number (ESN) of the particular flash device. Each ESN is different for every

flash device; therefore each password should be different for every flash device.

While programming in the password region, the customer may perform Password

Verify operations.

Once the desired password is programmed in, the customer must then set the

Password Mode Locking Bit. This operation achieves two objectives:

Permanently sets the device to operate using the Password Protection Mode. It is

not possible to reverse this function.

Disables all further commands to the password region. All program, and read op-

erations are ignored.

Both of these objectives are important, and if not carefully considered, may lead

to unrecoverable errors. The user must be sure that the Password Protection

method is desired when setting the Password Mode Locking Bit. More importantly,

the user must be sure that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations are disabled, there is no

means to verify what the password is afterwards. If the password is lost after set-

ting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit.

The Password Mode Locking Bit, once set, prevents reading the 64-bit password

on the DQ bus and further password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis-

tent Sector Protection Locking Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

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64-bit Password

The 64-bit Password is located in its own memory space and is accessible through

the use of the Password Program and Verify commands (see “Password Verify

Command”). The password function works in conjunction with the Password

Mode Locking Bit, which when set, prevents the Password Verify command from

reading the contents of the password on the pins of the device.

Write Protect (WP#)

The Write Protect feature provides a hardware method of protecting the upper

two and lower two sectors without using V_ID. This function is provided by the WP#

pin and overrides the previously discussed "High Voltage Sector Protection" sec-

tion method.

If the system asserts V_ILon the WP#/ACC pin, the device disables program and

erase functions in the two outermost 4 Kword sectors on both ends of the flash

array independent of whether it was previously protected or unprotected.

If the system asserts V_IHon the WP#/ACC pin, the device reverts the upper two

and lower two sectors to whether they were last set to be protected or unpro-

tected. That is, sector protection or unprotection for these sectors depends on

whether they were last protected or unprotected using the method described in

the "High Voltage Sector Protection" section.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent

behavior of the device may result.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of

the Password Mode Locking Bit after power-up reset. If the Password Mode Lock

Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the

ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue

the Password Unlock command. Successful execution of the Password Unlock

command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert-

ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock

Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit

is not set.

If the Password Mode Locking Bit is not set, including Persistent Protection Mode,

the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is

set by issuing the PPB Lock Bit Set command. Once set the only means for clear-

ing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password

Unlock command is ignored in Persistent Protection Mode.

High Voltage Sector Protection

Sector protection and unprotection may also be implemented using programming

equipment. The procedure requires high voltage (V_ID) to be placed on the RE-

SET# pin. Refer to Figure 1 for details on this procedure. Note that for sector

unprotect, all unprotected sectors must first be protected prior to the first sector

write cycle.

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START

Protect all sectors:

PLSCNT = 1

RESET# = V_ID

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

RESET# = V_ID

Wait 1 µs

unprotect address

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

Yes

Set up first sector

address

A7-A0 = 00000010

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A7-A0 =

Verify Sector

Protect: Write 40h

to sector address

with A7-A0 =

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

00000010

Verify Sector

Unprotect: Write

40h to sector

address with

A7-A0 =

Read from

sector address

with A7-A0 =

00000010

Increment

PLSCNT

No

00000010

No

PLSCNT

= 25?

Read from

sector address

with A7-A0 =

00000010

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Remove V

ID

Data = 00h?

Yes

from RESET#

No

Yes

Write reset

command

Remove V_ID

from RESET#

No

Last sector

verified?

Remove V

from RESET#

ID

Sector Protect

complete

Write reset

command

Yes

Write reset

command

Remove V_ID

from RESET#

Device failed

Sector Protect

complete

Sector Protect

complete

Write reset

command

Sector Protect

Algorithm

Device failed

Sector Unprotect

complete

Sector Unprotect

Algorithm

Figure 1. In-System Sector Protection/Sector Unprotection Algorithms

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Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to

change data in-system. The Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector addresses. Once V_IDis removed from

the RESET# pin, all the previously protected sectors are protected again. 2 shows

the algorithm, and 21 shows the timing diagrams, for this feature. While PPB lock

is set, the device cannot enter the Temporary Sector Unprotection Mode.

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL, upper two and lower two

sectors will remain protected).

2. All previously protected sectors are protected once again

Figure 2. Temporary Sector Unprotect Operation

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables

permanent part identification through an Electronic Serial Number (ESN) The

128-word Secured Silicon sector is divided into 64 factory-lockable words that

can be programmed and locked by the customer. The Secured Silicon sector is

located at addresses 000000h-00007Fh in both Persistent Protection mode and

Password Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the

factory-locked and customer locked status of the part.

The system accesses the Secured Silicon Sector through a command sequence

(see the "Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-

quence" section). After the system has written the Enter Secured Silicon Sector

command sequence, it may read the Secured Silicon Sector by using the ad-

dresses normally occupied by the boot sectors. This mode of operation continues

until the system issues the Exit Secured Silicon Sector command sequence, or

until power is removed from the device. On power-up, or following a hardware

reset, the device reverts to sending commands to the normal address space. Note

that the ACC function and unlock bypass modes are not available when the Se-

cured Silicon Sector is enabled.

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Factory-Locked Area (64 words)

The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is

locked when the part is shipped, whether or not the area was programmed at the

factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is perma-

nently set to a “1”. Optional Spansion programming services can program the

factory-locked area with a random ESN, a customer-defined code, or any combi-

nation of the two. Because only Spansion can program and protect the

factory-locked area, this method ensures the security of the ESN once the prod-

uct is shipped to the field. Contact your local sales office for details on using

Spansion’s programming services. Note that the ACC function and unlock bypass

modes are not available when the Secured Silicon sector is enabled.

Customer-Lockable Area (64 words)

The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is

shipped unprotected, which allows the customer to program and optionally lock

the area as appropriate for the application. The Secured Silicon Sector Cus-

tomer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently

locked to “1” by issuing the Secured Silicon Protection Bit Program Command.

The Secured Silicon Sector can be read any number of times, but can be pro-

grammed and locked only once. Note that the accelerated programming (ACC)

and unlock bypass functions are not available when programming the Secured

Silicon Sector.

The Customer-lockable Secured Silicon Sector area can be protected using one

of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region command se-

quence, and then follow the in-system sector protect algorithm as shown in

Figure 1, except that RESET# may be at either V_IHor V_ID. This allows in-sys-

tem protection of the Secured Silicon Sector Region without raising any de-

vice pin to a high voltage. Note that this method is only applicable to the

Secured Silicon Sector.

To verify the protect/unprotect status of the Secured Silicon Sector, follow the

algorithm shown in Figure 3.

Once the Secured Silicon Sector is locked and verified, the system must write the

Exit Secured Silicon Sector Region command sequence to return to reading and

writing the remainder of the array.

The Secured Silicon Sector lock must be used with caution since, once locked,

there is no procedure available for unlocking the Secured Silicon Sector area and

none of the bits in the Secured Silicon Sector memory space can be modified in

any way.

Secured Silicon Sector Protection Bits

The Secured Silicon Sector Protection Bits prevent programming of the Secured

Silicon Sector memory area. Once set, the Secured Silicon Sector memory area

contents are non-modifiable.

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START

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

Wait 1 µs

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Figure 3. Secured Silicon Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system noise.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not accept any write cycles. This pro-

tects data during V_CCpower-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

mode. Subsequent writes are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control pins to prevent unintentional writes

when V_CCis greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#, CE#, (CE1#, CE2# in PL129J) or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# (CE1# = CE2#

in PL129J)= V_IHor WE# = V_IH. To initiate a write cycle, CE# (CE1# / CE2# in

PL129J) and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# (CE1#, CE2# in PL129J) = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising edge of WE#. The internal

state machine is automatically reset to the read mode on power-up.

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Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h, any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 17–20. To

terminate reading CFI data, the system must write the reset command. The CFI

Query mode is not accessible when the device is executing an Embedded Program

or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 17–20. The system must write the reset

command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication

100. Contact your local sales office for copies of these documents.

Table 17. CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

Address for Alternate OEM Extended Table (00h = none exists)

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Table 18. System Interface String

Addresses

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0003h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^N

µs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 19. Device Geometry Definition

Addresses

Data

Description

0018h (PL127J)

0018h (PL129J)

0017h (PL064J)

0016h (PL032J)

27h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

00FDh (PL127J)

00FDh (PL129J)

007Dh (PL064J)

003Dh (PL032J)

31h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

32h

33h

34h

0000h

0001h

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

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Table 20. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

TBD

Silicon Revision Number (Bits 7-2)

Erase Suspend

46h

47h

48h

49h

0002h

0001h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

0001h

Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

0007h (PLxxxJ)

00E7h (PL127J)

00E7h (PL129J)

0077h (PL064J)

003Fh (PL032J)

Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

4Ah

Burst Mode Type

00 = Not Supported, 01 = Supported

4Bh

4Ch

4Dh

4Eh

0000h

0002h (PLxxxJ)

0085h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

0095h

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = Both top and bottom boot with write protect,

02h = Bottom Boot Device, 03h = Top Boot Device,

04h = Both Top and Bottom

4Fh

0001h

Program Suspend

0 = Not supported, 1 = Supported

50h

57h

0001h

0004h

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

0027h (PL127J)

0027h (PL129J)

0017h (PL064J)

000Fh (PL032J)

Bank 1 Region Information

X = Number of Sectors in Bank 1

58h

59h

0060h (PL127J)

0060h (PL129J)

0030h (PL064J)

0018h (PL032J)

Bank 2 Region Information

X = Number of Sectors in Bank 2

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Table 20. Primary Vendor-Specific Extended Query (Continued)

Addresses

Data

Description

0060h (PL127J)

0060h (PL129J)

0030h (PL064J)

0018h (PL032J)

Bank 3 Region Information

X = Number of Sectors in Bank 3

5Ah

0027h (PL127J)

0027h (PL129J)

0017h (PL064J)

000Fh (PL032J)

Bank 4 Region Information

X = Number of Sectors in Bank 4

5Bh

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Command Definitions

Writing specific address and data commands or sequences into the command

register initiates device operations. Table 21 defines the valid register command

sequences. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state. A reset com-

mand is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in

PL129J), whichever happens later. All data is latched on the rising edge of WE#

or CE# (CE1# / CE2# in PL129J), whichever happens first. Refer to the "AC Char-

acteristic" section section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No

commands are required to retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank

enters the erase-suspend-read mode, after which the system can read data from

any non-erase-suspended sector within the same bank. The system can read

array data using the standard read timing, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing

a programming operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See the "Erase Suspend/Erase

Resume Commands" section section for more information.

After the device accepts a Program Suspend command, the corresponding bank

enters the program-suspend-read mode, after which the system can read data

from any non-program-suspended sector within the same bank. See the "Pro-

gram Suspend/Program Resume Commands" section for more information.

The system must issue the reset command to return a bank to the read (or

erase-suspend-read) mode if DQ5 goes high during an active program or erase

operation, or if the bank is in the autoselect mode. See the next section, "Reset

Command" section, for more information.

See also "Requirements for Reading Array Data" section in the "Device Bus Op-

erations" section section for more information. The "AC Characteristic" section

table provides the read parameters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read

mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure begins, however, the device

ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program

command sequence before programming begins. This resets the bank to which

the system was writing to the read mode. If the program command sequence is

written to a bank that is in the Erase Suspend mode, writing the reset command

returns that bank to the erase-suspend-read mode. Once programming begins,

however, the device ignores reset commands until the operation is complete.

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The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autoselect mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while

in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command

returns the banks to the read mode (or erase-suspend-read mode if that bank

was in Erase Suspend and program-suspend-read mode if that bank was in

Pro-gram Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and device codes, and determine whether or not a sector is protected.

The autoselect command sequence may be written to an address within a bank

that is either in the read or erase-suspend-read mode. The autoselect command

may not be written while the device is actively programming or erasing in the

other bank.

The autoselect command sequence is initiated by first writing two unlock cycles.

This is followed by a third write cycle that contains the bank address and the au-

toselect command. The bank then enters the autoselect mode. The system may

read any number of autoselect codes without reinitiating the command sequence.

Table 21 shows the address and data requirements. To determine sector protec-

tion information, the system must write to the appropriate bank address (BA) and

sector address (SA). Table 4 shows the address range and bank number associ-

ated with each sector.

The system must write the reset command to return to the read mode (or

erase-suspend-read mode if the bank was previously in Erase Suspend).

Enter Secured Silicon Sector/Exit Secured Silicon Sector

Command Sequence

The Secured Silicon Sector region provides a secured data area containing a ran-

dom, eight word electronic serial number (ESN). The system can access the

Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon

Sector command sequence. The device continues to access the Secured Silicon

Sector region until the system issues the four-cycle Exit Secured Silicon Sector

command sequence. The Exit Secured Silicon Sector command sequence returns

the device to normal operation. The Secured Silicon Sector is not accessible when

the device is executing an Embedded Program or embedded Erase algorithm.

Table 21 shows the address and data requirements for both command sequences.

See also “Secured Silicon Sector Flash Memory Region” for further information.

Note that the ACC function and unlock bypass modes are not available when the

Secured Silicon Sector is enabled.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the program set-up com-

mand. The program address and data are written next, which in turn initiate the

Embedded Program algorithm. The system is not required to provide further con-

trols or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Table 21 shows the address and

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data requirements for the program command sequence. Note that the Secured

Silicon Sector, autoselect, and CFI functions are unavailable when a [pro-

gram/erase] operation is in progress.

When the Embedded Program algorithm is complete, that bank then returns to

the read mode and addresses are no longer latched. The system can determine

the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the

"Write Operation Status" section section for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately terminates the program

operation. The program command sequence should be reinitiated once that bank

has returned to the read mode, to ensure data integrity. Note that the Secured

Silicon Sector, autoselect and CFI functions are unavailable when the Secured Sil-

icon Sector is enabled.

Programming is allowed in any sequence and across sector boundaries. A bit

cannot be programmed from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate

the operation was successful. However, a succeeding read will show that the data

is still “0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program data to a bank faster

than using the standard program command sequence. The unlock bypass com-

mand sequence is initiated by first writing two unlock cycles. This is followed by

a third write cycle containing the unlock bypass command, 20h. That bank then

enters the unlock bypass mode. A two-cycle unlock bypass program command

sequence is all that is required to program in this mode. The first cycle in this se-

quence contains the unlock bypass program command, A0h; the second cycle

contains the program address and data. Additional data is programmed in the

same manner. This mode dispenses with the initial two unlock cycles required in

the standard program command sequence, resulting in faster total programming

time. Table 21 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-

pass Reset commands are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset command sequence. (See Table 22)

The device offers accelerated program operations through the WP#/ACC pin.

When the system asserts V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock

Bypass program command sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not

be at V_HHany operation other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

4 illustrates the algorithm for the program operation. Refer to the "Erase/Program

Operations" section table in the AC Characteristics section for parameters, and

Figure 14 for timing diagrams.

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START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 21 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 21 shows the address and data requirements

for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read

mode and addresses are no longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the "Write

Operation Status" section section for information on these status bits.

Any commands written during the chip erase operation are ignored. Note that Se-

cured Silicon Sector, autoselect, and CFI functions are unavailable when a

[program/erase] operation is in progress. However, note that a hardware reset

immediately terminates the erase operation. If that occurs, the chip erase com-

mand sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

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5 illustrates the algorithm for the erase operation. Refer to the "Erase/Program

Operations" section tables in the AC Characteristics section for parameters, and

Figure 16 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table 21 shows the address

and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory

for an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs.

During the time-out period, additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than 50 µs, otherwise erasure

may begin. Any sector erase address and command following the exceeded

time-out may or may not be accepted. It is recommended that processor inter-

rupts be disabled during this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase command is written. If

any command other than 30h, B0h, F0h is input during the time-out pe-

riod, the normal operation will not be guaranteed. The system must rewrite

the command sequence and any additional addresses and commands. Note that

Secured Silicon Sector, autoselect, and CFI functions are unavailable when a

[program/erase] operation is in progress.

The system can monitor DQ3 to determine if the sector erase timer has timed out

(See the section on DQ3: Sector Erase Timer). The time-out begins from the ris-

ing edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading

array data and addresses are no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read data from the non-erasing

bank. The system can determine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the "Write Operation

Status" section section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is

valid. All other commands are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

5 illustrates the algorithm for the erase operation. Refer to the "Erase/Program

Operations" section tables in the AC Characteristics section for parameters, and

Figure 16 section for timing diagrams.

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START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 21 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 5. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase

operation and then read data from, or program data to, any sector not selected

for erasure. The bank address is required when writing this command. This com-

mand is valid only during the sector erase operation, including the 80 µs time-out

period during the sector erase command sequence. The Erase Suspend command

is ignored if written during the chip erase operation or Embedded Program

algorithm.

When the Erase Suspend command is written during the sector erase operation,

the device requires a maximum of 35 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written during the sector erase

time-out, the device immediately terminates the time-out period and suspends

the erase operation. Addresses are “don’t-cares” when writing the Erase suspend

command.

After the erase operation has been suspended, the bank enters the erase-sus-

pend-read mode. The system can read data from or program data to any sector

not selected for erasure. (The device “erase suspends” all sectors selected for

erasure.) Reading at any address within erase-suspended sectors produces sta-

tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. Refer

to the "Write Operation Status" section section for information on these status

bits.

After an erase-suspended program operation is complete, the bank returns to the

erase-suspend-read mode. The system can determine the status of the program

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operation using the DQ7 or DQ6 status bits, just as in the standard Word Program

operation. Refer to the "Write Operation Status" section section for more

information.

In the erase-suspend-read mode, the system can also issue the autoselect com-

mand sequence. The device allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored in the memory array. When

the device exits the autoselect mode, the device reverts to the Erase Suspend

mode, and is ready for another valid operation. Refer to the "Secured Silicon Sec-

tor Addresses" section and the "Autoselect Command Sequence" section sections

for details.

To resume the sector erase operation, the system must write the Erase Resume

command (address bits are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command. Further writes of the

Resume command are ignored. Another Erase Suspend command can be written

after the chip has resumed erasing.

If the Persistent Sector Protection Mode Locking Bit is verified as programmed

without margin, the Persistent Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin. If the Secured Silicon

Sector Protection Bit is verified as programmed without margin, the Secured Sil-

icon Sector Protection Bit Program Command should be reissued to improve

program margin. µµAfter programming a PPB, two additional cycles are needed

to determine whether the PPB has been programmed with margin. If the PPB has

been programmed without margin, the program command should be reissued to

improve the program margin. Also note that the total number of PPB pro-

gram/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is

not guaranteed.

After erasing the PPBs, two additional cycles are needed to determine whether

the PPB has been erased with margin. If the PPBs has been erased without mar-

gin, the erase command should be reissued to improve the program margin. The

programming of either the PPB or DYB for a given sector or sector group can be

verified by writing a Sector Protection Status command to the device.

Note that there is no single command to independently verify the programming

of a DYB for a given sector group.

Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt an embedded

programming operation so that data can read from any non-suspended sector.

When the Program Suspend command is written during a programming process,

the device halts the programming operation within t_PSL(program suspend la-

tency) and updates the status bits. Addresses are “don’t-cares” when writing the

Program Suspend command. After the programming operation has been sus-

pended, the system can read array data from any non-suspended sector. The

Program Suspend command may also be issued during a programming operation

while an erase is suspended. In this case, data may be read from any addresses

not in Erase Suspend or Program Suspend. If a read is needed from the Secured

Silicon Sector area, then user must use the proper command sequences to enter

and exit this region. The system may also write the autoselect command se-

quence when the device is in Program Suspend mode. The device allows reading

autoselect codes in the suspended sectors, since the codes are not stored in the

memory array. When the device exits the autoselect mode, the device reverts to

Program Suspend mode, and is ready for another valid operation. See “Autoselect

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Command Sequence” for more information. After the Program Resume command

is written, the device reverts to programming. The system can determine the sta-

tus of the program operation using the DQ7 or DQ6 status bits, just as in the

standard program operation. See “Write Operation Status” for more information.

The system must write the Program Resume command (address bits are “don’t

care”) to exit the Program Suspend mode and continue the programming opera-

tion. Further writes of the Program Resume command are ignored. Another

Program Suspend command can be written after the device has resumed

programming.

Command Definitions Tables

Table 21. Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Command (Notes)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

1

RA

RD

F0

XXX

(BA)

555

(BA)

X00

Manufacturer ID

4

6

4

555

AA

2AA

55

90

01

(BA)

555

(BA)

X01

(BA)

X0E

(Note

10)

(BA)

X0F

(Note

10)

Device ID (Note 10)

227E

Autoselect

(Note 7)

Secured Silicon Sector

Factory Protect (Note 8)

(BA)

555

(Note

8)

AA

X03

Sector Group Protect

Verify (Note 9)

(BA)

555

(SA) XX00/

X02

AAA

XX01

Program

4

6

1

2

3

2

1

2

555

BA

AA

B0

30

98

A0

AA

A0

80

98

90

2AA

55

555

A0

80

PA

PD

Chip Erase

Sector Erase

555

AA

2AA

55

555

SA

10

30

AA

Program/Erase Suspend (Note 11)

Program/Erase Resume (Note 12)

CFI Query (Note 13)

BA

55

Accelerated Program (Note 15)

Unlock Bypass Entry (Note 15)

Unlock Bypass Program (Note 15)

Unlock Bypass Erase (Note 15)

Unlock Bypass CFI (Notes 13, 15)

Unlock Bypass Reset (Note 15)

XX

PA

2AA

PA

PD

55

PD

10

555

XX

555

20

XX

XXX

00

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by PL127J: Amax:A20, PL064J

and PL129J: Amax:A19, PL032J: Amax:A18.

PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE# (CE1#/CE2# for PL129J) pulse, whichever

happens later.

PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# (CE1#/CE2# for PL129J) pulse,

whichever happens first.

RA = Read Address (Amax:A0).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing.

WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#.

X = Don’t care

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

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4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

5. No unlock or command cycles required when bank is reading array data.

6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend)

when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information).

7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID

or device ID information. See "Autoselect Command Sequence" section section for more information.

8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked.

9. The data is 00h for an unprotected sector group and 01h for a protected sector group.

10. Device ID must be read across cycles 4, 5, and 6. PL127J (X0Eh = 2220h, X0Fh = 2200h), PL129J (X0Eh = 2221h, X0Fh =

2200h),PL064J (X0Eh = 2202h, X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h).

11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address.

12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.

13. Command is valid when device is ready to read array data or when device is in autoselect mode.

14. WP#/ACC must be at V_IDduring the entire operation of command.

15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required

to return to the reading array.

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Table 22. Sector Protection Command Definitions

Bus Cycles (Notes 1-4)

Command

(Notes)

Addr Data Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset

1

3

XXX

555

F0

Secured

Silicon

Sector Entry

AA

2AA

55

555

88

90

Secured

Silicon

4

6

555

AA

XX

00

68

Sector Exit

Secured

Silicon

ProtectionBit

Program

(Notes 5, 6)

2AA

55

555

60

OW

48

OW

RD(0)

Secured

Silicon

ProtectionBit

Status

5

555

AA

OW

48

RD(0)

Password

Program

(Notes 5, 7,

8)

4

7

555

AA

2AA

55

555

38

C8

28

XX[0-3]

PD[0-3]

Password

Verify (Notes

6, 8, 9)

PWA[0-3] PWD[0-3]

Password

Unlock

(Notes 7, 10,

11)

PWA[0]

PWD[0] PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3]

PPB Program

(Notes 5, 6,

12)

6

4

6

555

AA

2AA

55

555

60

90

60

(SA)WP

WP

68

RD(0)

60

(SA)WP

(SA)

48

40

(SA)WP RD(0)

PPB Status

All PPB Erase

(Notes 5, 6,

13, 14)

PPB Lock Bit

Set

3

4

555

AA

2AA

55

555

78

58

PPB Lock Bit

Status (Note

15)

SA

RD(1)

DYB Write

(Note 7)

4

555

AA

2AA

55

555

48

58

SA

X1

X0

DYB Erase

(Note 7)

DYB Status

(Note 6)

RD(0)

PPMLB

Program

(Notes 5, 6,

12)

6

5

6

5

555

AA

2AA

55

555

60

PL

SL

68

48

68

48

PL

SL

48

RD(0)

48

PL

SL

RD(0)

PPMLB

Status (Note

5)

SPMLB

Program

(Notes 5, 6,

12)

SPMLB

Status (Note

5)

RD(0)

Legend:

DYB = Dynamic Protection Bit

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

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PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A7:A0) is (00001010)

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)

WP = PPB Address (A7:A0) is (00000010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

5. The reset command returns device to reading array.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 =

0 in cycle 6, program command must be issued and verified again.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion of password.

9. Command sequence returns FFh if PPMLB is set.

10. The password is written over four consecutive cycles, at addresses 0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase

command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB

overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

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Write Operation Status

The device provides several bits to determine the status of a program or erase opera-

tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 23 and the following subsections describe

the function of these bits. DQ7 and DQ6 each offer a method for determining whether

a program or erase operation is complete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine whether an Embedded Program

or Erase operation is in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-

gram or Erase algorithm is in progress or completed, or whether a bank is in Erase

Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-

mand sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement

of the datum programmed to DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is complete, the device out-

puts the datum programmed to DQ7. The system must provide the program address

to read valid status information on DQ7. If a program address falls within a protected

sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns

to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide

an address within any of the sectors selected for erasure to read valid status in-

formation on DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the

bank returns to the read mode. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at an address within

a protected sector, the status may not be valid.

When the system detects DQ7 has changed from the complement to true data,

it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the

completion of an Embedded Program or Erase operation, DQ7 may change asyn-

chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,

the device may change from providing status information to valid data on DQ7.

Depending on when the system samples the DQ7 output, it may read the status

or valid data. Even if the device has completed the program or erase operation

and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid

data on DQ15–DQ0 will appear on successive read cycles.

Table 23 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling

algorithm. 18 in the "AC Characteristic" section section shows the Data# Polling

timing diagram.

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START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is

any sector address within the sector being erased. During chip erase, a valid address is

any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously

with DQ5.

Figure 6. Data# Polling Algorithm

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RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an

Embedded Algorithm is in progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command sequence. Since RY/BY#

is an open-drain output, several RY/BY# pins can be tied together in parallel with

a pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is high (Ready),

the device is in the read mode, the standby mode, or one of the banks is in the

erase-suspend-read mode.

Table 23 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. The system may use either OE# or CE#

to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 400 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the "DQ7: Data# Polling" section).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 µs after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

Table 23 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit

algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing di-

agrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical

form. See also the "DQ2: Toggle Bit II" section.

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START

Read Byte

(DQ7–DQ0)

Address =VA

Read Byte

(DQ7–DQ0)

Address =VA

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ7–DQ0)

Address = VA

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle

bit may stop toggling as DQ5 changes to “1.” See the "DQ6: Toggle Bit I" section and

"DQ2: Toggle Bit II" section for more information.

Figure 7. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular

sector is actively erasing (that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have

been selected for erasure. (The system may use either OE# or CE# (CE1# / CE2#

for PL129J) to control the read cycles.) But DQ2 cannot distinguish whether the

sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates

whether the device is actively erasing, or is in Erase Suspend, but cannot distin-

guish which sectors are selected for erasure. Thus, both status bits are required

for sector and mode information. Refer to Table 23 to compare outputs for DQ2

and DQ6.

Figure 7 shows the toggle bit algorithm in flowchart form, and the "DQ2: Toggle

Bit II" section explains the algorithm. See also the "DQ6: Toggle Bit I" section.

Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences

between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. Whenever the system initially be-

gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to

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determine whether a toggle bit is toggling. Typically, the system would note and

store the value of the toggle bit after the first read. After the second read, the

system would compare the new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-

cessfully completed the program or erase operation. If it is still toggling, the

device did not completed the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 has not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, determining the status as de-

scribed in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algo-

rithm when it returns to determine the status of the operation (top of Figure 7).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified inter-

nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the

program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the device halts the opera-

tion, and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return

to the read mode (or to the erase-suspend-read mode if a bank was previously

in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-

termine whether or not erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors are selected for erasure,

the entire time-out also applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also

the "Sector Erase Command Sequence" section.

After the sector erase command is written, the system should read the status of

DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase

algorithm has begun; all further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the device will accept addi-

tional sector erase commands. To ensure the command has been accepted, the

system software should check the status of DQ3 prior to and following each sub-

sequent sector erase command. If DQ3 is high on the second status check, the

last command might not have been accepted.

Table 23 shows the status of DQ3 relative to the other status bits.

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Table 23. Write Operation Status

DQ7

(Note 2)

DQ5

(Note 1)

DQ2

(Note 2)

Status

DQ6

DQ3

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ7#

0

Toggle

0

N/A

1

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase-Suspend-

Read

Erase

Suspend

Mode

Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

1

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Reading within Program Suspended

Sector

Invalid (Not Invalid (Not Invalid (Not Invalid (Not Invalid (Not

Allowed)

Program

Suspend

Mode

Allowed)

Reading within Non-program

Suspended Sector

Data

1

(Note 3)

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for

further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

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Absolute Maximum Ratings

Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

V_CC(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . .–0.5 V to +13.0 V

WP#/ACC (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,

input or I/O pins may overshoot V_SSto –2.0 V for periods of up to 20 ns. Maximum

DC voltage on input or I/O pins is V_CC+0.5 V. During voltage transitions, input or

I/O pins may overshoot to V_CC+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V.

During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V_SS

to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on

pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods

up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the

short circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this data sheet is not implied. Exposure of the device to absolute max-

imum rating conditions for extended periods may affect device reliability.

20 ns

V_CC

+2.0 V

+0.8 V

V_CC

–0.5 V

–2.0 V

+0.5 V

2.0 V

20 ns

Maximum Negative Overshoot Waveform

Maximum Positive Overshoot Waveform

Figure 8. Maximum Overshoot Waveforms

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Operating Ranges

Operating ranges define those limits between which the functionality of the de-

vice is guaranteed.

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Supply Voltages

V_CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7–3.6 V

V_IO(see Note)1.65–1.95 V (for PL127J and PL129J) or 2.7–3.6 V (for all PLxxxJ

devices)

Notes:

For all AC and DC specifications, V_IO= V_CC; contact your local sales office for other V_IO

options.

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DC Characteristics

Table 24. CMOS Compatible

Parameter

Parameter Description

Symbol

Test Conditions

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

,

I_LI

Input Load Current

±1.0

µA

V_CC= V_CC

max

I_LIT

I_LR

A9, OE#, RESET# Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; V_ID= 12.5 V

35

µA

V_OUT= V_SSto V_CC, OE# = V_IH

V_CC= V_{CC max}

I_LO

Output Leakage Current

±1.0

µA

5 MHz

20

45

15

30

55

25

OE# = V_IH, V_CC= V_{CC max}

(Note 1)

I_CC1

V_CCActive Read Current (Notes 1, 2)

mA

10 MHz

I_CC2

I_CC3

I_CC4

I_CC5

V_CCActive Write Current (Notes 2, 3)

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

OE# = V_IH, WE# = V_IL

mA

µA

CE#, RESET#, WP#/ACC

= V_IO± 0.3 V

0.2

5

RESET# = V_SS± 0.3 V

V_IH= V_IO± 0.3 V;

V_IL= V_SS± 0.3 V

Automatic Sleep Mode (Notes 2, 4)

5 MHz

10 MHz

5 MHz

21

46

21

46

45

70

45

70

V_CCActive Read-While-Program Current

(Notes 1, 2)

I_CC6

OE# = V_IH

,

mA

V_CCActive Read-While-Erase Current

(Notes 1, 2)

I_CC7

OE# = V_IH

mA

10 MHz

V_CCActive Program-While-Erase-

Suspended Current (Notes 2, 5)

I_CC8

I_CC9

17

10

25

V_CCActive Page Read Current (Note 2)

OE# = V_IH, 8 word Page Read

15

0.4

mA

V

V_IO= 1.65–1.95 V (PL127J and PL129J)

V_IO= 2.7–3.6 V

–0.4

–0.5

V_IO–0.4

2.0

V_IL

V_IH

Input Low Voltage

0.8

V

V_IO= 1.65–1.95 V (PL127J AND PL129J)

V_IO= 2.7–3.6 V

V_IO+0.4

V_CC+0.3

9.5

V

Input High Voltage

V

V_HH

V_ID

Voltage for ACC Program Acceleration

V_CC= 3.0 V ± 10%

8.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_CC= 3.0 V ± 10%

11.5

12.5

V

I_OL= 100 µA, V_CC= V_{CC min}, V_IO= 1.65–1.95

V (PL127J AND PL129J)

0.1

0.4

V

V_OL

Output Low Voltage

I

_OL= 2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6 V

I_OH= –100 µA, V_CC= V_{CC min}, V_IO

=

V_IO–0.1

1.65–1.95 V (PL127J AND PL129J)

V_OH

Output High Voltage

I_OH= –2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6

V

2.4

2.3

V

V_LKO

Low V_CCLock-Out Voltage (Note 5)

2.5

Notes:

1. The I_CCcurrent listed is typically less than 5 mA/MHz, with OE# at V_IH

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep

mode current is 1 mA.

5. Not 100% tested.

6. In S29PL129J there are two CE# (CE1#, CE2#).

7. Valid CE1#/CE2# conditions: (CE1# = V_IL,CE2# = V_IH,) or (CE1# = V_IH,CE2# = V_IL) or (CE1# = V_IH,CE2# = V_IH

)

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AC Characteristic

Test Conditions

3.6 V

2.7 kΩ

Device

Under

Test

Device

Under

Test

C

L

C

6.2 kΩ

L

V_IO= 3.0 V

Note: Diodes are IN3064 or equivalent

V_IO= 1.8 V (PL127J and PL129J)

Figure 9. Test Setups

Table 25. Test Specifications

Test Condition

All Speeds

1 TTL gate

30

Unit

Output Load

Output Load Capacitance, C_L(including jig capacitance)

pF

ns

V_IO= 1.8 V

(PL127J AND PL129J)

Input Rise and Fall Times

5

V_IO= 3.0 V

V_IO= 1.8 V

(PL127J AND PL129J)

0.0 - 1.8

Input Pulse Levels

V

V_IO= 3.0 V

0.0–3.0

V_IO/2

Input timing measurement reference levels

Output timing measurement reference levels

V

V_IO/2

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Switching Waveforms

Table 26. Key To Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

VIO

VIO/2

In

Measurement Level

Output

0.0 V

Figure 10. Input Waveforms and Measurement Levels

VCC RampRate

All DC characteristics are specified for a V_CCramp rate > 1V/100 µs and V_CC

>=V_CCQ- 100 mV. If the V_CCramp rate is < 1V/100 µs, a hardware reset

required.+

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Read Operations

Table 27. Read-Only Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std. Description

t_RCRead Cycle Time (Note 1)

t_ACCAddress to Output Delay

t_CEChip Enable to Output Delay

t_PACCPage Access Time

Te st S e tup

55

20

60

25

65

25

70

30

Unit

ns

Min

Max

t_AVQV

t_ELQV

CE#, OE# = V_IL

OE# = V_IL

ns

t_GLQV

t_EHQZ

t_OE

t_DF

Output Enable to Output Delay

30

ns

Chip Enable to Output High Z (Note 3)

16

ns

Output Enable to Output High Z (Notes 1,

3)

t_GHQZ

t_DF

Max

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 3)

t_AXQX

t_OH

Min

5

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 25 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V_CC/2. The time from OE#

high to the data bus driven to V_CC/2 is taken as t_DF

.

4. S29PL129J has two CE# (CE1#, CE2#).

5. Valid CE1# / CE2# conditions: (CE1# = V_IL,CE2# = V_IH) or (CE1# = V_IH,CE2# = V_IL) or (CE1# = V_IH,CE2# = V_IH

)

6. Valid CE1# / CE2# transitions: (CE1# = V_IL,CE2# = V_IH) or (CE1# = V_IH,CE2# = V_IL) to (CE1# = CE2# = V_IH

)

7. Valid CE1# / CE2# transitions: (CE1# = CE2# = V_IH) to (CE1# = V_IL,CE2# = V_IH) or (CE1# = V_IH,CE2# = V_IL)

8. For 70pF Output Load Capacitance, 2 ns will be added to the above t_ACC,t_CE,t_PACC,t_OEvalues for all speed grades

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t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OH

Valid Data

HIGH Z

RESET#

RY/BY#

0 V

Notes:

1. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 11. Read Operation Timings

Same Page

Amax

-

A3

A0

A2

Ad

Aa

Ab

Ac

t_PACC

t_ACC

Data

Qa

Qb

Qc

Qd

CE#

OE#

Notes:

1. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 12. Page Read Operation Timings

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Reset

Table 28. Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

t_RPD

t_RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Notes:

1. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2#

Figure 13. Reset Timings

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Erase/Program Operations

Table 29. Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

t_AVWL

Std

t_WC

t_AS

Description

55

60

65

70

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

55

60

65

70

0

ns

Address Setup Time to OE# low during toggle bit

polling

t_ASO

t_AH

Min

15

ns

t_WLAX

Address Hold Time

30

25

35

30

Address Hold Time From CE# (CE1#, CE#2 in PL129J)

or OE# high during toggle bit polling

t_AHT

0

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

ns

Data Hold Time

0

t_OEPH

Output Enable High during toggle bit polling

10

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# (CE1# or CE#2 in PL129J) Setup Time

CE# (CE1# or CE#2 in PL129J) Hold Time

Write Pulse Width

Min

Typ

Min

Max

Min

Max

0

ns

µs

sec

µs

ns

µs

t_WP

35

t_WPH

t_SR/W

Write Pulse Width High

20

25

Latency Between Read and Write Operations

0

6

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 4)

t_WHWH1Accelerated Programming Operation (Note 4)

t_WHWH2Sector Erase Operation (Note 4)

4

0.5

50

0

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

90

35

t_BUSY

t_PSL

Program/Erase Valid to RY/BY# Delay

Program Suspend Latency

Notes:

1. Not 100% tested.

2. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

3. S29PL129J - There are two CE# (CE1#, CE2#).

4. See the “Erase And Programming Performance” section for more information.

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Timing Diagrams

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address

2. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 14. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 15. Accelerated Program Timing Diagram

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Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

Data

Status

D

OUT

55h

30h

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”

2. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 16. Chip/Sector Erase Operation Timings

t_WC

t_RC

t_WC

Valid PA

t_AH

Valid RA

Valid PA

Addresses

t_AS

t_CPH

t_AS

t_AH

t_ACC

t_CE

CE#

OE#

t_CP

t_OE

t_OEH

t_GHWL

t_WP

WE#

Data

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 17. Back-to-back Read/Write Cycle Timings

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t_RC

VA

t_ACC

t_CE

Addresses

CE#

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ6–DQ0

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and

array data read cycle

Figure 18. Data# Polling Timings (During Embedded Algorithms)

t_AHT

t_AS

Addresses

CE#

t_AHT

t_ASO

t_CEPH

t_OEH

WE#

OE#

t_OEPH

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

RY/BY#

Valid Data

(first read)

(second read)

(stops toggling)

Notes:

1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

status read cycle, and array data read cycle

2. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 19. Toggle Bit Timings (During Embedded Algorithms)

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Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#

to toggle DQ2 and DQ6.

Figure 20. DQ2 vs. DQ6

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Protect/Unprotect

Table 30. Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 21. Temporary Sector Unprotect Timing Diagram

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V

ID

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Group Protect/Unprotect

Verify

40h

Data

60h

1 µs

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

CE#

WE#

OE#

Notes:

1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

2. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram

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Controlled Erase Operations

Table 31. Alternate CE# Controlled Erase and Program Operations

Parameter

JEDEC

Speed Options

Std

t_WC

t_AS

t_AH

t_DS

t_DH

Description

55

60

65

70

Unit

ns

t_AVAV

t_AVWL

t_ELAX

t_DVEH

t_EHDX

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

55

60

65

70

0

ns

30

25

35

30

ns

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_WS

t_WH

WE# Setup Time

Min

Typ

0

ns

µs

sec

WE# Hold Time

t_CP

CE# (CE1# or CE#2 in PL129J) Pulse Width

CE# (CE1# or CE#2 in PL129J) Pulse Width High

Programming Operation (Note 2)

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

35

20

40

25

t_EHEL

t_CPH

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

6

4

0.5

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

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555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device

4. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH

5. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings

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Table 32. CE1#/CE2# Timing (S29PL129J only)

Parameter

JEDEC

Std

t_CCR

Description

All Speed Options

Unit

CE1#/CE2# Recover Time (Note 1)

Min

0

ns

Notes:

1. This parameter is defined for CE1#/CE2# recover time for read/read, program/read, and read/program operations.

Program/program operation are not allowed and only a single program operation is allowed at one time.

CE1#

t_CCR

CE2#

Figure 24. Timing Diagram for Alternating Between CE1# and CE2# Control

Table 33. Erase And Programming Performance

Parameter

Typ (Note 1)

Max (Note 2)

Unit

sec

Comments

0.5

135

71

2

Sector Erase Time

PL127J/129J

PL064J

216

Excludes 00h programming

prior to erasure (Note 4)

113.6

62.4

Chip Erase Time

PL032J

39

Excludes system level

overhead (Note 5)

6

100

µs

Word Program Time

4

60

µs

Accelerated Word Program Time

PL127J/129J

50.4

25.2

12.6

200

50.4

25.2

sec

Chip Program Time

PL064J

PL032J

(Note 3)

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern. All values are subject to change.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles. All values are subject to change.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 21 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

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BGA Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

V_IN= 0

Typ

6.3

7.0

5.5

11

Max

7

Unit

pF

C_IN

C_OUT

C_IN2

C_IN3

Input Capacitance

Output Capacitance

V_OUT= 0

V_IN= 0

8

pF

Control Pin Capacitance

WP#/ACC Pin Capacitance

8

pF

V_IN= 0

12

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

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Physical Dimensions

VBG080—80-Ball Fine-pitch Ball Grid Array 8 x 11 mm Package

(PL127J)

0.05

(2X)

C

D1

D

A

e

8

7

6

5

4

3

2

1

e

7

SE

E1

E

M

L

K

J

H

G

F

E

D

C

B

A

A1 CORNER

INDEX MARK

10

PIN A1

CORNER

B

6

SD

NXφb

7

0.05

(2X)

C

φ 0.08

φ 0.15

M

C

C A

B

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.10

0.08

C

A2

A

C

A1

SEATING PLANE

NOTES:

PACKAGE

JEDEC

VBG 080

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

11.00 mm x 8.00 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

MAX

1.00

---

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

---

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.18

0.62

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

0.76

BODY THICKNESS

BODY SIZE

11.00 BSC.

8.00 BSC.

8.80 BSC.

5.60 BSC.

12

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

8

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

80

φb

0.33

---

0.43

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

8. NOT USED.

(A3-A6,B3-B6,L3-L6,M3-M6) DEPOPULATED SOLDER BALLS

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3329 \ 16-038.25b

March 2, 2005 S29PL-J_00_A7

S29PL-J

105

P r e l i m i n a r y

VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm package

(PL127J)

0.05

(2X)

C

D1

D

A

e

10

9

e

7

8

SE

7

6

E1

E

5

4

3

2

1

M

L

K

J

H

G

F

E

D

C

B

A

A1 CORNER

INDEX MARK

B

SD

7

6

0.05

(2X)

C

10

NXφb

φ 0.08

φ 0.15

M

C

TOP VIEW

C A

B

BOTTOM VIEW

0.10

C

A2

A

0.08

C

A1

SEATING PLANE

SIDE VIEW

NOTES:

PACKAGE

JEDEC

VBH 064

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

11.60 mm x 8.00 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

---

MAX

1.00

---

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.18

0.62

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

0.76

BODY THICKNESS

BODY SIZE

11.60 BSC.

8.00 BSC.

8.80 BSC.

7.20 BSC.

12

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

10

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

64

φb

0.33

---

0.43

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

(A2-9,B1-4,B7-10,C1-K1,

M2-9,C10-K10,L1-4,L7-10,

G5-6,F5-6)

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3330 \ 16-038.25b

106

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

VBK048—48-Ball Fine-pitch Ball Grid Array 8.15 x 6.15 mm

package (PL127J)

0.10 (4X)

D1

A

D

6

5

4

3

2

1

7

e

SE

E1

E

H

G

F

E

D

C

B

A

INDEX MARK

10

6

B

A1 CORNER

PIN A1

CORNER

7

φb

φ 0.08

φ 0.15

SD

M

C

TOP VIEW

C A B

BOTTOM VIEW

0.10

C

A2

A

SEATING PLANE

SIDE VIEW

0.08

C

A1

NOTES:

PACKAGE

JEDEC

VBK 048

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

8.15 mm x 6.15 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

MAX

1.00

---

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

---

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.18

0.62

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

8.15 BSC.

6.15 BSC.

5.60 BSC.

4.00 BSC.

8

0.76

BODY THICKNESS

BODY SIZE

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

6

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

48

φb

0.33

---

0.43

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

---

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3338 \ 16-038.25b

March 2, 2005 S29PL-J_00_A7

S29PL-J

107

P r e l i m i n a r y

VBU056—56-Ball Fine-pitch BGA 7 x 9mm package (PL064J and

PL032J)

D1

A

D

e

0.05

(2X)

C

8

7

6

SE

7

5

4

E

B

E1

3

e

2

1

H

G

F

E

D

C

B

A

A1 CORNER

INDEX MARK

6

10

NXφb

SD

7

φ 0.08

φ 0.15

M

C

0.05

(2X)

C

TOP VIEW

M

C A B

BOTTOM VIEW

0.10

C

A2

A

0.08

C

SEATING PLANE

A1

SIDE VIEW

NOTES:

PACKAGE

JEDEC

VBU 056

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

9.00 mm x 7.00 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

---

MAX

NOTE

OVERALL THICKNESS

BALL HEIGHT

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

1.00

---

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.17

0.62

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

0.76

BODY THICKNESS

BODY SIZE

9.00 BSC.

7.00 BSC.

5.60 BSC.

8

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

8

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

56

φb

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

A1,A8,D4,D5,E4,E5,H1,H8

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3440\ 16-038.25 \ 01.13.05

108

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

TS056—20 x 14 mm, 56-pin TSOP (PL127J)

A2

2

0.10 C

1

N

SEE DETAIL B

-A-

-B-

5

E

e

N

2

N

2

+1

5

A1

D1

4

C

D

SEATING

PLANE

B

A

0.08MM (0.0031")

M

C

A-B

6

S

B

b

7

SEE DETAIL A

WITH PLATING

c1

(c)

7

b1

BASE METAL

R

SECTION B-B

e/2

c

GAGE LINE

0.25MM (0.0098") BSC

0˚

-X-

X = A OR B

PARALLEL TO

SEATING PLANE

L

DETAIL A

DETAIL B

NOTES:

Package

TS 056

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

MO-142 (B) EC

Jedec

1

2

3

4

MIN

NOM MAX

1.20

Symbol

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

A

A1

A2

b1

b

c1

c

D

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

0.15

0.05

0.95

0.17

0.10

1.00

0.20

1.05

0.23

0.27

0.16

0.21

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT

HORIZONTAL SURFACE.

0.22

5

6

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15MM (.0059") PER SIDE.

19.80 20.00 20.20

18.30 18.40 18.50

13.90 14.00 14.10

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE

BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

D1

E

e

7

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

0.50 BASIC

L

0

R

N

0.50

0˚

0.60

3˚

0.70

5˚

8

9

LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

0.08

0.20

56

March 2, 2005 S29PL-J_00_A7

S29PL-J

109

P r e l i m i n a r y

Revision Summary

Revision A (January 29, 2004)

Initial release.

Revision A1 (February 12, 2004)

Software Features

Included backward compatibility with MBM29xx families.

General Description

48-ball BGA package is not supported and was removed.

Ordering Information

Model numbers for the 48-ball BGA configurations were removed.

64-Ball Fine Pitch BGA—MCP Compatible

An illustration was added to show the pin-out configuration.

Table 20

Added the description of 01h for address 4Fh and removed the 0004 data.

Table 34

Provided the time units of measure for the erase and programming

performances.

Revision A2 (February 17, 2004)

Table 21, “Memory Array Command Definitions”

Corrected typo in device ID.

Revision A3 (February 25, 2004)

Architectural Advantages

Added 3V V_IOfor PL064J and PL032J devices.

Ordering Information

Corrected the voltage rating, ball configuration, and physical dimensions for

model numbers 12 and 13.

Connection Diagrams

Removed the 64-ball, 8x9 mm diagram.

Operating Ranges

Clarified the supply voltages that apply to the PL127J/PL129J and all other PLxxxJ

products.

BGA Pin Capacitance

Added information applicable to the C_IN3symbol.

Package Drawings

Removed the 9x8 mm package drawing.

110

S29PL-J

S29PL-J_00_A7 March 2, 2005

P r e l i m i n a r y

Revision A4 (February 27, 2004)

Connection Diagrams

Added the 56-ball 7x9 mm pinout diagram.

Package Options

Updated to include the 8 x 6 mm, 48-ball Fine pitch BGA and 7 x 9 mm, 56-ball

Fine-pitch BGA options.

Physical Dimensions

Added the VBK048 package drawing.

Revision A5 (March 15, 2004)

Connection Diagrams

Changed name of "VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm pack-

age (PL127J)" section.

Revision A6 (August 30, 2004)

Global

Removed V_IO, added TSOP, fixed Secured Silicon DQ bits.

Product Selector Guide

Updated specs in this table.

Ordering Information

Updated the Model Number offerings.

Valid Combinations Table (128Mb)

Corrected the Package Markings for the 64-ball FBGA packages.

Added combinations for the TLC056 package on the PL064J and PL032J devices.

Valid Combinations for BGA Packages (128Mb)

Updated information in this table.

Package Options

Added the 7 x 9mm 56-ball package.

Connection Diagram

56-ball connection diagram

Erase/Programming Performance Table

Notes 1 and 2 corrected to reflect accurate temperature ranges and cycling.

Revision A7 (March 2, 2005)

Ordering Information

Updated the Model Number offerings

Valid Combinations table

Updated the Package Types information.

March 2, 2005 S29PL-J_00_A7

S29PL-J

111

P r e l i m i n a r y

Figure 1, “In-System Sector Protection/Sector Unprotection

Algorithms,” on page 61

Updated the illustration.

Program Suspend/Program Resume Commands

New section added. Made global changes to include program suspend/resume

commands.

Table 29 on page 94

Added Erase Suspend Latency.

Table 32 on page 103

Updated table and added a notes section.

Physical Dimensions

Added the VBU056 package.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-

tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other

abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development

by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement

of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the

use of the information in this document.

product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

112

S29PL-J

S29PL-J_00_A7 March 2, 2005


型号：	S29PL127J55BFI002
厂家：	CYPRESS
描述：	Flash Memory,
文件：	总114页 (文件大小：1040K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S29PL127J55BFI002 [CYPRESS]

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