S70FL01GSAGBHNC10 [CYPRESS]
Flash, 128MX8, PBGA24, BGA-24;
| 型号： | S70FL01GSAGBHNC10 |
| 厂家： | 
CYPRESS |
| 描述： | Flash, 128MX8, PBGA24, BGA-24 时钟 内存集成电路 |
| 文件： | 总18页 (文件大小：1891K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S70FL01GS
1 Gbit (128 Mbyte) 3.0V SPI Flash
Features
CMOS 3.0V Core
Security Features
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
One Time Program (OTP) array of 1024 bytes
Block Protection
– Status Register bits to control protection against program
or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
Cypress® 65 nm MirrorBit® Technology with Eclipse
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
Architecture
DDR
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
Temperature Range / Grade:
– AutoBoot – power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Extended (40 °C to +125 °C)
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock
systems
– Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles
Data Retention
– 16-lead SOIC (300 mils)
– BGA-24, 8 6 mm
– 5 5 ball (FAB024) footprint
– 20 Year Data Retention
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, refer to the discrete die datasheet provided in Table 1.
Table 1. Affected Documents/Related Documents
Document Title
Publication Number
S25FL512S 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Datasheet
001-98284
Cypress Semiconductor Corporation
Document Number: 001-98295 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 02, 2016
S70FL01GS
Contents
1.
2.
3.
4.
Block Diagram.............................................................. 3
10.2 Capacitance Characteristics ......................................... 11
Connection Diagrams.................................................. 4
Input/Output Summary................................................ 5
Device Operations ....................................................... 6
11. Ordering Information.................................................. 12
11.1 Valid Combinations — Standard................................... 13
11.2 Valid Combinations — Automotive Grade /
AEC-Q100 .................................................................... 13
4.1 Programming ................................................................. 6
4.2 Simultaneous Die Operation.......................................... 6
4.3 Sequential Reads........................................................... 6
4.4 Sector/Bulk Erase .......................................................... 6
4.5 Status Registers............................................................. 6
4.6 Configuration Register ................................................... 6
4.7 Bank Address Register .................................................. 6
4.8 Security and DDR Registers.......................................... 6
4.9 Block Protection............................................................. 6
12. Other Resources......................................................... 14
12.1 Cypress Flash Memory Roadmap ................................ 14
12.2 Links to Software .......................................................... 14
12.3 Links to Application Notes............................................. 14
13. SOIC 16 Physical Diagram ......................................... 15
13.1 SL3016 — 16-pin Wide Plastic Small
Outline Package (300-mil Body Width)......................... 15
14. FAB024 Physical Diagram.......................................... 16
5.
6.
7.
8.
9.
Read Identification (RDID)........................................... 7
RESET#......................................................................... 7
Versatile I/O Power Supply (VIO)................................. 7
DC Characteristics....................................................... 8
AC Test Conditions...................................................... 9
14.1 FAB024 — 24-Ball BGA (8 x 6 mm) Package .............. 16
15. Revision History.......................................................... 17
Sales, Solutions, and Legal Information ...........................18
Worldwide Sales and Design Support ............................18
Products .........................................................................18
PSoC® Solutions ...........................................................18
Cypress Developer Community ......................................18
Technical Support ..........................................................18
10. SDR AC Characteristics ............................................ 10
10.1 DDR AC Characteristics .............................................. 11
Document Number: 001-98295 Rev. *J
Page 2 of 18
S70FL01GS
1. Block Diagram
SI/IO0
WP#/IO2
SO/IO1
HOLD#/IO3
FL512S
Flash
Memory
VSS
VCC
SCK
CS#1
FL512S
Flash
Memory
CS#2
Document Number: 001-98295 Rev. *J
Page 3 of 18
S70FL01GS
2. Connection Diagrams
Figure 2.1 16-Pin Plastic Small Outline Package (SO)
16
15
14
SCK
1
2
3
HOLD#/IO3
VCC
SI/IO0
VIO/RFU
RESET#
DNU
13
12
4
5
NC
DNU
DNU
CS2#
6
11
DNU
VSS
CS1#
7
8
10
9
SO/IO1
WP#/IO2
Figure 2.2 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View
1
2
3
4
5
A
B
C
D
E
DNU
SCK
CS#
CS2# RESET# RFU
DNU
DNU
DNU
DNU
VSS
VCC
RFU
RFU WP#/IO2 RFU
SO/IO1 SI/IO0 HOLD#/IO3 DNU
DNU
DNU VIO/RFU DNU
Note:
1.
V
is not supported in the S70FL01GS device and is RFU. Refer to Section 7. for more details.
IO
Document Number: 001-98295 Rev. *J
Page 4 of 18
S70FL01GS
3. Input/Output Summary
Table 3.1 Signal List
Signal Name
Type
Description
Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used.
RESET#
Input
SCK
CS#
Input
Input
Input
Input
I/O
Serial Clock.
Chip Select.
CS1#
Chip Select. FL512S #1.
CS2#
Chip Select. FL512S #2.
SI / IO0
SO / IO1
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
I/O
Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up
resistor and may be left unconnected in the host system if not used for Quad commands.
WP# / IO2
I/O
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The
signal has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad commands.
HOLD# / IO3
I/O
VCC
VIO
Supply
Supply
Supply
Core Power Supply.
Versatile I/O Power Supply. Note: VIO is not supported in the S70FL01GS device. Refer to
Section 7. for more details.
VSS
Ground.
Not Connected. No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for routing
space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC
NC
Unused
must not have voltage levels higher than VCC
.
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use of the connector for a signal. It is recommended to not
use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.
RFU
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for connection
to any host system signal. Any DNU signal related function will be inactive when the signal is at
VIL. The signal has an internal pull-down resistor and may be left unconnected in the host
system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do
not connect any host system signal to this connection.
DNU
Reserved
Document Number: 001-98295 Rev. *J
Page 5 of 18
S70FL01GS
4. Device Operations
4.1
Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
4.2
Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
4.3
Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the user desires to
sequentially read across the two die, data must be read out of the first die via CS1# and then read out of the second die via CS2#.
4.4
Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via a single command is
not supported due to the nature of the dual die stack. A Bulk Erase command must be issued for each die.
4.5
Status Registers
Each Flash die of the dual die stack is managed by its own Status Registers. Reads and updates to the Status Registers must be
managed separately. It is recommended that Status Register control bit settings of each die are kept identical to maintain
consistency when switching between die.
4.6
Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the Configuration Register control bits
must be managed separately. It is recommended that Configuration Register control bit settings of each die are kept identical to
maintain consistency when switching between die.
4.7
Bank Address Register
It is recommended that the Bank Address Register bit settings of each die are kept identical to maintain consistency when switching
between die.
4.8
Security and DDR Registers
It is recommended that the bit settings for ASP Register, Password Register, PPB Lock Register, PPB Access Register, DYB
Access Register, and DDR Data Learning Register in each die are kept identical to maintain consistency when switching between
die.
4.9
Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and BPNV bits of each die must
be managed separately. By default, each die is configured to be protected starting at the top (highest address) of each array, but no
address range is protected. It is recommended that the Block Protection settings of each die are kept identical to maintain
consistency when switching between die. In addition, any update to the FREEZE bit must be managed separately for each die. If the
FREEZE bit is set to a logic 1, it cannot be cleared to a logic 0 until a power-on-reset is executed on each die that has the FREEZE
bit set to 1.
Document Number: 001-98295 Rev. *J
Page 6 of 18
S70FL01GS
5. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device
identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the FL01GS dual die stack will have identical
identification data as the FL512S die, with the exception of the CFI data at byte 27h, as shown in Table 5.1.
Table 5.1 Product Group CFI Device Geometry Definition
Byte
Data
Description
27h
1Bh
Device Size = 2N byte
6. RESET#
Note that the hardware RESET# input (pin 3 on the 16-pin SO package and ball A4 on the 5x5 BGA package) is bonded out and
active for the S70FL01GS device. For applications that do NOT require use of the RESET# pin, it is recommended to not use
RESET# for PCB routing channels that would cause the RESET# signal to be asserted Low (VIL). Doing so will cause the device to
reset to standby state. The RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not
used.
7. Versatile I/O Power Supply (VIO)
Note that the Versatile I/O (VIO) power supply (pin 14 on the 16-pin SO package and ball E4 on the 5x5 BGA package) is not
supported, and pin 14 and ball E4 are RFU (Reserved for Future Use) in the standard configuration of the S70FL01GS device.
Contact your local sales office to confirm availability with the VIO feature enabled.
Document Number: 001-98295 Rev. *J
Page 7 of 18
S70FL01GS
8. DC Characteristics
This section summarizes the DC Characteristics of the device.
Table 8.1 DC Characteristics
Symbol
VIL
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
Min
Typ (1)
Max
Unit
V
-0.5
0.2 x VCC
VCC + 0.4
0.15 x VCC
VIH
0.7 x VCC
V
VOL
VOH
ILI
IOL = 1.6 mA, VCC = VCC min
V
IOH = –0.1 mA
0.85 x VCC
V
Input Leakage Current VCC = VCC Max, VIN = VIH or VIL
Output Leakage Current VCC = VCC Max, VIN = VIH or VIL
±4
±4
µA
µA
ILO
Serial SDR @ 50 MHz
Serial SDR @ 133 MHz
Quad SDR @ 80 MHz
Quad SDR @ 104 MHz
Quad DDR @ 66 MHz
Outputs unconnected during read data
return (2)
18
36
50
61
75
Active Power Supply
Current (READ)
ICC1
mA
Active Power Supply
CS# = VCC
ICC2
ICC3
100
100
100
100
200
300
mA
mA
mA
mA
µA
Current (Page Program)
Active Power Supply
CS# = VCC
Current (WRR)
Active Power Supply
CS# = VCC
ICC4
Current (SE)
Active Power Supply
CS# = VCC
ICC5
Current (BE) (3)
RESET#, CS# = VCC; SI, SCK = VCC
Standby Current
ISB (Industrial)
70
70
or VSS, Industrial Temp
RESET#, CS# = VCC; SI, SCK = VCC
or VSS, Industrial Plus Temp
I
SB (Industrial Plus) Standby Current
µA
Notes:
1. Typical values are at T = 25°C and V = 3V.
AI
CC
2. Output switching current is not included.
3. Bulk Erase is on a per-die basis, not for the whole device.
Document Number: 001-98295 Rev. *J
Page 8 of 18
S70FL01GS
9. AC Test Conditions
Figure 9.1 Input, Output, and Timing Reference Levels
Input Levels
Output Levels
0.85 x VCC
VCC+ 0.4V
0.7 x VCC
Timing Reference Level
0.5 x VCC
0.2 x VCC
- 0.5V
0.15 x VCC
Figure 9.2 Test Setup
Device
Under
Test
C
L
Table 9.1 AC Measurement Conditions
Symbol
Parameter
Min
Max
Unit
30
15 (4)
CL
Load Capacitance
pF
Input Rise and Fall Times
Input Pulse Voltage
2.4
ns
V
0.2 x VCC to 0.8 VCC
0.5 VCC
Input Timing Ref Voltage
Output Timing Ref Voltage
V
0.5 VCC
V
Notes:
1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).
4. DDR Operation.
Document Number: 001-98295 Rev. *J
Page 9 of 18
S70FL01GS
10. SDR AC Characteristics
Table 10.1 SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V)
Symbol
FSCK, R
FSCK, C
Parameter
Min
DC
DC
Typ
Max
50
Unit
MHz
MHz
SCK Clock Frequency for READ and 4READ instructions
SCK Clock Frequency for single commands (4)
133
SCK Clock Frequency for the following dual and quad commands:
DOR, 4DOR, QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR
FSCK, C
DC
104
MHz
MHz
FSCK, QPP SCK Clock Frequency for the QPP, 4QPP commands
DC
1/ FSCK
45% PSCK
45% PSCK
0.1
80
PSCK
SCK Clock Period
Clock High Time (5)
Clock Low Time (5)
tWH, tCH
tWL, tCL
ns
ns
tCRT, tCLCH Clock Rise Time (slew rate)
tCFT, tCHCL Clock Fall Time (slew rate)
V/ns
V/ns
0.1
CS# High Time (Read Instructions)
tCS (7)
10
50
ns
CS# High Time (Program/Erase)
tCSS
tCSH
tSU
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
Data in Setup Time
3
3
3
2
ns
ns
ns
ns
3000 (6)
tHD
Data in Hold Time
8.0 (2)
7.65 (3)
6.5 (4)
tV
Clock Low to Output Valid
ns
tHO
tDIS
Output Hold Time
2
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Disable Time
0
tWPS
tWPH
tHLCH
tCHHH
tHHCH
tCHHL
tHZ
WP# Setup Time
20 (1)
8
WP# Hold Time
100 (1)
HOLD# Active Setup Time (relative to SCK)
HOLD# Active Hold Time (relative to SCK)
HOLD# Non-Active Setup Time (relative to SCK)
HOLD# Non-Active Hold Time (relative to SCK)
HOLD# Enable to Output Invalid
HOLD# Disable to Output Valid
3
3
3
3
tLZ
8
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Full V range (2.7 - 3.6V) and CL = 30 pF.
CC
3. Regulated V range (3.0 - 3.6V) and CL = 30 pF.
CC
4. Regulated V range (3.0 - 3.6V) and CL = 15 pF.
CC
5. ±10% duty cycle is supported for frequencies
50 MHz.
6. Maximum value only applies during Program/Erase Suspend/Resume commands.
7. When switching between die, a minimum time of t must be kept between the rising edge of one chip select and the falling edge of the other for operations and data
CS
to be valid.
Document Number: 001-98295 Rev. *J
Page 10 of 18
S70FL01GS
10.1 DDR AC Characteristics
Table 10.2 DDR AC Characteristics 66 MHz Operation
Symbol
FSCK, R
PSCK, R
tWH, tCH
tWL, tCL
tCS
Parameter
SCK Clock Frequency for DDR READ instruction
SCK Clock Period for DDR READ instruction
Clock High Time
Min
Typ
Max
66
Unit
MHz
ns
DC
15
45% PSCK
ns
Clock Low Time
45% PSCK
ns
CS# High Time (Read Instructions)
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
IO in Setup Time
10
3
ns
tCSS
ns
tCSH
3
3000 (2)
ns
ns
ns
ns
ns
ns
ns
ps
tSU
2
tHD
IO in Hold Time
2
tV
Clock Low to Output Valid
0
6.5 (1)
tHO
Output Hold Time
1.5
0
8
tDIS
Output Disable Time
tLZ
Clock to Output Low Impedance
First IO to last IO data valid time
8
tIO_skew
600
Notes:
1. Regulated V range (3.0 - 3.6V) and CL =15 pF.
CC
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
10.2 Capacitance Characteristics
Table 10.3 Capacitance
Parameter
Test Conditions
1 MHz
Min
Max
16
Unit
pF
CIN
Input Capacitance (applies to SCK, CS#1, CS#2, RESET#)
Output Capacitance (applies to All I/O)
COUT
1 MHz
16
pF
Note:
1. For more information on capacitance, please consult the IBIS models.
Document Number: 001-98295 Rev. *J
Page 11 of 18
S70FL01GS
11. Ordering Information
The ordering part number is formed by a valid combination of the following:
S70FL
01G
S
AG
M
F
I
0
1
1
Packing Type (Note 1)
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Sector Type)
1 = Uniform 256-kB sectors
Model Number
(Latency Type, Package Details, RESET# support)
0 = EHPLC, SO footprint
C = EHPLC, 5 x 5 ball BGA footprint with RESET#
Temperature Range / Grade
I = Industrial (-40°C to + 85°C)
V = Industrial Plus (-40°C to +105°C)
N = Extended (-40°C to +125°C)
A = Automotive, AEC-Q100 Grade 3 (-40°C to +85°C)
B = Automotive, AEC-Q100 Grade 2 (-40°C to +105°C)
M = Automotive, AEC-Q100 Grade 1(-40°C to +125°C)
Package Materials
F = Lead (Pb)-free
H = Low-Halogen, Lead (Pb)-free
Package Type
B = 24-ball BGA 8 x 6 mm package, 1.00 mm pitch
M = 16-pin SO package
Speed
AG = 133 MHz
DP = 66 MHz DDR
DS = 80 MHz DDR
Device Technology
S = 65 nm MirrorBit Process Technology
Density
01G = 1 Gbit
Device Family
S70FL
Cypress Stacked Memory 3.0V-Only, Serial Peripheral Interface (SPI) Flash Memory
Notes:
1. EHPLC = Enhanced High Performance Latency Code table.
2. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer.
Document Number: 001-98295 Rev. *J
Page 12 of 18
S70FL01GS
11.1 Valid Combinations — Standard
Table 11.1 lists the valid combinations configurations planned to be supported in volume for this device.
Table 11.1 S70FL01GS Valid Combinations — Standard
S70FL01GS Valid Combinations
Base Ordering
Part Number
Speed
Option
Package and
Temperature Number Packing Type
Model
Package Marking (1)
AG
DP
AG
DP
FL01GS + A + (temp) + F + (Model Number)
FL01GS + D + (temp) + F + (Model Number)
FL01GS + A + (temp) + H + (Model Number)
FL01GS + D + (temp) + H + (Model Number)
MFI, MFV,
01
0, 1, 3
0, 3
MFN
S70FL01GS
BHI, BHV,
BHN
C1
Note:
1. Package Marking omits the leading “S70” and package type.
11.2 Valid Combinations — Automotive Grade / AEC-Q100
Table 11.2 lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table
will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific
combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with
ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Table 11.2 S70FL01GS Valid Combinations — Automotive Grade / AEC-Q100
S70FL01GS Valid Combinations
Base Ordering
Part Number
Speed
Option
Package and
Temperature Number Packing Type
Model
Package Marking (1)
AG
DP
AG
DP
FL01GS + A + (temp) + F + (Model Number)
FL01GS + D + (temp) + F + (Model Number)
FL01GS + A + (temp) + H + (Model Number)
FL01GS + D + (temp) + H + (Model Number)
MFA, MFB,
01
0, 1, 3
0, 3
MFM
S70FL01GS
BHA, BHB,
BHM
C1
Note:
1. Package Marking omits the leading “S70” and package type.
Document Number: 001-98295 Rev. *J
Page 13 of 18
S70FL01GS
12. Other Resources
12.1 Cypress Flash Memory Roadmap
http://www.cypress.com/Flash-Roadmap
12.2 Links to Software
http://www.cypress.com/software-and-drivers-cypress-flash-memory
12.3 Links to Application Notes
http://www.cypress.com/cypressappnotes
Document Number: 001-98295 Rev. *J
Page 14 of 18
S70FL01GS
13. SOIC 16 Physical Diagram
13.1
SL3016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width)
A-B
C
0.20
0.10
C
D
2X
0.33
C
0.25
0.10
M
C A-B D
C
0.10
C
DIMENSIONS
NOTES:
SYMBOL
MIN.
NOM.
MAX.
2.65
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
A
A1
A2
b
2.35
0.10
2.05
-
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
-
0.30
2.55
0.51
0.48
-
0.31
0.27
0.20
0.20
-
b1
c
-
0.33
0.30
-
-
c1
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
D
E
10.30 BSC
10.30 BSC
7.50 BSC
E1
e
1.27 BSC
-
L
1.27
0.40
L1
L2
N
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
1.40 REF
0.25 BSC
16
h
0.25
0°
-
-
-
-
0.75
8°
0
0 1
0 2
5°
15°
-
0°
CYPRESS
Company Confidential
TITLE
PACKAGE OUTLINE, 16 LEAD SOIC
10.30X7.50X2.65 MM SO3016
DRAWN BY
KOTA
DATE
THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS
SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS
MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.
SPEC NO.
REV
**
OF
18-JUL-16
PACKAGE
CODE(S)
002-15547
SCALE :
TO FIT
SO3016
APPROVED BY
BESY
DATE
18-JUL-16
SHEET
1
2
Document Number: 001-98295 Rev. *J
Page 15 of 18
S70FL01GS
14. FAB024 Physical Diagram
14.1 FAB024 — 24-Ball BGA (8 x 6 mm) Package
NOTES:
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
1.
2.
3.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
A
A1
D
-
-
-
1.20
-
0.20
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
8.00 BSC
4.
5.
e REPRESENTS THE SOLDER BALL GRID PITCH.
E
6.00 BSC
4.00 BSC
4.00 BSC
5
D1
E1
MD
ME
N
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
5
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
PARALLEL TO DATUM C.
24
0.40
b
0.35
0.45
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
eE
eD
SD
SE
1.00 BSC
1.00 BSC
0.00 BSC
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
"SE" = eE/2.
8.
9.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
CYPRESS
Company Confidential
TITLE
PACKAGE OUTLINE, 24 BALL FBGA
8.0X6.0X1.2 MM FAB024
DRAWN BY
KOTA
DATE
THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS
SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS
MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.
SPEC NO.
REV
**
OF
18-JUL-16
PACKAGE
CODE(S)
002-15534
SCALE :
TO FIT
FAB024
APPROVED BY
BESY
DATE
18-JUL-16
SHEET
1
2
Document Number: 001-98295 Rev. *J
Page 16 of 18
S70FL01GS
15. Revision History
Document History Page
Document Title: S70FL01GS, 1 Gbit (128 Mbyte) 3.0V SPI Flash
Document Number: 001-98295
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
**
BWHA
11/06/2012 Initial release
Global: Datasheet designation updated from Advance Information to Preliminary
04/25/2013 DC Characteristics: DC Characteristics table: changed Max value of ILI, ILO,
ICC1, and ISB
*A
*B
BWHA
BWHA
SOIC 16 Physical Diagram: Updated package nomenclature from S03016 to
05/16/2013
SL3016
Valid Combinations: Valid Combinations table: added MFV
08/22/2013
*C
*D
BWHA
BWHA
DC Characteristics: DC Characteristics table: added ISB (Automotive)
11/08/2013 Global: Datasheet designation updated from Preliminary to Full Production
Features: Packages (all Pb-free): added BGA-24, 8 x 6 mm
Connections Diagrams: Added figure: 24-Ball BGA, 5 x 5 Ball Footprint (FAB024),
Top View
Ordering Information: Added options to: Model Number, Package Materials,
Package Type, and Speed
Valid Combinations: Added option to S70FL01GS Valid Combinations Table
SDR AC Characteristics: SDR AC Characteristics (Single Die Package, VCC =
*E
BWHA
03/19/2014
2.7V to 3.6V) table: updated tv Min
DDR AC Characteristics:Updated DDR AC Characteristics 66 MHz Operation
table
Capacitance Characteristics: Capacitance table: updated Max values and
removed note
*F
BWHA
BWHA
11/07/2014 Valid Combinations: Added DP Speed Option for BGA 5x5 package
04/21/2015 Valid Combinations: Added BHV option
*G
Updated to Cypress template.
*H
*I
4871631
5123878
BWHA
BWHA
08/24/2015 Changed Automotive Temperature Range to Industrial Plus Temperature Range
in Features and Section 4.
02/03/2016 Updated General Description.
Updated Features on page 1: Added Extended and Automotive Grade
temperatures.
Updated DDR AC Characteristics 66 MHz Operation on page 11 table: Corrected
tHO Min value, tCSH and tSU Max value.
*J
5536564
BWHA
12/02/2016
Ordering Information on page 12: Added Extended and Automotive Grade.
Added Other Resources on page 14.
Document Number: 001-98295 Rev. *J
Page 17 of 18
S70FL01GS
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Lighting & Power Control
Memory
cypress.com/support
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-98295 Rev. *J
Revised December 02, 2016
Page 18 of 18
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