S70FL01GSAGMFI011 [SPANSION]
Flash, 128MX8, PDSO16;
| 型号： | S70FL01GSAGMFI011 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 128MX8, PDSO16 时钟 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S70FL01GS
1 Gbit (128 Mbyte) MirrorBit® Flash Non-Volatile Memory
CMOS 3.0 Volt Core
Serial Peripheral Interface with Multi-I/O
S70FL01GS Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S70FL01GS_00
Revision 06
Issue Date March 19, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V range. Changes may also include those needed to clarify a
IO
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S70FL01GS
S70FL01GS_00_06 March 19, 2014
S70FL01GS
1 Gbit (128 Mbyte) MirrorBit® Flash Non-Volatile Memory
CMOS 3.0 Volt Core
Serial Peripheral Interface with Multi-I/O
Data Sheet
Features
Serial Peripheral Interface (SPI)
Security Features
One Time Program (OTP) array of 1024 bytes
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
Block Protection
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
– Individual sector protection controlled by boot code or password
READ Commands
Spansion 65 nm MirrorBit Technology with Eclipse™
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
– AutoBoot – power up or reset and execute a Normal or Quad read
command automatically at a preselected address
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
– Common Flash Interface (CFI) data for configuration information
Temperature Range:
Programming (1.5 Mbytes/s)
– Industrial (-40°C to +85°C)
– 512-byte Page Programming buffer
– Automotive In-Cabin (-40°C to +105°C)
– Quad-Input Page Programming (QPP) for slow clock systems
Packages (all Pb-free)
– 16-lead SOIC (300 mils)
– BGA-24, 8 x 6 mm
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 5 x 5 ball (FAB024) footprint
– 100,000 Program-Erase Cycles on any sector typical
Data Retention
– 20 Year Data Retention typical
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, please refer to the discrete die data sheet:
Document
Publication Identification Number (PID)
S25FL512S Data Sheet
S25FL512S_00
Publication Number S70FL01GS_00
Revision 06
Issue Date March 19, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-
duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
D a t a S h e e t
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.
2.
3.
4.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/Output Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Simultaneous Die Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sector/Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bank Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ASP Register, Password Register, PPB Lock Register, PPB Access
Register, DYB Access Register, DDR Data Learning Registers . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.9
6.
7.
8.
9.
Read Identification (RDID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Versatile I/O Power Supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IO
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10. AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11. SDR AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
11.1 DDR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11.2 Capacitance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
12. SOIC 16 Physical Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12.1 SL3016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . 17
13. FAB024 Physical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13.1 FAB024 — 24-Ball BGA (8 x 6 mm) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
S70FL01GS
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D a t a S h e e t
Figures
Figure 2.1
Figure 2.2
16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10.1 Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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D a t a S h e e t
Tables
Table 3.1
Table 4.1
Table 6.1
Table 9.1
Table 10.1
Table 11.1
Table 11.2
Table 11.3
Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
S70FL01GS Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Product Group CFI Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
SDR AC Characteristics (Single Die Package, V = 2.7V to 3.6V) . . . . . . . . . . . . . . . . . . .15
CC
DDR AC Characteristics 66 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6
S70FL01GS
S70FL01GS_00_06 March 19, 2014
D a t a S h e e t
1. Block Diagram
SI/IO0
WP#/IO2
SO/IO1
HOLD#/IO3
FL512S
Flash
Memory
VSS
SCK
CS#1
VCC
FL512S
Flash
Memory
CS#2
March 19, 2014 S70FL01GS_00_06
S70FL01GS
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D a t a S h e e t
2. Connection Diagrams
Figure 2.1 16-Pin Plastic Small Outline Package (SO)
16
15
14
SCK
1
2
3
HOLD#/IO3
VCC
SI/IO0
VIO/RFU
RESET#
DNU
13
4
5
NC
12
DNU
DNU
CS2#
6
11
DNU
VSS
CS1#
7
10
9
SO/IO1
8
WP#/IO2
Figure 2.2 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View
1
2
3
4
5
A
B
C
D
E
DNU
SCK
CS#
CS2# RESET# RFU
DNU
DNU
DNU
DNU
VSS
VCC
RFU
RFU WP#/IO2 RFU
SO/IO1 SI/IO0 HOLD#/IO3 DNU
DNU
DNU VIO/RFU DNU
Note:
1. VIO is not supported in the S70FL01GS device and is RFU. Refer to Section 8. for more details.
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D a t a S h e e t
3. Input/Output Summary
Table 3.1 Signal List
Description
Signal Name
Type
Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the
host system if not used.
RESET#
Input
SCK
CS#
Input
Input
I/O
Serial Clock.
Chip Select.
SI / IO0
SO / IO1
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
I/O
Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal
pull-up resistor and may be left unconnected in the host system if not used for Quad
commands.
WP# / IO2
I/O
I/O
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode.
The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used for Quad commands.
HOLD# / IO3
VCC
VIO
Supply
Supply
Supply
Core Power Supply.
Versatile I/O Power Supply. Note: VIO is not supported in the S70FL01GS device. Refer
to Section 8. for more details.
VSS
Ground.
Not Connected. No device internal signal is connected to the package connector nor is
there any future plan to use the connector for a signal. The connection may safely be
used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal
NC
Unused
connected to an NC must not have voltage levels higher than VCC
.
Reserved for Future Use. No device internal signal is currently connected to the
package connector but there is potential future use of the connector for a signal. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may
take advantage of future enhanced features in compatible footprint devices.
RFU
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Spansion for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive
when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for
PCB signal routing channels. Do not connect any host system signal to this connection.
DNU
Reserved
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D a t a S h e e t
4. Ordering Information
The ordering part number is formed by a valid combination of the following:
S70FL
01G
S
AG
M
F
I
0
1
1
Packing Type (Note 1)
0
1
3
=
=
=
Tray
Tube
13” Tape and Reel
Model Number (Sector Type)
Uniform 256-kB sectors
1
=
Model Number
(Latency Type, Package Details, RESET# support)
0
=
EHPLC, SO footprint
C
=
EHPLC, 5 x 5 ball BGA footprint with RESET#
Temperature Range
I
=
Industrial (-40°C to + 85°C)
V
=
Automotive In-Cabin (-40°C to +105°C)
Package Materials
F
=
Lead (Pb)-free
H
=
Low-Halogen, Lead (Pb)-free
Package Type
B
M
=
=
24-ball BGA 8 x 6 mm package, 1.00 mm pitch
16-pin SO package
Speed
AG
DP
DS
=
=
=
133 MHz
66 MHz DDR
80 MHz DDR
Device Technology
S
=
0.065 µm MirrorBit Process Technology
1 Gbit
Density
01G
=
Device Family
S70FL
Spansion Stacked Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory
Notes:
1. EHPLC = Enhanced High Performance Latency Code table.
2. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer.
4.1
Valid Combinations
Table 4.1 lists the valid combinations configurations planned to be supported in volume for this device.
Table 4.1 S70FL01GS Valid Combinations Table
S70FL01GS Valid Combinations
Base Ordering
Part Number
Speed Packageand Model
Option Temperature Number Packing Type
Package Marking (1)
AG
FL01GS + A + (temp) + F + (Model Number)
FL01GS + D + (temp) + F + (Model Number)
FL01GS + A + (temp) + H + (Model Number)
MFI, MFV
BHI
01
0, 1, 3
0, 3
S70FL01GS
DP
AG
C1
Note:
1. Package Marking omits the leading “S70” and package type.
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D a t a S h e e t
5. Device Operations
5.1
5.2
5.3
Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the
user desires to sequentially read across the two die, data must be read out of the first die via CS1# and then
read out of the second die via CS2#.
5.4
5.5
5.6
Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via
a single command is not supported due to the nature of the dual die stack. A Bulk Erase command must be
issued for each die.
Status Registers
Each Flash die of the dual die stack is managed by its own Status Registers. Reads and updates to the
Status Registers must be managed separately. It is recommended that Status Register control bit settings of
each die are kept identical to maintain consistency when switching between die.
Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the
Configuration Register control bits must be managed separately. It is recommended that Configuration
Register control bit settings of each die are kept identical to maintain consistency when switching between
die.
5.7
5.8
Bank Address Register
It is recommended that the Bank Address Register bit settings of each die are kept identical to maintain
consistency when switching between die.
ASP Register, Password Register, PPB Lock Register, PPB Access
Register, DYB Access Register, DDR Data Learning Registers
It is recommended that the bit settings for all of the above registers in each die are kept identical to maintain
consistency when switching between die.
5.9
Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and
BPNV bits of each die must be managed separately. By default, each die is configured to be protected
starting at the top (highest address) of each array, but no address range is protected. It is recommended that
the Block Protection settings of each die are kept identical to maintain consistency when switching between
die. In addition, any update to the FREEZE bit must be managed separately for each die. If the FREEZE bit is
set to a logic 1, it cannot be cleared to a logic 0 until a power-on-reset is executed on each die that has the
FREEZE bit set to 1.
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D a t a S h e e t
6. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the
two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the
FL01GS dual die stack will have identical identification data as the FL512S die, with the exception of the CFI
data at byte 27h, as shown in Table 6.1.
Table 6.1 Product Group CFI Device Geometry Definition
Byte
Data
Description
27h
1Bh
Device Size = 2N byte
7. RESET#
Note that the hardware RESET# input (pin 3 on the 16-pin SO package and ball A4 on the 5x5 BGA package)
is bonded out and active for the S70FL01GS device. For applications that do NOT require use of the RESET#
pin, it is recommended to not use RESET# for PCB routing channels that would cause the RESET# signal to
be asserted Low (V ). Doing so will cause the device to reset to standby state. The RESET# signal has an
IL
internal pull-up resistor and may be left unconnected in the host system if not used.
8. Versatile I/O Power Supply (V )
IO
Note that the Versatile I/O (V ) power supply (pin 14 on the 16-pin SO package and ball E4 on the 5x5 BGA
IO
package) is not supported, and pin 14 and ball E4 are RFU (Reserved for Future Use) in the standard
configuration of the S70FL01GS device. Contact your local sales office to confirm availability with the V
feature enabled.
IO
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D a t a S h e e t
9. DC Characteristics
This section summarizes the DC Characteristics of the device.
Table 9.1 DC Characteristics
Symbol
VIL
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
Min
-0.5
Typ (1)
Max
Unit
V
0.2 x VCC
VCC + 0.4
0.15 x VCC
VIH
0.7 x VCC
V
VOL
VOH
ILI
IOL = 1.6 mA, VCC = VCC min
IOH = –0.1 mA
V
0.85 x VCC
V
Input Leakage Current VCC = VCC Max, VIN = VIH or VIL
4
4
µA
Output Leakage
ILO
VCC = VCC Max, VIN = VIH or VIL
Current
µA
Serial SDR @ 50 MHz
Serial SDR @ 133 MHz
Quad SDR @ 80 MHz
Quad SDR @ 104 MHz
Quad DDR @ 66 MHz
18
36
50
61
75
Active Power Supply
Current (READ)
ICC1
mA
Outputs unconnected during read data
return (2)
Active Power Supply
ICC2
Current (Page
Program)
CS# = VCC
100
mA
Active Power Supply
Current (WRR)
ICC3
ICC4
CS# = VCC
CS# = VCC
CS# = VCC
100
100
100
200
300
mA
mA
mA
µA
Active Power Supply
Current (SE)
Active Power Supply
Current (BE) (3)
ICC5
RESET#, CS# = VCC; SI, SCK = VCC or
VSS, Industrial Temp
I
SB (Industrial)
Standby Current
70
70
RESET#, CS# = VCC; SI, SCK = VCC or
VSS, Automotive Temp
I
SB (Automotive) Standby Current
µA
Notes:
1. Typical values are at TAI = 25°C and VCC = 3V.
2. Output switching current is not included.
3. Bulk Erase is on a per-die basis, not for the whole device.
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10. AC Test Conditions
Figure 10.1 Input, Output, and Timing Reference Levels
Input Levels
Output Levels
0.85 x V
V
+ 0.4V
CC
CC
0.7 x V
0.5 x V
0.2 x V
CC
CC
CC
Timing Reference Level
0.15 x V
CC
- 0.5V
Figure 10.2 Test Setup
Device
Under
Test
C
L
Table 10.1 AC Measurement Conditions
Symbol
Parameter
Min
Max
Unit
30
CL
Load Capacitance
pF
15 (4)
Input Rise and Fall Times
Input Pulse Voltage
2.4
ns
V
0.2 x VCC to 0.8 VCC
0.5 VCC
Input Timing Ref Voltage
V
Output Timing Ref
Voltage
0.5 VCC
V
Notes:
1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).
4. DDR Operation.
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11. SDR AC Characteristics
Table 11.1 SDR AC Characteristics (Single Die Package, V = 2.7V to 3.6V)
CC
Symbol
FSCK, R
FSCK, C
Parameter
Min
DC
DC
Typ
Max
50
Unit
MHz
MHz
SCK Clock Frequency for READ and 4READ
instructions
SCK Clock Frequency for single commands (4)
133
SCK Clock Frequency for the following dual and
quad commands: DOR, 4DOR, QOR, 4QOR, DIOR,
4DIOR, QIOR, 4QIOR
FSCK, C
DC
104
MHz
MHz
FSCK, QPP
PSCK
tWH, tCH
tWL, tCL
SCK Clock Frequency for the QPP, 4QPP commands
SCK Clock Period
DC
1/ FSCK
45% PSCK
45% PSCK
0.1
80
∞
Clock High Time (5)
ns
ns
Clock Low Time (5)
tCRT, tCLCH
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
V/ns
V/ns
t
CFT, tCHCL
0.1
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50
tCS (7)
ns
tCSS
tCSH
tSU
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
Data in Setup Time
3
3
3
2
ns
ns
ns
ns
3000 (6)
tHD
Data in Hold Time
8.0 (2)
7.65 (3)
6.5 (4)
tV
Clock Low to Output Valid
ns
tHO
Output Hold Time
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDIS
Output Disable Time
0
8
tWPS
tWPH
WP# Setup Time
20 (1)
WP# Hold Time
100 (1)
tHLCH
tCHHH
tHHCH
tCHHL
tHZ
HOLD# Active Setup Time (relative to SCK)
HOLD# Active Hold Time (relative to SCK)
HOLD# Non-Active Setup Time (relative to SCK)
HOLD# Non-Active Hold Time (relative to SCK)
HOLD# Enable to Output Invalid
HOLD# Disable to Output Valid
3
3
3
3
8
8
tLZ
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Full VCC range (2.7 - 3.6V) and CL = 30 pF.
3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF.
4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF.
5. 10% duty cycle is supported for frequencies ≤ 50 MHz.
6. Maximum value only applies during Program/Erase Suspend/Resume commands.
7. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the
other for operations and data to be valid.
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11.1 DDR AC Characteristics
Table 11.2 DDR AC Characteristics 66 MHz Operation
Symbol
Parameter
Min
Typ
Max
Unit
FSCK, R
SCK Clock Frequency for DDR READ instruction
DC
66
MHz
PSCK, R
tWH, tCH
WL, tCL
tCS
SCK Clock Period for DDR READ instruction
Clock High Time
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
∞
45% PSCK
t
Clock Low Time
45% PSCK
CS# High Time (Read Instructions)
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
IO in Setup Time
10
3
tCSS
tCSH
tSU
3
2
3000 (2)
6.5 (1)
tHD
IO in Hold Time
2
tV
Clock Low to Output Valid
Output Hold Time
0
tHO
tDIS
tLZ
0
Output Disable Time
8
8
Clock to Output Low Impedance
First IO to last IO data valid time
0
tIO_skew
600
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
11.2 Capacitance Characteristics
Table 11.3 Capacitance
Parameter
Test Conditions
1 MHz
Min
Max
Unit
pF
CIN
Input Capacitance (applies to SCK, CS#1, CS#2, RESET#)
Output Capacitance (applies to All I/O)
16
16
COUT
1 MHz
pF
Note:
1. For more information on capacitance, please consult the IBIS models.
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12. SOIC 16 Physical Diagram
12.1
SL3016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width)
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13. FAB024 Physical Diagram
13.1 FAB024 — 24-Ball BGA (8 x 6 mm) Package
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14. Revision History
Section
Description
Revision 01 (November 6, 2012)
Initial release
Revision 02 (April 25, 2013)
Global
Data sheet designation updated from Advance Information to Preliminary
DC Characteristics table: changed Max value of ILI, ILO, ICC1, and ISB
DC Characteristics
Revision 03 (May 16, 2013)
SOIC 16 Physical Diagram
Revision 04 (August 22, 2013)
Valid Combinations
Updated package nomenclature from S03016 to SL3016
Valid Combinations table: added MFV
DC Characteristics
DC Characteristics table: added ISB (Automotive)
Revision 05 (November 8, 2013)
Global
Data sheet designation updated from Preliminary to Full Production
Revision 06 (March 19, 2014)
Features
Packages (all Pb-free): added BGA-24, 8 x 6 mm
Connections Diagrams
Ordering Information
Valid Combinations
Added figure: 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View
Added options to: Model Number, Package Materials, Package Type, and Speed
Added option to S70FL01GS Valid Combinations Table
SDR AC Characteristics
DDR AC Characteristics
Capacitance Characteristics
SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V) table: updated tv Min
Updated DDR AC Characteristics 66 MHz Operation table
Capacitance table: updated Max values and removed note
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
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20
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S70FL01GS_00_06 March 19, 2014
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