S71VS256RD0AHK4L0 [CYPRESS]
Memory Circuit, 256MX1, CMOS, PBGA56, VFRBGA-56;
| 型号： | S71VS256RD0AHK4L0 |
| 厂家： | 
CYPRESS |
| 描述： | Memory Circuit, 256MX1, CMOS, PBGA56, VFRBGA-56 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
“Spansion, Inc.” and “Cypress Semiconductor Corp.” have merged together to deliver high-performance, high-quality solutions at
the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive
consumer and mobile devices. The new company “Cypress Semiconductor Corp.” will continue to offer “Spansion, Inc.” products
to new and existing customers.
CONTINUITY OF SPECIFICATIONS
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future revisions
will occur when appropriate, and changes will be noted in a document history page.
CONTINUITY OF ORDERING PART NUMBERS
Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in
this document.
FOR MORE INFORMATION
Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products
and services.
OUR CUSTOMERS
Cypress is for true innovators – in companies both large and small.
Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that revolutionize
their industries or create new industries with products and solutions that nobody ever thought of before.
ABOUT CYPRESS
Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative automotive,
industrial, home automation and appliances, consumer electronics and medical products. Cypress’s programmable systems-on-
chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance
memories help engineers design differentiated products and get them to market first.
Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators
and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to
www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 002-00377 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 13, 2017
S71VS/XS-R
MirrorBit® 1.8 V Simultaneous Read/Write
Burst Mode Multiplexed Flash and Burst
Features
Power supply voltage of 1.7V to 1.95V
MCP BGA Packages
– 52 ball, 6.0 x 5.0 mm, 0.5 mm ball pitch
– 56 ball, 7.7 x 6.2 mm, 0.5 mm ball pitch
– 56 ball, 9.2 x 8.0 mm, 0.5 mm ball pitch
Operating Temperature
Flash / pSRAM Burst Speed: 108 MHz, 104 MHz, 83 MHz
– Wireless, –25 °C to +85 °C
– Industrial, –40 °C to +85 °C
General Description
The S71VS-R Series is a product line of stacked Multi-Chip Package (MCP) memory solutions and consists of the following items:
One or more S29VS-R Flash memory die
One or more pSRAM
The products covered by this document are listed in the table below. For details about their specifications, please refer to their
individual data sheet for further details.
Flash Density
64 Mb
pSRAM Density
32 Mb
Product
S71VS064RB0
S71VS128RB0
S71VS128RC0
S71VS256RC0
S71VS256RD0
128 Mb
32 Mb
128 Mb
64 Mb
256 Mb
64 Mb
256 Mb
128 Mb
For detailed specifications, please refer to the individual data sheets:
Document
Cypress Document Number
S29VS256R, S29VS128R datasheet
S29VS064R datasheet
002-00833
002-00949
32 Mb CellularRAM Address/Data multiplexed
32 Mb CellularRAM Address/Data multiplexed
64 Mb CellularRAM Address/Data multiplexed
128 Mb CellularRAM Address/Data multiplexed
128 Mb CellularRAM Address/Data multiplexed
SWM032D108M1R
SWM032D108M3R
SWM064D108M1R
SWM128D108M1R
SWM128D108M3R
Cypress Semiconductor Corporation
Document Number: 002-00377 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Monday, November 13, 2017
S71VS/XS-R
1. Ordering Information
The order number is formed by a valid combinations of the following:
S71VS
256
R
C
0
AH
K
4L
0
Packing Type
0
3
= Tray
= 13-inch Tape and Reel
Model Number
See Valid Combinations table below
Package Modifier
T
K
= 6.0 x 5.0, 52-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
7.7 x 6.2, 56-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
=
Package Type
AH = Very Thin Fine-Pitch Ball Grid Array (VFRBGA) — 1.0 mm max height with
0.5 mm pitch; Lead (Pb)-free Package; Low-Halogen
Chip Contents
0
= No content (default)
pSRAM Density
B
C
D
= 32 Mb
= 64 Mb
= 128 Mb
Process Technology
= 65 nm MirrorBit Technology
R
Flash Density
256 = 256 Mb
128 = 128 Mb
64 = 64 Mb
Product Family
S71VS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode
Address and Data Multiplexed (ADM) Flash Memory + pSRAM
Document Number: 002-00377 Rev. *S
Page 3 of 18
S71VS/XS-R
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Base
Flash /
pSRAM
Speed
Model
Number
Packing
Type
Flash
Boot
Temperature
Range
Pinout and
Package Notes
Ordering Part Package
Number
pSRAM Type
3L
Top
Pinout: S71VS-R
52-ball Package:
RLG052
BL
Bottom
SWM032D108M1R
Wireless
Industrial
4L
CL
0M
8M
3M
Top
Bottom
Top
Pinout: S71VS-R
108 MHz 52-ball Package:
RSE052
S71VS064RB0
AHT
Bottom
Top
SWM032D108M3R
SWM032D108M1R
Pinout: S71VS-R
52-ball Package:
RLG052
BM
3L
Bottom
Top
Pinout: S71VS-R
56-ball Package:
BL
4L
CL
4L
Bottom
Top
RLA056
S71VS128RB0
AHK
108 MHz
Pinout: S71VS-R
56-ball Package:
RSD056
0, 3
Bottom
Top
Pinout: S71VS-R
56-ball
S71VS128RC0
S71VS256RC0
AHK
AHK
SWM064D108M1R
SWM064D108M1R
108 MHz
CL
Bottom
Package: RSD056
4L
Top
Pinout: S71VS-R
108 MHz 56-ball Package:
RLA056
Wireless
CL
Bottom
3L
BL
4L
Top
Bottom
Top
108 MHz
Pinout: S71VS-R
56-ball Package:
RSD056
SWM128D108M1R
SWM128D108M3R
S71VS256RD0
AHK
CL
3C
BC
3M
Bottom
Top
83 MHz
Bottom
Top
Industrial
108 MHz
Note:
If a choice exists, Spansion recommends Top Boot.
Document Number: 002-00377 Rev. *S
Page 4 of 18
S71VS/XS-R
2. Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions (Sheet 1 of 2)
Symbol
Description
Flash
RAM
X
AMAX–A16
Address inputs.
X
X
A/DQ15–A/DQ0 Multiplexed Address/Data.
X
Address Valid input. Indicates to device that the valid address is present on the address
inputs.
AVD#
CLK
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched.
X
X
X
X
High = device ignores address inputs
Clock input. In burst mode, after the initial word is output, subsequent active edges of
CLK increment the internal address counter. Should be at VIL or VIH while in
asynchronous mode.
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Spansion for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive
when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections
for PCB signal routing channels. Do not connect any host system signal to these
connections.
DNU
OE#
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
X
X
X
F-CE#
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default “Active HIGH” configuration)
VOL = data invalid
VOH = data valid
Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of
the Flash RDY signal.
F-RDY/R-WAIT
X
X
pSRAM WAIT (using default “Active HIGH” configuration)
VOL = data valid
VOH = data invalid
To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0
(Active LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0
(Active LOW RDY).
F-RST#
F-VPP
Hardware reset input. Low = device resets and returns to reading array data
X
X
Accelerated input. At VHH, accelerates programming; automatically places device in
unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH
for all other conditions.
Not Connected. No device internal signal is connected to the package connector nor is
there any future plan to use the connector for a signal. The connection may safely be
used for routing space for a signal on a Printed Circuit Board (PCB).
NC
R-CE#
R-CRE
R-LB#
R-UB#
Chip-enable input for pSRAM.
Control Register Enable (pSRAM).
Lower Byte Control (pSRAM).
Upper Byte Control (pSRAM).
X
X
X
X
Document Number: 002-00377 Rev. *S
Page 5 of 18
S71VS/XS-R
Table 2.1 Input/Output Descriptions (Sheet 2 of 2)
Symbol
Description
Flash
RAM
Reserved For Future Use. No device internal signal is currently connected to the
package connector but there is potential future use for the connector for a signal. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB
may take advantage of future enhanced features in compatible footprint devices.
RFU
VCC
Flash and pSRAM 1.8 Volt-only single power supply.
Flash and pSRAM Input/Output Power Supply.
Ground.
X
X
X
X
X
X
X
X
X
X
VCCQ
VSS
VSSQ
WE#
Input/Output Ground.
Write Enable input.
3. MCP Block Diagram
Figure 3.1 S71VS-R MCP Block Diagram
F-RST#
RST#
A/DQ15-A/DQ0
CLK
ADQ15-ADQ0
CLK
F-VPP
F-RDY/R-WAIT
F-CE#
VPP
RDY
CE#
OE#
WE#
AVD#
MUX
FLASH
MEMORY
VS-R
OE#
WE#
AVD#
Amax-A16
Amax-A16
VCC
VCC
VSS, VSSQ
VSS
VCCQ
VCCQ
VSSQ
R-UB#
R-LB#
R-CE#
UB#
LB#
A/DQ15-A/DQ0
CLK
MUX
pSRAM
MEMORY
CE#
OE#
WE#
ADV#
VSS
Amax-A16
VCC
VCCQ
VSSQ
WAIT
CRE
R-CRE
Document Number: 002-00377 Rev. *S
Page 6 of 18
S71VS/XS-R
4. Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71VS-R.
4.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time.
4.2
Connection Diagrams
Figure 4.1 S71VS-R 56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
NC
NC
Not Connected
Do Not Use
NC
RFU
A21
A16
R-LB# R-UB#
RFU
A17
NC
A22
VSS
OE#
Reserved for Future Use
Flash/RAM Shared
F-RDY/
R-WAIT
VSS
A20
CLK
VCC
WE#
F-VPP
A19
A18
VCCQ
VSS
AVD#
A23 F-RST# RFU
F-CE#
Flash Only
RAM Only
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8
G
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
H
J
NC
RFU
R-CE# R-CRE
RFU
NC
K
NC
NC
Document Number: 002-00377 Rev. *S
Page 7 of 18
S71VS/XS-R
Figure 4.2 S71VS-R 52-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend
1
2
3
4
5
6
7
8
9
10
NC
A
B
C
D
E
F
NC
RFU
A21
R-LB#
VCC
RFU
R-UB#
WE#
RFU
Not Connected
Do Not Use
F-RDY/
R-WAIT
VSS
A20
CLK
F-VPP
RFU
A19
A18
A17
RFU
VSS
OE#
ADQ0
NC
VCCQ
VSS
A16
AVD#
F-RST#
F-CE#
ADQ8
ADQ1
RFU
Reserved for Future Use
Flash/RAM Shared
Flash Only
ADQ7
ADQ6 ADQ13 ADQ12 ADQ3
ADQ2
ADQ9
ADQ15 ADQ14
VSS
ADQ5
ADQ4 ADQ11 ADQ10 VCCQ
R-CE# R-CRE
NC
RFU
RAM Only
Notes:
1. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
2. and V must be connected together.
V
SS
SSQ
MCP
Flash-Only Addresses
Shared Addresses
A20–A16
Shared ADQ Pins
S71VS064RB0
S71VS128RB0
S71VS128RC0
S71VS256RC0
S71VS256RD0
A21
A22–A21
A22
A20–A16
A21–A16
A/DQ15-A/DQ0
A23–A22
A23
A21–A16
A22–A16
Document Number: 002-00377 Rev. *S
Page 8 of 18
S71VS/XS-R
4.3
Physical Dimensions
Figure 4.3 RLG052 - 52-ball VFRBGA 6.0 x 5.0 mm
NOTES:
PACKAGE
JEDEC
RLG 052
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
6.00 mm x 5.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
MIN
NOM
---
MAX
NOTE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
D
---
1.00
---
PROFILE
0.18
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
6.00 BSC.
5.00 BSC.
4.50 BSC.
2.50 BSC.
10
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
6
52
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
Ib
0.25
0.30
0.35
BALL DIAMETER
e
0.50 BSC.
0.25 BSC.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SE / SD
SOLDER BALL PLACEMENT
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3A,3F,4A,4F,7A,7F,8A,8F DEPOPULATED SOLDER BALLS
g1002-1 \ f16-038.63 \ 08.25.10
Document Number: 002-00377 Rev. *S
Page 9 of 18
S71VS/XS-R
Figure 4.4 RLA056 - 56-ball VFRBGA 7.7 x 6.2 mm
NOTES:
PACKAGE
JEDEC
RLA 056
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
4. REPRESENTS THE SOLDER BALL GRID PITCH.
N/A
D X E
7.70 mm x 6.20 mm
PACKAGE
e
SYMBOL
MIN
NOM
---
MAX
NOTE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
A2
D
---
1.00
---
PROFILE
0.18
0.62
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
---
0.74
BODY THICKNESS
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X E
7.70 BSC.
6.20 BSC.
6.50 BSC.
4.50 BSC.
14
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
10
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
56
b
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
eE
eD
SE SD
0.50 BSC.
0.50 BSC.
0.25 BSC.
BALL PITCH
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
BALL PITCH
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
g1007 \ f16-038.63 \ 08.18.10
Document Number: 002-00377 Rev. *S
Page 10 of 18
S71VS/XS-R
Figure 4.5 RSD056—56-ball VFRBGA 7.7 x 6.2 mm
NOTES:
PACKAGE
JEDEC
RSD 056
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
7.70 mm x 6.20 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
SYMBOL
MIN
NOM
0.90
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.80
0.18
0.62
1.00
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
BALL HEIGHT
A2
---
0.74
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
7.70 BSC
6.20 BSC
6.50 BSC
4.50 BSC
14
E
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
n
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
10
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
0.50 BSC
0.50 BSC
0.25 BSC
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
SE SD
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3719 \ f16-038.63 \ 1.26.9
Document Number: 002-00377 Rev. *S
Page 11 of 18
S71VS/XS-R
Figure 4.6 RSE052—52-ball VFRBGA 6.0 x 5.0 mm
NOTES:
PACKAGE
JEDEC
RSE 052
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
4. REPRESENTS THE SOLDER BALL GRID PITCH.
D X E
6.00 mm x 5.00 mm
PACKAGE
e
SYMBOL
MIN
NOM
---
MAX
NOTE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
D
---
1.00
---
PROFILE
0.18
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
6.00 BSC.
5.00 BSC.
4.50 BSC.
2.50 BSC.
10
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
6
52
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
b
0.25
0.30
0.35
BALL DIAMETER
e
0.50 BSC.
0.25 BSC.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SE / SD
SOLDER BALL PLACEMENT
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3A,3F,4A,4F,7A,7F,8A,8F DEPOPULATED SOLDER BALLS
g1004-1 \ f16-038.63 \ 08.25.10
Document Number: 002-00377 Rev. *S
Page 12 of 18
S71VS/XS-R
5. Revision History
Section
Description
Revision 01 (August 25, 2008)
Initial release
Revision 02 (November 4, 2008)
Global
Added OPNs S71VS064RB0AHT00/04/80/84
Connection Diagrams
Physical Dimensions
General Description
Added S71VS-R 52-ball connection diagram
Added RSB052
Changed 128 Mb Mux pSRAM PID from TBD to pSRAM_39
Revision 03 (November 10, 2008)
General Description
Changed 64 Mb MUX pSRAM Type 3 PID from muxpsram_14 to muxpsram_15
Revision 04 (January 13, 2009)
Physical Dimensions
Replaced NLD056 with NSD056
Revision 05 (January 23, 2009)
Valid Combinations
Physical Dimensions
Added OPN S71VS128RC0AHK20
Added RSD056
Revision 06 (March 11, 2009)
Valid Combinations
Added 108 MHz speed grade to S71VS128RC0 and S71VS256RC0
Revision 07 (September 29, 2009)
General Description
Valid Combinations
Added S71VS128RB0; added muxpsram_10
Added OPN S71VS128RB0
Revision 08 (April 9, 2010)
Added SWM064D108M1R
General Description
Updated pSRAM documentation names
Added OPNs: S71VS128RC0AHK4L, S71VS256RC0AHK4L
Removed Bottom Boot options
Valid Combinations
Connection Diagrams
Updated VSSQ ball to VSS
Revision 09 (May 4, 2010)
Added reference to S29VS064R data sheet
Removed CustComspec_01 for 32 Mb MUX pSRAM
General Description
Valid Combinations
Corrected pSRAM type for S71VS064RB0 from CustComspec_01 to SWM032D108M1R
Added OPNs: S71VS064RB0AHT0L, S71VS256RD0AHK40
Revision 10 (June 14, 2010)
Removed S71XS256RD0 from table
Unified data sheet reference for S29VS/XS-R
Removed MUX pSRAM Type 3
General Description
Added SWM128D108M1R
Restored necessary bottom boot options.
Added OPNs: S71VS256RD0AHK3L/BL/3C/BC
Removed OPNs: S71VS064RB0AHT00/04
Valid Combinations
Updated MUX pSRAM Type 3 entries to the Common RAM type specifications
Removed table after Figure 4.3 S71XS-R 56-ball Fine-Pitch Ball Grid Array
Document Number: 002-00377 Rev. *S
Page 13 of 18
S71VS/XS-R
Section
Description
Revision 11 (July 28, 2010)
Features
Corrected MCP BGA Packages information
Corrected Package Modifier information
Removed 7 inch Tape and Reel option
Ordering Information
Corrected package information for S71VS064RB0AHT0L
Added OPN S71VS064RB0AHT8L, S71VS128RC0AHKCL, S71VS256RC0AHKCL
Removed OPN S71VS256RD0AHK40
Valid Combinations
MCP Block Diagram
Removed figure S71XS-R MCP Block Diagram
Corrected figure S71VS-R 52-ball Fine-Pitch Ball Grid Array
Removed figure S71XS-R 56-ball Fine-Pitch Ball Grid Array
Connection Diagrams/
Physical Dimensions
Replaced figure RSB052—52-ball VFBGA 5.0 x 7.5 mm with RSE052—52-ball VFRBGA 6.0 x 5.0 mm
Refreshed DNU/RFU/NC definitions
Revision 12 (August 27, 2010)
Corrected package information for S71VS128RB0AHK0L/8L (RLA056)
Valid Combinations
Corrected speed for OPNs S71VS256RD0AHK3L/BL to 108 MHz
Reverted DNU balls to RFU
Connection Diagrams
Physical Dimensions
Added diagram for RLA056
Revision 13 (December 9, 2010)
Features
Added Industrial temperature
Added references to S29VS_XS-R_SP, S29VS064R_XS064R_SP, SWM032D108M3R,
SWM128D108M3R
General Description
Added OPNs S71VS064RB0AHT3L/BL/0M/8M, S71VS128RB0AHK3L/BL, S71VS256RD0AHK3M,
S71VS256RD0AHK40/C0
Valid Combinations
Added Temperature Range Column
Revision 14 (April 13, 2011)
General Description
Removed SWM032D108M1N and SWM064D108M1N references
Removed OPNs S71VS064RB0AHT3M/BM, S71VS128RB0AHK2L/AL, S71VS128RC0AHK20,
S71VS128RC0ZHKxx, S71VS256RC0ZHKxx, S71VS256RD0ZHExx
Valid Combinations
Physical Dimensions: Removed NLB056 and NSD056 diagrams. Added diagram for RLG052
Revision 15 (June 20, 2011)
Valid Combinations
Added OPNs S71VS128RB0AHK4L/CL, , S71VS064RB0AHT4L/CL
Revision 16 (June 29, 2012)
Valid Combinations
Added OPNs S71VS064RB0AHT3M/BM
Revision 17 (October 2, 2012)
Valid Combinations
Updated the S71VS256RC0AHK4L/CL package from RSD056 to RLA056
Revision 18 (January 31, 2014)
General Description
Removed 128 Mb MUX pSRAM Type 5
Removed OPNs S71VS064RB0AHT0L/BL, S71VS256RD0AHK40/C0
Added OPN S71VS256RD0AHK4L/CL
Valid Combinations
Document Number: 002-00377 Rev. *S
Page 14 of 18
S71VS/XS-R
Document History Page
Document Title: S71VS/XS-R, MirrorBit® 1.8 V Simultaneous Read/Write Burst Mode Multiplexed Flash and Burst Mode
pSRAM
Document Number: 002-00377
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
RYSU
08/25/2008 Initial release
Global:
Added OPNs S71VS064RB0AHT00/04/80/84
Connection Diagrams:
Added S71VS-R 52-ball connection diagram
Physical Dimensions:
*A
RYSU
11/04/2008
Added RSB052
General Description:
Changed 128 Mb Mux pSRAM PID from TBD to pSRAM_39
General Description:
*B
*C
RYSU
RYSU
11/10/2008 Changed 64 Mb MUX pSRAM Type 3 PID from muxpsram_14 to
muxpsram_15
Physical Dimensions:
01/13/2009
Replaced NLD056 with NSD056
Valid Combinations:
Added OPN S71VS128RC0AHK20
Physical Dimensions:
Added RSD056
*D
*E
*F
RYSU
RYSU
RYSU
01/23/2009
Valid Combinations:
Added 108 MHz speed grade to S71VS128RC0 and S71VS256RC0
03/11/2009
General Description:
Added S71VS128RB0; added muxpsram_10
Valid Combinations:
09/29/2009
Added OPN S71VS128RB0
General Description:
Added SWM064D108M1R
Updated pSRAM documentation names
Valid Combinations:
Added OPNs: S71VS128RC0AHK4L, S71VS256RC0AHK4L
Removed Bottom Boot options
Connection Diagrams:
Updated VSSQ ball to VSS
*G
*H
RYSU
RYSU
04/09/2010
General Description:
Added reference to S29VS064R data sheet
Removed CustComspec_01 for 32 Mb MUX pSRAM
05/04/2010 Valid Combinations:
Corrected pSRAM type for S71VS064RB0 from CustComspec_01 to
SWM032D108M1R
Added OPNs: S71VS064RB0AHT0L, S71VS256RD0AHK40
Document Number: 002-00377 Rev. *S
Page 15 of 18
S71VS/XS-R
Document History Page (Continued)
Document Title: S71VS/XS-R, MirrorBit® 1.8 V Simultaneous Read/Write Burst Mode Multiplexed Flash and Burst Mode
pSRAM
Document Number: 002-00377
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
General Description:
Removed S71XS256RD0 from table
Unified data sheet reference for S29VS/XS-R
Removed MUX pSRAM Type 3
Added SWM128D108M1R
*I
RYSU
06/14/2010 Valid Combinations:
Restored necessary bottom boot options.
Added OPNs: S71VS256RD0AHK3L/BL/3C/BC
Removed OPNs: S71VS064RB0AHT00/04
Updated MUX pSRAM Type 3 entries to the Common RAM type specifications
Removed table after Figure 4.3 S71XS-R 56-ball Fine-Pitch Ball Grid Array
Features:
Corrected MCP BGA Packages information
Ordering Information:
Corrected Package Modifier information
Removed 7 inch Tape and Reel option
Valid Combinations:
Corrected package information for S71VS064RB0AHT0L
Added
OPN
S71VS064RB0AHT8L,
S71VS128RC0AHKCL,
S71VS256RC0AHKCL
Removed OPN S71VS256RD0AHK40
MCP Block Diagram:
*J
RYSU
07/28/2010
Removed figure S71XS-R MCP Block Diagram
Connection Diagrams/Physical Dimensions:
Corrected figure S71VS-R 52-ball Fine-Pitch Ball Grid Array
Removed figure S71XS-R 56-ball Fine-Pitch Ball Grid Array
Replaced figure RSB052—52-ball VFBGA 5.0 x 7.5 mm
with RSE052—52-ball VFRBGA 6.0 x 5.0 mm
Refreshed DNU/RFU/NC definitions
Valid Combinations:
Corrected package information for S71VS128RB0AHK0L/8L (RLA056)
Corrected speed for OPNs S71VS256RD0AHK3L/BL to 108 MHz
*K
RYSU
08/27/2010 Connection Diagrams:
Reverted DNU balls to RFU
Physical Dimensions:
Added diagram for RLA056
Features:
Added Industrial temperature
General Description:
Added references to S29VS_XS-R_SP, S29VS064R_XS064R_SP,
SWM032D108M3R, SWM128D108M3R
*L
RYSU
12/09/2010
Valid Combinations:
Added OPNs S71VS064RB0AHT3L/BL/0M/8M, S71VS128RB0AHK3L/BL,
S71VS256RD0AHK3M, S71VS256RD0AHK40/C0
Added Temperature Range Column
Document Number: 002-00377 Rev. *S
Page 16 of 18
S71VS/XS-R
Document History Page (Continued)
Document Title: S71VS/XS-R, MirrorBit® 1.8 V Simultaneous Read/Write Burst Mode Multiplexed Flash and Burst Mode
pSRAM
Document Number: 002-00377
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
General Description:
Removed SWM032D108M1N and SWM064D108M1N references
Valid Combinations:
Removed OPNs S71VS064RB0AHT3M/BM, S71VS128RB0AHK2L/AL,
S71VS128RC0AHK20, S71VS128RC0ZHKxx, S71VS256RC0ZHKxx,
S71VS256RD0ZHExx
*M
RYSU
04/13/2011
Physical Dimensions: Removed NLB056 and NSD056 diagrams. Added dia-
gram for RLG052
Valid Combinations:
Added OPNs S71VS128RB0AHK4L/CL, S71VS064RB0AHT4L/CL
*N
*O
*P
RYSU
RYSU
RYSU
06/20/2011
06/29/2012
10/02/2012
Valid Combinations:
Added OPNs S71VS064RB0AHT3M/BM
Valid Combinations:
Updated the S71VS256RC0AHK4L/CL package from RSD056 to RLA056.
General Description:
Removed 128 Mb MUX pSRAM Type 5
Valid Combinations:
Removed OPNs S71VS064RB0AHT0L/BL, S71VS256RD0AHK40/C0
*Q
RYSU
01/31/2014
Added OPN S71VS256RD0AHK4L/CL
Updated , General Description on page 2:
Updated table for detailed specifications:
Replaced “Publication Identification Number” with “Cypress Document
Number” in column heading.
Replaced “S29VS/XS-R” with “S29VS256R, S29VS128R datasheet” in
“Document” column.
Replaced “S29VS_XS-R_00” with “002-00833” in “Cypress Document
*R
5175865
RYSU
03/23/2016 Number” column.
Removed “S29VS/XS-R Supplement” document and its details.
Replaced “S29VS064R/XS064R” with “S29VS064R datasheet” in “Document”
column.
Replaced “S29VS_XS064R_00” with “002-00949” in “Cypress Document
Number” column.
Removed “S29VS064R/XS064R Supplement” document and its details.
Updated to Cypress template.
*S
5965598 AESATMP8 11/13/2017 Updated logo and Copyright.
Document Number: 002-00377 Rev. *S
Page 17 of 18
S71VS/XS-R
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-00377 Rev. *S
Revised Monday, November 13, 2017
Page 18 of 18
相关型号：
S71VS256RD0ZHE400
Memory Circuit, 16MX16, CMOS, PBGA56, 9.20 X 8 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, HALOGEN AND LEAD FREE, VFBGA-56
SPANSION
S71VS256RD0ZHE440
Memory Circuit, 16MX16, CMOS, PBGA56, 9.20 X 8 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, HALOGEN AND LEAD FREE, VFBGA-56
SPANSION
S71VS256RD0ZHE442
Memory Circuit, 16MX16, CMOS, PBGA56, 9.20 X 8 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, HALOGEN AND LEAD FREE, VFBGA-56
SPANSION
S71VS256RD0ZHEC00
Memory Circuit, 16X16, CMOS, PBGA56, 9.20 X 8 MM, 0.50 MM PITCH, LEAD FREE, VFBGA-56
SPANSION
S71VS256RD0ZHEC02
Memory Circuit, 16X16, CMOS, PBGA56, 9.20 X 8 MM, 0.50 MM PITCH, LEAD FREE, VFBGA-56
SPANSION
S71VS256RD0ZHEC42
Memory Circuit, 16X16, CMOS, PBGA56, 9.20 X 8 MM, 0.50 MM PITCH, LEAD FREE, VFBGA-56
SPANSION
©2020 ICPDF网 联系我们和版权申明