S72XS256RE0AHBJ23 [CYPRESS]
Memory Circuit, 16MX16, CMOS, PBGA133, BGA-133;
| 型号： | S72XS256RE0AHBJ23 |
| 厂家： | 
CYPRESS |
| 描述： | Memory Circuit, 16MX16, CMOS, PBGA133, BGA-133 内存集成电路 |
| 文件： | 总7页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S72XS-R MCP
256 Mb (16M x 16 bit), 1.8V
MirrorBit® Flash and DDR DRAM
Features
General Description
■ Power supply voltage
❐ 1.7V to 1.95V
This datasheet contains information on the S72XS-R Multi-Chip
Product (MCP) stacked products. Refer to the S29VS256R,
S29VS128R, S29XS256R, S29XS128R datasheet (002-00833)
for full electrical specifications of the Flash memory component.
■ Burst speed
❐ Flash = 83 MHz, 104 MHz or 108 MHz
❐ DDR DRAM = 166 MHz
The S72XS series is a product line of stacked products (MCPs), and
consists of:
■ Packages
❐ 8.0 8.0 mm, 133-ball MCP
■ S29XS family Address-High, Address-Low, Data Multiplexed
Flash memory die
■ Temperature range
❐ Wireless: –25 °C to +85 °C
❐ Industrial: –40 °C to +85 °C
■ DDR DRAM
Table 1 and Table 2 lists the products covered in this datasheet.
Table 1. Memory Density
Flash Density
DRAM Density
256 Mb
S72XS256RE0
Table 2. DDR DRAM Specification Reference
Density
Reference Name
256 Mb (16M 16-bit) DDR DRAM
Document Identification Number
256 Mb
SDM256D166D1R/D3R
Block Diagram
F-RS T#
F-V P P
A DQ15-A DQ0
F-CLK
F-RDY
NOR
F-CE #
F-OE #
F-W E #
F-A V D#
FLASH
XS-R
(AADM )
F-V CC
F-V CCQ
V S S
D-RA S #
D-CA S #
D-B A 0
D-CLK
D-CLK #
D-LDQS
D-UDQS
D-LDQM
D-UDQM
DDR
DRAM
M EM ORY
D-B A 1
D-CK E
D-W E #
D-CE #
D-A m ax - D-A 0
D-V CC
D-DQ15 - D-DQ0
V S S
D-V CCQ
Notes
1. Amax indicates highest address bit for memory component: Amax = A12 for 256 Mb DDR DRAM.
2. For Flash, A15 - A0 is tied to DQ15 - DQ0.
Cypress Semiconductor Corporation
Document Number: 002-00772 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 18, 2016
S72XS-R MCP
Pin Diagram
Figure 1. 133-Ball Fine-Pitch Ball Grid Array MCP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
Index Location
DNU
DNU
DNU
VSS D-VCCQ D-DQ9 D-DQ8
VSS D-VCC D-VCC D-DQ5 D-DQ3
VSS
DNU
DNU
VSS D-DQ13 D-UDQS D-DQ10 VSS D-VCCQD-VCCQD-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU
Do Not Use
No Connect
D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM VSS D-VCC VSS
D-DQ7 D-LDQS D-DQ2 D-DQ0
VSS
RFU
RFU
NC
NC
INDEX
F-OE# ADQ8 D-VCC
ADQ9 ADQ1 ADQ0
DRAM Only
RFU
RFU
RFU
RFU
Code Flash Only
Reserved for Future Use
VSS
RFU
VSS
ADQ3 ADQ2
G
F-CE#
RFU F-WE#
F-VCCQ ADQ11 ADQ10
ADQ13 ADQ12 ADQ4
H
J
F-VPP F-VCC F-CLK
RFU
VSS
NC
NC
VSS
NC
VSS
ADQ5
K
L
RFU F-AVD#
ADQ7 ADQ6
RFU F-RST# D-CE#
F-VCCQ ADQ15 ADQ14
M
N
NC
RFU
D-A3
D-A6
D-A9 D-CKE
VSS D-WE# D-A10
D-A1
D-A2
RFU
RFU
RFU
F-RDY
VSS
DNU
DNU
VSS D-VCC D-A5
D-A8 D-CAS# D-CLK# D-BA1 D-A11
D-A12
F-VCC DNU
P
DNU
NC
D-A4
D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC VSS
DNU
DNU
Table 3. DRAM Address Maximum
MCP Device ID
DDR DRAM Density
D-Amax
S72XS256RE0
256 Mb
D-A12
Document Number: 002-00772 Rev. *J
Page 2 of 7
S72XS-R MCP
Signal Description
Table 4. Input/Output Description
Symbol
ADQ15 – ADQ0
F-CE#
Description
Flash RAM
Flash multiplexed Address and Data
X
X
X
X
X
X
X
X
X
Flash Chip-enable input
F-OE#
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
Flash Write Enable input
F-WE#
F-VCC
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
Ground
F-VCCQ
VSS
F-RDY
Flash ready output. Indicates the status of the Burst read. VOL = Data invalid, VOH = Data valid.
Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input
and activates burst mode operation. After the initial word is output, subsequent rising edges of
CLK increment the internal address counter. CLK should remain low during asynchronous
access.
F-CLK
X
Flash Address Valid input. Indicates to device that the valid address is present on the address
inputs. VIL = For asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched on rising edge of CLK. VIH = Device ignores address inputs.
F-AVD#
F-RST#
F-VPP
X
X
X
Flash hardware reset input. VIL= device resets and returns to reading array data.
Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other
conditions.
D-Amax – D-A0
D-DQ15 – D-DQ0
D-CLK
DRAM Address input
DRAM Data input/output
DRAM System Clock
DRAM Chip Select
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D-CE#
D-CKE
DRAM Clock Enable
D-BA1 – BA0
D-RAS#
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
D-CAS#
D-UDQM – D-LDQM DRAM Data Input Mask
D-WE#
DRAM Write Enable input
D-VCCQ
D-VCC
DRAM Input/Output Buffer power supply
DRAM device power supply
D-UDQS
D-LDQS
D-CLK#
DRAM Upper Data Strobe, output with read data and input with write data
DRAM Lower Data Strobe, output with read data and input with write data
DDR Clock for negative edge of CLK
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use for the connector for a signal. It is recommended to
not use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.
RFU
NC
Not Connected. No device internal signal is connected to the package connector nor is there any
future plan to use the connector for a signal. The connection may safely be used for routing space
for a signal on a Printed Circuit Board (PCB).
Do Not Use. A device internal signal may be connected to the package connector. The connection
may be used by Cypress for test or other purposes and is not intended for connection to any host
system signal. Any DNU signal related function will be inactive when the signal is at VIL. The
signal has an internal pull-down resistor and may be left unconnected in the host system or may
be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect
any host system signal to these connections.
DNU
Document Number: 002-00772 Rev. *J
Page 3 of 7
S72XS-R MCP
Ordering Information
The order number (Valid Combination) is formed by the following:
S72XS
256
R
E0
AH
B
HE
3
Packing Type
0 = Tray
3 = 13-inch Tape and Reel
Model Number
See Valid Combinations (Table 5)
Package Modifier
B = 133-ball, 8x8 mm, FBGA MCP
Package and Material Type
AH = Thin profile Fine-pitch BGA Pb-free Low-Halogen MCP (0.5 mm pitch)
DDR DRAM and Data Flash Density
E0 = 256 Mb DDR, No Data Flash
Process Technology
R = 65 nm, MirrorBit Technology
Code Flash Density
256 = 256 Mb
Product Family
S72XS Multi-Chip Product (MCP)
1.8V Address-High, Address-Low, Data Multiplexed, SRW, Burst Mode Flash and DDR
DRAM on Split Bus
Valid Combinations
Valid combinations in Table 5 list the configurations planned to be supported in volume for this device. Contact your local sales
office to confirm the availability of specific valid combinations and to check on newly released combinations.
Table 5. Valid Combinations
Electronic
Serial
Number
DDR
DRAM
Density (MHz)
Flash
Speed Speed
DRAM
Model
Packing
Flash
Boot
Temperature
Range
Flash
Density
DRAM
Specification
Base OPN[4]
Package
Package
Number Type[3, 4]
(MHz)
SDM256D166
D1R
H1
J1
Top
Yes
No
Wireless
Industrial
Bottom
Top
8.0 8.0 mm
133-ball MCP
(RSC133)
HH
S72XS256RE0
0, 3
256 Mb
256 Mb
108
AHB
166
SDM256D166
D3R
JH
H2
J2
Bottom
Top
Yes
Bottom
Electronic Serial Number
For applicable devices, the Factory Secured Silicon Area contains a random, 128-bit ESN, stored in the address range
000000h-000007h.
Notes
3. Packing Type 0 is standard. Specify other options as required.
4. BGA package marking omits leading “S” and packing type designator from ordering part number.
Document Number: 002-00772 Rev. *J
Page 4 of 7
S72XS-R MCP
Package Diagram
Figure 2. RSC133 133-Ball Fine-Pitch Ball Grid Array (FBGA) 8.0 8.0 mm
Document Number: 002-00772 Rev. *J
Page 5 of 7
S72XS-R MCP
Document History Page
Document Title: S72XS-R MCP, 256 Mb (16M x 16 bit), 1.8V MirrorBit® Flash and DDR DRAM
Document Number: 002-00772
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
BWHA
BWHA
10/07/2008 Initial release
*A
01/13/2009 Global: Added section Electronic Serial Number
Global: Added SDM128D166D1K OPN
Product Block Diagram:
Figure: Updated D-VSS and D-VSSQ connections. Removed D-TEST signal
Physical Dimensions: Updated with RSC133
*B
*C
BWHA
BWHA
12/18/2009
02/01/2010 Connection Diagrams: Updated figure: changed Ball A2 with DNU
Global: Updated references for Low Power DDR SDRAM to SDM128D166D1R
DDR Specification Reference: Added reference for 256 Mb DDR DRAM
Product Selector Guide:
Added “not recommended for new designs” note to OPN S72XS128RD0AHBH60
Added OPN S72XS256RE0AHBH1
Removed OPN S72XS256RD0AHBHE
Product Block Diagram: Updated block diagram to show common Ground. Updated Note 1b.
Connection Diagrams:
08/19/2010 Updated connection diagram to show common Ground
Updated to show D-A12
*D
BWHA
Added table to show D-Amax value for related MCP
Balls F1, M2 and M12 changed from NC to RFU
Input/Output Descriptions:
Replaced F-VSS, D-VSS, D-VSSQ with VSS
Corrected F-ACC to F-VPP
Refreshed descriptions for DNU, NC, RFU
Ordering Information/Valid Combinations: Updated for new OPN S72XS256RE0AHBH1
*E
*F
BWHA
BWHA
12/10/2010 Global: Updated 256 Mb DRAM specification reference
Global:
03/17/2011 Removed SDM128D166D1K references
Removed OPN S72XS128RD0AHBH60, Added OPN S72XS256RE0AHBJ1
Ordering Information: Replaced Product Selector Guide section
Valid Combinations:
Made a separate section
*G
BWHA
10/05/2011
Added OPNs: S72XS128RD0AHBHD, S72XS256RE0AHBHH/JH
04/17/2012 Ordering Information: Added ESN support for S72XS256RE0AHBH1
10/13/2015 Updated to new template.
*H
*I
BWHA
BWHA
NFB
4960467
*J
5181007
03/18/2016 Removed S72XS128RD0 as it is EOL’d.
Document Number: 002-00772 Rev. *J
Page 6 of 7
S72XS-R MCP
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Document Number: 002-00772 Rev. *J
Revised March 18, 2016
Page 7 of 7
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相关型号：
S72XS256RE0AHBJH0
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
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