SM3603T-6.6 [CYPRESS]
Synchronous DRAM, 8MX8, 4.5ns, CMOS, PDSO54,;
| 型号： | SM3603T-6.6 |
| 厂家： | 
CYPRESS |
| 描述： | Synchronous DRAM, 8MX8, 4.5ns, CMOS, PDSO54, 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总19页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Features
Description
•
•
•
High Performance 150 MHz SDRAM
Fast 4.5 ns Clock Access Time
Low Latency Operation (2:3:2 @ 150 MHz)
The Enhanced Memory Systems SM3603 High-Speed
SDRAM (HSDRAM) device is a high performance
version of the proposed JEDEC PC-133 SDRAM. While
compatible with standard SDRAM, it provides the faster
clock access time (4.5 ns), shorter random access latency
(31.2 ns), and fast bank cycle time (53.3 ns) needed to
improve system stability, capacity, and performance in
systems operating at 150 MHz bus speed. The
HSDRAM is ideal for any high performance system
including PCs, workstations, servers, communications
switches, DSP systems, 3-D graphics, and embedded
computers.
•
•
•
CAS Latency = 2
RAS to CAS Delay = 3
Precharge Delay = 2
•
•
•
•
•
Fast Random Access Time (31.2 ns)
Fast Random Cycle time (53.3 ns)
Programmable Burst length (1, 2, 4, 8, full page)
Programmable CAS Latency (2, 3)
Low Power suspend, Self Refresh, and Power Down
Modes Supported
•
•
•
4K Refresh / 64 ms
Single 3.3V ± 0.3V Power Supply
54-pin TSOP-II (0.8mm pin pitch)
Block Diagram
BANK A
BANK B
BANK C
BANK D
BA1
BA0
A(11:0)
4K rows x
512 col x
8 bits
4K rows x
512 col x
8 bits
4K rows x
512 col x
8 bits
4K rows x
512 col x
8 bits
SENSE AMPLIFIERS
COLUMN DECODER
SENSE AMPLIFIERS
COLUMN DECODER
SENSE AMPLIFIERS
COLUMN DECODER
SENSE AMPLIFIERS
COLUMN DECODER
Data I/O Buffers
DQ(7:0)
CLK
CKE
/CS
/RAS
/CAS
/WE
COMMAND
DECODER
and
TIMING
GENERATOR
DQM
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 1 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
Pin Assignments (Top View)
8Mx8
VDD
DQ0
VDD
NC
1
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ7
VSS
NC
2
3
4
DQ1
VSS
5
DQ6
VDD
NC
6
NC
DQ2
VDD
NC
7
8
DQ5
VSS
NC
9
54 PIN TSOP-II
400 x 875 mils
0.8 mm pitch
10
11
DQ3
DQ4
VSS
NC
12
13
43
42
VDD
NC
VDD
NC
14
15
16
17
18
19
20
21
22
23
24
25
26
27
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
NC
/WE
/CAS
/RAS
/CS
DQM
CLK
CKE
NC
BA0
BA1
A10/AP
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 2 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Pin Descriptions
Symbol
CLK
Type
Input
Input
Function
Clocks: All SDRAM input signals are sampled on the positive edge of CLK.
CKE
Clock Enable: CKE activate (high) or deactivate (low) the CLK signals. Deactivating the
clock initiates the Power-Down and Self-Refresh operations (all banks idle), or Clock
Suspend operation. CKE is synchronous until the device enters Power-Down and Self-
Refresh modes where it is asynchronous until the mode is exited.
CS#
Input
Chip Select: CS# enables (low) or disables (high) the command decoder. When the
command decoder is disabled, new commands are ignored but previous operations
continue.
RAS#, CAS#,
WE#
Input
Input
Input
Command Inputs: Sampled on the rising edge of CLK, these inputs define the command
to be executed.
BA1, BA0
(A12, A13)
Bank Addresses: These inputs define to which of the 4 banks a given command is being
applied.
A0-A11
Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-
A8 define the column address during Read and Write commands. A10/AP invokes the
Auto-precharge operation. During manual Precharge commands, A10/AP low specifies a
single bank precharge while A10/AP high precharges all banks. The address inputs are
also used to program the Mode Register.
DQ0-DQ7
DQM
Input/
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these
pins and must be set-up and held relative to the rising edge of clock. For Read cycles, the
device drives output data on these pins after the CAS latency is satisfied.
Output
Input
Data I/O Mask Input: DQM input masks write data (zero latency) and acts as a
synchronous output enable (2-cycle latency) for read data.
VDD
VSS
NC
Supply
Supply
-
Power Supply: +3.3 V
Ground
No connect - open pin.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 3 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
HSDRAM Command Truth Table
CKE
Previous
/CS
/RAS /CAS /WE
DQM BA1, A10/
BA0 AP
A11,
A9
A8-A0
Function
Current
Cycle
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
L
Mode Register Set
No Operation (NOP)
Bank Activate
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Op Code (BA1=0, BA0=0)
X
X
X
X
X
Row Address
Write with Auto-Precharge
Write
H
H
H
H
H
L
BS
BS
BS
BS
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Column
L
L
Column
Read with Auto-Precharge
Read
L
H
H
L
1
Column
L
0
Column
Burst termination
H
H
H
L
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Single Bank Precharge
Precharge All Banks
Auto-Refresh (CBR)
Self Refresh Entry
Self Refresh Exit
L
BS
X
L
L
H
X
X
X
X
X
X
X
X
X
X
L
H
H
X
L
L
X
H
X
L
NOP or DESEL
X
Device Deselect
H
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Entry
Clock Suspend Mode Exit
Power Down Mode Entry
Power Down Mode Exit
Data Write/Output Enable
Data Mask/ Output Disable
X
H
L
X
H
L
NOP or DESEL
NOP or DESEL
X
H
X
X
X
H
H
X
X
X
X
X
X
X
X
X
H
X
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 4 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Mode Register Set (Address Input for Mode Set)
BA1
BA0
A11
A10
BA1
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Operation Mode
CAS Latency
Burst Length
BA1
0
BA0
0
M11
0
M10
0
M9
0
M8
0
M7
0
M3
0
Burst type
Sequential
Interleaved
1
Burst Length
M2
M1
M0
M6
0
M5
0
M4
0
CAS Latency
Reserved
Reserved
2
Sequential
Interleaved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
0
0
1
0
1
0
4
4
0
1
1
3
8
8
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
1
0
1
1
1
0
1
1
1
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 5 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
Electrical Characteristics
Absolute Maximum Ratings
Description
Symbol
VDD
Value
Power Supply Voltage
-1V to +4.6V
Voltage on any Pin with Respect to Ground
Operating Temperature (ambient)
Storage Temperature
VIN, VOUT
TA
-0.5V to +4.6V
0°C to +70°C
-55°C to +125°C
TBD
Tstg
Power Dissipation
PD
DC Output Current (I/O pins)
IOUT
50mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only, and the functional operation of the device at these, or any other conditions above those listed in the
operational section of the specification, is not implied. Exposure to conditions at absolute maximum ratings for extended
periods may affect device reliability.
DC Operating Conditions (TA = 0°C to 70°C)
Symbol
VDD
VIH
Parameter
Min
3.0
2.0
-0.3
-
Typical
Max
3.6
Units
V
Notes
Supply Voltage
3.3
Input High Voltage
3.3
VDD + 0.3
0.8
V
VIL
Input Low Voltage
0.0
V
II(L)
Input Leakage Current
-
-
-
-
±1
µA
µA
V
IO(L)
VOH
VOL
Output Leakage Current
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = +4mA)
-
±1
2.4
0.0
VDD
0.4
V
Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ±0.3V, not 100% tested)
Symbol
CIn1
Parameter
Min
2.5
2.5
3.5
Typical
3.3
Max
4.0
4.0
5.5
Units
pF
Notes
Input Capacitance (BA1, BA0, A0-11)
Input Capacitance (all control inputs)
I/O Capacitance (DQ0-7)
CIn2
3.3
pF
CI/O
4.5
pF
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 6 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Operating Currents (TA = 0°C to 70°C)
Parameter
Operating Current
Symbol
ICC1A
Test Condition
Value
130
Units Notes
BL = 1, CL = 3, Read or Write,
CKE VIH(min), tRC = min., tCK = min.
mA
mA
mA
1
(One Bank Active)
Standby Current in Power Down
Mode (DRAM Precharged)
ICC2P
2.5
2.0
CKE VIL, tCK = min.,
Input Change Every Two Cycles
ICC2PS
CKE VIL, tCK = Infinity,
No Input Change
Standby Current in Non-Power
Down Mode (DRAM Precharged)
ICC2N
ICC2NS
ICC3N
35
12
65
mA
mA
mA
CKE VIH, tCK = min.
CKE VIH, tCK = Infinity
Device Deselected (DRAM
Active)
CKE VIH, tCK = min.,
Input Change Every Two Cycles
ICC3P
ICC4B
3
mA
mA
CKE VIL, tCK = min.,
Input Change Every Two Cycles
Burst Operating Current
(Both Banks Active)
BL = Full Page, CL = 2,3, Read or Write,
140
1,2
tRC = Infinity, tCK = min.
Auto (CBR) Refresh Current
Self Refresh Current
Notes:
ICC5F
ICC5D
ICC6
CL = 3, tCK = min., tRC = tRC(min).
CL = 3, tCK = min., tRC = 15.625 µs
CKE ꢀꢁꢂꢃ9ꢄꢀ1Rꢀ,QSXWꢀ&KDQJH
210
35
4
mA
mA
mA
3,4,5
3,4,5
1. The specified value is obtained with the outputs open.
2. The specified value is obtained when the programmed burst length is executed to completion without interruption by a subsequent burst read or
burst write cycle.
3. The specified value is valid when addresses are changed no more than once during tCK(min).
4. The specified value is valid when No Operation commands are registered on every rising clock edge during tRC(min).
5. The specified value is valid when data inputs (DQs) are stable during tRC(min).
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 7 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
AC Characteristics (TA = 0°C to 70°C)
1. An initial pause of 200µs is required after power-up, then a Precharge All Banks command must be given followed by
a minimum of eight Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the VTT = 1.4V crossover point.
VTT
tT
VIH
VTT
VIL
Clock
RT = 50 ohm
tSETUP tHOLD
Z0 = 50 ohm
Output
Input
CLOAD = 50pF
tOH
tAC
tLZ
VTT
Output
AC Output Load Circuit
3. The transition time is measured between VIH and VIL (or between VIH and VIL).
4. AC measurements assume tT = 1ns.
5. In addition to meeting the transition rate specification, the clock and CKE must transition VIH and VIL (or between VIH
and VIL) in a monotonic manner.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 8 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
AC Operating Conditions (TA = 0°C to 70°C)
Clock and Clock Enable Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
6.6
6.6
2.5
2.5
1.5
0.8
1.5
-
Max
tCK3
Clock Cycle Time, CL = 3
ns
ns
ns
ns
ns
ns
ns
ns
tCK2
Clock Cycle Time, CL = 2
tCKH3, tCKL3
tCKH2, tCKL2
tCKES
Clock High & Low Times, CL=3
Clock High & Low Times, CL=2
Clock Enable Set-Up Time
Clock Enable Hold Time
-
-
1
1
-
tCKEH
-
tCKSP
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
-
tT
4
Notes:
1. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an
additional [(trise+tfall)/2-1] ns.
Common Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
1.5
Max
tCS
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
-
ns
ns
tCH
0.8
-
tRCD
tRC
tRAS
tRP
18.0
53.3
33.3
13.3
13.3
6.6
-
ns
Bank Cycle Time
120K
ns
Bank Active Time
120K
ns
Precharge Time
-
-
-
-
ns
tRRD
tCCD
tMRD
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
Mode Register Set to Active Delay
ns
ns
2
CLK
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 9 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
Read and Write Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
-
Max
tAC3
tAC2
tOH3
tOH2
tLZ
Clock Access Time, CL = 3
Clock Access Time, CL = 2
Data Output Hold Time (CL=3)
Data Output Hold Time (CL=2)
Data Output to Low-Z Time
Data Output to High-Z Time (CL=2, 3)
Data Input Set-Up Time
4.5
ns
ns
1,2
1,2
-
4.5
2.7
2.7
1
-
ns
-
ns
-
ns
tHZ2
tDS
-
4.5
ns
3
4
1.5
0.8
13.3
4
-
-
-
-
-
-
ns
tDH
Data Input Hold Time
ns
tDPL
tDAL
tDQW
Data Input to Precharge
ns
Data Input to ACTV/Refresh
Data Write Mask Latency
CLK
CLK
CLK
0
tDQZ
DQM Data Output Disable Time
2
Notes:
1. Access time is measured at 1.4V (LVTTL) at max clock rate for the CAS latency specified. See AC Test Load.
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time.
3. Referenced to the time at which the output achieves an open circuit condition.
4. tDAL is equal to tDPL + tRP and can be less than 4 clocks if tDPL and tRP are both satisfied.
Refresh Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
-
Max
64
-
tREF
Refresh Period
ms
ns
ns
1, 2
3
tSREX
Self Refresh Exit Time
Refresh Cycle Time
2CLK+tRC
60.0
tRFC
Notes:
1. 4096 cycles.
2. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.
3. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not
completed until tRC is satisfied once the Self-Refresh Exit command is registered.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 10 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Timing Diagrams (B = Bank Address, R = Row Address, C = Column Address)
Power Up and Initialization Sequence
CLK
tRP
tRFC
tRFC
tMRD
/CS
/RAS
/CAS
/WE
B
R
R
BA(1:0)
A10/AP
Addr
DQM
DQ
DQM High
High-Z
CBR
Precharge All
CBR
MRS
Bank Activate
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 11 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
Burst Reads (BL=4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRCD
tRP
tRAS
tRC
/CS
/RAS
/CAS
/WE
B
R
R
B
C
B
B*
B
R
R
BA(1:0)
A10/AP
Addr
C
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
DQ
Bank Activate
Read
Read
Precharge
(*If A10/AP is
high, BA pins
Bank Activate
are don’t care)
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 12 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
Burst Writes (BL=4)
8Mx8 HSDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRC D
tDPL
tRP
tDAL
tRAS
tRC
/CS
/RAS
/CAS
/WE
B
R
R
B
B
B*
B
R
R
BA(1:0)
A10/AP
Addr
C
C
D0
D1
D2
D3
D0
D1
D2
D3
DQ
Bank Activate
Write
Write
Precharge
(*If A10/AP is
high, BA pins
Bank Activate
are don’t care)
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 13 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
Burst Read/Write (BL=4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRC D
tDPL
tRP
tDAL
/CS
/RAS
/CAS
/WE
B
R
R
B
C
B
C
B*
B
R
R
BA(1:0)
A10/AP
Addr
Q0
Q1
Q2
Q3
D0
D1
D2
D3
DQ
Bank Activate
Read
Write
Precharge
(*If A10/AP is
high, BA pins
Bank Activate
are don’t care)
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 14 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Auto Refresh (CBR)
CLK
tRFC
/CS
/RAS
/CAS
/WE
B
R
R
BA(1:0)
A10/AP
Addr
High-Z
DQ
CBR
Bank Activate
(All banks must be
precharged prior to
CBR command)
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 15 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
DQM Operation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
CMD
Rd
Wr
DQM
DQ (CL2)
DQ (CL3)
Q0
Q1
Q0
Q3
Q2
D0
D2
D3
Q3
D0
D2
D3
Read
Write
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 16 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
CKE Operation
8Mx8 HSDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
Commands are ignored one clock following CKE low.
Wr
Rd
CMD
DQ (CL2)
DQ (CL3)
Q0
Q1
Q0
Q2
Q1
Q3
Q2
D0
D1
D2
D3
Q3
D0
D1
D2
D3
Read
Write
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 17 of 19
64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
Revision Log
Revision
Date
Summary of Changes
1.1
1.2
7/25/00
8/7/00
Updated 150MHz data. Changed timing parameters from 3:2:2 to 2:3:2.
Added Truth Table, MRS Diagram, and Timing Diagrams.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 18 of 19
Revision 1.2
64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Ordering Information
Maximum
Operating
Frequency
(MHz)
Part Number
CAS
Latencies
I/O Width
I/O Type
Package
Power
Supply
SM3603T-6.6
2, 3
x8
LVTTL
54-pin TSOP II
3.3V
150
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 19 of 19
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