STK11C88-S25I [CYPRESS]

32KX8 NON-VOLATILE SRAM, 25ns, PDSO28, 0.350 INCH, PLASTIC, SOIC-28;


型号：	STK11C88-S25I
厂家：	CYPRESS
描述：	32KX8 NON-VOLATILE SRAM, 25ns, PDSO28, 0.350 INCH, PLASTIC, SOIC-28 可编程只读存储器电动程控只读存储器电可擦编程只读存储器静态存储器光电二极管内存集成电路
文件：	总10页 (文件大小：285K)
中文：	中文翻译
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STK11C88

32K x 8 nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

FEATURES

DESCRIPTION

• 25ns, 35ns and 45ns Access Times

The Simtek STK11C88 is a fast static RAM with a

nonvolatile element incorporated in each static

memory cell. The SRAM can be read and written an

unlimited number of times, while independent non-

volatile data resides in Nonvolatile Elements. Data

transfers from the SRAM to the Nonvolatile Elements

(the STORE operation), or from Nonvolatile Elements

to SRAM (the RECALL operation), are initiated using

a software sequence. Data transfers from the Non-

volatile Elements to the SRAM (the RECALL opera-

tion) also occur upon restoration of power.

• STORE to Nonvolatile Elements Initiated by

Software

• RECALL to SRAM Initiated by Software or

Power Restore

• 10mA Typical I_CCat 200ns Cycle Time

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to Nonvolatile Ele-

ments (Commercial/Industrial)

• 100-Year Data Retention in Nonvolatile Ele-

ments (Commercial/Industrial)

The STK11C88 is pin-compatible with industry-

standard SRAMs.

• Single 5V + 10% Operation

• Commercial and Industrial Temperatures

• 28-Pin PDIP and SOIC Packages

BLOCK DIAGRAM

PIN CONFIGURATIONS

A₁₄

A₁₂

A₇

V_CC

QUANTUM TRAP

512 x 512

A₁₃

A₈

A₅

A₆

A₅

A₉

A₆

STORE

STORE/

RECALL

A₄

A₁₁

A₁₀

DQ₇

DQ₆

DQ₅

DQ₄

DQ₃

A₇

A₃

A₈

STATIC RAM

ARRAY

A₂

CONTROL

RECALL

A₉

A₁

A₁₁

A₁₂

A₁₃

A₁₄

512 x 512

A₀

28 - 300 PDIP

28 - 600 PDIP

28 - 300 SOIC

28 - 350 SOIC

DQ₀

DQ₁

DQ₂

V_SS

SOFTWARE

DETECT

- A

COLUMN I/O

PIN NAMES

COLUMN DEC

- A

Address Inputs

Write Enable

Data In/Out

Chip Enable

Output Enable

Power (+5V)

Ground

A A A

A A

1 4

2 3

DQ - DQ

September 2003

Document Control # ML0012 rev 0.1

STK11C88

ABSOLUTE MAXIMUM RATINGS^a

Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V

Voltage on Input Relative to V_SS. . . . . . . . . . –0.6V to (V_CC+ 0.5V)

Voltage on DQ_0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V_CC+ 0.5V)

Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at condi-

tions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS

(V_CC= 5.0V ± 10%)

COMMERCIAL

INDUSTRIAL

SYMBOL

PARAMETER

UNITS

NOTES

MIN

MAX

MIN

MAX

Average V Current

100

= 25ns

= 35ns

= 45ns

AVAV

Average V Current during STORE

All Inputs Don’t Care, V = max

Average V Current at t

= 200ns

W ≥ (V – 0.2V)

AVAV

5V, 25°C, Typical

All Others Cycling, CMOS Levels

Average V Current

= 25ns, E ≥ V

AVAV

(Standby, Cycling TTL Input Levels)

= 35ns, E ≥ V

= 45ns, E ≥ V

Standby Current

E ≥ (V

- 0.2V)

750

±1

750

±1

µA

(Standby, Stable CMOS Input Levels)

All Others V ≤ 0.2V or ≥ (V – 0.2V)

IN CC

Input Leakage Current

= max

ILK

= V to V

Off-State Output Leakage Current

= max

OLK

±5

= V to V , E or G ≥ V

Input Logic “1” Voltage

Input Logic “0” Voltage

Output Logic “1” Voltage

Output Logic “0” Voltage

Operating Temperature

2.2

+ .5

2.2

V + .5

All Inputs

– .5

0.8

V – .5

0.8

2.4

=–4mA

= 8mA

OUT

0.4

–40

°C

Note b: I_CCand I_CC3are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

Note c: I_CC¹is the average current required for the duration of the STORE cycle (t_STORE).

Note d: E ≥²V_IHwill not produce standby current levels until any nonvolatile cycle in progress has timed out.

AC TEST CONDITIONS

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1

5.0V

480 Ohms

CAPACITANCE^e

(T_A= 25°C, f = 1.0MHz)

OUTPUT

SYMBOL

PARAMETER

Input Capacitance

Output Capacitance

MAX

UNITS

CONDITIONS

∆V = 0 to 3V

30 pF

INCLUDING

SCOPE AND

FIXTURE

255 Ohms

OUT

Note e: These parameters are guaranteed but not tested.

Figure 1: AC Output Loading

September 2003

Document Control # ML0012 rev 0.1

STK11C88

SRAM READ CYCLES #1 & #2

(V_CC= 5.0V + 10%)

SYMBOLS

STK11C88-25 STK11C88-35 STK11C88-45

PARAMETER

UNITS

NO.

#1, #2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

Chip Enable Access Time

ELQV

ACS

Read Cycle Time

AVAV

Address Access Time

AVQV

Output Enable to Data Valid

Output Hold after Address Change

Chip Enable to Output Active

Chip Disable to Output Inactive

Output Enable to Output Active

Output Disable to Output Inactive

Chip Enable to Power Active

Chip Disable to Power Standby

GLQV

AXQX

ELQX

EHQZ

GLQX

OLZ

OHZ

GHQZ

ELICCH

EHICCL

d, e

Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.

Note g: I/O state assumes E, G < V_ILand W > V_IH; device is continuously selected.

Note h: Measured ± 200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlled^{f, g}

AVAV

ADDRESS

AVQV

AXQX

DQ (DATA OUT)

DATA VALID

SRAM READ CYCLE #2: E Controlled^f

AVAV

ADDRESS

EHICCL

ELQV

ELQX

EHQZ

GHQZ

GLQV

GLQX

DQ (DATA OUT)

DATA VALID

ELICCH

ACTIVE

STANDBY

September 2003

Document Control # ML0012 rev 0.1

STK11C88

SRAM WRITE CYCLES #1 & #2

(V_CC= 5.0V + 10%)

SYMBOLS

STK11C88-25

STK11C88-35

STK11C88-45

NO.

PARAMETER

UNITS

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

Write Cycle Time

Write Pulse Width

AVAV

WLWH

WLEH

Chip Enable to End of Write

Data Set-up to End of Write

Data Hold after End of Write

Address Set-up to End of Write

Address Set-up to Start of Write

Address Hold after End of Write

Write Enable to Output Disable

Output Active after End of Write

ELWH

DVWH

WHDX

ELEH

DVEH

EHDX

AVWH

AVEH

AVWL

WHAX

AVEL

EHAX

h, i

WLQZ

WHQX

Note i: If W is low when E goes low, the outputs remain in the high-impedance state.

Note j: E or W must be ≥ V_IHduring address transitions.

SRAM WRITE CYCLE #1: W Controlled^j

AVAV

ADDRESS

WHAX

ELWH

AVWH

AVWL

WLWH

DVWH

WHDX

DATA IN

DATA VALID

WLQZ

WHQX

HIGH IMPEDANCE

DATA OUT

PREVIOUS DATA

SRAM WRITE CYCLE #2: E Controlled^j

AVAV

ADDRESS

ELEH

AVEL

EHAX

AVEH

WLEH

DVEH

EHDX

DATA IN

DATA VALID

HIGH IMPEDANCE

DATA OUT

September 2003

Document Control # ML0012 rev 0.1

STK11C88

STORE INHIBIT/POWER-UP RECALL

(V_CC= 5.0V + 10%)

SYMBOLS

STK11C88

NO.

PARAMETER

UNITS NOTES

Standard

MIN

MAX

550

Power-up RECALL Duration

STORE Cycle Duration

µs

RESTORE

STORE

Low Voltage Trigger Level

Low Voltage Reset Level

4.0

4.5

SWITCH

RESET

3.6

Note k: t_RESTOREstarts from the time V_CCrises above V_SWITCH

STORE INHIBIT/POWER-UP RECALL

V_CC

V_SWITCH

V_RESET

STORE INHIBIT

POWER-UP RECALL

RESTORE

DQ (DATA OUT)

POWER-UP

RECALL

BROWN OUT

STORE INHIBIT

BROWN OUT

STORE INHIBIT

BROWN OUT

STORE INHIBIT

NO RECALL

RECALL WHEN

(V DID NOT GO

RETURNS

BELOW V

)

BELOW V

)

ABOVE V

SWITCH

RESET

September 2003

Document Control # ML0012 rev 0.1

STK11C88

SOFTWARE STORE/RECALL MODE SELECTION

- A (hex)

MODE

I/O

NOTES

0E38

31C7

03E0

3C1F

303F

0FC0

Read SRAM

Output Data

Output High Z

Read SRAM

m, n

Read SRAM

Nonvolatile STORE

0E38

31C7

03E0

3C1F

303F

0C63

Read SRAM

Output Data

Output High Z

Read SRAM

m, n

Read SRAM

Nonvolatile RECALL

Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

Note m: While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.

SOFTWARE STORE/RECALL CYCLE^{n, o}

(V_CC= 5.0V ± 10%)

STK11C88-25

STK11C88-35

STK11C88-45

NO.

SYMBOLS

PARAMETER

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

STORE/RECALL Initiation Cycle Time

Address Set-up Time

Clock Pulse Width

µs

AVAV

AVEL

ELEH

Address Hold Time

ELAX

RECALL Duration

RECALL

Note n: The software sequence is clocked with E controlled reads.

Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,

303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive

cycles.

SOFTWARE STORE/RECALL CYCLE: E Controlled^o

AVAV

ADDRESS #1

ADDRESS #6

ADDRESS

AVEL

ELEH

ELAX

RECALL

_STORE/ t

HIGH IMPEDANCE

DATA VALID

DQ (DATA

September 2003

Document Control # ML0012 rev 0.1

STK11C88

DEVICE OPERATION

The STK11C88 is a versatile memory chip that pro-

SOFTWARE NONVOLATILE STORE

vides several modes of operation. The STK11C88

can operate as a standard 32K x 8 SRAM. It has a

32K x 8 Nonvolatile Elements shadow to which the

SRAM information can be copied or from which the

SRAM can be updated in nonvolatile mode.

The STK11C88 software STORE cycle is initiated by

executing sequential READ cycles from six specific

address locations. During the STORE cycle an erase

of the previous nonvolatile data is first performed,

followed by a program of the nonvolatile elements.

The program operation copies the SRAM data into

nonvolatile memory. Once a STORE cycle is initi-

ated, further input and output are disabled until the

cycle is completed.

NOISE CONSIDERATIONS

Note that the STK11C88 is a high-speed memory

and so must have a high-frequency bypass capaci-

tor of approximately 0.1µF connected between V

Because a sequence of READs from specific

addresses is used for STORE initiation, it is impor-

tant that no other READ or WRITE accesses inter-

vene in the sequence or the sequence will be

aborted and no STORE or RECALL will take place.

and V , using leads and traces that are as short as

possible. As with all high-speed CMOS ICs, normal

careful routing of power, ground and signals will help

prevent noise problems.

SRAM READ

To initiate the software STORE cycle, the following

READ sequence must be performed:

The STK11C88 performs a READ cycle whenever E

and G are low and W is high. The address specified

on pins A_0-14determines which of the 32,768 data

bytes will be accessed. When the READ is initiated

by an address transition, the outputs will be valid

after a delay of ^t_AVQV(READ cycle #1). If the READ is

initiated by E or G, the outputs will be valid at t_ELQVor

at t_GLQV, whichever is later (READ cycle #2). The data

outputs will repeatedly respond to address changes

within the t_AVQVaccess time without the need for tran-

sitions on any control input pins, and will remain valid

until another address change or until E or G is

brought high.

1. Read address

2. Read address

3. Read address

4. Read address

5. Read address

6. Read address

0E38 (hex)

31C7 (hex)

03E0 (hex)

3C1F (hex)

303F (hex)

0FC0 (hex)

Valid READ

Initiate STORE cycle

The software sequence must be clocked with E con-

trolled READs.

Once the sixth address in the sequence has been

entered, the STORE cycle will commence and the

chip will be disabled. It is important that READ cycles

and not WRITE cycles be used in the sequence,

although it is not necessary that G be low for the

sequence to be valid. After the t_STOREcycle time has

been fulfilled, the SRAM will again be activated for

READ and WRITE operation.

SRAM WRITE

A WRITE cycle is performed whenever E and W are

low. The address inputs must be stable prior to

entering the WRITE cycle and must remain stable

until either E or W goes high at the end of the cycle.

The data on the common I/O pins DQ_0-7will be writ-

ten into the memory if it is valid t_DVWHbefore the end

of a W controlled WRITE or t_DVEHbefore the end of an

E controlled WRITE.

SOFTWARE NONVOLATILE RECALL

A software RECALL cycle is initiated with a sequence

of READ operations in a manner similar to the soft-

ware STORE initiation. To initiate the RECALL cycle,

the following sequence of READ operations must be

performed:

It is recommended that G be kept high during the

entire WRITE cycle to avoid data bus contention on

the common I/O lines. If G is left low, internal circuitry

will turn off the output buffers t_WLQZafter W goes low.

1. Read address

2. Read address

3. Read address

4. Read address

5. Read address

6. Read address

0E38 (hex)

31C7 (hex)

03E0 (hex)

3C1F (hex)

303F (hex)

0C63 (hex)

Valid READ

Initiate RECALL cycle

September 2003

Document Control # ML0012 rev 0.1

STK11C88

Internally, RECALL is a two-step procedure. First,

the SRAM data is cleared, and second, the nonvola-

tile information is transferred into the SRAM cells.

After the t_RECALLcycle time the SRAM will once again

be ready for READ and WRITE operations. The

RECALL operation in no way alters the data in the

Nonvolatile Elements. The nonvolatile data can be

recalled an unlimited number of times.

HARDWARE PROTECT

The STK11C88 offers hardware protection against

inadvertent STORE operation during low-voltage

conditions. When V_CC< V_SWITCH, all software STORE

operations are inhibited.

LOW AVERAGE ACTIVE POWER

POWER-UP RECALL

The STK11C88 draws significantly less current

when it is cycled at times longer than 50ns. Figure 2

shows the relationship between I_CCand READ cycle

time. Worst-case current consumption is shown for

both CMOS and TTL input levels (commercial tem-

perature range, V_CC= 5.5V, 100% duty cycle on chip

enable). Figure 3 shows the same relationship for

WRITE cycles. If the chip enable duty cycle is less

than 100%, only standby current is drawn when the

chip is disabled. The overall average current drawn

by the STK11C88 depends on the following items:

1) CMOS vs. TTL input levels; 2) the duty cycle of

chip enable; 3) the overall cycle rate for accesses;

4) the ratio of READs to WRITEs; 5) the operating

During power up, or after any low-power condition

(V_CC< V_RESET), an internal RECALL request will be

latched. When V_CConce again exceeds the sense

voltage of V_SWITCH, a RECALL cycle will automatically

be initiated and will take t_RESTOREto complete.

If the STK11C88 is in a WRITE state at the end of

power-up RECALL, the SRAM data will be corrupted.

To help avoid this situation, a 10K Ohm resistor

should be connected either between W and system

V_CCor between E and system V_CC.

temperature; 6) the V level; and 7) I/O loading.

100

TTL

CMOS

TTL

CMOS

100

150

200

100

150

200

Cycle Time (ns)

Figure 2: I (max) Reads

Figure 3: I (max) Writes

September 2003

Document Control # ML0012 rev 0.1

STK11C88

ORDERING INFORMATION

- W F 25 I

STK11C88

Temperature Range

Blank = Commercial (0 to 70°C)

I = Industrial (–40 to 85°C)

Access Time

25 = 25ns

35 = 35ns

45 = 45ns

Lead Finish

Blank = 85%Sn/15%Pb

F = 100% Sn (Matte Tin)

Package

W=Plastic 28-pin 600 mil DIP

P=Plastic 28-pin 300 mil DIP

S=Plastic 28-pin 350 mil SOIC

N=Plastic 28-pin 300 mil SOIC

September 2003

Document Control # ML0012 rev 0.1

STK11C88

Document Revision History

Revision

0.0

Date

December 2002

September 2003

Summary

Removed 20 nsec device

Added lead free lead finish

0.1

September 2003

Document Control # ML0012 rev 0.1

STK11C88-S25I [CYPRESS]

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