U630H16D1C35G1 [CYPRESS]
2KX8 NON-VOLATILE SRAM, 35ns, PDIP28, 0.600 INCH, GREEN, PLASTIC, DIP-28;型号: | U630H16D1C35G1 |
厂家: | CYPRESS |
描述: | 2KX8 NON-VOLATILE SRAM, 35ns, PDIP28, 0.600 INCH, GREEN, PLASTIC, DIP-28 静态存储器 光电二极管 |
文件: | 总15页 (文件大小:152K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Obsolete - Not Recommended for New Designs
U630H16
HardStore 2K x 8 nvSRAM
Features
Description
• High-performance CMOS nonvo- The U630H16 has two separate
further input or output are disabled
until the cycle is completed.
latile static RAM 2048 x 8 bits
• 25, 35 and 45 ns Access Times
• 12, 20 and 25 ns Output Enable
Access Times
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
• Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 106 STORE cycles to EEPROM
• 100 years data retention in
EEPROM
• Automatic RECALL on Power Up The U630H16 is a fast static RAM
• Hardware RECALL Initiation
(RECALL Cycle Time < 20 ms)
• Unlimited RECALL cycles from
EEPROM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
• Unlimited Read and Write to
SRAM
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0to70 ×C
-40to85 ×C
-40to125 °C(only 35 ns)
• QS 9000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
• RoHS compliance and Pb- free
• Packages:SOP28 (300 mil),
PDIP28 (300/600 mil)
Once a STORE cycle is initiated,
Pin Configuration
Pin Description
1
NE
n.c.
A7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
2
Signal Name Signal Description
3
n.c.
A8
4
A6
A0 - A10
Address Inputs
Data In/Out
5
A5
A9
DQ0 - DQ7
6
A4
n.c.
G
Chip Enable
E
7
A3
PDIP
SOP
Output Enable
Write Enable
G
8
A2
A10
E
W
9
A1
10
11
12
13
14
NE
VCC
VSS
Nonvolatile Enable
Power Supply Voltage
Ground
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
VSS
Top View
March 31, 2006
1
Rev 1.0
STK Control #ML0036
U630H16
Block Diagram
EEPROM Array
32 x (64 x 8)
VCC
VSS
STORE
A5
A6
A7
A8
A9
SRAM
Array
RECALL
32 Rows x
64 x 8 Columns
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
Column I/O
Store/
Recall
Control
VCC
Column Decoder
G
NE
A0 A1 A2 A3 A4A10
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
NE
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
*
*
*
H
H
H
High-Z
H
H
H
L
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± ±200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
Output Voltage
VO
PD
V
Power Dissipation
W
Operating Temperature
C-Type
K-Type
A-Type
0
-40
-40
70
85
85
°C
°C
°C
Ta
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Rev 1.0
March 31, 2006
STK Control #ML0036
2
U630H16
Recommended
Symbol
VCC
Conditions
Min.
4.5
Max.
Unit
V
Operating Conditions
Power Supply Voltage
Input Low Voltage
Input High Voltage
5.5
0.8
-2 V at Pulse Width
10 ns permitted
VIL
-0.3
2.2
V
VIH
VCC+0.3
V
C-Type
K-Type
A-Type
Symbol
Conditions
Unit
DC Characteristics
Min. Max. Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC = 5.5 V
VIL
VIH
= 0.8 V
= 2.2 V
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
90
80
75
95
85
80
-
85
-
mA
mA
mA
Average Supply Current during
STOREc
ICC2
VCC = 5.5 V
6
7
7
mA
E
W
≥ VCC-0.2 V
≥ VCC-0.2 V
≤ 0.2 V
VIL
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1 VCC = 5.5 V
E
≥±VIH
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
30
23
20
34
27
23
-
27
-
mA
mA
mA
Average Supply Current
at tcR = 200 nsb
(Cycling CMOS Input Levels)
ICC3
VC
W
VIL
VIH
= 5.5 V
15
15
15
mA
C
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Standby Supply Currentd
ICC(SB) VCC = 5.5 V
1
1
2
mA
(Stable CMOS Input Levels)
E
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c: ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E ≥±VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
March 31, 2006
3
Rev 1.0
STK Control #ML0036
U630H16
Symbol
Conditions
Min.
Max.
Unit
DC Characteristics
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
V
V
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
8
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
μA
μA
=
0 V
-1
-1
Output Leakage Current
VCC
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
1
μA
μA
=
0 V
SRAM Memory Operations
Symbol
25
35
45
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQX
tGLQX
tAXQX
tELICCH
tEHICCL
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Zh
25
25
12
13
13
35
35
20
17
17
45
45
25
20
20
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
5
0
3
0
5
0
3
0
5
0
3
0
G LOW to Output in Low-Z
Output Hold Time after Addr. Changeg
10 Chip Enable to Power Activee
tPU
11 Chip Disable to Power Standbyd, e
tPD
25
35
45
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
Rev 1.0
March 31, 2006
STK Control #ML0036
4
U630H16
f
=
=
VIL, W = NE = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
tcR
(1)
Ai
Address Valid
(2)
ta(A)
DQi
Output
Output Data Valid
Previous Data Valid
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
tcR
(1)
Ai
E
Address Valid
ta(A)
(2)
ta(E)
(3)
tdis(E)
(5)
ten(E)
(7)
G
ta(G)
(4)
tdis(G) (6)
ten(G) (8)
DQi
Output
High Impedance
Output Data Valid
tPD
t
PU (10)
(11)
ACTIVE
ICC
STANDBY
Symbol
25
35
45
Switching Characteristics
Write Cycle
No.
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
25
20
20
0
35
30
30
0
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
tw(W)
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH tsu(W)
tAVWL
tAVEL
tsu(A)
tsu(A-WH)
tsu(E)
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
tAVWH tAVEH
tELWH
20
20
20
12
0
30
30
30
18
0
35
35
35
20
0
tELE
tw(E)
H
tDVWH tDVEH
tWHDX tEHDX
tWHAX tEHAX
tWLQZ
tsu(D)
th(D)
th(A)
0
0
0
tdis(W)
ten(W)
10
13
15
tWHQX
5
5
5
March 31, 2006
5
Rev 1.0
STK Control #ML0036
U630H16
Write Cycle #1: W-controlledj
tcW
(12)
Ai
Address Valid
tsu(E)
(17)
th(A)
(21)
E
tsu(A-WH)
(16)
W
tw(W)
(13)
tsu(D) (19)
Input Data Valid
ten(W)
tsu(A)
(15)
th(D) (20)
DQi
Input
tdis(W)
(22)
(23)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
tsu(A)
(15)
tw(E)
th(A)
(21)
(18)
(14)
tsu(W)
W
th(D)
tsu(D)
(19)
(20)
DQi
Input
Input Data Valid
High Impedance
tdis(W) (22)
ten(E) (7)
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
>
j: E or W and NE must be
V
IH during address transitions.
Rev 1.0
March 31, 2006
STK Control #ML0036
6
U630H16
Nonvolatile Memory Operations
Symbol
Alt. IEC
STORE Cycle Inhibit and
No.
Min.
Max.
Unit
Automatic Power Up RECALL
24 Power Up RECALL Durationk, e
tRESTORE
VSWITCH
650
4.5
μs
Low Voltage Trigger Level
4.0
V
k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE Cycle Inhibit and Automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Mode Selection
E
W
G
NE
Mode
Power
Notes
L
L
H
L
L
L
L
Nonvolatile RECALL
Nonvolatile STORE
Active
ICC2
l
H
L
L
L
H
L
H
L
No operation
Active
*
* H or L
l: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
March 31, 2006
7
Rev 1.0
STK Control #ML0036
U630H16
STORE Cycles
Symbol
No. STORE Cycle W-controlled
Min.
Max.
Unit
Alt.
IEC
25 STORE Cycle Timem
26 STORE Initiation Cycle Timen
27 Output Disable Setup to NE Fall
28 NE Setup
tWLQX
tWLNH
tGHNL
tNLWL
tELWL
td(W)S
tw(W)S
tsu(G)S
tsu(N)S
tsu(E)S
10
ms
ns
ns
ns
ns
25
5
5
29 Chip Enable Setup
5
STORE Cycle: W-controlledo
NE
G
tsu(G)S
(27)
tsu(N)S
(28)
tw(W)S
(26)
W
tsu(E)S
(29)
E
td(W)S
(25)
DQi
High Impedance
Output
Symbol
IEC
No. STORE Cycle E-controlled
Min.
Max.
Unit
Alt.
30 STORE Cycle Time
31 STORE Initiation Cycle Time
32 Output Disable Setup to E Fall
33 NE Setup
tELQXS
tELNHS
tGHEL
tNLEL
td(E)S
tw(E)S
10
ms
ns
ns
ns
ns
25
5
tsu(G)S
tsu(N)S
tsu(W)S
5
34 Write Enable Setup
tWLEL
5
STORE Cycle: E-controlledo
tsu(N)S
(33)
NE
G
t
su(G)S (32)
tsu(W)S
(34)
W
E
tw(E)S (31)
td(E)S
(30)
DQi
High Impedance
Output
Rev 1.0
March 31, 2006
STK Control #ML0036
8
U630H16
RECALL Cycles
Symbol
No. RECALL Cycle NE-controlled
Min.
Max.
Unit
Alt.
IEC
35 RECALL Cycle Timep
36 RECALL Initiation Cycle Timeq
37 Output Enable Setup
38 Write Enable Setup
tNLQX
tNLNH
tGLNL
tWHNL
tELNL
tNLQZ
td(N)R
20
μs
ns
ns
ns
ns
ns
tw(N)R
tsu(G)R
tsu(W)R
tsu(E)R
tdis(N)R
25
5
5
39 Chip Enable Setup
5
40 NE Fall to Output Inactive
25
RECALL Cycle: NE-controlledo
tw(N)R
(36)
NE
tsu(G)R
(37)
G
W
E
tsu(W)R
(38)
tdis(N)R
(40)
tsu(E)R
td(N)R
(35)
(39)
High Impedance
DQi
Output
Symbol
No. RECALL Cycle E-controlled
Min.
Max.
Unit
Alt.
IEC
41 RECALL Cycle Time
42 RECALL Initiation Cycle Time
43 NE Setup
tELQXR
tELNHR
tNLEL
td(E)R
tw(E)R
20
μs
ns
ns
ns
ns
25
5
tsu(N)R
tsu(G)R
tsu(W)R
44 Output Enable Setup
45 Write Enable Setup
tGLEL
5
tWHEL
5
RECALL Cycle: E-controlledo
tsu(N)R
(43)
NE
G
tsu(G)R (44)
tsu(W)R
(45)
W
E
tw(E)R
(42)
td(E)R
(41)
DQi
Output
High Impedance
March 31, 2006
9
Rev 1.0
STK Control #ML0036
U630H16
Symbol
No. RECALL Cycle G-controlled
Min.
Max.
Unit
Alt.
IEC
46 RECALL Cycle Time
47 RECALL Initiation Cycle Time
48 NE Setup
tGLQXR
tGLNH
tNLGL
tWHGL
tELGL
td(G)R
tw(G)R
tsu(N)R
tsu(W)R
tsu(E)R
20
μs
ns
ns
ns
ns
25
5
49 Write Enable Setup
50 Chip Enable Setup
5
5
RECALL Cycle: G-controlledo, r
tsu(N)R
(48)
NE
G
tw(G)R
(47)
tsu(W)R
W
E
(49)
tsu(E)R
(50)
td(G)R
(46)
High Impedance
DQi
Output
m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are inhibited/aborted by VCC < VSWITCH
(STORE inhibit).
n: Once tw(W)S has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W and E may be used to
terminate the STORE initiation cycle.
o: If E is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated.
For E-controlled STORE during tw(E)S W, G, NE have to be static.
p: Measured with W and NE both HIGH, and G and E LOW.
q: Once tw(N)R has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to
terminate the RECALL initiation cycle.
r: If W is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL.
Rev 1.0
March 31, 2006
STK Control #ML0036
10
U630H16
Test Configuration for Functional Check
5 V
t
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
480
VIH
VIL
VO
s
30 pF
NE
E
W
G
255
VSS
s: In measurement of tdis-times and ten-times the capacitance is 5 pF.
t: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC = 5.0 V
Input Capacitance
CI
8
7
pF
VI
f
= VSS
= 1 MHz
= 25 °C
Output Capacitance
CO
pF
Ta
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
Type
U630H16
S
C
25 G1
Leadfree Option
blank= Standard Package
Package
D = PDIP28 (300 mil)
G1 = Leadfree Green Package
u
D1= PDIP28 (600 mil)
S = SOP28 (300 mil)
Access Time
25 = 25 ns
35 = 35 ns (C/K Type on special request)
45 = 45 ns
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
A = -40 to 125 °C (only 35 ns and SOP28 package)
u: on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
U630H16SC
25 Z 0425
G1
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Internal Code
Leadfree Green Package
March 31, 2006
11
Rev 1.0
STK Control #ML0036
U630H16
Device Operation
disturb SRAM data. During a STORE cycle, previous
nonvolatile data is erased and the SRAM contents are
then programmed into nonvolatile elements. Once a
STORE cycle is initiated, further input and output is
disabled and the DQ0 - 7 pins are tristated until the
cycle is completed.
If E and G are LOW and W and NE are HIGH at the
end of the cycle, a READ will be performed and the out-
puts will go active, indicating the end of the STORE.
The U630H16 has two separate modes of operation:
SRAM mode and nonvolatile mode, determined by the
state of the NE pin. In SRAM mode, the memory opera-
tes as a standard fast static RAM. In nonvolatile mode,
data is transferred from SRAM to EEPROM (the
STORE operation) or from EEPROM to SRAM (the
RECALL operation). In this mode SRAM functions are
disabled.
Hardware Nonvolatile RECALL
SRAM READ
A RECALL cycle is performed when E, G and NE are
LOW while W is HIGH. Like the STORE cycle, RECALL
is initiated when the last of the three clock-signals goes
to the RECALL state. Once initiated, the RECALL cycle
will take „RECALL Cycle Time“ to complete, during
which all inputs are ignored. When the RECALL com-
pletes, any READ or WRITE state on the input pins will
take effect.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL in no way alters the data in the nonvolatile
cells. The nonvolatile data can be recalled an unlimited
number of times.
The U630H16 performs a READ cycle whenever E and
G are LOW while W and NE are HIGH. The address
specified on pins A0 - A10 determines which of the
2048 data bytes will be accessed. When the READ is
initiated by an address transition, the outputs will be
valid after a delay of tcR. If the READ is initiated by E or
G, the outputs will be valid at ta(E) or at ta(G), whichever
is later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W or NE is brought LOW.
SRAM WRITE
Like the STORE cycle, a transition must occur on some
control pins to cause a RECALL, preventing inadver-
tend multi-triggering.
A WRITE cycle is performed whenever E and W are
LOW and NE is HIGH. The address inputs must be sta-
ble prior to entering the WRITE cycle and must remain
stable until either E or W goes HIGH at the end of the
cycle. The data on pins DQ0 - 7 will be written into the
memory if it is valid tsu(D) before the end of a W control-
led WRITE or tsu(D) before the end of an E controlled
WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Automatic Power Up RECALL
On power up, once VCC exceeds the sense voltage of
VSWITCH, a RECALL cycle is automatically initiated. The
voltage on the VCC pin must not drop below VSWITCH
once it has risen above it in order for the RECALL to
operate properly. Due to this automatic RECALL,
SRAM operation cannot commence until tRESTORE after
VCC exceeds VSWITCH. If the U630H16 is in a WRITE
state at the end of power up RECALL, the SRAM data
will be corrupted.
Noise Consideration
To help avoid this situation, a 10 KΩ resistor should be
connected between W and system VCC
.
The U630H16 is a high speed memory and therefore
must have a high frequency bypass capacitor of appro-
ximately 0.1 μF connected between VCC and VSS using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise pro-
blems.
Hardware Protection
The U630H16 offers two levels of protection to sup-
press inadvertent STORE cycles. If the control signals
(E, G, W and NE) remain in the STORE condition at the
end of a STORE cycle, a second STORE cycle will not
be started. The STORE (or RECALL) will be initiated
only after a transition on any one of these signals to the
required state. In addition to multi-trigger protection, the
U630H16 offers hardware protection through VCC
Sense. When VCC < VSWITCH the externally initiated
STORE operation will be inhibited.
Hardware Nonvolatile STORE
A STORE cycle is performed when NE, E and W are
LOW while G is HIGH. While any sequence to achieve
this state will initiate a STORE, only W initiation and E
initiation are practical without risking an unintentional
SRAM WRITE that would
Rev 1.0
March 31, 2006
STK Control #ML0036
12
U630H16
Low Average Active Power
The U630H16 has been designed to draw significantly 1. CMOS or TTL input levels
less power when E is LOW (chip enabled) but the 2. the time during which the chip is disabled (E HIGH)
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
The overall average current drawn by the part depends 6. the VCC level
on the following items:
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
March 31, 2006
13
Rev 1.0
STK Control #ML0036
U630H16
LIFE SUPPORT POLICY
Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the Simtek product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However, Simtek makes
no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or
damage of whatever nature resulting from the use of, or reliance upon it. The information in this document descri-
bes the type of component and shall not be considered as assured characteristics.
Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms
and conditions of sale.
Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
March 31, 2006
Change record
Date/Rev
Name
Change
01.11.2001 Ivonne Steffens
format revision and release for „Memory CD 2002“
11.08.2003 Matthias Schniebel
adding A-Type with ICC1 = 85mA; ICC2 = 7mA; ICC3 = 15mA;
ICC(SB) = 2mA; ICC(SB)1 = 27 mA
20.04.2004 Matthias Schniebel
adding „Leadfree Green Package“ to ordering information
adding „Device Marking“
6
7.4.2005
Stefan Günther
changing to 10 endurance cycles and 100a data retention, delete ESD
classes, change ordering code, PDIP 300 on special request, RoHS
and Pb- free added, C/K limitation for PDIP deleted
31.3.2006
1.0
Troy Meester
Simtek
changed to obsolete status
Assigned Simtek Document Control Number
相关型号:
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