U634H256CD1K45G1 [CYPRESS]
32KX8 NON-VOLATILE SRAM, 45ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32;
| 型号： | U634H256CD1K45G1 |
| 厂家： | 
CYPRESS |
| 描述： | 32KX8 NON-VOLATILE SRAM, 45ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U634H256
PowerStore 32K x 8 nvSRAM
Packages:PDIP32 (600 mil)
SOP32 (300 mil)
Transfers from the EEPROM to the
SRAM (the RECALL operation) take
place automatically on power up.
The U634H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
Features
High-performance CMOS non-
Description
volatile static RAM 32768 x 8 bits
25, 35 and 45 ns Access Times
10, 15 and 20 ns Output Enable
Access Times
ICC = 15 mA at 200 ns Cycle Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
The U634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
integrity.
STORE cycles also may be initiated
under user control via a software
sequence or via a single pin (HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
Unlimited RECALL cycles from
EEPROM
The U634H256 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 µF capacitor.
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Pin Configuration
Pin Description
VCAP
A14
A12
A7
1
2
3
4
5
6
7
8
VCCX
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Signal Name Signal Description
HSB
W
A0 - A14
Address Inputs
Data In/Out
A13
A8
DQ0 - DQ7
A6
A5
A9
Chip Enable
E
A4
A11
Output Enable
Write Enable
PDIP
SOP
G
A3
G
W
n.c.
A2
9
10
n.c.
A10
E
VCCX
VSS
VCAP
Power Supply Voltage
Ground
A1
A0
DQ0
DQ1
DQ2
VSS
11
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
Capacitor
Hardware Controlled Store/Busy
HSB
Top View
1
December 12, 1997
U634H256
Block Diagram
VCCX
VSS
EEPROM
Array
A5
A6
A7
A8
VCAP
STORE
RECALL
SRAM
Array
VCCX
VCAP
Power
Control
A9
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
Store/
Recall
Control
HSB
DQ0
DQ1
Column I/O
DQ2
DQ3
DQ4
Software
Detect
Column Decoder
A0 - A13
DQ5
DQ6
A0 A1 A2 A3 A4A10
G
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
HSB
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
H
H
H
H
High-Z
*
*
H
H
High-Z
H
L
L
*
Data Outputs Low-Z
Data Inputs High-Z
Write
*H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
C-Type
K-Type
0
-40
70
85
°C
°C
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
December 12, 1997
U634H256
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltageb
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
Input Low Voltage
Input High Voltage
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentc
ICC1
VCC
VIL
VIH
= 5.5 V
= 0.8 V
= 2.2 V
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
95
75
65
100
80
70
mA
mA
mA
Average Supply Current during
STOREc
ICC2
VCC
E
= 5.5 V
≤ 0.2 V
6
7
mA
W
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Average Supply Current during
PowerStore Cycle
ICC4
VCC
VIL
= 4.5 V
= 0.2 V
4
4
mA
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1 VCC
E
= 5.5 V
= VIH
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
40
36
33
42
38
35
mA
mA
mA
Operating Supply Current
at tcR = 200 nsc
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
15
15
mA
≥ VCC-0.2 V
Standby Supply Curentd
ICC(SB) VCC
= 5.5 V
3
3
mA
(Stable CMOS Input Levels)
E
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
b: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is con-
nected to ground.
c:
I
CC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
CC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
I
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION able.
The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
3
December 12, 1997
U634H256
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
8
2.4
8
V
V
0.4
-4
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
1
µA
µA
=
0 V
-1
-1
-1
-1
Output Leakage Current
VCC
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
1
1
µA
µA
=
0 V
SRAM MEMORY OPERATIONS
Symbol
25
35
45
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tcR
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
ta(A)
ta(E)
ta(G)
25
25
10
10
10
35
35
15
13
13
45
45
20
15
15
Output Enable Access Time to Data Valid tGLQV
E HIGH to Output in High-Zh
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
tEHQZ tdis(E)
tGHQZ tdis(G)
tELQX ten(E)
tGLQX ten(G)
5
0
3
0
5
0
3
0
5
0
3
0
G LOW to Output in Low-Z
Output Hold Time after Address Change
tAXQX
tELICCH tPU
tEHICCL tPD
tv(A)
10 Chip Enable to Power Activee
11 Chip Disable to Power Standbyd, e
25
35
45
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
4
December 12, 1997
U634H256
f
=
=
VIL, W = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
1
tcR
Ai
Address Valid
2
ta(A)
DQi
Output
Previous
Data Valid
Output Data
Valid
9
tv(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
1
tcR
Address Valid
Ai
2
11
ta(A)
tPD
3
ta(E)
5
tdis(E)
E
7
ten(E)
4
ta(G)
G
6
tdis(G)
8
DQi
Output
ten(G)
High Impedance
Output Data
Valid
10
tPU
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
25
35
45
Switching Characteristics
Write Cycle
No.
Unit
IEC
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
25
20
20
0
35
25
25
0
45
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVWL tAVEL
tAVWH tAVEH
tELWH
tsu(A-WH)
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
20
20
20
10
0
25
25
25
12
0
30
30
30
15
0
tsu(E)
tw(E)
tsu(D)
th(D)
tELEH
tDVWH tDVEH
tWHDX tEHDX
tWHAX tEHAX
tWLQZ
th(A)
0
0
0
tdis(W)
ten(W)
10
13
15
tWHQX
5
5
5
5
December 12, 1997
U634H256
Write Cycle #1: W-controlledj
12
tcW
Ai
E
Address Valid
21
th(A)
17
tsu(E)
16
tsu(A-WH)
13
tw(W)
W
15
19
20
tsu(A)
tsu(D)
th(D)
Input Data
Valid
DQi
Input
22
tdis(W)
23
ten(W)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
12
tcW
Ai
Address Valid
15
21
th(A)
18
tw(E)
tsu(A)
E
14
tsu(W)
W
19
tsu(D)
20
th(D)
Input Data
Valid
DQi
Input
DQi
High Impedance
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
6
December 12, 1997
U634H256
NONVOLATILE MEMORY OPERATIONS
MODE SELECTION
A13 - A0
(hex)
E
W
HSB
Mode
I/O
Power
Notes
H
L
L
L
X
H
L
H
H
H
H
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
l
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
k, l
k, l
k, l
k, l
k, l
k
Nonvolatile STORE
L
H
X
H
L
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
Nonvolatile RECALL
X
X
STORE/Inhibit
Output High Z
I
CC2/Standby
m
k: The six consecutive addresses must be in order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a Store cycle or (0E38, 31C7, 03E0, 3C1F,
303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and dia-
grams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any)
completes, the part will go into standby mode inhibiting all operation until HSB rises.
Symbol
PowerStore Power Up RECALL/
No.
Conditions
Min. Max. Unit
Hardware Controlled STORE
Alt.
IEC
24 Power Up RECALL Durationn, e
25 STORE Cycle Duration
26 HSB Low to Inhibit One
27 HSB High to Inhibit Offe
28 External STORE Pulse Widthe
HSB Output Low Currente,o
HSB Output High Currente, o
Low Voltage Trigger Level
tRESTORE
tHLQX
650
10
µs
ms
µs
ns
>
td(H)S
tdis(H)S
ten(H)S
tw(H)S
VCC 4.5 V
tHLQZ
1
tHHQX
700
tHLHX
20
3
ns
IHSBOL
IHSBOH
VSWITCH
HSB = VOL
HSB = VIL
mA
µA
V
5
60
4.0
4.5
n:
tRESTORE starts from the time VCC rises above VSWITCH.
o: HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 U634H256 to be ganged
together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other U634H256 HSB pins.
7
December 12, 1997
U634H256
PowerStore and automatic Power Up RECALL
VCAP
5.0 V
VSWITCH
t
PowerStore
Power Up
p
tPDSTORE
24
24
RECALL
tRESTORE
tRESTOR
E
W
p
tDELAY
DQi
BROWN OUT
NO STORE
(NO SRAM WRITES)
BROWN OUT
PowerStore
POWER UP
RECALL
Hardware Controlled STORE
HSB
28
tw(H)S
q
27
ten(H)S
26
tdis(H)S
DQi
High Impedance
Previous Data Valid
Data Valid
Output
25
td(H)S
Symbol
25
35
45
Software Controlled STORE/
RECALL Cycle
No.
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
29 STORE/RECALL Initiation Time
30 Chip Enable to Output Inactives
31 STORE Cycle Time
tAVAV
tELQZ
tcR
tdis(E)SR
td(E)S
25
35
45
ns
ns
ms
µs
ns
ns
ns
600
10
600
10
600
10
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
32 RECALL Cycle Timer
td(E)R
20
20
20
33 Address Setup to Chip Enablet
34 Chip Enable Pulse Widths, t
35 Chip Disable to Address Changet
tsu(A)SR
tw(E)SR
th(A)SR
0
20
0
0
25
0
0
30
0
p: tPDSTORE approximate td(E)S or td(H)S; tDELAY approximate tdis(H)S
q: After tw(H)S HSB is hold down internal by STORE operation.
.
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
SWITCH once it has been exceeded for the RECALL to function properly.
V
s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
t: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
8
December 12, 1997
U634H256
SOFTWARE CONTROLLED STORE/RECALL CYCLEt, u, v, w (E = HIGH after STORE initiation)
29
tcR
29
tcR
ADDRESS 1
ADDRESS 6
Ai
E
35
th(A)SR
34
34
tw(E)SR
tw(E)SR
35
th(A)SR
33
tsu(A)SR
5
33
tsu(A)SR
tdis(E)
31
/
32
td(E)S / td(E)R
High Impedance
VALID
VALID
DQi
Output
30
tdis(E)SR
SOFTWARE CONTROLLED STORE/RECALL CYCLEt, u, v, w (E = LOW after STORE initiation)
29
tcR
ADDRESS 1
ADDRESS 6
Ai
E
35
th(A)SR
34
tw(E)SR
33
tsu(A)SR
33
35
tsu(A)SR
th(A)SR
31
/
32
td(E)S / td(E)R
High Impedance
DQi
Output
VALID
VALID
30
tdis(E)SR
u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
9
December 12, 1997
U634H256
Test Configuration for Functional Check
5 V
Y
VCCX
VCAP
A0
A1
A2
A3
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A5
480
A6
A7
VIH
A8
A9
A10
A11
A12
A13
VIL
VO
A14
30 pF x
HSB
E
HSB
W
255
G
VSS
x: In measurement of tdis-times and ten-times the capacitance is 5 pF.
y: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC = 5.0 V
Input Capacitance
CI
8
pF
VI
f
= VSS
= 1 MHz
= 25 °C
Output Capacitance
CO
7
pF
Ta
All Pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U634H256
S
C
25
C
Type
ESD Class
V z
B > 1000
C > 500 V
Access Time
25 = 25 ns
35 = 35 ns (on special request)
45 = 45 ns (on special request)
Package
D1= PDIP (600 mil)
S = SOP (300 mil)
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
z: ESD protection > 1000 V and 2000 V under development
10
December 12, 1997
U634H256
Device Operation
and initiate a STORE operation.
Figure 1 shows the proper connection of capacitors for
automatic STORE operation. The charge storage capa-
citor should have a capacity of at least 100 µF (± 20 %)
at 6 V.
Each U634H256 must have its own 100 µF capacitor.
Each U634H256 must have a high quality, high fre-
quency bypass capacitor of 0.1 µF connected between
The U634H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates In SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
V
CAP and VSS, using leads and traces that are short as
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also auto-
matically initiated when the power supply voltage level
of the chip falls below VSWITCH. RECALL operations are
automatically initiated upon power up and may also
occur when the VCCX rises above VSWITCH, after a low
power condition. RECALL cycles may also be initiated
by a software sequence.
possible. This capacitor do not replace the normal
expected high frequency bypass capacitor between the
power supply voltage and VSS
.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITES have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
SRAM READ
The U634H256 performs a READ cycle whenever E
and G are LOW and HSB and W are HIGH. The
address specified on pins A0 - A14 determines which of
the 32768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of tcR. If the READ is initiated
AUTOMATIC RECALL
During power up, an automatic RECALL takes place.
At a low power condition (power supply voltage <
by E or G, the outputs will be valid at ta(E) or at ta(G)
,
whichever is later. The data outputs will repeatedly
respond to address changes within the tcR access time
without the need for transition on any control input pins,
and will remain valid until another address change or
until E or G is brought HIGH or W or HSB is brought
LOW.
VSWITCH) an internal RECALL request may be latched.
As soon as power supply voltage exceeds the sense
voltage of VSWITCH, a requested RECALL cycle will
automatically be initiated and will take tRESTORE to com-
plete.
If the U634H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pins DQ0 - 7 will be written
into the memory if it is valid tsu(D) before the end of a W
controlled WRITE or tsu(D) before the end of an E con-
trolled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
SOFTWARE NONVOLATILE STORE
The U634H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U634H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
AUTOMATIC STORE
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
During normal operation, the U634H256 will draw cur-
rent from VCCX to charge up a capacitor connected to
the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the VCCX pin drops below VSWITCH, the part
will automatically disconnect the VCAP pin from VCCX
11
December 12, 1997
U634H256
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex) Valid READ
31C7 (hex) Valid READ
03E0 (hex) Valid READ
3C1F (hex) Valid READ
303F (hex) Valid READ
0FC0 (hex) Initiate STORE
the STORE operation will begin immediately.
HARDWARE-STORE-BUSY (HSB) is a high speed,
low drive capability bidirectional control line.
In order to allow a bank of U634H256s to perform syn-
chronized STORE functions, the HSB pin from a num-
ber of chips may be connected together. Each chip
contains a small internal current source to pull HSB
HIGH when it is not being driven LOW. To decrease the
sensitivity of this signal to noise generated on the PC
board, it has to be pulled to power supply via an exter-
nal resistor with a value such that the combined load of
the resistor and all parallel chip connections does not
exceed IHSBOL at VOL (see Figure 1 and 2).
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
If HSB is to be connected to external circuits other than
other U634H256s, an external pull-up resistor has to be
used.
SOFTWARE NONVOLATILE RECALL
During any STORE operation, regardless of how it was
initiated, the U634H256 will continue to drive the HSB
pin LOW, releasing it only when the STORE is com-
plete.
Upon completion of a STORE operation, the part will be
disabled until HSB actually goes HIGH.
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
HARDWARE PROTECTION
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex) Valid READ
31C7 (hex) Valid READ
03E0 (hex) Valid READ
3C1F (hex) Valid READ
303F (hex) Valid READ
0C63 (hex) Initiate RECALL
The U634H256 offers hardware protection against
inadvertent STORE operation during low voltage condi-
tions. When VCAP < VSWITCH, all software or HSB initia-
ted STORE operations will be inhibited.
PREVENTING AUTOMATIC STORES
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
an unlimited number of times.
The PowerStore function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15 mA at VOH of at least 2.2 V as it will have to overpo-
wer the internal pull-down device that drives HSB LOW
for 50 ns at the onset of an PowerStore.
When the U634H256 is connected for PowerStore ope-
ration (see Figure 1) and VCCX crosses VSWITCH on the
way down, the U634H256 will attempt to pull HSB
LOW; if HSB doesn′t actually get below VIL, the part will
stop trying to pull HSB LOW and abort the PowerStore
attempt.
HSB NONVOLATILE STORE
The hardware controlled STORE Busy pin (HSB) is
connected to an open drain circuit acting as both input
and output to perform two different functions. When
driven LOW by the internal chip circuitry it indicates that
a STORE operation (initiated via any means) is in pro-
gress within the chip. When driven LOW by external cir-
cuitry for longer than tw(H)S, the chip will conditionally
DISABELING AUTOMATIC STORES
If the PowerStore function is not required, then VCAP
should be tied directly to the power supply and VCCX
should by tied to ground. In this mode, STORE opera-
tion may be triggered through software control or the
HSB pin. In either event, VCAP (Pin 1) must always
have a proper bypass capacitor connected to it (Figure
2).
initiate a STORE operation after tdis(H)S
.
READ and WRITE operations that are in progress
when HSB is driven LOW (either by internal or external
circuitry) will be allowed to complete before the STORE
operation is performed, in the following manner.
After HSB goes LOW, the part will continue normal
SRAM operation for tdis(H)S. During tdis(H)S, a transition
on any address or control signal will terminate SRAM
operation and cause the STORE to commence.
Note that if an SRAM WRITE is attempted after HSB
has been forced LOW, the WRITE will not occur and
12
December 12, 1997
U634H256
DISABELING AUTOMATIC STORES: STORE CYCLE INHIBIT and AUTOMATIC POWER UP RECALL
VCAP
5.0 V
VSWITCH
t
STORE inhibit
24
Power Up
RECALL
tRESTORE
Power
Supply
VCAP
VCCX
HSB
VCAP
VCCX
HSB
10 kΩ
Power
Supply
1
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(optional,
2
2
mandatory if HSB
is used with
external circuitry)
10 kΩ
3
3
(optional,
mandatory if HSB
is used with
external circuitry)
4
4
5
5
6
6
+
7
8
9
10
11
12
13
14
7
8
9
10
11
12
13
14
100 µF
± 20 % Bypass
0.1 µF
0.1 µF
Bypass
15
16
15
16
VSS
VSS
Figure 1: AUTOMATIC STORE OPERATION
Figure 2: DISABELING AUTOMATIC STORES
Schematic Diagram
Schematic Diagram
LOW AVERAGE ACTIVE POWER
The U634H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
When E is HIGH the chip consumes only standby cur- 4. the ratio of READs to WRITEs
rent. 5. the operating temperature
The overall average current drawn by the part depends 6. the power supply voltage level
on the following items:
13
December 12, 1997
Memory Products 1998
PowerStore 32K x 8 nvSRAM U634H256
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
The information describes the type of component and shall not be considered as
assured characteristics.
Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH
Grenzstraße 28 • D-01109 Dresden• P. O.B. 800134 •D-01101 Dresden•Germany
Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de
Internet Web Site: http://www.zmd.de
相关型号：
©2020 ICPDF网 联系我们和版权申明