UL62H1616A20 [CYPRESS]
SRAM,;
| 型号： | UL62H1616A20 |
| 厂家： | 
CYPRESS |
| 描述： | SRAM, 静态存储器 |
| 文件： | 总9页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
UL62H1616B
Low Voltage Automotive Fast 64K x 16 SRAM
Features
Description
F 65536 x 16 bit static CMOS RAM
F 15 and 20 ns Access Time
F Common data inputs and
data outputs
F Three-state outputs
F Standby current < 50 µA at 125°C - Word Read
F Power supply voltage 2.5 V
F Operating temperature range
K-Type:-40 °C to 85 °C
The UL62H1616B is a static RAM
G. If LB = L the data lower byte will
be available at the outputs DQ0-
DQ7, on UB = L the data upper
byte appear at the outputs DQ8-
DQ15. After the address change,
the data outputs go High-Z until the
new information is available. The
data outputs have no preferred
state. The Read cycle is finished by
the falling edge of W, or by the
rising edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Lower / Upper Byte Read
- Lower / Upper Byte Write
- Word Write
- Standby
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L and W = H each address
change leads to a new Read cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
A-Type:-40 °C to 125 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity >100 mA
F Package: SOP44 (525 mil)
Pin Configuration
Pin Description
A5
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A6
A7
G
2
A2
3
A1
4
UB
A0
5
LB
E
6
Signal Name Signal Description
DQ15
DQ14
DQ13
DQ12
VSS
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
W
7
A0 - A15
Address Inputs
8
9
DQ0 - DQ15
Data In/Out
10
11
12
13
14
15
16
17
18
19
20
21
22
Chip Enable
E
Output Enable
Write Enable
G
SOP
VCC
W
DQ11
DQ10
UB
LB
Upper Byte Enable
Lower Byte Enable
Power Supply Voltage
Ground
DQ9
DQ8
VCC
VSS
n.c.
n.c.
A8
A15
A14
A13
A12
n.c.
A9
not connected
A10
A11
n.c.
Top View
November 01, 2001
1
UL62H1616B
Preliminary
Block Diagram
A7
DQ0
DQ1
A8
A9
A4
A11
A12
A13
A14
A15
Memory Cell
Array
DQ2
DQ3
DQ4
512 Rows x
128 x 16 Columns
DQ5
DQ6
DQ7
A0
A1
A2
DQ8
DQ9
DQ10
A3
A10
A5
Sense Amplifier/
Write Control Logic
A6
DQ11
DQ12
DQ13
Address
Change
Detector
Clock
Generator
DQ14
DQ15
Truth Table
VCC
VSS
E
W
G UB LB
Operating Mode
E
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Standby/not selected
H
*
*
*
*
High-Z
High-Z
High-Z
L
L
H
*
H
*
*
H
*
H
Internal Read
High-Z
Lower Byte Read
Upper Byte Read
Word Read
L
L
L
L
L
L
H
H
H
L
L
L
L
*
L
H
L
H
L
L
H
L
L
Data Outputs Low-Z
High-Z
High-Z
Data Outputs Low-Z
Data Outputs Low-Z Data Outputs Low-Z
Lower Byte Write
Upper Byte Write
Word Write
L
Data Inputs High-Z
High-Z
High-Z
L
*
H
L
Data Inputs High-Z
Data Inputs High-Z
L
*
Data Inputs High-Z
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.2 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
-
3.6
VCC + 0.3
VCC + 0.3
1
V
V
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
°C
K-Type
A-Type
-40
-40
85
125
Storage Temperature
Tstg
-65
150
°C
Output Short-Circuit Current
at VCC = 2.5 V and VO = 0 V**
| IOS
|
100
mA
**Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
2
November 01, 2001
Preliminary
UL62H1616B
Recommended
Operating Conditions
Symbol
VCC
Conditions
Min.
2.3
Max.
2.7
Unit
V
Power Supply Voltage
Input Low Voltage*
VIL
-0.2
2.0
0.6
V
Input High Voltage
VIH
VCC + 0.2
V
*
-2 V at Pulse Width 10 ns
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
VIH
tcW
tcW
tcW
= 2.7 V
= 0.6 V
= 2.0 V
= 35 ns
= 55 ns
= 60 ns
90
70
60
mA
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
VE
= 2.7 V
= VCC - 0.2 V
50
µA
Supply Current - Standby Mode
(LVTTL level)
ICC(SB)1
VCC
VE
= 2.7 V
= 2.0 V
K-Type
A-Type
10
20
mA
mA
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 2.3 V
= -0.5 mA
= 2.3 V
2.0
V
V
0.4
2
= 0.5 mA
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 2.7 V
= 2.7 V
= 2.7 V
µA
µA
-2
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 2.3 V
= 2.0 V
= 2.3 V
= 0.4 V
-0.5
mA
mA
0.5
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 2.7 V
= 2.7 V
= 2.7 V
2
µA
µA
Low at Three-State Outputs
-2
=
0 V
November 01, 2001
3
UL62H1616B
Preliminary
Symbol
15
20
Switching Characteristics
Read Cycle
Unit
Min.
Max.
Min.
Max.
Alt.
tRC
tAA
tACE
tOE
IEC
tcR
Read Cycle Time
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
ta(A)
15
15
7
20
20
9
ta(E)
ta(G)
ta(B)
LB, UB LOW to Data Valid
tB
7
9
E HIGH to Output in High-Z
G HIGH to Output in High-Z
LB, UB HIGH to Output in High-Z
E LOW to Output in Low-Z
tHZCE
tHZOE
tHZB
tLZCE
tLZOE
tLZB
tOH
tdis(E)
tdis(G)
tdis(B)
ten(E)
ten(G)
ten(B)
tv(A)
7
8
7
8
7
8
4
0
0
3
0
4
0
0
3
0
G LOW to Output in Low-Z
LB, UB LOW to Output in Low-Z
Output Hold Time from Address Change
E LOW to Power-Up Time
tPU
E HIGH to Power-Down Time
tPD
15
20
Symbol
15
20
Switching Characteristics
Write Cycle
Unit
Min.
15
10
10
0
Max.
Min.
20
12
12
0
Max.
Alt.
tWC
IEC
tcW
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
tWP
tw(W)
tsu(W)
tsu(A)
Write Setup Time
tWP
Address Setup Time
tAS
t
Address Valid to End of Write
Chip Enable Setup Time
Byte Enable Setup Time
Pulse Width Chip Enable to End of Write
Pulse Width Byte Enable to End of Write
Data Setup Time
tAW
10
10
10
10
10
7
12
12
12
12
12
9
su(A-WH)
tCW
tsu(E)
tBW
tsu(B)
tw(E)
tCW
tBW
tw(B)
tDS
tsu(D)
th(D)
Data Hold Time
tDH
0
0
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
tAH
th(A)
0
0
tHZWE
tHZOE
tLZWE
tLZOE
tdis(W)
tdis(G)
ten(W)
ten(G)
7
7
8
8
3
0
3
0
4
November 01, 2001
Preliminary
UL62H1616B
Data Retention Mode
E - controlled
VCC
2.3 V
VCC(DR) ≥ 1.5 V
2.0 V
2.0 V
tsu(DR)
trec
Data Retention
E
0 V
V
- 0.2 V ≤ V
≤ V
+ 0.3 V
CC(DR)
CC(DR)
E(DR)
Data Retention
Characteristics
Symbol
Alt. IEC
VCC(DR)
ICC(DR) VCC(DR) = 2 V
Conditions
Min. Typ. Max.
Unit
Data Retention Supply Voltage
Data Retention Supply Current
1.5
2.7
30
V
µA
VE = VCC(DR) - 0.2 V
Data Retention Setup Time
Operating Recovery Time
tCDR
tR
tsu(DR) See Data Retention
0
ns
ns
Waveforms (above)
trec
tcR
Test Configuration for Functional Check
2.5 V
A0
VCC
A1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
A2
A3
A4
A5
481
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VIH
VIL
VO
30 pF1)
E
W
G
LB
UB
255
DQ15
VSS
1)
In measurement of t
,t
, t
, t
, t
the capacitance is 5 pF.
dis(E) dis(W) en(E) en(W) en(G)
November 01, 2001
5
UL62H1616B
Preliminary
Capacitance
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
VCC
VI
f
= 2.5 V
= VSS
= 1 MHz
= 25 °C
CI
7
7
pF
Output Capacitance
Co
pF
T
a
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
UL62H1616
S
15
A
Type
Access Time
15 = 15 ns
Package
S = SOP44 525 mil
20 = 20 ns
Operating Temperature Range
K = -40 to 85 °C
A = -40 to 125 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
6
November 01, 2001
Preliminary
UL62H1616B
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)
tcR
Ai
Address Valid
ta(A)
DQi
Output Data Valid
Previous Data Valid
Output
tv(A)
Read Cycle 2: G-, E-, LB-, UB-controlled (during Read Cycle: W = VIH)
tcR
Ai
E
Address Valid
ta(E)
tsu(A)
tdis(E)
ten(E)
ten(G)
ten(B)
tdis(G)
ta(G)
G
tdis(B)
ta(B)
LB, UB
DQi
Output
High-Z
tPU
Output Data Valid
tPD
ICC(OP)
ICC(SB)
50 %
50 %
Write Cycle1: W-controlled
tcW
Ai
E
Address Valid
tsu(E)
th(A)
tsu(B)
LB, UB
W
tsu(A-WH)
tw(W)
tsu(A)
tsu(D)
th(D)
DQi
Input
Input Data Valid
ten(W)
tdis(W)
DQi
High-Z
Output
G
November 01, 2001
7
UL62H1616B
Preliminary
Write Cycle 2: E-controlled
tcW
Ai
E
Address Valid
tw(E)
tsu(A)
th(A)
tsu(B)
LB, UB
W
tsu(W)
tsu(D)
th(D)
DQi
Input
Input Data Valid
High-Z
tdis(W)
ten(E)
DQi
Output
tdis(G)
G
Write Cycle 3: LB-, UB-controlled
tcW
Ai
Address Valid
tsu(E)
E
tsu(A)
th(A)
tw(B)
LB, UB
tsu(W)
W
th(D)
tsu(D)
DQi
Input
Input Data Valid
High-Z
tdis(W)
ten
(B)
DQi
Output
tdis(G)
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
8
November 01, 2001
Preliminary
UL62H1616B
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
November 01, 2001
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: sales@zmd.de • http://www.zmd.de
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