W133HT [CYPRESS]
Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, 0.300 INCH, SSOP-56;
| 型号： | W133HT |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, 0.300 INCH, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
W133
Spread Spectrum System Frequency Synthesizer
CPU Output Jitter: ......................................................250 ps
Features
CPUdiv2 Output Jitter:.................................................250 ps
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Intel CK98 Specification compliant
• 0.5% downspread outputs deliver up to 10 dB lower EMI
• Four skew-controlled copies of CPU output
• EightcopiesofPCIoutput(synchronousw/CPUoutput)
• Four copies of 66-MHz fixed frequency 3.3V clock
• Two copies of CPU/2 outputs for synchronous memory
reference
48 MHz, 3V66, PCI, IOAPIC Output Jitter:..................500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew:.........................175 ps
PCI_F, PCI1:7 Output Skew:.......................................500 ps
3V66_0:3, IOAPIC0:2 Output Skew; ...........................250 ps
CPU to 3V66 Output Offset:............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
• Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Powermanagementcontrolpinsforclockstopandshut
down
Logic inputs, except SEL133/100#, have 250-kΩ pull-up
resistors.
Table 1. Pin Selectable Frequency[1]
SEL133/100#
CPU0:3 (MHz)
133 MHz
PCI
1
0
33.3 MHz
33.3 MHz
100 MHz
• Available in 56-pin SSOP
Note:
1. See Table 2 for complete mode selection details.
Key Specifications
Supply Voltages:...................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
Pin Configuration
2
GND
REF0
REF1
VDDQ3
X1
X2
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
VDDQ2
IOAPIC2
IOAPIC1
IOAPIC0
GND
1
X1
XTAL
OSC
REF0:1
2
X2
3
4
CPU_STOP#
5
STOP
Clock
Logic
6
VDDQ2
4
2
CPU0:3
7
CPUdiv2_1
CPUdiv2_0
GND
VDDQ2
CPU3
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PCI_F
PCI1
8
9
VDDQ3
PCI2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
÷2
CPUdiv2_0:1
3V66_0:3
SPREAD#
SEL0
PCI3
GND
PLL 1
PCI4
SEL1
STOP
Clock
Logic
4
PCI5
SEL133/100#
÷2/÷1.5
VDDQ3
PCI6
PCI7
1
7
GND
PCI_F
PCI1:7
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL1
3V66_0
3V66_1
VDDQ3
GND
STOP
Clock
Logic
34
33
32
31
30
29
÷2
PWRDWN#
PCI_STOP#
SEL0
25
26
27
28
3V66_2
VDDQ3
48MHz
GND
3V66_3
VDDQ3
3
SEL133/100#
Power
Down
Logic
÷2
IOAPIC0:2
Three-state
Logic
1
PLL2
48MHz
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07166 Rev. *A
Revised December 15, 2002
PRELIMINARY
W133
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CPU0:3
41, 42, 45, 46
O
CPU Clock Outputs 0 through 3: These four CPU clocks run at a frequency set by
SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2.
CPUdiv2_ 0:1
49,50
O
O
O
Synchronous Memory Reference Clock Output 0 through 1: Reference clock for
Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage
swing is set by the voltage applied to VDDQ2.
PCI1:7
PCI_F
9, 11, 12, 14, 15,
17, 18
PCI Clock Outputs 1 through 7: These seven PCI clock outputs run synchronously
to the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7
outputs are stopped when PCI _STOP# is held LOW.
8
PCI_F (PCI Free-running): This PCI clock output runs synchronously to the CPU
clock. Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected
by the state of PCI_STOP#.
REF0:1
2, 3
O
O
O
O
I
14.318-MHz Reference Clock Output: 3.3V copies of the 14.318-MHz reference
clock.
IOAPIC0:2
48MHz
53, 54, 55
I/O APIC Clock Output: Provides 16.67-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
30
48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
3V66_0:3
SEL0:1
21, 22, 25, 26
66-MHz Output 0 through 3: Fixed 66-MHz outputs. Output voltage swing is con-
trolled by voltage applied to VDDQ3.
32, 33
28
5
Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock
output modes.
SEL133/100#
X1
I
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output
frequency as shown in Table 1.
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or an external reference signal.
X2
6
O
I
Crystal Connection: An output connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
SPREAD#
PWRDWN#
CPU_STOP#
34
35
36
Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
I
Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that
requests the device to enter power-down mode.
I
Active LOW CPU Clock Stop: 3.3V LVTTL-compatible asynchronous input that
stops all CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by
this input.
PCI_STOP#
VDDQ3
37
I
Active LOW PCI Clock Stop: 3.3V LVTTL-compatible asynchronous input that
stops all PCI outputs except PCI_F when held LOW.
4, 10, 16, 23, 27,
31, 39
P
PowerConnection:PowersupplyforPCIoutputbuffers,48-MHzUSBoutputbuffer,
Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect
to 3.3V supply.
VDDQ2
GND
43, 47, 51, 56
P
Power Connection: Power supply for IOAPIC, CPU, and CPUdiv2 output buffers.
Connect to 2.5V supply.
1, 7, 13, 19, 20,
24, 29, 38, 40,
44, 48, 52
G
Ground Connection: Connect all ground pins to the common system ground plane.
nous to CPU clock, 48-MHz Universal Serial Bus (USB) clock,
and replicates the 14.31818-MHz reference clock.
Overview
The W133 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel® archi-
tecture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
All CPU, PCI, and IOAPIC clocks can be synchronously mod-
ulated for spread spectrum operations. Cypress employs pro-
prietary techniques that provide the maximum EMI reduction
while minimizing the clock skews that could reduce system
timing margins. Spread Spectrum modulation is enabled by
the active LOW control signal SPREAD#.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W133 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also
provides skew-controlled PCI and IOAPIC clocks synchro-
The W133 also includes power management control inputs.
By using these inputs, system logic can stop CPU and/or PCI
Document #: 38-07166 Rev. *A
Page 2 of 13
PRELIMINARY
W133
clocks or power down the entire device to conserve system
power.
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Spread Spectrum Clocking
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 1.
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% downspread. Figure
2 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Figure 1, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Figure 1. Typical Clock and SSFTG Comparison
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Time
Figure 2. Modulation Waveform Profile
Document #: 38-07166 Rev. *A
Page 3 of 13
PRELIMINARY
W133
Mode Selection Functions
The W133 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs.
Table 2. Select Functions
SEL133/100#
SEL1
SEL0
Function
All Outputs Three-State
(Reserved)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Active 100 MHz, 48 MHz PLL Inactive
Active 100 MHz, 48 MHz PLL Active
Test Mode
(Reserved)
Active 133 MHz, 48 MHz PLL Inactive
Active 133 MHz, 48 MHz PLL Active
Table 3. Truth Table
SEL
133/100# SEL1 SEL0
CPU
CPUdiv2
HI-Z
3V66
HI-Z
PCI
48MHz
HI-Z
n/a
REF
HI-Z
n/a
IOAPIC
HI-Z
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HI-Z
n/a
HI-Z
n/a
2
n/a
n/a
n/a
100 MHz
100 MHz
TCLK/2
n/a
50 MHz
50 MHz
TCLK/4
n/a
66 MHz
66 MHz
TCLK/4
n/a
33 MHz
33 MHz
TCLK/8
n/a
HI-Z
14.318 MHz 16.67 MHz
3
48 MHz 14.318 MHz 16.67 MHz 4, 7, 8
TCLK/2
n/a
TCLK
n/a
TCLK16
n/a
5, 6
133 MHz
133 MHz
66 MHz
66 MHz
66 MHz
66 MHz
33 MHz
33 MHz
HI-Z
14.318 MHz 16.67 MHz
3
48 MHz 14.318 MHz 16.67 MHz 4, 7, 8
Table 4. Maximum Supply Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2=2.625V
Max. 3.3V supply consumption
Max. discrete cap loads,
VDDQ3=3.465V or GND
Condition
All static inputs=VDDQ3 or GND
Powerdown Mode
(PWRDWN#=0)
100 µA
75 mA
200 µA
FUll Active 100MHz
SEL133/100#=0
160 mA
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
Full Active 133MHz
SEL133/100#=0
90 mA
160 mA
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
Notes:
2. Provided for board level “bed of nails” testing.
3. 48-MHz PLL disabled to reduce component jitter.
4. “Normal” mode of operation.
5. TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic.
6. Required for DC output impedance verification.
7. Range of reference frequency is min.=14.316, nominal = 14.31818 MHz, max.=14.32 MHz.
8. Frequency accuracy of 48 MHz is +167 PPM to match USB default.
Document #: 38-07166 Rev. *A
Page 4 of 13
PRELIMINARY
W133
Table 5. Clock Enable Configuration[9, 10, 11, 12, 13, 14]
REF,
PCI PCI_F 48MHz OSC. VCOs
CPU_STOP# PWRDWN# PCI_STOP# CPU CPUdiv2 IOAPIC 3V66
X
0
0
1
1
0
1
1
1
1
X
0
1
0
1
LOW
LOW
LOW
ON
LOW
ON
LOW
ON
LOW LOW LOW
LOW
ON
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
ON
LOW LOW
ON
ON
ON
ON
ON
ON
LOW
ON
ON
LOW
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Table 6. Power Management State Transition[15, 16]
Latency
Signal
Signal State
0 (disabled)
1 (enabled)
0 (disabled)
1 (enabled)
No. of rising edges of PCI Clock
CPU_STOP#
1
1
1
PCI_STOP#
PWRDWN#
1
1 (normal operation)
0 (power down)
3 ms
2 max.
Timing Diagrams
CPU_STOP# Timing Diagram[17, 18, 19, 20, 21, 22]
CPU
(internal)
PCI
CPU_STOP#
PCI_STOP#
HI
HI
PWRDWN#
CPU
(external)
3V66
Notes:
9. LOW means outputs held static LOW as per latency requirement below.
10. ON means active.
11. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
12. All 3V66 as well as all CPU clocks stop cleanly when CPU_STOP# is pulled LOW.
13. CPUdiv2, IOAPIC, REF, 48MHz signals are not controlled by the CPU_STOP# functionality and are enabled in all conditions except PWRDWN#=LOW.
14. An “x” indicates a “don’t care” condition.
15. Clock on/off latency is defined in the number of rising edges of the free-running PCI clock between when the clock disable goes LOW/HIGH to when the first
valid clock comes out of the device.
16. Power up latency is from when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
17. All internal timing is referenced to the CPU clock.
18. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed.
19. CPU_STOP# signal is an input signal that must be made synchronous to free-running PCI_F.
20. 3V66 clocks also stop/start before.
21. PWRDWN# and PCI_STOP# are shown in a HIGH state.
22. Diagrams shown with respect to 133 MHz. Similar operation when CPU clock is 100 MHz.
Document #: 38-07166 Rev. *A
Page 5 of 13
PRELIMINARY
W133
Timing Diagrams (continued)
PCI_STOP# Timing Diagram[17, 18, 22, 23, 24, 25]
CPU
PCI
(internal)
PCI_STOP#
HI
HI
CPU_STOP#
PWRDWN#
PCI_F
(external)
PCI
(external)
PWRDWN# Timing Diagram[17, 22, 26, 27]
CPU
(internal)
PCI
(internal)
PWRDWN#
CPU
(external)
PCI
(external)
VCO
Crystal
Notes:
23. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output.
24. All other clocks continue to run undisturbed.
25. PWRDWN# and CPU_STOP# are shown in a HIGH state.
26. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed.
27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is required to be synchronized.
28. The shaded sections on the VCO and the Crystal signals indicate an active clock.
Document #: 38-07166 Rev. *A
Page 6 of 13
PRELIMINARY
W133
Absolute Maximum Ratings[29]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
VDD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
TSTG
TA
°C
°C
°C
kV
Operating Temperature
TB
Ambient Temperature under Bias
Input ESD Protection
–55 to +125
2 (min.)
ESDPROT
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD-3.3V
IDD-2.5
Combined 3.3V Supply Current
Combined 2.5V Supply Current
CPU0:3 =133 MHz[30]
CPU0:3 =133 MHz[30]
160
90
mA
mA
Logic Inputs (All referenced to VDDQ3 = 3.3V)
VIL
Input Low Voltage
GND –
0.3
0.8
V
VIH
IIL
Input High Voltage
Input Low Current[31]
Input High Current[31]
Input Low Current, SEL133/100#[31]
Input High Current, SEL133/100#[31]
2.0
VDD + 0.3
V
–25
10
–5
5
µA
µA
µA
µA
IIH
IIL
IIH
Clock Outputs
CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2
)
Test Condition
IOL = 1 mA
Min.
Typ.
Max.
Unit
mV
V
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
50
IOH = –1 mA
VOL = 1.25V
VOH = 1.25V
Test Condition
IOL = 1 mA
2.2
45
65
65
100
100
Max.
50
mA
mA
Unit
mV
V
IOH
45
48MHz, REF (Referenced to VDDQ3
)
Min.
Typ.
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
IOH = –1 mA
VOL = 1.5V
3.1
45
65
65
100
100
Max.
50
mA
mA
Unit
mV
V
IOH
VOH = 1.5V
45
PCI, 3V66 (Referenced to VDDQ3
)
Test Condition
IOL = 1 mA
Min.
Typ.
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
IOH = –1 mA
VOL = 1.5V
3.1
70
65
100
95
145
135
mA
mA
IOH
VOH = 1.5V
Notes:
29. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
30. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors.
31. W133 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
Document #: 38-07166 Rev. *A
Page 7 of 13
PRELIMINARY
W133
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input threshold Voltage[32]
1.65
18
V
CLOAD
Load Capacitance, Imposed on
External Crystal[33]
pF
CIN,X1
X1 Input Capacitance[34]
Pin X2 unconnected
Except X1 and X2
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
5
6
7
pF
pF
nH
COUT
LIN
Output Pin Capacitance
Input Pin Inductance
3.3V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[35]
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Frequency
Test Condition/Comments
Note 36
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
66.6
tR
tF
tD
fST
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 0.4V to 2.4V
1
1
4
4
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
45
55
3
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
Ω
Notes:
32. X1 input threshold voltage (typical) is VDD/2.
33. The W133 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
34. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
35. Period, jitter, offset, and skew measured on rising edge at 1.5V.
36. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Document #: 38-07166 Rev. *A
Page 8 of 13
PRELIMINARY
W133
PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V[37]
Min. Typ. Max. Unit
tP
tH
tL
30
12
12
1
ns
ns
High Time
Low Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
ns
tR
tF
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
4
4
V/ns
V/ns
%
1
tD
tJC
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
ps
tSK
tO
Output Skew
Measured on rising edge at 1.5V.
500
4
ps
ns
3V66 to PCI Clock
Skew
Covers all 3V66/PCI outputs. Measured on rising edge at
1.5V. 3V66 leads PCI output.
1.5
fST
FrequencyStabilization Assumes full supply voltage reached within 1 ms from
3
ms
from Power-up (cold
power-up. Short cycles exist prior to frequency stabilization.
start)
Zo
AC Output Impedance Average value during switching transition. Used for deter-
mining series termination value.
15
Ω
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
14.318
Max. Unit
f
tR
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within
ms
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value duringswitching transition. Used
for determining series termination value.
25
Ω
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
Min.
Typ.
48.008
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
Ω
Note:
37. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Document #: 38-07166 Rev. *A
Page 9 of 13
PRELIMINARY
W133
2.5V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[38]
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 133MHz
CPU = 100MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
tP
tH
tL
7.5
1.87
1.67
1
7.65
10
3.0
2.8
1
10.2
ns
ns
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
%
1
1
Duty Cycle
Measured on rising and falling edge at
45
55
45
55
1.25V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
tSK
fST
Output Skew
Measured on rising edge at 1.25V
175
3
175
3
ps
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1ms from power-up. Short cycles
exist prior to frequency stabilization.
ms
Zo
AC Output Impedance Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
20
Ω
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
Min. Typ. Max. Min. Typ. Max. Unit
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
tP
tH
tL
15
5.25
5.05
1
15.3
20
7.5
7.3
1
20.4
ns
ns
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
%
1
1
Duty Cycle
Measured on rising and falling edge at
45
55
45
55
1.25V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
tSK
fST
Output Skew
Measured on rising edge at 1.25V
175
3
175
3
ps
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within1msfrompower-up. Shortcycles
exist prior to frequency stabilization.
ms
Zo
AC Output Impedance Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
20
Ω
Note:
38. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
Document #: 38-07166 Rev. *A
Page 10 of 13
PRELIMINARY
W133
IOAPIC Clock Outputs, IOAPIC0:2 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency
Test Condition/Comments
Min
Typ
Max
Unit
MHz
V/ns
V/ns
%
f
Note 39
16.67
tR
tF
tD
fST
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 0.4V to 2.0V
1
1
4
4
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.25V
45
55
3
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Averagevalueduringswitchingtransition.Used
for determining series termination value.
20
Ω
Note:
39. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Ordering Information
Package
Ordering Code
W133
Name
Package Type
H
56-pin SSOP (300 mils)
Intel is a registered trademark of Intel Corporation.
Document #: 38-07166 Rev. *A
Page 11 of 13
PRELIMINARY
W133
Package Diagram
56-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07166 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
W133
Document Title: W133 Spread Spectrum System Frequency Synthesizer
Document Number: 38-07166
Issue
Date
Orig. of
REV.
**
ECN NO.
110276
122807
Change Description of Change
11/05/01
12/15/02
SZV
RBI
Change from Spec number: 38-00823 to 38-07166
Add Power up Requirements to Absolute Maximum Ratings Information
*A
Document #: 38-07166 Rev. *A
Page 13 of 13
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