W134M [CYPRESS]
Direct Rambus Clock Generator; 直接RAMBUS时钟发生器型号: | W134M |
厂家: | CYPRESS |
描述: | Direct Rambus Clock Generator |
文件: | 总12页 (文件大小:200K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
W134M/W134S
Direct Rambus™ Clock Generator
Features
Description
• Differential clock source for Direct Rambus™ memory
subsystem for up to 800-MHz data transfer rate
The Cypress W134M/W134S provides the differential clock
signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
• Provide synchronization flexibility: the Rambus®
Channel can optionally be synchronous to an external
system or processor clock
• Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
• WorkswithCypressCY2210, W133, W158, W159, W161,
and W167 to support Intel® architecture platforms
• Low-power CMOS design packaged in a 24- pin QSOP
(150-mil SSOP) package
Block Diagram
Pin Configuration
REFCLK
MULT0:1
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
S0
S1
VDD
GND
CLK
PLL
NC
CLKB
GND
VDD
MULT0
MULT1
GND
CLK
Output
Logic
Phase
PCLKM
CLKB
Alignment
VDD
SYNCLKN
VDDIPD
STOPB
PWRDNB
10
11
12
Test
S0:1
Logic
STOPB
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07426 Rev. *B
Revised December 11, 2003
W134M/W134S
Pin Definitions
Pin Name
No.
Type
Description
REFCLK
2
I
Reference Clock Input. Reference clock input, normally supplied by a system frequency
synthesizer (Cypress W133).
PCLKM
6
7
I
I
Phase Detector Input. The phase difference between this signal and SYNCLKN is used
to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
Phase Detector Input. The phase difference between this signal and PCLKM is used to
synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
SYNCLKN
STOPB
11
12
I
I
I
Clock Output Enable. When this input is driven to active LOW, it disables the differential
Rambus Channel clocks.
PWRDNB
MULT 0:1
Active LOW Power-down. When this input is driven to active LOW, it disables the differ-
ential Rambus Channel clocks and places the W134M/W134S in power-down mode.
15, 14
PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to
determine the multiply ratio for the PLL for the input REFCLK.
W134S
W134M
PLL/REFCLK
PLL/REFCLK
MULT0
MULT1
4
6
8
4.5
6
8
0
0
1
1
0
1
1
0
5.333
5.333
CLK, CLKB
S0, S1
20, 18
24, 23
O
I
Complementary Output Clock. Differential Rambus Channel clock outputs.
Mode Control Input. These inputs control the operating mode of the W134M/W134S.
MODE
Normal
S0
0
S1
0
Output Enable Test
Bypass
0
1
1
1
0
1
Test
NC
VDDIR
VDDIPD
19
1
10
–
No Connect
RefV Reference for REFCLK. Voltage reference for input reference clock.
RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.
VDD
3, 9, 16, 22
P
Power Connection. Power supply for core logic and output buffers. Connected to 3.3V
supply.
GND
4, 5, 8, 13, 17,
21
G
Ground Connection. Connect all ground pins to the common system ground plane.
W134M/W134S
W133
W158
W159
W161
W167
Refclk
Phase
PLL
Busclk
Align
D
CY2210
RAC
RMC
Pclk
M
N
4
DLL
Synclk
Gear
Ratio
Logic
Figure 1. DDLL System Architecture
Document #: 38-07426 Rev. *B
Page 2 of 12
W134M/W134S
Pclk is the clock used in the memory controller (RMC) in the
core logic, and Synclk is the clock used at the core logic
interface of the RAC. The DDLL together with the Gear Ratio
Logic enables users to exchange data directly from the Pclk
domain to the Synclk domain without incurring additional
latency for synchronization. In general, Pclk and Synclk can
be of different frequencies, so the Gear Ratio Logic must
select the appropriate M and N dividers such that the
frequencies of Pclk/M and Synclk/N are equal. In one inter-
esting example, Pclk = 133 MHz, Synclk = 100 MHz, and
M = 4 while N = 3, giving Pclk/M = Synclk/N = 33 MHz. This
example of the clock waveforms with the Gear Ratio Logic is
shown in Figure 2.
The output clocks from the Gear Ratio Logic, Pclk/M, and
Synclk/N, are output from the core logic and routed to the
DRCG Phase Detector inputs. The routing of Pclk/M and
Synclk/N must be matched in the core logic as well as on the
board.
After comparing the phase of Pclk/M vs. Synclk/N, the DRCG
Phase Detector drives a phase aligner that adjusts the phase
of the DRCG output clock, Busclk. Since everything else in the
distributed loop is fixed delay, adjusting Busclk adjusts the
phase of Synclk and thus the phase of Synclk/N. In this
manner the distributed loop adjusts the phase of Synclk/N to
match that of Pclk/M, nulling the phase error at the input of the
DRCG Phase Detector. When the clocks are aligned, data can
be exchanged directly from the Pclk domain to the Synclk
domain.
Key Specifications
Supply Voltage:...................................... VDD = 3.3V±0.165V
Operating Temperature: ...................................0°C to +70°C
Input Threshold:.................................................. 1.5V typical
Maximum Input Voltage: ........................................VDD+0.5V
Maximum Input Frequency: .....................................100 MHz
Output Duty Cycle:...................................40/60% worst case
Output Type: ...........................Rambus signaling level (RSL)
DDLL System Architecture and Gear Ratio
Logic
Figure 1 shows the Distributed Delay Lock Loop (DDLL)
system architecture, including the main system clock source,
the Direct Rambus clock generator (DRCG), and the core logic
that contains the Rambus Access Cell (RAC), the Rambus
Memory Controller (RMC), and the Gear Ratio Logic. (This
diagram abstractly represents the differential clocks as a
single Busclk wire.)
The purpose of the DDLL is to frequency-lock and phase-align
the core logic and Rambus clocks (Pclk and Synclk) at the
RMC/RAC boundary in order to allow data transfers without
incurring additional latency. In the DDLL architecture, a PLL is
used to generate the desired Busclk frequency, while a
distributed loop forms a DLL to align the phase of Pclk and
Synclk at the RMC/RAC boundary.
The main clock source drives the system clock (Pclk) to the
core logic, and also drives the reference clock (Refclk) to the
DRCG. For typical Intel architecture platforms, Refclk will be
half the CPU front side bus frequency. A PLL inside the DRCG
multiplies Refclk to generate the desired frequency for Busclk,
and Busclk is driven through a terminated transmission line
(Rambus Channel). At the mid-point of the channel, the RAC
senses Busclk using its own DLL for clock alignment, followed
by a fixed divide-by-4 that generates Synclk.
Table 1 shows the combinations of Pclk and Busclk
frequencies of greatest interest, organized by Gear Ratio.
Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio
Gear Ratio and Busclk
Pclk
2.0
1.5
1.33
1.0
67 MHz
267 MHz
100 MHz
133 MHz
150 MHz
200 MHz
300 MHz
400 MHz
400 MHz
267 MHz
400 MHz
356 MHz
400 MHz
Pclk
Synclk
Pclk/M =
Synclk/N
Figure 2. Gear Ratio Timing Diagram
Document #: 38-07426 Rev. *B
Page 3 of 12
W134M/W134S
StopB
S0/S1
W134M/W134S
W133
W158
W159
W161
W167
Refclk
Phase
PLL
Busclk
Align
D
CY2210
RAC
RMC
Pclk
M
N
4
DLL
Synclk
Gear
Ratio
Logic
Figure 3. DDLL Including Details of DRCG
Figure 3 shows more details of the DDLL system architecture,
Table 2. PLL Divider Selection
W134M
including the DRCG output enable and bypass modes.
W134S
Phase Detector Signals
Mult0
Mult1
A
9
6
8
16
B
2
1
1
3
A
4
6
8
16
B
1
1
1
3
The DRCG Phase Detector receives two inputs from the core
logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N
dividers in the core logic are chosen so that the frequencies of
PclkM and SynclkN are identical. The Phase Detector detects
the phase difference between the two input clocks, and drives
the DRCG Phase Aligner to null the input phase error through
the distributed loop. When the loop is locked, the input phase
error between PclkM and SynclkN is within the specification
0
0
1
1
0
1
1
0
Table 3 shows the logic for enabling the clock outputs, using
the StopB input signal. When StopB is HIGH, the DRCG is in
its normal mode, and Clk and ClkB are complementary outputs
following the Phase Aligner output (PAclk). When StopB is
LOW, the DRCG is in the Clk Stop mode, the output clock
drivers are disabled (set to Hi-Z), and the Clk and ClkB settle
to the DC voltage VX,STOP as given in the Device Character-
istics table. The level of VX,STOP is set by an external resistor
network.
t
ERR,PD given in the Device Characteristics table after the lock
time given in the State Transition Section.
The Phase Detector aligns the rising edge of PclkM to the
rising edge of SynclkN. The duty cycle of the phase detector
input clocks will be within the specification DCIN,PD given in the
Operating Conditions table. Because the duty cycles of the two
phase detector input clocks will not necessarily be identical,
the falling edges of PclkM and SynclkN may not be aligned
when the rising edges are aligned.
Table 3. Clock Stop Mode Selection
The voltage levels of the PclkM and SynclkN signals are deter-
mined by the controller. The pin VDDIPD is used as the voltage
reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
directly, by bypassing the Phase Aligner. If PclkM and SynclkN
are not used, those inputs must be grounded.
Mode
Normal
Clk Stop
StopB
Clk
PAclk
VX,STOP
ClkB
PAclkB
VX,STOP
1
0
Table 4 shows the logic for selecting the Bypass and Test
modes. The select bits, S0 and S1, control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the Refclk input all the way to the output, bypassing
both the PLL and the Phase Aligner. In the Output Test mode
(OE), both the Clk and ClkB outputs are put into a
high-impedance state (Hi-Z). This can be used for component
testing and for board-level testing.
Selection Logic
Table 2 shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLclk = Refclk*A/B.
Document #: 38-07426 Rev. *B
Page 4 of 12
W134M/W134S
Table of Frequencies and Gear Ratios
Table 4. Bypass and Test Mode Selection
Bypclk
Table 6 shows several supported Pclk and Busclk
frequencies, the corresponding A and B dividers required in
the DRCG PLL, and the corresponding M and N dividers in the
gear ratio logic. The column Ratio gives the Gear Ratio as
defined Pclk/Synclk (same as M and N). The column F@PD
gives the divided down frequency (in MHz) at the Phase
Detector, where F@PD = Pclk/M = Synclk/N.
Mode
Normal
S0
0
S1
0
(int.)
Gnd
–
Clk
PAclk
Hi-Z
ClkB
PAclkB
Hi-Z
Output Test (OE)
Bypass
Test
0
1
1
1
0
1
PLLclk PLLclk PLLclkB
Refclk Refclk RefclkB
State Transitions
Table 5 shows the logic for selecting the Power-down mode,
using the PwrDnB input signal. PwrDnB is active LOW
(enabled when 0). When PwrDnB is disabled, the DRCG is in
its normal mode. When PwrDnB is enabled, the DRCG is put
into a powered-off state, and the Clk and ClkB outputs are
three-stated.
The clock source has three fundamental operating states.
Figure 4 shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and
StopB.
Table 5. Power-down Mode Selection
In Power-down mode, the clock source is powered down with
the control signal, PwrDnB, equal to 0. The control signals S0
and S1 must be stable before power is applied to the device,
and can only be changed in Power-down mode (PwrDnB = 0).
The reference inputs, VDDR and VDDPD, may remain on or may
be grounded during the Power-down mode.
Mode
Normal
Power-down
PwrDnB
Clk
PAclk
GND
ClkB
PAclkB
GND
1
0
Table 6. Examples of Frequencies, Dividers, and Gear Ratios
Pclk
67
100
100
133
133
Refclk
33
50
50
67
Busclk
267
300
400
267
Synclk
67
75
100
67
100
A
8
6
8
4
6
B
1
1
1
1
1
M
2
8
4
4
8
N
2
6
4
2
6
Ratio
1.0
1.33
1.0
2.0
1.33
F@PD
33
12.5
25
33
16.7
67
400
VDD Turn-On
VDD Turn-On
G
J
M
L
Test
Normal
N
B
F
K
A
E
VDD Turn-On
H
VDD Turn-On
D
C
Power-Down
Clk Stop
Figure 4. Clock Source State Diagram
The control signals Mult0 and Mult1 can be used in two ways.
If they are changed during Power-down mode, then the
Power-down transition timings determine the settling time of
the DRCG. However, the Mult0 and Mult1 control signals can
also be changed during Normal mode. When the Mult control
signals are “hot-swapped” in this manner, the Mult transition
timings determine the settling time of the DRCG.
Table 7. Control Signals for Clock Source States
Clock
Output
State
Power-down
Clock Stop
Normal
PwrDnB
StopB
Source
Buffer
0
1
1
X
0
1
OFF
ON
ON
Ground
Disabled
Enabled
In Normal mode, the clock source is on, and the output is
enabled.
Figure 5 shows the timing diagrams for the various transitions
between states, and Table 8 specifies the latencies of each
state transition. Note that these transition latencies assume
the following.
Table 7 lists the control signals for each state.
Refclk input has settled and meets specification shown in
Table .
Mult0, Mult1, S0 and S1 control signals are stable.
Document #: 38-07426 Rev. *B
Page 5 of 12
W134M/W134S
Timing Diagrams
Power-down Exit and Entry
PwrDnB
Clk/ClkB
t
t
POWERDN
POWERUP
Output Enable Control
t
ON
t
STOP
t
StopB
CLKON
t
CLKOFF
t
CLKSETL
Clk/ClkB
Output clock
not specified
glitches may
occur
Clock output settled within
50 ps of the phase before
disabled
Clock enabled
and glitch-free
Figure 5. State Transition Timing Diagrams
Mult0 and/or Mult1
Clk/ClkB
tMULT
Figure 6. Multiply Transition Timing
Table 8. State Transition Latency Specifications
Transition Latency
Transition
From
To
Parameter
Max.
Description
A
Power-down
Normal
tPOWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
C
K
G
H
M
J
Power-down
Power-down
Clk Stop
Test
tPOWERUP
tPOWERUP
tPOWERUP
tPOWERUP
tPOWERUP
tMULT
3 ms
3 ms
3 ms
3 ms
3 ms
1 ms
Time from PwrDnB until the internal PLL and clock has
turned ON and settled.
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
VDD ON
VDD ON
VDD ON
Normal
Clk Stop
Test
Time from VDD is applied and settled until Clk/ClkB
output settled (excluding tDISTLOCK).
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
Normal
Normal
Time from when Mult0 or Mult1 changed until Clk/ClkB
output resettled (excluding tDISTLOCK).
Document #: 38-07426 Rev. *B
Page 6 of 12
W134M/W134S
Table 8. State Transition Latency Specifications (continued)
Transition Latency
Transition
From
To
Parameter
Max.
Description
E
Clk Stop
Normal
tCLKON
10 ns Time from StopB until Clk/ClkB provides glitch-free
clock edges.
E
Clk Stop
Normal
tCLKSETL 20 cycles Time from StopB to Clk/ClkB output settled to within 50
ps of the phase before CLK/CLKB was disabled.
F
L
Normal
Test
Clk Stop
Normal
tCLKOFF
tCTL
5 ns
3 ms
Time from StopB to Clk/ClkB output disabled.
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding tDISTLOCK).
N
Normal
Test
tCTL
3 ms
1 ms
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding tDISTLOCK).
Time from PwrDnB to the device in Power-down.
B,D
Normal or Clk Stop Power-down tPOWERDN
Figure 5 shows that the Clk Stop to Normal transition goes
through three phases. During tCLKON, the clock output is not
specified and can have glitches. For tCLKON < t < tCLKSETL, the
clock output is enabled and must be glitch-free. For
t > tCLKSETL, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At
this time, the clock output must also meet the voltage and
timing specifications of Table . The outputs are in a
high-impedance state during the Clk Stop mode.
Table 9. Distributed Loop Lock Time Specification
Parameter
Description
Min.
Max.
Unit
tDISTLOCK Time from when Clk/ClkB output is settled to when the phase error between SynclkN and
5
ms
PclkM falls within the tERR,PD spec in Table .
Table 10.Supply and Reference Current Specification
Parameter
IPOWERDOWN
ICLKSTOP
INORMAL
IREF,PWDN
IREF,NORM
Description
Min.
Max.
250
65
100
50
Unit
µA
mA
mA
µA
“Supply” current in Power-down state (PwrDnB 1 = 0)
“Supply” current in Clk Stop state (StopB = 0)
“Supply” current in Normal state (StopB = 1,PwrDnB = 1)
Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)
Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)
–
–
–
–
–
2
mA
Document #: 38-07426 Rev. *B
Page 7 of 12
W134M/W134S
Absolute Maximum Conditions[1]
Parameter
VDD, ABS
VI, ABS
Description
Max. voltage on VDD with respect to ground
Max. voltage on any pin with respect ground
Min.
–0.5
–0.5
Max.
4.0
VDD+0.5
Unit
V
V
External Component Values[2]
Parameter
Description
Min.
39
Max.
±5%
Unit
Ω
RS
Serial Resistor
RP
CF
CMID
Parallel Resistor
Edge Rate Filter Capacitor
AC Ground Capacitor
51
±5%
±10%
0.1 µF
Ω
4 – 15[3]
470 pF
pF
±20%
Operating Conditions[4]
Parameter
VDD
TA
Description
Min.
3.135
0
Max.
3.465
70
Unit
V
°C
Supply Voltage
Ambient Operating Temperature
tCYCLE,IN
tJ,IN
Refclk Input Cycle Time
10
–
40
30
–
40
250
60
ns
ps
%tCYCLE
kHz
Input Cycle-to-Cycle Jitter[5]
DCIN
FMIN
PMIN
Input Duty Cycle over 10,000 Cycles
Input Frequency of Modulation
33
[6]
Modulation Index for Triangular Modulation
Modulation Index for Non-Triangular Modulation
Phase Detector Input Cycle Time at PclkM & SynclkN
Initial Phase error at Phase Detector Inputs
Phase Detector Input Duty Cycle over 10,000 Cycles
0.6
0.5[8]
100
0.5
75
%
%
ns
–
tCYCLE,PD
tERR,INIT
DCIN,PD
tI,SR
30
–0.5
25
1
tCYCLE,PD
tCYCLE,PD
V/ns
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,
4
SynclkN, and Refclk
CIN,PD
DCIN,PD
CIN,CMOS
Input Capacitance at PclkM, SynclkN, and Refclk[7]
Input Capacitance matching at PclkM and SynclkN[7]
–
–
–
7
0.5
10
pF
pF
pF
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and
Refclk)[7]
VIL
VIH
Input (CMOS) Signal Low Voltage
Input (CMOS) Signal High Voltage
Refclk input Low Voltage
–
0.7
–
0.7
–
0.7
1.235
1.235
0.3
–
0.3
–
0.3
–
3.465
2.625
VDD
VDD
VDDIR
VDDIR
VDDIPD
VDDIPD
V
VIL,R
VIH,R
VIL,PD
VIH,PD
VDDIR
VDDIPD
Refclk input High Voltage
Input Signal Low Voltage for PD Inputs and StopB
Input Signal High Voltage for PD Inputs and StopB
Input Supply Reference for Refclk
Input Supply Reference for PD Inputs
V
Notes:
1. Represents stress ratings only, and functional operation at the maximums is not guaranteed.
2. Gives the nominal values of the external components and their maximum acceptable tolerance, assuming Z = 28Ω.
CH
3. Do not populate C . Leave pads for future use.
F
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Refclk jitter measured at V (nom)/2.
DDIR
6. If input modulation is used: input modulation is allowed but not required.
7. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and V < 100 mV.
AC
8. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Document #: 38-07426 Rev. *B
Page 8 of 12
W134M/W134S
Device Characteristics
Parameter
tCYCLE
Description
Min.
2.5
–
–
–
Max.
3.75
60
100
100
160
–
Unit
ns
ps
ps
ps
Clock Cycle Time
tJ
Cycle-to-Cycle Jitter at Clk/ClkB[9]
Total Jitter over 2, 3, or 4 Clock Cycles[9]
266-MHz Cycle-to-Cycle Jitter[10]
266-MHz Total Jitter over 2, 3, or 4 Clock Cycles[10]
Phase Aligner Phase Step Size (at Clk/ClkB)
–
1
ps
ps
tSTEP
tERR,PD
Phase Detector Phase Error for Distributed Loop Measured at
–100
100
ps
PclkM-SynclkN (rising edges) (does not include clock jitter)
tERR,SSC
VX,STOP
VX
VCOS
VOH
VOL
rOUT
IOZ
IOZ,STOP
DC
PLL Output Phase Error when Tracking SSC
Output Voltage during Clk Stop (StopB=0)
Differential Output Crossing-Point Voltage
Output Voltage Swing (p-p single-ended)[11]
Output High Voltage
–100
1.1
1.3
0.4
–
1.0
12
–
–
40
–
250
–
100
2.0
1.8
0.6
2.0
–
50
50
500
60
50
ps
V
V
V
V
V
Output Low voltage
Output Dynamic Resistance (at pins)[12]
Output Current during Hi-Z (S0 = 0, S1 = 1)
Output Current during Clk Stop (StopB = 0)
Output Duty Cycle over 10,000 Cycles
Output Cycle-to-Cycle Duty Cycle Error
Output Rise and Fall Times (measured at 20%–80% of output voltage)
Ω
µA
µA
%tCYCLE
ps
tDC,ERR
tR,tF
tCR,CF
500
100
ps
ps
Difference between Output Rise and Fall Times on the Same Pin of a
Single Device (20%–80%)
Notes:
9. Output Jitter spec measured at t
10. Output Jitter Spec measured at t
= 2.5 ns.
CYCLE
CYCLE
= 3.75 ns.
11. V
= V –V
OH OL.
COS
12. r
= DV / D I . This is defined at the output pins.
O O
OUT
Document #: 38-07426 Rev. *B
Page 9 of 12
W134M/W134S
Layout Example
+3.3V Supply
FB
10 µF
C40.005 µF
G
C3
G
VDDIR
G
1
2
3
24
23
22
G
G
G
G
G
G
G
4
21
20
G
5
6
7
19
18
G
G
G
G
G
8
17
46
15
14
G
G
9
G
10
11
12
VDDIPD
G
13
Internal Power Supply Plane
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
= VIA to GND plane layer
G
All Bypass cap = 0.1 Ceramic XR7
Ordering Information
Ordering Code
W134M/W134SH
W134M/W134SHT
W134M/W134SSQC
W134M/W134SSQCT
W134SH
Package Type
24-pin QSOP (150 mils, SSOP)
24-pin QSOP (150 mils, SSOP) – Tape and Reel
24-pin QSOP (150 mils, SSOP) – (Lead-free)
24-pin QSOP (150 mils, SSOP) – Tape and Reel – (Lead-free)
24-pin QSOP (150 mils, SSOP)
W134SHT
24-pin QSOP (150 mils, SSOP) – Tape and Reel
Document #: 38-07426 Rev. *B
Page 10 of 12
W134M/W134S
Package Diagram
24-Lead Quarter Size Outline Q13
51-85055-*B
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc. Intel is a registered trademark of Intel
Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07426 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W134M/W134S
Document History Page
Document Title: W134M/W134S Direct Rambus™ Clock Generator
Document Number: 38-07426
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
Change from Spec number: 38-00822 to 38-07246
Add power-up requirements to operating information
Added Lead-free to the W134M device in the ordering information table
115531
122927
131671
05/10/02
12/14/02
12/15/03
DSG
RBI
RGL
*B
Document #: 38-07426 Rev. *B
Page 12 of 12
相关型号:
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