W180-51G [CYPRESS]
Peak Reducing EMI Solution; 峰值抑制EMI解决方案
| 型号： | W180-51G |
| 厂家： | 
CYPRESS |
| 描述： | Peak Reducing EMI Solution |
| 文件： | 总10页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W180
Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
W180-01, 02, 03
Output
W180-51, 52, 53
Output
SS%
• Generates an EMI optimized clocking signal at the
output
0
1
Fin > Fout > Fin – 1.25% Fin + 0.625% > Fin > – 0.625%
Fin > Fout > Fin – 3.75% Fin + 1.875% > Fin > –1.875%
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
Table 2. Frequency Range Selection
W180 Option#
-01, 51
(MHz)
-02, 52
(MHz)
-03, 53
(MHz)
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
FS2 FS1
0
0
1
1
0
1
0
1
8 < FIN < 10
8 < FIN < 10
N/A
Key Specifications
10 < FIN < 15 10 < FIN < 15
N/A
Supply Voltages:............................................VDD = 3.3V±5%
or VDD = 5V±10%
15 < FIN < 18
18 < FIN < 28
N/A
N/A
15 < FIN < 18
18 < FIN < 28
Frequency Range:...............................8 MHz < Fin < 28 MHz
Cycle to Cycle Jitter: ........................................300 ps (max.)
Selectable Spread Percentage:.................... 1.25% or 3.75%
Output Duty Cycle: ...............................40/60% (worst case)
Output Rise and Fall Time:...................................5 ns (max.)
Simplified Block Diagram
Pin Configurations
3.3V or 5.0V
SOIC
CLKIN or X1
NC or X2
GND
FS2
1
2
3
4
8
7
6
5
FS1
X1
VDD
XTAL
SS%
CLKOUT
Input
X2
Spread Spectrum
Output
W180
(EMI suppressed)
CLKIN or X1
NC or X2
GND
SSON#
FS1
1
2
3
4
8
7
6
5
VDD
SS%
CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W180
Output
(EMI suppressed)
Cypress Semiconductor Corporation
Document #: 38-07156 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 5, 2005
W180
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CLKOUT
5
O
I
Output Modulated Frequency: Frequency modulated copy of the unmodulated
input clock (SSON# asserted).
CLKIN or X1
NC or X2
1
2
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It may either be connected to an external crystal, or to an external reference
clock.
I
I
I
I
Crystal Connection: Input connection for an external crystal. If using an external
reference, this pin must be left unconnected.
SSON#
FS1:2
SS%
8 (-02, -03 52, 53)
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns
the internal modulation waveform on. This pin has an internal pull-down resistor.
7, 8 (-01, 51)
4
Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of
operation. Refer to Table 2. These pins have internal pull-up resistors.
Modulation Width Selection: When Spread Spectrum feature is turned on, this pin
is used to select the amount of variation and peak EMI reduction that is desired on
the output signal. Internal pull-up resistor.
VDD
GND
6
3
P
Power Connection: Connected to 3.3V or 5V power supply.
G
Ground Connection: This should be connected to the common ground plane.
Document #: 38-07156 Rev. *B
Page 2 of 10
W180
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W180 the output
frequency is equal to the input frequency.) The unique feature
of the Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a
predetermined frequency band.
Overview
The W180 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer
techniques. By frequency modulating the output with a
low-frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum
process has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The
Simplified Block Diagram on page 1 shows a simple imple-
mentation.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI
reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Functional Description
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pin
SS% as shown in Table 1.
The W180 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
A larger spreading percentage improves EMI reduction.
However, large spread percentages may either exceed
system maximum frequency ratings or lower the average
frequency to a point where performance is affected. For these
reasons, spreading percentages options are provided.
V
DD
Clock Input
CLKOUT
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Post
Dividers
Reference Input
(EMI suppressed)
Σ
VCO
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
Document #: 38-07156 Rev. *B
Page 3 of 10
W180
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing
Generation
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions.
Figure 3 details the Cypress spreading pattern. Cypress does
offer options with more spread and greater EMI reduction.
Contact your local Sales representative for details on these
devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the ampli-
tudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
SSFTG
Typical Clock
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07156 Rev. *B
Page 4 of 10
W180
Absolute Maximum Ratings[1]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
rating only. Operation of the device at these or any other condi-
.
Parameter
DD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
TSTG
TA
°C
°C
°C
W
Operating Temperature
TB
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
PD
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5%
Parameter
IDD
Description
Supply Current
Test Condition
Min.
Typ.
Max.
Unit
mA
ms
18
32
5
tON
Power Up Time
First locked clock cycle after Power
Good
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
0.8
0.4
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
2.4
V
2.4
V
Note 2
–50
µA
µA
mA
mA
pF
kΩ
Ω
IIH
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
Note 2
50
7
IOL
IOH
CI
@ 0.4V, VDD = 3.3V
@ 2.4V, VDD = 3.3V
15
15
RP
500
25
ZOUT
Notes:
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Inputs FS2:1& SS% have a pull-up resistor; Input SSON# has a pull-down resistor.
Document #: 38-07156 Rev. *B
Page 5 of 10
W180
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10%
Parameter
IDD
Description
Supply Current
Test Condition
Min.
Typ.
Max.
50
Unit
mA
ms
30
tON
Power Up Time
First locked clock cycle after
Power Good
5
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
0.15VDD
0.4
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
0.7VDD
V
2.4
V
Note 3
–50
µA
µA
mA
mA
pF
kΩ
Ω
IIH
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
Note 3
50
7
IOL
IOH
CI
@ 0.4V, VDD = 5V
@ 2.4V, VDD = 5V
24
24
RP
500
25
ZOUT
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%
Parameter
Description
Input Frequency (-01)
Output Frequency (-01)
Output Rise Time
Test Condition
Input Clock, Note 4
Min.
Typ.
Max.
28
28
5
Unit
MHz
MHz
ns
fIN
fOUT
tR
8
8
Spread Off, Note 4
15-pF load 0.8V–2.4V
15-pF load 2.4 –0.8V
15-pF load
2
2
tF
Output Fall Time
5
ns
tOD
tID
Output Duty Cycle
Input Duty Cycle
40
40
60
60
300
%
%
tJCYC
Jitter, Cycle-to-Cycle
Harmonic Reduction
250
ps
fout = 20 MHz, third harmonic
measured, reference board, 15-pF
load
8
dB
Notes:
3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
4. Frequency range listed for -01 version. See Table 2 for frequency range of -02 and -03 versions.
Document #: 38-07156 Rev. *B
Page 6 of 10
W180
increased trace inductance will negate its decoupling
capability. The 10-µF decoupling capacitor shown should be a
tantalum type. For further EMI protection, the VDD connection
can be made via a ferrite bead, as shown.
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
Recommended Board Layout
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the
Figure 5 shows a recommended 2-layer board layout.
Xtal Connection or Reference Input
1
2
3
4
8
7
6
5
Xtal Connection or NC
GND
Clock
Output
R1
C1
µF
0.1
3.3V or 5V System Supply
FB
C2
10
µF Tantalum
Figure 4. Recommended Circuit Configuration
High frequency supply decoupling
µF recommended).
C1 =
capacitor (0.1-
Common supply low frequency
C2 =
µF tantalum
decoupling capacitor (10-
recommended).
R1 =
Match value to line impedance
Ferrite Bead
FB
=
Via To GND Plane
G
=
Xtal Connection or Reference Input
NC
C1
G
G
Clock Output
R1
G
C2
Power Supply Input
(3.3V or 5V)
FB
Figure 5. Recommended Board Layout (2-Layer Board)
Document #: 38-07156 Rev. *B
Page 7 of 10
W180
Ordering Information
Ordering Code
W180-01G
Package Type
8-pin Plastic SOIC (150-mil)
Operating Temperature Range
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
W180-01GT
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
W180-02G
W180-02GT
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
W180-03G
W180-03GT
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
W180-51G
W180-51GT
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
W180-52G
W180-52GT
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
W180-53G
W180-53GT
8-pin Plastic SOIC (150-mil)- Tape and Reel
Lead-free
CYW180-01SX
CYW180-01SXT
CYW180-02SX
CYW180-02SXT
CYW180-03SX
CYW180-03SXT
CYW180-51SX
CYW180-51SXT
CYW180-52SX
CYW180-52SXT
CYW180-53SX
CYW180-53SXT
8-pin Plastic SOIC (150-mil)
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
0°C to 70°C, Commercial
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
8-pin Plastic SOIC (150-mil)- Tape and Reel
8-pin Plastic SOIC (150-mil)
8-pin Plastic SOIC (150-mil)- Tape and Reel
Document #: 38-07156 Rev. *B
Page 8 of 10
W180
Package Diagram
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
PREMIS is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-07156 Rev. *B
Page 9 of 10
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
W180
Document Title: W180 Peak Reducing EMI Solution
Document Number: 38-07156
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
110266
122588
402292
Description of Change
Change from Spec number: 38-00796 to 38-07156
Added power up requirements to maximum ratings information.
Added Lead-free devices
12/15/01
12/27/02
See ECN
SZV
RBI
*A
*B
RGL
Document #: 38-07156 Rev. *B
Page 10 of 10
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