W42C32 [CYPRESS]
Spread Spectrum Frequency Timing Generator; 扩展频谱频率时序发生器
| 型号： | W42C32 |
| 厂家： | 
CYPRESS |
| 描述： | Spread Spectrum Frequency Timing Generator |
| 文件： | 总8页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W42C32-05
Spread Spectrum Frequency Timing Generator
Features
Key Specifications
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Generates a spread spectrum timing signal
• Reduces measured EMI by as much as 12 dB
• Integrated loop filter components
• Requires a single low-cost fundamental crystal (or
other frequency reference) for proper operation
• Special spread spectrum control functions
• Low-power CMOS design
Cycle-to-Cycle Jitter ....................................................250 ps
45/55 Duty Cycle.................................... approximately 1.4V
Selectable Frequency spread
2 ns rise/fall time 0.4V to 2.0V, 3.3V supply
2 ns rise/fall time 0.8V to 2.4V, 5.0V supply
Table 1. Frequency Spread Selection
W42C32-05
• Available in 16-pin SOIC package, (300 mil)
REFOUT
(MHz)
CLKOUT
(MHz)
VDD
(V)
FS2 FS1 FS0
Overview
0
0
0
0
0
1
0
1
0
22.1148
22.1148
14.7456
44.2296 ±
2.5%
5.0
5.0
5.0
The W42C32 modulates the output of a single PLL in order to
‘spread’ the bandwidth of a synthesized clock and, more im-
portantly, decrease the peak amplitudes of its fundamental
harmonics. Since peak amplitudes are reduced, the radiated
electromagnetic emissions of the W42C32-05 are significantly
lower than the typical narrow band signal produced by oscilla-
tors and most frequency generators. Lowering a signal’s am-
plitude by increasing its bandwidth is a method of reducing
EMI called ‘spread spectrum frequency timing generation’.
This patented technique not only reduces the emissions of the
primary clock, but also impacts every signal synchronized to it.
44.2296
±1.5%
29.4912 ±
2.5%
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
18.432
14.318
18.432 ± 2.5%
66.66 – 2%
5.0
3.3
3.3
3.3
3.3
Reserved
14.318
100 – 2%
Reserved
Pin Configuration
SOIC
PD#
X1
REFOUT
FS2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
FS1
GND
SSON#
RESET
VDD
AGND
FS0
TEST
CLKOUT
AVDD
REFEN#
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 28, 1999, rev. **
W42C32-05
Pin Definitions[1]
Pin
Pin Name
CLKOUT
REFOUT
X1
Pin No.
Type
Pin Description
8
16
2
O
O
I
Output Modulated Frequency: Frequency is set using FS0:2 (refer to Table 1).
Reference Output: A buffered version of the input frequency.
Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as either an external crystal connection, or as an external reference
frequency input.
X2
3
I
I
Crystal Connection: If using an external reference, this pin must be left unconnected.
SSON#
13
Spread Spectrum Control (active LOW):Pulling thisinput signal HIGH turns the internal
modulating waveform off. This pin has an internal pull-down resistor.
FS0
6
14
15
1
I
I
I
I
I
I
Frequency Selection Bit 0:This pin selects the frequency and spreading characteristics.
Refer to Table 1. This pin has an internal pull-up resistor.
FS1
Frequency Selection Bit 1:This pin selects the frequency and spreading characteristics.
Refer to Table 1. This pin has an internal pull-up resistor.
FS2
Frequency Selection Bit 2:This pin selects the frequency and spreading characteristics.
Refer to Table 1 (note the V specification). This pin has an internal pull-up resistor.
DD
PD#
Power-down (active LOW): Enabling power-down reduces current consumption and
disables the clock outputs. This pin has an internal pull-up resistor.
REFEN#
RESET
9
Reference Clock Selection Input: Pulling this signal LOW turns the REFOUT clock
output on. This pin has an internal pull-up resistor.
12
Reset: A reset starts the spread spectrum modulating frequency at the beginning point
of the modulation profile. This pin has an internal pull-down resistor. To reset the spread
spectrum modulating frequency, pull this pin from LOW to HIGH.
VDD
11
10
P
P
Power Connection: Connected to either 3.3V or 5.0V power supply. V and AV must
DD DD
be the same voltage level.
AVDD
Analog Power Connection: Connected to either 3.3V or 5.0V power supply. V and
DD
AV must be the same voltage level.
DD
GND
4
5
7
G
G
I
Ground Connection: Connect to the common system ground plane.
Analog Ground Connection: Connect to the common system ground plane.
Three-state Input: Pulling this input pin and REFEN# pin HIGH, CLKOUT will be
AGND
TEST
[2]
three-stated. This pin has an internal pull-down resistor.
Notes:
1. Pull-up resistors not CMOS level.
2. Pulling PD# and REFEN# input pins HIGH, REFOUT will be three-stated.
2
W42C32-05
Using frequency select bits (FS2:0 pins), various spreading
percentages for different input frequency ranges can be cho-
sen. For example, refer to the W42C32-05 in Table 1. If the
logic level on FS2:0 = 000, then an input reference frequency
between 14 and 24 MHz will produce an output frequency at
twice the reference frequency with a spread of ±2.5%.
Functional Description
The W42C32-05 uses a phase-locked loop (PLL) to multiply
the frequency of a low-cost, low-frequency crystal up to the
desired clock frequency. The basic circuit topology is shown in
Figure 1. An on-chip crystal driver causes the crystal to oscil-
late at its fundamental. The resulting reference signal is divid-
ed by Q and fed to the phase detector. The VCO output is
divided by P and also fed back to the phase detector. The PLL
will force the frequency of the VCO output signal to change
until the divided output signal and the divided reference signal
match at the phase detector input. The output frequency is
then equal to the ratio of P/Q times the reference frequency.
The unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between ±0.875% and ±2.5% are
most common.
Additional Features of the W42C32-05
A RESET pin is available to aid in applications which have
multiple PLL clock generators. When a reset is issued, the
modulation profile shown in Figure 3 is reset to its starting
point. This feature is necessary for applications in which two
spread spectrum systems must synchronize with each other.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
The REFOUT out pin provides a buffered version of the input
clock frequency.
Frequency Selection With SSFTG
The SSON# pin disables the spread spectrum function when
set to logic HIGH. Otherwise, an internal pull-down resistor
leaves this feature enabled.
In Spread Spectrum frequency timing generation, EMI reduc-
tion depends on the shape, modulation percentage, and fre-
quency of the modulating waveform. While the shape and fre-
quency of the modulating waveform in the W42C32 are fixed,
the modulation percentage may be varied.
The PD# pin reduces power consumption and disables the
clock outputs when set to logic LOW. Otherwise, an internal
pull-up resistor places the W42C32-05 into normal mode.
VDD
X1
CLKOUT
Post
Dividers
XTAL
Freq.
Divider
Q
Phase
Detector
Charge
Pump
VCO
Σ
X2
Modulating
Waveform
Feedback
Divider
Crystal load
capacitors
as needed
P
PLL
GND
Figure 1. System Block Diagram (Concept, not actual implementation)
3
W42C32-05
Spread Spectrum Frequency Timing
Generation
5dB/div
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
SSFTG
Typical Clock
Contrast the typical clock EMI with the Cypress spread spec-
trum clock. Notice the spike in the typical clock. This spike can
make systems fail quasi-peak EMI testing. The FCC and other
regulatory agencies test for peak emissions. With Cypress’s
Spread Spectrum Frequency Timing Generator (SSFTG), the
peak energy is much lower (at least 8 dB) because the energy
is spread out across a wider bandwidth.
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
Figure 2. Typical Clock and SSFTG Comparison
±
f
X
% in the frequency spread selection table.
Center
MOD
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
–
proach is f
X
%. Whenever this expression is used,
MAX
MOD
Cypress has taken care to ensure that f
will never be ex-
MAX
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Time
Figure 3. Modulation Waveform Profile
4
W42C32-05
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
Unit
V
V
, V
–0.5 to +7.0
–65 to +150
0 to +70
DD IN
T
°C
°C
°C
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
–55 to +125
B
DC Electrical Characteristics: 0°C < T < 70°C, V = 5.0V±10%, 3.3V±5%
A
DD
Parameter
Description
Supply Current
Test Condition
= 5.0, 100 MHz
DD
Min
Typ
Max
45
4
Unit
I
t
t
V
35
mA
DD
[3]
Power Down Time
Power Up Time
cycles
ms
OFF
ON
First locked clock cycle after
PD# goes HIGH
5
[3]
t
Enable/Disable Time
Input Low Voltage
Time required for output to be
enabled/disabled
4
cycles
EN
V
V
V
V
V
V
= 5.0V
= 3.3V
= 5.0V
= 3.3V
0.8
V
V
V
V
V
V
V
IL
DD
DD
DD
DD
0.15V
DD
Input High Voltage
3.0
IH
0.7V
DD
V
V
Output Low Voltage
Output High Voltage
0.4
OL
V
V
= 5.0V
= 3.3V
2.4
2.4
OH
DD
DD
µ
I
I
I
I
Input Low Current
–100
A
A
IL
µ
Input High Current
10
IH
Output Low Current
Output High Current
Input Capacitance
@ 0.4V, V = 3.3V
2.4
2.4
mA
mA
pF
pF
kΩ
Ω
OL
OH
DD
@ 2.4V, V = 3.3V
DD
C
C
R
All pins except X1, X2
Pins X1, X2
7
I
XTAL Load Capacitance
Input Pull-Up Resistor
Clock Output Impedance
16
L
V
= 0V
300
33
P
IN
Z
Any clock output pin
OUT
Note:
3. Cycle refers to input clock cycles supplied by the input crystal or reference.
5
W42C32-05
AC Electrical Characteristics: T = 0°C to +70°C, V = 5V±10%. 3.3V±5%
A
DD
Symbol
Parameter
Input Frequency
Test Condition
Min
12
Typ
Max
28
100
2
Unit
MHz
MHz
ns
f
IN
f
t
t
t
t
t
t
Output Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-Cycle
Harmonic Reduction
18
OUT
R
15-pF load 0.4V–2.4V
15-pF load 2.4V–0.8V
1
1
2
ns
F
15-pF load, V = 5.0V
45
40
40
55
60
60
300
%
OD
OD
ID
DD
15-pF load, V = 3.3V
%
DD
%
250
8
ps
JCYC
f = 16 MHz, ninth harmonic measured,
dB
in
reference board, 15-pF load
6
W42C32-05
The 10-µF decoupling capacitor shown should be a tantalum
Application Information
type. For further EMI protection, the V
made via a ferrite bead, as shown.
connection can be
DD
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
The 16-pF XTAL load capacitors can be used to raise the inte-
grated 12-pF capacitors up to a total load of 20 pF on the
crystal.
V
decoupling is important to both reduce phase jitter and
DD
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
Recommended Board Layout
DD
Figure 4 shows a recommended 2-layer board layout.
REFOUT
33
Ω
C1 =16 pF
1
2
16
15
XTAL1
C2 = 16 pF
3
4
14
G
G
13
12
5
6
7
C5
(Via to ground plane)
Ground
11
10
G
G
C6
33
Ω
CLKOUT
Voltage Supply Input
(3.3V, 5.0V)
8
9
Ferrite Bead
(Modulated Output)
C1, C2 = XTAL load capacitors.
Typical value is 16 pF.
µ
C3 = 0.1
F
C3, C5, C6 = High frequency supply decoupling
µF recommended).
capacitor (0.1-
C4 = Common supply low frequency
µF tantalum
decoupling capacitor (10-
recommended).
µ
F
C4 = 10
33
Ω
=
Match value to line impedance.
Ground
Figure 4. Recommended Board Layout (2-Layer Board)
Ordering Information
Freq. Mask
Package
Name
Ordering Code
Code
Package Type
W42C32
05
G
16-pin Plastic SOIC (300-mil)
Document #: 38-00808
7
W42C32-05
Package Diagram
16-Pin Small Outline Integrated Circuit (SOIC, 300-mil)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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