W48S87-72 [CYPRESS]
Desktop/Notebook Frequency Generator; 台式机/笔记本电脑频率发生器型号: | W48S87-72 |
厂家: | CYPRESS |
描述: | Desktop/Notebook Frequency Generator |
文件: | 总19页 (文件大小:247K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
W48S87-72
Desktop/Notebook Frequency Generator
• Two fixed outputs separately selectable as 24-MHz or
48-MHz (default = 48-MHz)
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• ±0.5% Spread Spectrum clocking
• Equivalent to the W48S67-72 with Spread Spectrum for
Tilamook, MMO, and Deschutes processors
• Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, USB plus 14.318-MHz (REF0:1)
• Serial data interface (SDATA, SCLOCK inputs) provides
additional CPU/PCI clock frequency selections, individ-
ual output clock disabling and other functions
• MODE input pin selects optional power management
input control pins (reconfigures pins 26 and 27)
• V
= 3.3V±5%, V
= 2.5V±5%
DDQ3
DDQ2
• Uses external 14.318-MHz crystal
• Available in 48-pin SSOP (300 mils)
10 CPU output impedance
•
Ω
[1]
Table 1. Pin Selectable Frequency
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
60/66_SEL
0
1
60
30
66.8
33.4
Block Diagram
Pin Configuration
VDDQ3
REF0
REF1
REF0
GND
X1
X2
MODE
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
CPU2.5#
VDDQ2
IOAPIC
PWR_DWN#
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
VDDQ3
REF1
X1
X2
XTAL
OSC
PLL Ref Freq
VDDQ2
IOAPIC
VDDQ2
CPU0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU1
CPU2
CPU3
CPU_STOP#
MODE
Stop
Output
Control
I/O
Control
GND
VDDQ3
60/66_SEL
SDATA
SCLOCK
VDDQ3
48/24MHZ
48/24MHZ
GND
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
PLL 1
60/66_SEL
÷2
PCI_F
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
Stop
Output
Control
Power
Down
Control
PWR_DWN#
PLL2
48/24MHZ
48/24MHZ
Note:
1. Additional frequency selections provided by serial data interface; refer to Ta bl e 5 on page 8.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 4, 2000 rev. *A
W48S87-72
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
CPU0:3
42, 41, 39,
38
O
CPU Outputs 0 through 3: These four CPU outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI0:5
9, 11, 12,
13, 14, 16
O
PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
8
O
Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM0:5
36, 35, 33,
32, 30, 29
O
SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run
synchronous to the CPU clock outputs. Output voltage swing is controlled by
voltage applied to VDDQ3.
SDRAM6/
CPU_STOP#
27
I/O
SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM
clock output 6.
Regarding use as a CPU_STOP# input: When brought LOW, clock outputs
CPU0:3 are stopped LOW after completing a full clock cycle (2–3 CPU clock
latency). When broughtHIGH, clock outputs CPU0:3 are started beginning with
a full clock cycle (2–3 CPU clock latency).
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM7/
PCI_STOP#
26
I/O
SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM
clock output 7.
PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW
after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5
are started beginning with a full clock cycle. Clock latency provides one PCI_F
rising edge of PCI clock following PCI_STOP# state change.
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
IOAPIC
45
O
O
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output
voltage swing is controlled by VDDQ2.
48/24MHz
22, 23
48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following
device power-up. Either or both can be changed to 24 MHz through use of the
serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled
by voltage applied to VDDQ3
REF0:1
2, 1
O
Fixed 14.318-MHz Outputs 0 through 1: Used for various system applica-
tions. Output voltage swing is controlled by voltage applied to VDDQ3. REF0
is stronger than REF1 and should be used for driving ISA slots.
CPU_2.5#
60/66_SEL
47
18
I
I
Set to logic 0 for V
= 2.5V (0 to 2.5V CPU output swing).
DDQ2
60- or 66-MHz Input Selection: Selects power-up default CPU clock frequency
as shown in Table 1 on page 1 (also determines SDRAM and PCI clock fre-
quency selections). Can be used to change CPU clock frequency while device
is in operation if serial data port bits 0–2 of Byte 7 are logic 1 (default power-
up condition).
X1
X2
4
5
I
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
2
W48S87-72
Pin Definitions (continued)
Pin
Pin
Pin Name
PWR_DWN#
No.
Type
Pin Description
44
I
Power-Down Control: When this input is LOW, the device goes into a low-
power standby condition. All outputs are actively held LOW while in power-
down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing
a full clock cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU,
SDRAM, and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
MODE
6
I
Mode Control: This input selects the function of device pin 26
(SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to descrip-
tion for those pins.
SDATA
SCLOCK
VDDQ3
VDDQ2
GND
19
20
I/O
I
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
7, 15, 21, 25
28, 34, 48
P
Power Connection: Power supply for PCI0:5, REF0:1, and 48/24MHz output
buffers. Connected to 3.3V supply.
46, 40
P
Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Con-
nected to 2.5V supply.
3, 10, 17,
24, 31, 37,
43
G
Ground Connection: Connect all ground pins to the common system ground
plane.
3
W48S87-72
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.5% of the center frequen-
cy. Figure 2 details the Cypress spreading pattern. Cypress
does offer options with more spread and greater EMI reduc-
tion. Contact your local Sales representative for details on
these devices.
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 1.
As depicted in Figure 1, a harmonic of a modulated clock has
a much lower amplitude than that of an unmodulated signal.
The reduction in amplitude is dependent on the harmonic num-
ber and the frequency deviation or spread. The equation for
the reduction is
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate values for bits 1–0 in data byte 0 of the
2
I C data stream. Refer to Table 4 for more details.
dB = 6.5 + 9*log (P) + 9*log (F)
10
10
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+.0.5%)
MIN. (–0.5%)
Figure 2. Typical Modulation Profile
4
W48S87-72
of the chipset. Clock device register changes are normally
made upon system initialization, if any are required. The inter-
face can also be used during system operation for power man-
agement functions. Table 2 summarizes the control functions
of the serial data interface.
Serial Data Interface
The W48S87-72 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S87-72
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is write-
only (to the clock chip) and is the dedicated function of device
pins SDATA and SCLOCK. In motherboard applications,
SDATA and SCLOCK are typically driven by two logic outputs
Operation
Data is written to the W48S87-72 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
48-/24-MHzClockOutput 48-/24-MHz clock outputs can be set to 48 MHz or Provides flexibility in Super I/O and USB de-
Frequency Selection
24 MHz.
vice selection.
CPU Clock Frequency
Selection
ProvidesCPU/PCIfrequency selections beyond the For alternate CPU devices, and power man-
60- and 66.6-MHz selections that are provided by agement options. Smooth frequency transi-
the SEL60/66 input pin. Frequency is changed in a tion allows CPU frequency change under nor-
smooth and controlled fashion.
mal system operation.
Output Three-state
Test Mode
Puts all clock outputs into a high-impedance state. Production PCB testing.
All clock outputs toggle in relation with X1 input,
Production PCB testing.
internal PLL is bypassed. Refer to Table 4.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Table 3. Byte Writing Sequence
Byte Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the W48S87-72 to accept the bits in Data Bytes 0–7 for
internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to have a specific slave
address for each potential receiver. The slave receiver address for the
W48S87-72 is 11010010. Register setting will not be made if the Slave
Address is not correct (or is for an alternate slave receiver).
2
3
Command
Code
Don’t Care
Don’t Care
Unused by the W48S87-72, therefore bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Byte Count
Unused by the W48S87-72, therefore bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Refer to Table 4 The data bits in Data Bytes 0–7 set internal W48S87-72 registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 4, Data Byte Serial Configuration
Map.
6
7
8
9
10
11
5
W48S87-72
Writing Data Bytes
7. Table 4 gives the bit formats for registers located in Data
Bytes 0–7.
Each bit in the data bytes control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
Table 5 details additional frequency selections that are avail-
able through the serial data interface.
Table 6 details the select functions for Byte 0, bits 1 and 0.
Table 4. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
--
--
--
--
--
--
(Reserved)
(Reserved)
SEL_4
--
--
0
0
Refer to Table 5
Refer to Table 5
Refer to Table 5
5
--
0
4
--
SEL_3
0
3
23
22
--
48/24MHZ 48-/24-MHz Clock Output Frequency Selection
48/24MHZ 48-/24-MHz Clock Output Frequency Selection
24 MHz
24 MHz
48 MHz
48 MHz
0
2
0
1–0
--
Bit 1 Bit 0
Function (See Table 6 for function details)
Normal Operation
00
0
0
1
1
0
1
0
1
Test Mode
Spread Spectrum On
All Outputs Three-stated
Data Byte 1
7
23
22
--
48/24MHZ Clock Output Disable
48/24MHZ Clock Output Disable
Low
Low
--
Active
Active
--
1
1
0
0
1
1
1
1
6
5
--
(Reserved)
4
--
--
(Reserved)
--
--
3
38
39
41
42
CPU3
CPU2
CPU1
CPU0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
2
1
0
Data Byte 2
7
--
8
--
(Reserved)
--
--
0
1
1
1
1
1
1
1
6
PCI_F
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
5
16
14
13
12
11
9
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
26
27
29
30
32
33
35
36
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
1
1
6
W48S87-72
Table 4. Data Bytes 0–7 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 4
7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Data Byte 5
7
--
--
--
45
--
--
1
--
--
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
0
0
0
6
5
--
4
IOAPIC
--
Clock Output Disable
(Reserved)
Low
--
Active
--
1
0
0
1
1
3
2
--
(Reserved)
--
--
1
REF1
REF0
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
0
2
Data Byte 6
7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Data Byte 7
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SEL_2
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
1
1
1
Refer to Table 5
SEL_1
Refer to Table 5
Refer to Table 5
SEL_0
7
W48S87-72
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Date Byte 0
Date Byte 7
Bit 5
SEL_4
Bit 4
SEL_3
60/66_SEL
(Pin 18)
Bit 2
SEL_2
BIT 1
SEL_1
BIT 0
SEL_0
CPU0:3
SDRAM0:7
PCI_F
PCI0:5
Spread
Spectrum%
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
0
0
1
1
0
0
1
1
1
X
X
X
X
X
X
0
1
0
1
0
1
0
1
1
X
X
X
X
X
X
75.0
75.0
CPU/2
32
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
–0.5
±0.5
–0.5
±0.5
–0.5
83.31
33.41
50.11
68.52
60.0
32
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
CPU/2
60.0
66.82
60.0
66.6
60.0
66.6
60.0
66.6
Table 6. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Output Conditions
PCI_F,
Data Byte 0
CPU0:3,
Function
Normal Operation
Test Mode
Bit 1
Bit 0
SRAM0:7
PCI0:5
Note 2
X1/4
REF0:2, IOAPIC
14.318 MHz
X1
48/24MHZ
48 or 24 MHz
Note 3
0
0
1
1
0
1
0
1
Note 2
X1/2
Spread Spectrum On
Three-state
Note 2
Hi-Z
Note 2
Hi-Z
14.318 MHz
Hi-Z
48 or 24 MHz
Hi-Z
Notes:
2. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5.
3. In Test Mode, the 48-/24-MHz clock outputs are:
- X1/2 if 48-MHz is selected.
- X1/4 if 24-MHz is selected.
8
W48S87-72
Although the W48S87-72 is a receive-only device (no data
write-back capability), it does transmit an “acknowledge” data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
How To Use the Serial Data Interface
Electrical Requirements
Figure 3 illustrates electrical characteristics for the serial inter-
face bus used with the W48S87-72. Devices send data over
the bus with an open drain logic output that can (a) pull the bus
line LOW, or (b) let the bus default to logic 1. The pull-up resis-
tors on the bus (both clock and data lines) establish a default
logic 1. All bus devices generally have logic inputs to receive
data.
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration to-
tal bus line capacitance.
Ω
Ω
Figure 3. Serial Interface Bus Electrical Characteristics
9
W48S87-72
Signaling Requirements
Sending Data to the W48S87-72
As shown in Figure 4, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double buff-
ered). Partial transmission is allowed meaning that a transmis-
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Transmis-
sion is truncated with either a stop bit or new start bit (restart
condition).
A write sequence is initiated by a “start bit” as shown in Figure
5. A “stop bit” signifies that a transmission has ended.
As stated previously, the W48S87-72 sends an “acknowledge”
pulse after receiving eight data bits in each byte as shown in
Figure 6.
Figure 4. Serial Data Bus Valid Data Bit
Figure 5. Serial Data Bus Start and Stop Bit
10
W48S87-72
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
kV
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Input ESD Protection
–55 to +125
2 (min.)
B
ESD
PROT
DC Electrical Characteristics:
T = 0°C to +70°C, V
= 3.3V±5% (3.135–3.465V) f
= 14.31818 MHz, V = 2.5±5%
DDQ2
A
DDQ3
XTL
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
I
Supply Current (3.3V)
CPUCLK =66.8 MHz
Outputs Loaded
120
150
200
50
mA
mA
DDQ3
[4]
I
Supply Current (2.5V)
CPUCLK =66.8 MHz
DDQ2
[4]
Outputs Loaded
Logic Inputs
V
V
Input Low Voltage
Input High Voltage
0.8
V
V
IL
2.0
IH
[5]
I
I
Input Low Current
10
10
µA
µA
IL
IH
[5]
Input High Current
Clock Outputs
V
Output Low Voltage
I
I
= 1 mA
50
mV
V
OL
OL
V
Output High Voltage
= –1 mA
= –1 mA
OH
3.1
2.2
OH
OH
V
Output High Voltage (CPU, IOAPIC)
I
V
OH
I
Output Low Current
CPU0:3
V
= 1.25V
= 1.5V
= 1.5V
= 1.25V
= 1.5V
= 1.5V
= 1.5V
= 1.25V
= 1.5V
= 1.5V
= 1.25V
= 1.5V
= 1.5V
= 1.5V
155
100
95
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OL
OL
SDRAM0:7
PCI_F, PCI0:5
IOAPIC
V
OL
V
OL
V
85
OL
REF0
V
75
OL
REF1
V
60
OL
48/24MHZ
CPU0:3
V
60
OL
I
Output High Current
V
125
95
OH
OL
SDRAM0:7
PCI_F, PCI0:5
IOAPIC
V
OL
V
100
80
OL
V
OL
REF0
V
80
OL
REF1
V
65
OL
48/24MHZ
V
60
OL
Notes:
4. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
5. W48S87-72 logic inputs have internal pull-up devices. (Not CMOS level.)
12
W48S87-72
DC Electrical Characteristics: (continued)
T = 0°C to +70°C, V
= 3.3V±5% (3.135–3.465V) f
= 14.31818 MHz, V = 2.5±5%
DDQ2
A
DDQ3
XTL
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
[6]
V
X1 Input Threshold Voltage
V
= 3.3V
DD
1.65
14
V
TH
C
Load Capacitance, Imposed on
pF
LOAD
[7]
External Crystal
[8]
C
X1 Input Capacitance
Pin X2 unconnected
Except X1 and X2
28
pF
IN,X1
Pin Capacitance/Inductance
C
C
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
5
6
7
pF
pF
nH
IN
OUT
IN
L
Serial Input Port
V
V
Input Low Voltage
Input High Voltage
Input Low Current
V
V
= 3.3V
= 3.3V
0.4
2.4
10
0.3V
DD
V
V
IL
DD
DD
0.7V
IH
DD
I
I
I
No internal pull-up/down
on SCLOCK
10
10
15
10
µA
IL
Input High Current
No internal pull-up/down
on SCLOCK
10
10
5
µA
mA
pF
IH
Sink Current into SDATA or SCLOCK,
Open Drain N-Channel Device On
I
= 0.3V
DD
5
OL
OL
C
Input Capacitance of SDATA and
SCLOCK
IN
C
C
Total Capacitance of SDATA Bus
Total Capacitance of SCLOCK Bus
400
400
pF
pF
SDATA
SCLOCK
Notes:
6. X1 input threshold voltage (typical) is VDDQ3/2.
7. The W48S87-72 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal
is 14 pF; this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
13
W48S87-72
AC Electrical Characteristics
T = 0°C to +70°C, V = V
= 3.3V±5% (3.135–3.465V) f
= 14.31818 MHz, V
= 2.5±5%
DDQ2
A
DD
DDQ3
XTL
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
CPU = 60 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Min. Typ. Max. Min. Typ. Max. Unit
t
15
16.7
ns
P
f
Frequency, Actual
66.8
59.876
MH
z
t
t
t
t
t
High Time
Low Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
5.2
5
6
5.8
1
ns
ns
H
L
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
4
4
4
4
V/ns
V/ns
%
R
F
D
1
1
Duty Cycle
Measured on rising and falling edge at
1.25V
45
52
55
45
52
55
t
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V.
Maximum difference of cycle time be-
tween two adjacent cycles.
250
250
ps
JC
t
f
Output Skew
Measured on rising edge at 1.25V
250
3
250
3
ps
SK
FrequencyStabilization Assumes full supply voltage reached
ms
ST
from Power-up (cold
start)
within 1 ms from power-up. Short cy-
cles exist prior to frequency stabiliza-
tion.
Z
AC Output Impedance Average value during switching transi-
tion. Used for determining series ter-
mination value.
10
10
Ω
o
SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz
CPU = 60 MHz
Parameter
Description
Period
Frequency, Actual
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Min. Typ. Max. Min. Typ. Max. Unit
t
15
16.7
ns
MHz
V/ns
V/ns
%
P
f
t
t
t
66.8
50
59.876
50
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
1
4
4
1
1
4
4
R
F
Duty Cycle
Measured on rising and falling edge at
45
55
45
55
D
1.5V
t
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
JC
t
t
Output Skew
Measured on rising edge at 1.5V
100
100
ps
ps
SK
CPU to SDRAM Clock Covers all CPU/SDRAM outputs. Mea-
Skew
500
3
500
3
SK
sured on rising edge at 1.5V.
f
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
ms
ST
Z
AC Output Impedance Average value during switching transi-
tion. Used for determining series termi-
nation value.
16
16
Ω
o
14
W48S87-72
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz
CPU = 60 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
t
f
t
t
t
t
t
30
33.3
ns
MHz
ns
P
Frequency, Actual
High Time
33.4
29.938
12
12
1
13.3
13.3
1
H
L
Low Time
ns
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
4
4
V/ns
V/ns
%
R
F
D
1
1
Measured on rising and falling edge at
1.5V
45
51
55
45
51
55
t
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maxi-
mum difference of cycle time between
two adjacent cycles.
250
250
ps
JC
t
t
Output Skew
Measured on rising edge at 1.5V
250
4
250
4
ps
ns
SK
CPU to PCI Clock
Skew
Covers all CPU/PCI outputs. Measured
on rising edge at 1.5V. CPU leads PCI
output.
1
1
O
f
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
ST
Z
AC Output Impedance Average value during switching transi-
tion. Used for determining series termi-
nation value.
30
30
Ω
o
I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 60/66.8 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
14.31818
t
t
t
f
1
1
4
4
R
F
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
45
52.5
15
55
D
Frequency Stabilization
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
ST
Z
AC Output Impedance
Average value during switching transition.
Ω
o
Used for determining series termination value.
15
W48S87-72
REF0 Clock Output (Lump Capacitance Test Load = 45 pF)
CPU = 60/66.8 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
14.31818
t
t
t
f
1
1
4
4
R
Measured from 2.4V to 0.4V
F
Measured on rising and falling edge at 1.5V
45
50
16
55
1.5
D
Frequency Stabilization
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Assumes full supply voltage reached within
ms
ST
Z
AC Output Impedance
Average value during switching transition.
Ω
o
Used for determining series termination value.
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 60/66.8 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
Frequency generated by crystal oscillator
14.31818
t
t
t
f
0.5
0.5
45
2
2
R
F
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
55
1.5
D
Frequency Stabilization
ms
ST
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
40
Ω
o
48/24MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 60/66.8 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio
(see n/m below)
48.008/24.004
MHz
f
Deviation from 48 MHz
PLL Ratio
(48.008 – 48)/48
+167
ppm
D
m/n
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
t
t
t
f
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
R
F
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
50
40
55
3
D
Frequency Stabilization
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
ms
ST
Z
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
Ω
o
16
W48S87-72
Serial Input Port
Parameter
Description
Test Condition
Normal Mode
Min.
0
Typ.
Max.
Unit
kHz
µs
f
t
t
t
t
t
SCLOCK Frequency
Start Hold Time
100
SCLOCK
STHD
LOW
4.0
4.7
4.0
250
0
µs
SCLOCK Low Time
SCLOCK High Time
Data Set-up Time
Data Hold Time
µs
HIGH
DSU
ns
(Transmitter should provide a 300-ns hold
time to ensure proper timing at the receiver.)
ns
DHD
t
Rise Time, SDATA and
SCLOCK
From 0.3V to 0.7V
1000
300
ns
ns
R
F
DD
DD
t
Fall Time, SDATA and
SCLOCK
From 0.7V to 0.3V
DD
DD
µs
µs
t
t
Stop Set-up Time
4.0
4.7
STSU
Bus Free Time between
Stop and Start Condition
SPF
ns
t
Allowable Noise Spike
Pulse Width
50
SP
Ordering Information
Freq. Mask
Code
Package
Name
Ordering Code
Package Type
W48S87
72
H
X
48-pin SSOP (300 mils)
48-pin TSSOP
Document #: 38-00855-*A
17
W48S87-72
Package Diagrams
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
18
W48S87-72
Package Diagrams (continued)
48-Pin Thin Shrink Small Outline Package (TSSOP)
12
11
10
9
8
7
6
5
4
3
2
1
H
G
F
H
G
F
THIS TABLE IN MILLIMETERS
S
COMMON
NOTE
VARI-
ATIONS
AA
4
6
Y
M
B
N
DIMENSIONS
NOM.
D
S
N
O
O
L
T
E
MIN.
12.40
13.90
NOM.
12.50
14.00
MAX.
12.60
14.10
MIN.
0.37
0.12
NOM.
0.50
MAX.
MIN.
MAX.
1.10
48
56
A
0.05
0.85
0.17
0.17
0.090
0.090
0.10
0.90
0.15
0.95
0.27
0.23
0.200
0.160
AB
0.25
A1
A2
b
b1
C
8
0.20
8
0.127
SEE VARIATIONS
C1
D
4
4
6.00
6.10
0.50 BSC
8.10
6.20
E
e
H
7.95
0.50
8.25
0.75
0.60
5
6
E
D
C
B
A
L
E
D
C
B
A
N
C
SEE VARIATIONS
OC
0°
4°
8°
THIS TABLE IN INCHES
S
COMMON
NOTE
VARI-
ATIONS
AA
4
6
N
Y
M
B
N
DIMENSIONS
D
S
O
O
L
T
E
MIN.
.488
.547
NOM.
.492
.551
MAX.
.496
.555
MIN.
.0146
.0047
NOM.
.0197
.0098
MAX.
MIN.
NOM.
MAX.
.0433
.006
48
56
A
.002
.0335
.0067
.0067
.0035
.0035
.004
.0354
AB
A1
A2
b
b1
C
.0374
.011
.0090
.0078
.0063
8
.0078
.0050
8
C1
D
SEE VARIATIONS
4
4
.236
.240
.0197 BSC
.319
.244
E
e
H
.313
.020
.325
.030
.024
5
6
L
N
C
SEE VARIATIONS
OC
0°
4°
8°
TITLE
SIZE
PACKAGE OUTLINE, 6.10mm (.240") BODY,
TSSOP, 0.50mm LEAD PITCH
A1 DWG.
NO.
REV.
34389
SHEET
2
02
SCALE
OF
1
2
8/1
12
11
10
9
8
7
6
5
4
3
2
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号:
W49C65-01H
Processor Specific Clock Generator, 75MHz, CMOS, PDSO48, 0.300 INCH, MO-118AA, SSOP-48
CYPRESS
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