Z9953 [CYPRESS]

3.3V, 180MHz, Multi-Output Zero Delay Buffer; 3.3V ， 180MHz的，多输出零延迟缓冲器


型号：	Z9953
厂家：	CYPRESS
描述：	3.3V, 180MHz, Multi-Output Zero Delay Buffer 3.3V ， 180MHz的，多输出零延迟缓冲器
文件：	总6页 (文件大小：46K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Z9953

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Frequency Table

Product Features

BYPASS# PLL_EN VCO_SEL Q(0:7)

FB_OUT

REF

REF/4

REF/8

VCO/4

VCO/8

REF

REF/4

REF/8

VCO/4

VCO/8

•

110MHz Clock Support

Supports PowerPC^TM, Intel and RISC Processors

9 Clock Outputs: drive up to 18 loads

LVPECL Reference Input Clock

Output Disable Control

Spread Spectrum Compatible

3.3V Power Supply

Pin Compatible with MPC953

Industrial Temp. Range: -40°C to +85°C

32-Pin TQFP Package

Table 1

Function Table

BYPASS#

‘1’ = PLL Enabled

‘0’ = PLL Bypass

‘1’ = Outputs Disabled HiZ

‘0’ = Outputs Enabled

‘1’ = VCO/2

‘0’ = VCO

‘1’ = Select VCO

‘0’ = Select PECL_CLK

MR/OE#

VCO_SEL

PLL_EN

Table 2

Pin Configuration

Block Diagram

FB_OUT

Q(0:6)

PECL_CLK

PECL_CLK#

VDD

FB_IN

VSS

Phase

Detector

VDDC

VSS

FB_IN

VCO

200-500M

Z9953 20 Q3

LPF

VDDC

VSS

VCO_SEL

BYPASS#

PECL_CLK

MR/OE#

PLL_EN

Figure 1

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07086 Rev. *B

12/26/2002

Page 1 of 6

Z9953

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Pin Description

NAME

PECL_CLK

PECL_CLK#

Q(7:0)

PWR

I/O

Description

PECL Input Clock.

Clock Output.

12, 14, 16,

18, 20, 22,

24, 26

VDDC

Feedback Clock Output. Connect to FB_IN for normal

operation. A bypass delay capacitor at this output will

control Input Reference / Output phase relationships.

Feedback Clock Input. Connect to FB_OUT for accessing

the PLL.

Master Reset/Output Enable Input. When asserted high,

resets all of the internal flip-flops and also disables all of the

outputs. When pulled low, releases the internal flip-flops

from reset and enables all of the outputs.

FB_OUT

FB_IN

MR/OE#

PLL Select Input. When asserted high, VCO output is

selected. And when set low, PECL_CLK is the input to the

output dividers.

PLL_EN

PLL Enable Input. When high, PLL is enabled and when

low, PLL is bypassed.

VCO Divider Select Input. When set high, VCO output is

divided by 2. When set low, the divider is bypassed.

3.3V Power Supply for Output Clock Buffers.

BYPASS#

VCO_SEL

VDDC

11, 15, 19,

23, 27

3.3V Power Supply for PLL

Common Ground

VDD

VSS

7, 13, 17, 21,

25, 29

3, 4, 5, 6

No Connection

PD = Internal Pull-Down, PU = Internal Pull-Up.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07086 Rev. *B

12/26/2002

Page 2 of 6

Z9953

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Maximum Ratings¹

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

and Vout should be constrained to the range:

Maximum Input Voltage Relative to VSS: VSS - 0.3V

Maximum Input Voltage Relative to VDD: VDD + 0.3V

Storage Temperature:

Operating Temperature:

Maximum ESD protection

-65°C to + 150°C

-40°C to +85°C

2KV

VSS<(Vin or Vout)<VDD

Maximum Power Supply:

Maximum Input Current:

5.5V

±20mA

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD).

DC Parameters

Characteristic

Symbol Min

Typ

Max

0.8

Units

Conditions

Input Low Voltage

VIL

VIH

IIL

VSS

2.0

Input High Voltage

VDD

-120

120

Input Low Current (@VIL = VSS)

Input High Current (@VIL =VDD)

Peak-to-Peak Input Voltage

PECL_CLK

µA

Note 2

Note 3

IIH

VPP

300

1000

Common Mode Range

PECL_CLK

VCMR

VDD-

1.5

VDD-

0.6

Output Low Voltage

Output High Voltage

VOL

VOH

0.6

IOL = 20mA, Note 4

IOH = -20mA, Note 4

VDD-

0.6

Quiescent Supply Current

PLL Supply Current

Input Capacitance

IDDC

IDD

Cin

All VDDC and VDD

VDD only

VDD = VDDC = 3.3V ±5%, TA = -40°C to +85°C

Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT

required.

Note 2: Inputs have pull-up, pull-down resistors that affect input current.

Note 3: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when

the “High” input is within the VCMR range and the input lies within the VPP specification.

Note 4: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Output buffers are dual staged to control

drive strength in order to reduce over/under shoot.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07086 Rev. *B

12/26/2002

Page 3 of 6

Z9953

3.3V, 180MHz, Multi-Output Zero Delay Buffer

AC Parameters¹

SYMBOL

PARAMETER

MIN

TYP

MAX

3.0

UNITS

CONDITIONS

Tr / Tf

Fref

TCLK Input Rise / Fall

Reference Input Frequency²

Reference Input Duty Cycle

PLL VCO Lock Range

110

MHz

FrefDC

Fvco

200

500

MHz

Tlock

Tr / Tf

Fout

Maximum PLL lock Time

Output Clocks Rise / Fall Time^4,5

Maximum Output Frequency

0.10

1.0

0.8V to 2.0V

VCO_SEL = ‘0’

VCO_SEL = ‘1’

Bypass Mode

110

62.5

200

MHz

FoutDC

TCCJ

Output Duty Cycle^4,5

Cycle to Cycle Jitter (peak to

100

peak)^4,5

TSKEW

Tpd

Any Output to Any Output Skew^4,5

250

125

Input to FB_IN Delay (PLL

locked)^3,4,5

-75

tpZL,

tpZH

Output enable time (all outputs)

Output disable time (all outputs)

Input to Q Delay (PLL bypassed)

tpLZ,

tpHZ

Tpd

VDD = VDDC = 3.3V +/- 5%, TA = -40°C to +85°C

Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production.

Note 2: Maximum and minimum input reference is limited by the VCO lock range.

Note 3: The Tpd (PLL locked) is input reference frequency dependent.

Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2) transmission lines.

Note 5: Outputs loaded with 30pF each

Description

The Z9953 is a PLL based clock generator that provides low skew and low jitter clock outputs for high performance

systems. The Z9953 features a differential PLL to minimize cycle-to-cycle and phase jitter. The PLL is

ensured stable operation given that the VCO is configured to run between 200MHz and 500MHz.

The input reference is a differential LVPECL clock. All other control inputs are LVCMOS/LVTTL compatible

The Z9953 features 9 LVCMOS/LVTTL compatible outputs each capable of driving two series terminated 50Ω

transmission lines. With this capability the Z9953 has an effective fan-out of 1:18. The outputs can also be tri-stated when

MR/OE# is set high.

When used as a zero-delay buffer any of the 9 outputs can be used as the feedback input to the PLL. The PLL works to

align the output edge with the input reference edge thus producing a near zero delay.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07086 Rev. *B

12/26/2002

Page 4 of 6

Z9953

3.3V, 180MHz, Multi-Output Zero Delay Buffer

32 Pin TQFP Outline Dimensions

INCHES

MILLIMETERS

SYMBOL

MIN

NOM

MAX

0.047

0.006

0.041

MIN

NOM

MAX

A₁

1.20

0.15

1.05

0.002

0.037

0.05

0.95

0.354

9.00

D₁

0.276

7.00

10°

0.012

0.018

0.30

0.45

A₂

A₁

0.031 BSC

0.80 BSC

0.018

0.030

0.45

0.75

Ordering Information

Part Number

Package Type

Production Flow

Industrial, -40°C to +85°C

Z9953AA

32 PIN TQFP

Note:

The ordering part number is formed by a combination of device number, device revision, package style, and

screening as shown below.

Marking: Example: Cypress

Z9953AA

Date Code, Lot #

Z9953AA

Package

A = TQFP

Revision

Device Number

Notice

Cypress Semiconductor Corp. reserves the right to make changes to its products in order to improve design,

performance or reliability. Cypress Semiconductor Corp. assumes no responsibility for the use of its products in life

supporting and medical applications where the failure or malfunction of the product could cause failure of the life

supporting and medical systems. Products are not authorized for use in such applications unless a written approval is

requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corp. for the use of its

products in the life supporting and medical applications

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07086 Rev. *B

12/26/2002

Page 5 of 6

Z9953

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Document Title: Z9953 3.3V 180 MHz, Multi-Output Zero Delay Buffer

Document Number: 38-07086

Rev. ECN

No.

Issue

Date

Orig. of Description of Change

Change

107122

108065

122771

06/05/01 IKA

07/03/01 NDP

12/26/02 RBI

Convert from IMI to Cypress

Changed Commercial to Industrial (See page 5)

Add power up requirements to maximum ratings

information

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07086 Rev. *B

12/26/2002

Page 6 of 6

Z9953 [CYPRESS]

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