ES51990中文资料_数据手册_规格书

ES51990(6000counts)

DMM Analog front end

Description

Features

ES51990 is an analog frond end chip of

DMM built-in 6000(SADC)/600(FADC)

counts dual ADCs. The SADC is operated at

slower speed for higher resolution. The

FADC is operated at higher speed for lower

resolution. ES51990 provides voltage &

current (AC/DC) measurement, resistance

measurement, capacitance measurement,

diode/continuity measurement, frequency

measurement, and duty cycle measurement.

The ES51990 also supports multi-level

battery detection, low-pass-filter feature for

AC mode and dual mode measurement for

V+F & A+F. A 3-wire serial bus for MPU I/O

port will be used easily for firmware design.

Flexible function design is supported for

different kinds of DMM or Clamp-on meter

application.

• 6000 counts dual-slope SADC (2-5 cnvs/s.)

• Input signal full scale: 630mV (Max. 6300 count)

• Built-in 600 counts fast speed (x10) FADC

• Fast ADC conversion rate: 20-50 times/s

• 100L LQFP package

• 3V DC regulated power supply

• Support digital multi-meter function

*Voltage measurement (AC/DC)

*Current measurement (AC/DC)

*Dual mode for frequency with voltage or current

*Resistance measurement (600.0Ω – 60.00MΩ)

*Capacitance measurement (6.000nF – 60.00mF)

(Taiwan patent no.: 323347, 453443)

*Diode or continuity mode measurement

*Frequency counter with duty cycle display:

60.00Hz – 60.00MHz

5% – 95%

• ADP mode (AC or DC mode is available)

• 3dB BW selectable for low pass filter at AC mode

(Taiwan patent no.: 362409)

.

(China patent no.: 1363073)

• Band-gap reference voltage output

• 3-wire serial bus for MPU I/O port

• MPU I/O power level selectable by external pins

• On-chip buzzer driver and frequency selectable by

MPU command

• High-crest-factor signal detection

(Taiwan patent no.: 234661)

• Multi-level battery voltage detection

• Support sleep mode by external chip select pin

Application

Clamp-on meter

Digital multi-meter

ver 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

Pin Assignment

1

2

3

4

5

6

D

C

B

A

1

75

BUFH

2

NC

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CAZH

3

NC

4

CL+

5

CL-

6

CIL

7

CAZL

8

BUFL

C

B

A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

RAZ

OHMC3

OHMC2

OHMC1

VRH

VA+

FREQ

STBEEP

ES51990

NC

VA-

EXTSRC

NC

LPFOUT

LPC3

LPC2

LPC1

R1K

R9K

NC

OR1

VR5

VR4

VR3

VR2

NC

OVSG

VR1

NC

1

2

3

4

5

6

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12/01/12

ES51990(6000counts)

DMM Analog front end

Pin Description

Pin No

Symbol

BUFH

CAZH

NC

Type

Description

1

2

3

O

-

High-speed buffer output pin. Connect to integral resistor.

High-speed auto-zero capacitor connection.

Not connected

4

5

CL+

CL-

IO Positive connection for reference capacitor of high-resolution A/D.

IO Negative connection for reference capacitor of high- resolution A/D.

6

7

8

9

10

11

12

13

14

CIL

O

I

High-resolution integrator output. Connect to integral capacitor.

High-resolution auto-zero capacitor connection.

High-resolution Buffer output pin. Connect to integral resistor

Buffer output pin in AZ and ZI phase.

Filter capacitor connection for resistance mode.

Output of band-gap voltage reference. Typically –1.23V

De-integrating voltage positive input. The input should be higher than

VA-.

CAZL

BUFL

RAZ

OHMC3

OHMC2

OHMC1

VRH

VA+

15

VA-

I

De-integrating voltage negative input. The input should be lower than

VA+.

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

EXTSRC

NC

OR1

VR5

VR4

VR3

VR2

OVSG

VR1

OVX

OVH

OVH1

NC

I

-

O

I

External source input available for Res/Diode/ADP mode

Not connected

Reference resistor connection for 600.0Ω range

Voltage measurement ÷10000 attenuator(1000V)

Voltage measurement ÷1000 attenuator(600.0V)

Voltage measurement ÷100 attenuator(60.00V)

Voltage measurement ÷10 attenuator(6.000V)

Sense low voltage for resistance/voltage measurement

Measurement Input. Connect to a precise 10MΩ resistor.

Sense input for resistance/capacitance measurement

Output connection for resistance measurement

Output connection1 for resistance measurement (optional)

Not connected

Signal Ground.

Current measurement input for 6000μA, 600mA and 60A modes.

Current measurement input for 600μA, 60mA.

Measurement input in ADP mode.

Independent operational amplifier negative input

Independent operational amplifier positive input

Independent operational amplifier output

DC signal low input in ACV/ACA mode. Connect to negative output

of external AC to DC converter.

I

O

-

G

I

O

NC

SGND

IVSH

IVSL

ADP

OPIN-

OPIN+

OPOUT

ACVL

44

ACVH

O

DC signal high input in ACV/ACA mode. Connect to positive output

of external AC to DC converter.

45

46

47

48

49

ADI

ADO

TEST5

CA-

I

O

Negative input of internal AC-to-DC OPAMP.

Output of internal AC-to-DC OPAMP.

Buffer output of OVSG

IO Negative auto-zero capacitor connection for capacitor measurement

IO Positive auto-zero capacitor connection for capacitor measurement

CA+

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12/01/12

ES51990(6000counts)

DMM Analog front end

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

OHMC4

NC

R9K

O

-

O

-

Filter capacitor connection for resistance mode.

Not connected

Connect to a precise 9KΩ resister for capacitor measurement.

Connect to a precise 1KΩ resister for capacitor measurement.

Capacitor C1 connection for internal low-pass filter

Capacitor C2 connection for internal low-pass filter

Capacitor C3 connection for internal low-pass filter

Capacitor C1 connection for internal low-pass filter

Not connected

R1K

LPC1

LPC2

LPC3

LPFOUT

NC

STBEEP

-

O

Not connected

Fast low-impedance sensed output for CONT./Diode mode Build-in a

internal comparator for OVX pin.

Frequency counter input, offset V-/2 internally by the chip.

Not connected

Crystal oscillator output connection

Crystal oscillator input connection

Set to high to enable ES51990. Set to low to enter sleep mode

MPU I/O level LOW setting. Connect to DGND or V-.

Buzzer frequency output. Normal low state.

Test mode used. Not connected

65

66-77

78

79

80

81

82

83

84

85

86

87

88

89

90

FREQ

NC

OSC2

OSC1

CS

I

-

O

I

-

O

I

IO_CTRL

BZOUT

TEST

DATA_NEW

SCLK

SDATA

C+

New ADC data ready

Serial clock input

IO Serial data input/output

O

I

Positive capacitor connection for on-chip DC-DC converter.

Negative capacitor connection for on-chip DC-DC converter.

Low battery configuration input.

Negative supply voltage.

C-

LBAT

V-

P

91

V-

P

Negative supply voltage.

92

93

94

95

96

97

98

99

uPVCC

V+

DGND

AGND

CH+

P

Switch 5 for function selection.

Output of on-chip DC-DC converter.

Digital ground.

Analog ground.

O

G

IO Positive connection for reference capacitor of high-speed A/D.

IO Negative connection for reference capacitor of high-speed A/D.

CH-

100

CIH

O

High-speed integrator output. Connect to integral capacitor.

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

Absolute Maximum Ratings

Characteristic

Supply Voltage (V- to AGND)

Analog Input Voltage & EXTSRC pin

V+

Rating

-4V

V- -0.6 to V+ +0.6

V+ ≥ (AGND/DGND+0.5V)

AGND/DGND

AGND/DGND ≥ (V- -0.5V)

V- -0.6 to uPVCC+0.6

500mW

Digital Input (IO_CTRL=V-)

Power Dissipation. Flat Package

Operating Temperature

0℃ to 70℃

Storage Temperature

-55℃ to 125℃

Electrical Characteristics

TA=25℃, V- = -3.0V

Parameter

Power supply

Operating supply current

In DCV mode

SADC²Voltage roll-over error

FADC³Voltage roll-over error

Symbol

V-

I_DD

Test Condition

Min.

-2.8

—

Typ.

-3.0

2.8

Max

-3.2

3.2

Units

V

mA

Normal operation

In sleep mode

I_SS

1

3

µA

—

10MΩ input resistor

±0.1 %F.S¹

±0.5 %F.S¹

—

Best case straight

line

Best case straight

line

VA+-VA- = 200mV

SADC²voltage nonlinearity

NLV1

NLV2

±0.1 %F.S¹

—

FADC³voltage nonlinearity

±1.0 %F.S¹

Voltage full scale range of SADC²

Voltage full scale range of FADC³

Input Leakage for VR1 input

Zero input reading

600

1

630

—

mV

pA

—

-10

10

10MΩ input resistor -000

000

+000 Count

Band-gap reference voltage

100KΩ resistor

V_RH

between VRH and

AGND

-1.30

-1.22

-1.14

V

Open circuit voltage for 600Ω range

measurement

Open circuit voltage for other Ω

measurement

—

V-

V

V_RH

Between V- pin and

CS

Internal pull-high to 0V

current

—

1.2

µA

AC frequency response at 6.000V

range

±1%

40-400

400-2000

200

—

HZ

±5%

C_L=10pF

R_L=10MΩ

OP unity gain bandwidth

OP slew rate at unity gain

OP input offset voltage

GB

SR

V_IO

I_B

kHz

V/us

mV

pA

3.5

0.1

OP input bias current

OP input common mode

voltage range

10

—

V_ICR

+2

V

3dB=Full (ADP)

3dB=10k (ADP)

3dB=1k (ADP)

—

10

1

—

100

—

kHz

3dB frequency for LPF⁴active

f_3dB

—

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

—

V_t1

V_t2

V_t3

2.15

2.03

1.83

V

Multi-level low battery detector

LBAT vs. V-

—

STBEEP comparator in Diode mode

STBEEP comparator in Cont. mode

OVX to SGND

+9

-7

mV

—

HCF detection voltage

VR2-VR5

1100

—

mV

mVp

Square wave with

Duty cycle 40-60%

Frequency input sensitivity (FREQ)

Fin

500

400

—

Sine wave

mVrms

Reference voltage temperature

coefficient

100KΩ

Between

resister

VRH

—

ppm/℃

TC_RF

50

0℃<TA<70℃

Capacitance measurement

Accuracy⁵

—

-2.5

-3

2.5

3

%F.S

6.0nF – 60mF

counts

Note:

1. Full Scale (6000 counts for SADC and 600 counts for FADC)

2. SADC = High resolution ADC (slow speed)

3. FADC = High speed ADC (lower resolution)

4. ES51990 built-in 3^rdorder low pass filter available for AC mode

5. Gain calibration is necessary for higher accuracy

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

AC electrical characteristics

Parameter

Symbol

Min.

Typ.

Max.

Unit

kHz

SCLK clock frequency

SCLK clock time “L”

SLCK clock time “H”

SDATA output delay time

SDATA output hold time

Start condition setup time

Start condition hold time

Data input setup time

f_SCLK

t_LOW

t_HIGH

t_AA

-

4.7

4.0

0.1

100

4.7

4.0

200

0

4.7

-

4.7

0

-

100

-

3.5

-

us

t_DH

ns

us

t_SU.STA

t_HD.STA

t_{SU. DAT}

t_HD.DAT

t_SU.STO

t_R

t_F

t_BUF

t_SU.EOC

t_HD.EOC

ns

us

Data input hold time

Stop condition setup time

SCLK/SDATA rising time

SCLK/SDATA falling time

Bus release time

EOC setup time in read mode

EOC hold time in read mode

-

1.0

0.3

-

ns

-

MPU I/O timing diagram

SCLK

SDATA IN

SDATA OUT

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

Function Description

1. MPU serial I/O function overview

1.1 Introduction

ES51990 configures a 3-wire serial I/O interface to external microprocessor unit (MPU).

The SDATA pin is bi-directional and SCLK & DATA_NEW are unilateral. The SDATA pin

is configured by open-drain circuit design. The DATA_NEW is used to check the data

buffer of ADC ready or not. When the ADC conversion cycle is finished, the DATA_NEW

pin will be pulled high until MPU send a valid read command to ES51990. After the first ID

byte is confirmed, the DATA_NEW will be driven to low until the next ADC conversion

finished again.

The data communication protocol is shown below. The write protocol is configured by an

ID byte with four command bytes. The read protocol is configured by an ID byte with ten

data bytes.

Write command:

ID byte, Write control byte1, Write control byte2, Write control byte3, Write control byte4

START BIT

B

U

Z

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

1

0

1

0

STOP BIT

WRITE

Read command:

ID byte, Read data byte1, Read data byte2 ~ Read data byte9, Read data byte10

START BIT

B

U

Z

A

C

K

A

C

K

A

C

K

A

C

K

1

0

1

0

1

READ

A

C

K

N

A

K

STOP BIT

DATA_NEW

SDATA

ADC data ready

ID code confirmed

Next ADC data ready

ID code

0

1

0

1

0

1

Read command

SCLK

Start bit

Stop bit

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

The ID byte of ES51990 is header of “110010” followed by a buzzer on/off control bit and

R/W bit. The start/stop bit definition is shown on the diagram below.

1.2 Read/Write command description

The write command includes one ID byte with four command bytes. If the valid write ID

code is received by ES51990 at any time, the write command operation will be enabled.

The next table shows the content of write command.

Byte

ID

W1

W2

W3

W4

Bit7

1

SHBP

B0

AC

0

Bit6

1

F3

B1

0

Bit5

0

F2

B2

0

Bit4

0

F1

C0

EXT

0

Bit3

1

F0

C1

FS60

0

Bit2

0

Q2

FQ2

LPF1

OP0

Bit1

BUZ

Q1

FQ1

LPF0

OP1

Bit0

R/W=0

Q0

FQ0

FRES

EXT_ADP

0

Auxiliary low-resistance detection control bit for Continuity and Diode modes: SHBP

Measurement function control bit: F3/F2/F1/F0

Range control bit for V/A/R/C modes: Q2/Q1/Q0

Range control bit for Freq mode: FQ2/FQ1/FQ0

Buzzer frequency selection: B2/B1/B0

Buzzer driver ON/OFF control bit: BUZ

ADC conversion rate control bit: C1/C0

AC mode control enable bit: AC

3dB BW for low-pass-filter selection: LPF1/LPF0

External source for Diode mode control bit: EXT

OP configuration control bit: OP1/OP0

Frequency mode input resistance control bit: FRES

ADP mode control bit: EXT_ADP

ADP DC mode full scale control bit: FS60

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

The read command includes one ID byte with ten data bytes. When DATA_NEW is ready¹,

MPU could send the read data command to get the result of ADC conversion

(D0/D1/D2/D3)²or status flag from ES51990.

The next table shows the content of read command.

Byte

ID

R1

R2

R3

R4

R5

R6

R7

Bit7

1

ASIGN

HF

D0:3

D0:11

D1:0

D1:8

D2:6

D2:14

D3:3

D3:11

Bit6

1

BSIGN

LF

D0:4

D0:12

D1:1

D1:9

D2:7

D2:15

D3:4

D3:12

Bit5

0

X

Bit4

0

X

Bit3

1

Bit2

0

Bit1

BUZ

STA0

D0:1

D0:9

D0:17

D1:6

D2:4

D2:12

D3:1

D3:9

D3:17

Bit0

R/W=1

ALARM

D0:2

D0:10

D0:18

D1:7

D2:5

D2:13

D3:2

BTS0

F_FIN

D0:7

D0:15

D1:4

D2:2

D2:10

D2:18

D3:7

D3:15

BTS1

D0:0

D0:8

D0:16

D1:5

D2:3

D2:11

D3:0

D3:8

D3:16

LDUTY

D0:5

D0:13

D1:2

D2:0

D2:8

D2:16

D3:5

D3:13

STA1

D0:6

D0:14

D1:3

D2:1

D2:9

D2:17

D3:6

D3:14

R8

R9

R10

D3:10

D3:18

¹Note: DATA_NEW will be active with D1 data updated when one fast ADC (FADC) conversion finished. If

MCU access slow ADC output only, ten FADC conversion cycle delay is necessary. DATA_NEW for

frequency or capacitance mode will be active when D0 or D3 data ready.

²Note: D0/D1/D2/D3 all are binary code format. D0 is SADC output and D1 is FADC output

The ADC data output for measurement mode: F3/F2/F1/F0

F3

0

1

F2

0

1

0

F1

0

1

0

1

0

1

F0

0

1

0

1

0

1

0

1

0

1

0

Measurement mode

V mode

Read data bytes

D0(0:18), D1(0:9)

ACV + Hz mode

A mode

D0(0:18), D1(0:9), D3(0:18)

D0(0:18), D1(0:9)

ACA + Hz mode

Resistance mode

Continuity mode

Diode mode

D0(0:18), D1(0:9), D3(0:18)

D0(0:18), D1(0:9)

F + duty mode

D0(0:18), D2(0:18), D3(0:18)

Capacitance Mode D0(0:18)

ADP mode

D0(0:18), D1(0:9)

D0(0:18), D1(0:9), D3(0:18)

ADP + Hz mode

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

Buzzer frequency selection: B2/B1/B0

B2

0

1

B1

0

1

0

1

B0

0

1

0

1

0

1

0

1

Buzzer frequency

1.00kHz

1.33kHz

2.00kHz

2.22kHz

2.67kHz

3.08kHz

3.33kHz

4.00kHz

Set B2-B0 properly to get the target frequency. Use BUZ control bit to enable/disable the

BUZOUT (pin82) driver output. If MPU control BUZ only, it is available to set ID byte with

ending of stop bit.

A

C

K

R

/W

START BIT

1

0

1

0

STOP BIT

Buzzer OFF

R

/W

1

1 0 0 1 0 1

Buzzer ON

ADC conversion rate selection: C1/C0

C1

C0

SADC Conversion Time

(High resolution ADC)

FADC Conversion Time

SADC Line

noise rejection

50/60Hz

50Hz

(High speed ADC)

0

1

0

1

0

1

500ms

300ms

250ms

200ms

50ms

30ms

25ms

20ms

60Hz

50Hz

Set C1-C0 to change the target conversion rate for SADC & FADC simultaneously.

ver. 2.8

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ES51990(6000counts)

DMM Analog front end

Status flags for measurement mode: ● = function available

Measurement mode

V mode

ACV + Hz mode

A mode

ACA + Hz mode

Res. mode

ASIGN

●

BSIGN

●

BTS0

●

BTS1

●

ALARM

●

Cont. mode

Diode mode

F + duty mode

Cap. Mode

●

ADP mode

●

ADP + Hz mode

Measurement mode

V mode

HF

●

LF

●

LDUTY

STA0

STA1

●

F_FIN

●

V + Hz mode

A mode

A + Hz mode

Res. mode

●

Cont. mode

Diode mode

F + duty mode

Cap. Mode

ADP mode

ADP + Hz mode

●

Description of status flags:

ASIGN: Sign bit of SADC output (-1 * D0 if ASIGN=1)

BSIGN: Sign bit of FADC output (-1 * D1 if BSIGN=1)

BTS0/BTS1: Multi-level battery voltage indication

ALARM: Large capacitor indication/High crest factor signal detection in ACV mode

HF: Higher frequency indication for Hz mode

LF: Lower frequency indication for Hz mode

LDUTY: Low duty indication for Hz + duty mode

STA0/STA1: divider indication for Hz mode

STA0: Status flag for capacitor discharging mode

F_FIN: Measurement cycle finished for Hz mode

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

1.3 Power & I/O level selection

The ES51990 provide a flexible I/O level setting for different MPU system configuration.

The uP_VCC should be connected to the same potential of external Vcc of MCU. The

uP_VCC is allowed to be set between DGND ~ V+. The IO_CTRL pin selects the Vss level

of MCU. If IO_CTRL is set to DGND, the Vss level of MCU is the same as DGND. If

IO_CTRL is set to V-, the Vss level of MCU is the same as V-.

ver. 2.8

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12/01/12

ES51990(6000counts)

DMM Analog front end

2. Operating Modes

2.1. Voltage Measurement

MPU send write command to select the voltage measurement function. The Hz mode

measurement is available to be enabled with the ACV function (set AC bit to 1)

simultaneously. The measured signal is applied to VR1 terminal (pin25) through 10MΩ.

See the next table of function command:

F3

0

F2

0

F1

0

F0

0

AC

0

Measurement mode

DCV mode

Read data bytes

D0(0:18), D1(0:9)

0

1

ACV mode

D0(0:18), D1(0:9)

0

1

ACV + Hz mode

D0(0:18), D1(0:9), D3(0:18)

Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Range control for voltage mode (ACV/DCV)

Q2 Q1 Q0

Full Scale Range

600.0mV

6.000V

Divider Ratio

1

Resister Connection

VR1 (10MΩ)

VR2 (1.111MΩ)

VR3 (101kΩ)

VR4 (10.01kΩ)

VR5 (1kΩ)

0

1

0

1

0

1

0

1

0

1/10

1/100

1/1000

1/10000

60.00V

600.0V

1000V

Frequency range control for ACV+Hz mode

FQ2 FQ1 FQ0 Full Scale Range

0

1

0

1

0

1

60.00Hz

600.0Hz

6.000kHz

60.00kHz

Note: See frequency mode (section 2.8) also

ALARM bit at voltage mode is used for high crest factor (HCF) signal detection. If MPU

check the ALARM status flag active when data and range are stable, it should consider the

making the existing range up to avoid the signal clamping saturation caused by HCF signal.

There is higher peak voltage with lower RMS value for HCF signal. So if the range is up

according to the ALARM bit, MCU should set the lower under-limit counts temporarily to

avoid the ranging unstable for this case.

ver. 2.8

14

12/01/12

ES51990(6000counts)

DMM Analog front end

2.2 Current measurement

MPU send write command to select the current measurement function. The Hz mode

measurement is available to be enabled with the ACA function (set AC bit to 1)

simultaneously. The measured signal is applied to IVSL/IVSH terminals (pin37-38).

See the next table of function command:

F3

0

F2

0

F1

1

F0

0

AC

0

Measurement mode

DCA mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

1

ACA mode

D0(0:18), D1(0:9)

0

1

ACA + Hz mode

D0(0:18), D1(0:9), D3(0:18)

Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Range control for current mode (ACA/DCA)

Q2 Q1 Q0

Full Scale Range

300mV 6000counts

Input terminal

IVSL

0

1

IVSH

Current measurement mode configuration example: (max. voltage drop 300mV)

90K

600.0 / 6000uA

FUSE

1

60.00 / 600.0mA

V - V +

10K

uA / mA

49.5

2

3

-

100K

6

TL061

+

IVSL

IVSH

V -

V +

V -

0.495

100K

Zero Offset

FUSE

1. 5K

6A/ 20A

1

0.1uF

A

0.005

100K

1

COM

AGND

SGND

(max voltage drop = ~ 1V)

0.005

20A

6A

0.045

0.45

mA

4.5

45

mA

uA

A

100K

IVSH

IVSL

mA

uA

450

Frequency range control for ACA+Hz mode

ver. 2.8

15

12/01/12

ES51990(6000counts)

DMM Analog front end

FQ2 FQ1 FQ0 Full Scale Range

0

1

0

1

0

1

60.00Hz

600.0Hz

6.000kHz

60.00kHz

Note: See frequency mode (section 2.8) also.

2.3 Low pass filter (LPF) mode for ACA/ACV mode

A 3^rdorder low pass filter with is built in ES51990. The 3dB bandwidth of the low pass

filter could be selectable by MPU. The LPF mode is active when the LPF control bit is set

to be active.

The LPF mode is allowed to be enabled in F + duty mode to reject high-frequency noise

for sine wave input, but the 3dB will be fixed at 10kHz only.

LPF1

LPF0

Low pass filter effect

Disable

0

1

0

1

0

1

3dB = 1kHz

3dB = 10kHz

3dB > 100kHz

2.4 Resistance Measurement

MPU send write command to select the resistance measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

Resistance mode

Note1: D0/D1 both are binary format. ASIGN/BSIGN bits are ignored.

Range control for resistance mode

Q2 Q1 Q0 Full Scale Range

Relative Resistor

OR1

Equivalent value

100Ω

0

1

0

1

0

1

0

1

0

1

600.0Ω

6.000KΩ

60.00KΩ

600.0KΩ

6.000MΩ

60.00MΩ

VR5

1KΩ

10KΩ

100KΩ

1MΩ

10MΩ

VR4 || VR1

VR3 || VR1

VR2 || VR1

VR1

ver. 2.8

16

12/01/12

ES51990(6000counts)

DMM Analog front end

2.5 Capacitance Measurement

MPU send write command to select the capacitance measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18)

1

0

Capacitance mode

Note1: D0 is binary format. ASIGN bit is ignored.

Range control for capacitance mode

Measurement Period

0.5 sec

Q2

0

1

Q1

0

1

0

1

Q0

0

1

0

1

0

1

0

1

Full Scale Range Relative Resistor

6.000nF

60.00nF

600.0nF

6.000uF

60.00uF

600.0uF

6.000mF

60.00mF

-

0.5 sec

1.25 sec

OVX pin VR

-

0.4 sec max.

0.5 sec max.

1.0 sec max.

1.35 sec max.

6.75 sec max.

R9K / R1K



ALARM bit at capacitance mode is used for increasing the ranging speed. If MPU

check the ALARM=1 at lower range, it could set the next range to 6.000uF directly

and the ADC output should be ignored.

STA0 status bit is used for detection of DUT capacitor voltage. If STA0=1, the internal

capacitor discharging mode is active and the capacitance measurement is inhibited. It is

recommended to discharge the DUT capacitor externally.

2.6 Continuity Check measurement

MPU send write command to select the continuity measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

1

Continuity mode

Note1: D0/D1 both are binary format. ASIGN/BSIGN bits both are ignored.

Continuity mode shares the same configuration with 600.0Ω resistance measurement circuit

and support the low-resistance detection. If the STBEEP output (pin64) is low, it means the

low-resistance status is detected (It means the OVX terminal voltage less than -7mV). It

could be faster than the FADC result, so MPU could monitor the STBEEP output and FADC

(D1) data output make the high speed detection for short circuit detection. Set SHBP=1 to

enable the built-in buzzer driving automatically when STBEEP is active.

ver. 2.8

17

12/01/12

ES51990(6000counts)

DMM Analog front end

2.7 Diode Measurement

MPU send write command to select the diode measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

Diode mode

Note1: D0/D1 both are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Diode measurement mode shares the same configuration with 6.000V voltage measurement

circuit and support the low-resistance detection. If the STBEEP output (pin64) is low, it

means the low-resistance status is detected (It means the OVX terminal voltage less than

9mV). It could be faster than the FADC result, so MPU could monitor the STBEEP output

and FADC (D1) data output make the high speed detection for short circuit detection. Set

SHBP=1 to enable the built-in buzzer driving automatically when STBEEP is active.

The default source voltage at diode mode is the same as V+ potential. MPU could set the

control bit EXT=1 to change the source voltage to external source. The external voltage

source (positive or negative) input applied from EXTSRC (pin16). The available external

source range should be from V+ to V-.

ver. 2.8

18

12/01/12

ES51990(6000counts)

DMM Analog front end

2.8 Frequency/duty cycle mode measurement

The default typical input impedance of frequency with duty cycle mode is 1MΩ. The MPU

could set control bit FRES=1 to change the input impedance down to 100kΩ. MPU send

write command to select the frequency/duty cycle measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

0

1

Hz + Duty mode

D0(0:18), D2(0:18), D3(0:18)

Note1: D0/D2/D3 all are binary format. ASIGN bit is ignored.

Note2: Set LPF1 = 1 to enable the smooth function for sine wave input automatically

Range control for frequency mode

FQ2 FQ1 FQ0

Full Scale

60.00Hz

600.0Hz

6.000KHz

60.00KHz

600.0KHz

6.000MHz

60.00MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

Available minimum frequency input (Depends on ADC conversion rate setting)

C1

0

C0

0

F_MIN(AC+Hz mode) F_MIN(Hz+Duty mode)

4.00Hz

0

1

0

6.00Hz

4.00Hz

8.00Hz

1

10.00Hz

Frequency & duty cycle mode computed by D0/D2/D3 (if F_FIN=1)

Flag

STA0=0

STA0=1

Range

STA1=1

STA1=0

60.00Hz

600.0Hz

FREQ=100000000/D3

FREQ=10000000/D3

FREQ=2000000/D3

FREQ=200000/D3

FREQ=400000000/D3

FREQ=40000000/D3

FREQ=32000000/D3

FREQ=25600000/D3

FREQ=800000000/D3

FREQ=160000000/D3

FREQ=256000000/D3

FREQ=204800000/D3

6.000KHz

60.00KHz

600.0KHz

6.000MHz

60.00MHz

FREQ = D0

Status Flag

LDUTY=1

LDUTY=0

Duty cycle (<60kHz)

10000-D2*10000/D3

D2*10000/D3

ver. 2.8

19

12/01/12

ES51990(6000counts)

DMM Analog front end

The status flag F_FIN indicate the frequency input signal available (> F_MIN) or not. If the

computed result less than F_MIN, the frequency/duty cycle readings should be set to zero.

The status flags HF & LF are used for fast judgment of proper range. If frequency input is

larger than 7 kHz, HF will be active. If frequency input is floating or frequency detected too

low, LF will be active.

Auto range consideration for MPU by using Status Flags of frequency mode

Flag

Range

60.00Hz

F_FIN=0

LF=0

F_FIN=1

LF=1*

Hz/Duty=0

F_FIN=1

HF=LF=0

HF=1**

Set range to

600.0Hz

6.000KHz

60.00KHz

600.0KHz

6.000MHz

60.00MHz

60.00kHz range

Change range

depends on data

computed

Data and Range

is not necessary

to be updated

Set range to

60.00Hz range

Change range

depends on data

computed

*Note: LF=1 @ 60Hz range implies the frequency is not available to be measured. The Hz/Duty readings

should be set to zero.

**Note: When ACV+Hz/ACA+Hz/ADP+Hz mode is selected, the HF status should be ignored. Change range

depends on data calculation result.

Duty cycle mode range (Input sensitivity > 2Vpp @ duty cycle= 5.0% or 95.0%)

Freq. range

Duty range

60.00Hz

600.0Hz

5.0% - 95.0%

6.000KHz

60.00KHz

10.0% - 90.0%

20.0% – 80.0%

ver. 2.8

20

12/01/12

ES51990(6000counts)

DMM Analog front end

2.9 ADP mode

MPU send write command to select the ADP mode measurement function. The Hz mode

measurement is available to be enabled with the ADP AC function (set AC bit to 1)

simultaneously. The measured signal is applied to ADP terminal (pin39). The signal full

scale is 600mV for DC mode and 600mVrms for AC mode. The FS60 control bit is used for

ADP DC mode. When FS60=1, the full scale will be change from 600mV to 60mV. It

means the resolution will be improved to 0.01mV, but the ADC conversion rate will be

reduced to 0.9 /sec.

See the next table of function command:

F3

1

F2

0

F1

0

F0

1

AC

0

Measurement mode

ADP DC mode

Read data bytes

D0(0:18), D1(0:9)

1

0

1

ADP AC mode

D0(0:18), D1(0:9)

1

0

1

0

1

ADP + Hz mode

D0(0:18), D1(0:9), D3(0:18)

Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Frequency range control for ADP+Hz mode

FQ2 FQ1 FQ0 Full Scale Range

0

1

0

1

0

1

60.00Hz

600.0Hz

6.000kHz

60.00kHz

Note: See frequency mode (section 2.8) also

If MPU set the control bit EXT_ADP=1, the voltage on EXTSRC pin could be switched to

ADP terminal internally. It is helpful for a voltage pulled application of ADP mode.

External source

pull high or low

EXT_ADP

ADC IN+

ADP_IN

ADC IN-

SGND

ver. 2.8

21

12/01/12

ES51990(6000counts)

DMM Analog front end

2.10 Sleep

Set CS pin (pin 80) to logic low to make the ES51990 entering the sleep mode. The current

consumption will be less than 3uA typically. Set CS pin to logic high or kept floating, the

ES51990 will return to normal operation.

2.11 Multi-level battery voltage indication

The ES51990 is built-in a comparator for batter voltage indication. The voltage is applied to

LBAT pin (pin 89) vs. V- terminal. MPU could check the status bit BTS1/BTS0 and monitor

the LBAT voltage status.

Battery voltage

V_LBT> V_t1

V_t2< V_LBT< V_t1

V_t3< V_LBT< V_t2

V_LBT< V_t3

BTS1

BST0

1

0

1

0

1

0

Low battery configuration for 9V/1.5V*4/1.5V*3 battery

Low battery test circuit (a)

Low battery test circuit (b)

6V

9V

360K

BA

470K

BA

LBAT

TT

0.1u

TT

0.1u

AGND

V-

AGND

V-

270K

180K

0V

Low battery test circuit (c)

4.5V

360K

BA

LBAT

TT

0.1u

AGND

V-

470K

0V

ver. 2.8

22

12/01/12

ES51990(6000counts)

DMM Analog front end

2.12 Independent OPAMP

ES51990 is built-in an independent OPAMP with low drift offset using for general purpose.

MPU could control the OP1/OP0 to change the OPAMP configuration:

OP1

OP0

OPAMP configuration

Normal

0

1

0

1

0

1

OP disable

Unity gain buffer

Zero calibration

Independent OPAMP configuration

Normal operation

OPIN-

OPIN+

OPOUT

-

+

Zero offset calibration

OPOUT

OPIN-

OPIN+

-

+

Unity gain operation

OPOUT

OPIN-

OPIN+

-

+

ver. 2.8

23

12/01/12

ES51990(6000counts)

DMM Analog front end

3. Application Circuit

3.1 AVG circuit

Close to IC

+

26

27

28

29

30

31

32

33

34

35

36

100

OVX

OVH

OVH1

NC

CIH

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

C4

10nF

CH-

CH+

AGND

DGND

V+

NC

V+

VCC

NC

u PVCC

V-

NC

SGND

IVSH

IVSL

ADP

OPIN-

OPIN+

OPOUT

ACVL

ACVH

ADI

V-

IVSH 100K

IVSL 100K

ADP 100K

R6 37

R7 38

R8 39

40

LBAT9

C5

L BAT

C-

470nF

C+

OPIN-

OPIN+

OPout

ACVL

ACVH

ADI

SDA

SCL

SDATA

SCL K

DATA_new

NC

41

42

84 DATA_new

83

82 BUZOUT

81

80

79

78

77

76

43

44

BZOUT

IO_ CT RL

CS

45

VSS

CS

ADO

46

ADO

TEST5

CA-

CA+

OHM C4

TEST5

47

OSC1

OSC2

NC

C8 470nF+/- 10% 48

49

50

NC

+

ver. 2.8

24

12/01/12

ES51990(6000counts)

DMM Analog front end

3.2 RMS circuit (ES636)

Close to IC

+

S

R M C V A

W S 2

26

27

28

29

30

31

32

33

34

35

36

100

OVX

OVH

OVH1

NC

CIH

CH-

99 C4

10nF

98

CH+

97

AGND

DGND

V+

96

NC

95

NC

94

NC

93

NC

V+

92 VCC

91

NC

u PVCC

V-

NC

90

SGND

IVSH

IVSL

ADP

OPIN-

OPIN+

OPOUT

ACVL

ACVH

ADI

V-

IVSH 100K

IVSL 100K

ADP 100K

R6 37

R7 38

R8 39

40

89 LBAT9

88 C5

87

L BAT

C-

470nF

C+

OPIN-

OPIN+

OPout

86 SDA

85 SCL

84 DATA_new

83

SDATA

SCL K

41

42

DATA_new

NC

43

ACVH

ADI

44

82 BUZOUT

81 VSS

80 CS

79

BZOUT

IO_ CT RL

CS

45

46

ADO

TEST5

CA-

CA+

OHM C4

47

OSC1

OSC2

NC

C8 470nF+/- 10% 48

78

49

50

77

76

NC

+

C24

2.2uF

ver. 2.8

25

12/01/12

ES51990(6000counts)

DMM Analog front end

4. Package Information

4.1 100L LQFP Outline drawing

4.2 Dimension parameters

ver. 2.8

26

12/01/12

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ES51990

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