MTE2D0N06RFP [CYSTEKEC]

N-Channel Enhancement Mode Power MOSFET;


型号：	MTE2D0N06RFP
厂家：	CYSTECH ELECTONICS CORP.
描述：	N-Channel Enhancement Mode Power MOSFET
文件：	总8页 (文件大小：652K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 1/ 8

N-Channel Enhancement Mode Power MOSFET

MTE2D0N06RFP

BVDSS

ID@VGS=10V, TC=25°C

60V

125A(silicon limit)

17.7A

Features

ID@VGS=10V, TA=25°C

RDS(ON)@VGS=10V, ID=50A

2.8mΩ(typ)

 Low On Resistance

 Simple Drive Requirement

 Low Gate Charge

 Fast Switching Characteristic

 Insulating package, front/back side insulating voltage=2500V(AC)

 RoHS compliant package

Symbol

Outline

TO-220FP

MTE2D0N06RFP

G：Gate D：Drain S：Source

G D S

Ordering Information

Device

Shipping

50 pcs/tube, 20 tubes/box, 4 boxes / carton

Package

TO-220FP

(RoHS compliant)

MTE2D0N06RFP-0-UB-G

Environment friendly grade : S for RoHS compliant products, G for RoHS compliant

and green compound products

Packing spec, UB : 50 pcs / tube, 20 tubes/box

Product rank, zero for no rank products

Product name

MTE2D0N06RE3

CYStek Product Specification

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 2/ 8

Absolute Maximum Ratings (TC=25C)

Parameter

Symbol

Limits

Unit

Drain-Source Voltage (Note 1)

Gate-Source Voltage

Continuous Drain Current @ TC=25C, VGS=10V (silicon limit) (Note 1)

Continuous Drain Current @ TC=100C, VGS=10V (silicon limit) (Note 1)

Continuous Drain Current @ TC=25C, VGS=10V (package limit) (Note 1)

VDS

VGS

±20

125

17.7

14.2

500

100

Continuous Drain Current @TA=25C, VGS=10V

Continuous Drain Current @TA=70C, VGS=10V

Pulsed Drain Current @ VGS=10V

(Note 2)

IDSM

(Note 2)

IDM

IAS

Avalanche Current @L=0.1mH

Single Pulse Avalanche Energy @ L=1mH, ID=50 Amps, VDD=25V

EAS

EAR

1250

(Note 4)

Repetitive Avalanche Energy

(Note 3)

(Note 1)

(Note 2)

100

TC=25C

TC=100C

TA=25C

TA=70C

Power Dissipation

PDSM

1.3

Maximum Temperature for Soldering @ Lead at 0.063 in(1.6mm)

from case for 10 seconds

Maximum Temperature for Soldering @ Package Body for 10

seconds

300

260

C

TPKG

Operating Junction and Storage Temperature

Tj, Tstg -55~+175

*Drain current limited by maximum junction temperature

Thermal Data

Parameter

Thermal Resistance, Junction-to-case, max

Thermal Resistance, Junction-to-ambient, max (Note 2)

Symbol

RθJC

RθJA

Value

1.5

62.5

Unit

C/W

Note : 1 The power dissipation P_Dis based on T_J(MAX)=175 C, using junction-to-case thermal resistance, and is more useful

in setting the upper dissipation limit for cases where additional heatsinking is used.

2 The value of R_θJAis measured with the device mounted on 1 in²FR-4 board with 2 oz. copper, in a still air environment

with T_A=25 C. The power dissipation P_DSMis based on R_θJAand the maximum allowed junction

temperature of 150°C. The value in any given application depends on the user’s specific board design, and the

maximum temperature of 175°C may be used if the PCB allows it.

3 Repetitive rating, pulse width limited by junction temperature T_J(MAX)=175 C. Ratings are based on low frequency

and low duty cycles to keep initial TJ=25°C.

4. 100% tested by condition of VDD=25V, ID=25A, L=1mH, VGS=15V.

5. The static characteristics are obtained using <300μs pulses, duty cycle 0.5% maximum.

6. The RθJA is the sum of thermal resistance from junction to case RθJC and case to ambient.

MTE2D0N06RE3

CYStek Product Specification

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 3/ 8

Characteristics (Tj=25C, unless otherwise specified)

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Static

BV_DSS

∆BV_DSS/∆Tj

V_GS(th)

24.2

2.8

100

mV/C

V_GS=0V, I_D=250μA

Reference to 25C, I_D=250μA

V_DS= V_GS, I_D=250μA

V_DS=10V, I_D=20A

*G_FS

I_GSS

V_GS= 20V, V_DS=0V

V_DS=48V, V_GS=0V

V_DS=48V, V_GS=0V, Tj=125C

V_GS=10V, I_D=50A

I_DSS

μA

*R_DS(ON)

Dynamic

*Qg

3.7

124

*Qgs

*Qgd

*t_d(ON)

*tr

*t_d(OFF)

*t_f

Ciss

Coss

Crss

V_DD=48V, I_D=50A,V_GS=10V

35.9

48.4

40.6

77.6

27.8

7289

1179

151

V_DD=30V, I_D=50A, V_GS=10V, R_G=1

V_GS=0V, V_DS=30V, f=1MHz

f=1MHz

1.4

Source-Drain Diode

*I_S

*I_SM

*V_SD

*trr

500

1.2

0.83

42.3

43.3

I_S=30A, V_GS=0V

V_GS=0V, I_F=30A, dI_F/dt=100A/μs

*Qrr

*Pulse Test : Pulse Width 300μs, Duty Cycle2%

MTE2D0N06RE3

CYStek Product Specification

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 4/ 8

Typical Characteristics

Brekdown Voltage vs Ambient Temperature

Typical Output Characteristics

1.4

1.2

200

180

160

140

120

100

10V, 9V, 8V

0.8

0.6

0.4

ID=250μA,

VGS=0V

VGS=4.5V

-75 -50 -25

25 50 75 100 125 150 175 200

Tj, Junction Temperature(°C)

VDS, Drain-Source Voltage(V)

Static Drain-Source On-State resistance vs Drain Current

Reverse Drain Current vs Source-Drain Voltage

1.2

VGS=0V

VGS=10V

0.8

0.6

0.4

0.2

Tj=25°C

Tj=150°C

10 12 14 16 18 20

0.1

100

ID, Drain Current(A)

IDR, Reverse Drain Current(A)

Drain-Source On-State Resistance vs Junction Tempearture

VGS=10V, ID=50A

Static Drain-Source On-State Resistance vs Gate-Source

Voltage

2.4

ID=50A

1.6

1.2

0.8

0.4

RDS(ON)@Tj=25°C : 2.8mΩ typ.

-75 -50 -25

25 50 75 100 125 150 175 200

VGS, Gate-Source Voltage(V)

Tj, Junction Temperature(°C)

MTE2D0N06RE3

CYStek Product Specification

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 5/ 8

Typical Characteristics(Cont.)

Threshold Voltage vs Junction Tempearture

Capacitance vs Drain-to-Source Voltage

10000

1.4

1.2

Ciss

ID=1mA

0.8

0.6

0.4

0.2

1000

Coss

ID=250μA

Crss

100

-75 -50 -25

25 50 75 100 125 150 175 200

VDS, Drain-Source Voltage(V)

Tj, Junction Temperature(°C)

Forward Transfer Admittance vs Drain Current

VDS=10V

Gate Charge Characteristics

100

VDS=30V

VDS=12V

VDS=48V

VDS=15V

0.1

0.01

Ta=25°C

Pulsed

ID=50A

100 120

140

0.001

0.01

0.1

100

Qg, Total Gate Charge(nC)

ID, Drain Current(A)

Maximum Drain Current vs Case Temperature

Maximum Safe Operating Area

150

120

1000

100

RDS(ON)

10μs

Limited

silicon limit

100μs

1ms

10ms

package limit

100ms

TC=25°C, Tj=175°C,

VGS=10V,RθJC=1.5°C/W

single pulse

VGS=10V, RθJC=1.5°C/W

0.1

100

125

150 175

200

0.1

100

VDS, Drain-Source Voltage(V)

TC, Case Temperature(°C)

MTE2D0N06RE3

CYStek Product Specification

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 6/ 8

Typical Characteristics(Cont.)

Single Pulse Maximum Power Dissipation

Typical Transfer Characteristics

200

1500

1200

900

600

300

VDS=10V

180

TJ(MAX)=175°C

TC=25°C

160

140

120

100

RθJC=1.5°C/W

0.0001

0.001

0.01 0.1

Pulse Width(s)

VGS, Gate-Source Voltage(V)

Transient Thermal Response Curves

D=0.5

1.RθJC(t)=r(t)*RθJC

0.2

0.1

2.Duty Factor, D=t1/t2

3.TJM-TC=PDM*RθJC(t)

4.RθJC=1.5 °C/W

0.05

0.02

0.1

0.01

Single Pulse

1.E-03

0.01

1.E-04

1.E-02

1.E-01

1.E+00

1.E+01

t1, Square Wave Pulse Duration(s)

MTE2D0N06RE3

CYStek Product Specification

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 7/ 8

Recommended wave soldering condition

Product

Peak Temperature

Soldering Time

5 +1/-1 seconds

Pb-free devices

260 +0/-5 C

Recommended temperature profile for IR reflow

Profile feature

Average ramp-up rate

(Tsmax to Tp)

Sn-Pb eutectic Assembly

Pb-free Assembly

3C/second max.

Preheat

−Temperature Min(TS min)

−Temperature Max(TS max)

−Time(ts min to ts max)

100C

150C

60-120 seconds

150C

200C

60-180 seconds

Time maintained above:

−Temperature (TL)

− Time (tL)

183C

60-150 seconds

217C

60-150 seconds

Peak Temperature(TP)

240 +0/-5 C

260 +0/-5 C

Time within 5C of actual peak

temperature(tp)

10-30 seconds

20-40 seconds

Ramp down rate

6C/second max.

6 minutes max.

8 minutes max.

Time 25 C to peak temperature

Note : All temperatures refer to topside of the package, measured on the package body surface.

MTE2D0N06RE3

CYStek Product Specification

Spec. No. : C037E3

Issued Date : 2018.09.27

Revised Date :

CYStech Electronics Corp.

Page No. : 8/ 8

TO-220FP Dimension

Marking:

E2D0

N06R

Device Name

Date Code

3-Lead TO-220FP Plastic Package

CYStek Package Code: FP

Style: Pin 1.Gate 2.Drain 3.Source

*Typical

Millimeters

Inches

DIM

Millimeters

Inches

DIM

Min.

Max.

Min.

4.35

Max.

4.65

Min.

0.246

Max.

0.258

Min.

6.25

Max.

6.55

0.171

0.183

0.051 REF

1.300 REF

0.138 REF

0.055 REF

0.256 0.272

3.50 REF

1.40 REF

6.50 6.90

0.112

0.102

0.020

0.031

0.124

0.110

0.030

0.041

2.85

2.60

0.50

0.80

3.15

2.80

0.75

1.05

0.031 REF

0.020

0.80 REF

0.50 REF

0.047 REF

1.20 REF

1.102

0.043

0.036

1.118

0.051

0.043

28.00

1.10

0.92

28.40

1.30

1.08

0.020

0.396

0.583

0.030

0.404

0.598

0.500

10.06

14.80

0.750

10.26

15.20

0.067 REF

0.012 REF

1.70 REF

0.30 REF

0.100 *

0.106 REF

2.54*

2.70 REF

Notes: 1.Controlling dimension: millimeters.

2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material.

3.If there is any question with packing specification or packing method, please contact your local CYStek sales office.

Material:

 Lead: Pure tin plated.

 Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0.

Important Notice:

 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.

 CYStek reserves the right to make changes to its products without notice.

 CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.

 CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.

MTE2D0N06RE3

CYStek Product Specification

相关型号：