DS1217M1-25 [DALLAS]

Nonvolatile Read/Write Cartridge; 非易失性读/写墨盒


型号：	DS1217M1-25
厂家：	DALLAS SEMICONDUCTOR
描述：	Nonvolatile Read/Write Cartridge 非易失性读/写墨盒存储内存集成电路静态存储器
文件：	总8页 (文件大小：87K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS1217M

Nonvolatile Read/Write Cartridge

FEATURES

PIN ASSIGNMENT

• User-insertable

Name

Position

Name

Ground

+5 Volts

No Connect

Address 14

Address 12

Address 7

Address 6

Address 5

Address 4

Address 3

Address 2

Address 1

Address 0

Data I/O 0

Data I/O 1

Data I/O 2

Ground

• Data retention greater than 5 years

• Capacity up to 512K x 8

Write Enable

Address 13

Address 8

• Standard bytewide pinout facilitates connection to

JEDEC 28-pin DIP via ribbon cable

Address 9

• Software-controlled banks maintain 32 x 8 JEDEC

28-pin compatibility

Address 11

Output Enable

Address 10

Cartridge Enable

Data I/O 7

• Multiple cartridges can reside on a common bus

A10

A11

A12

A13

A14

A15

B10

B11

B12

B13

B14

B15

• Automatic write protection circuitry safeguards

against data loss

Data I/O 6

Data I/O 5

• Manual switch unconditionally protects data

• Compact size and shape

Data I/O 4

Data I/O 3

• Rugged and durable

• Wide operating temperature range of 0°C to 70°C

3”

See Mech. Drawings Section

DESCRIPTION

The DS1217M is a nonvolatile RAM designed for porta-

ble applications requiring a rugged and durable pack-

age. The Nonvolatile Cartridge has memory capacities

from 64K x 8 to 512K x 8. The cartridge is accessed in

continuous 32K byte banks. Bank switching is accom-

plished under software control by pattern recognition

fromtheaddressbus. Acardedgeconnectorisrequired

for connection to a host system. A standard 30-pin con-

nector can be used for direct mount to a printed circuit

board. Alternatively, remote mounting can be accom-

plished with a ribbon cable terminated with a 28-pin DIP

plug. The remote method can be used to retrofit existing

systems which have JEDEC 28-pin bytewide memory

sites.

030598 1/8

DS1217M

source. Normal RAM operation can resume after V

exceeds 4.5 volts.

READ MODE

The DS1217M executes a read cycle whenever WE

(write enable) is inactive (high) and CE (cartridge en-

able) is active (low). The unique address specified by

the address inputs (A0-A14) defines which byte of data

is to be accessed. Validdatawillbeavailabletotheeight

TheDS1217Mchecksbatterystatustowarnofpotential

data loss. Each time that V power is restored to the

cartridge the battery voltage is checked with a precision

comparator. If the battery supply is less than 2.0 volts,

the second memory cycle is inhibited. Battery status

can, therefore, be determined by performing a read

cycle after power-up to any location in memory, record-

ing that memory location content. A subsequent write

cycle can then be executed to the same memory loca-

tion, altering data. If the next read cycle fails to verify the

written data, the contents of the memory are question-

able.

data I/O pins within t

(access time) after the last ad-

ACC

dress input signal is stable, providing that CE (cartridge

enable) and OE (output enable) access times are also

satisfied. If OE and CE times are not satisfied, then data

access mustbemeasuredfromthelateoccurringsignal

(CE or OE) and the limiting parameter is either t

for

CE or t

for OE rather than address access. Read

cycles can only occur when V

is greater than 4.5

volts. When V is less than 4.5 volts, the memory is in-

hibited and all accesses are ignored.

In many applications, data integrity is paramount. The

cartridge thus has redundant batteries and an internal

isolationswitchwhichprovidesfortheconnectionoftwo

batteries. During battery backup time, the battery with

the highest voltage is selected for use. If one battery

fails, the other will automatically take over. The switch

between batteries is transparent to the user. A battery

status warning will occur only if both batteries are less

than 2.0 volts.

WRITE MODE

The DS1217M is in the write mode whenever both the

WE and CE signals are in the active (low) state after ad-

dress inputs are stable. The last occurring falling edge

of either CE or WE will determine the start of the write

cycle. The write cycle is terminated by the first rising

edge of either CE or WE. All address inputs must be

kept valid throughout the write cycle. WE must return to

the high state for a minimum recovery time (t ) before

BANK SWITCHING

another cycle can be initiated.The OE control signal

should be kept inactive (high) during write cycles to

avoid bus contention. However, if the output bus has

been enabled (CE and OE active) then WE will disable

Bank switching is accomplished via address lines A8,

A9,A10, andA11.Initially, onpower-upallbanksarede-

selectedsothatmultiplecartridgescanresideonacom-

monbus. Bank switching requires that a predefined pat-

tern of 64 bits is matched by sequencing 4 address

inputs(A8 through A11) 16 times while ignoring all other

addressinputs. Priortoenteringthe64-bitpatternwhich

will set the band switch, a read cycle of 1111 (address

inputs A8 through A11) must be executed to guarantee

that pattern entry starts with the first set of 3 bits. Each

set of address inputs is entered into the DS1217M by

executing read cycles.The first eleven cycles must

match the exact bit pattern as shown in Table 2. The last

five cycles must match the exact bit pattern for address-

es A9, A10, and A11. However, address line 8 defines

which of the 16 banks is to be enabled, or all banks are

deselected, as per Table 3. Switching from one bank to

another occurs as the last of the 16 read cycles is com-

pleted. A single bank is selected at any one time. A se-

lected bank will remain active until a new bank is se-

lected, all banks are deselected, or until power is lost.

(See DS1222 BankSwitch Chip data sheet for more de-

tail.)

the outputs in t

from its falling edge. Write cycles

ODW

canonlyoccurwhenV isgreaterthan4.5volts. When

is less than 4.5 volts, the memory is write-pro-

tected.

DATA RETENTION MODE

The Nonvolatile Cartridge provides full functional capa-

bilityfor V greater than 4.5 volts and guarantees write

protection for V

less than 4.5 volts. Data is main-

tainedin the absence of V without any additional sup-

port circuitry. The DS1217M constantly monitors V

Should the supply voltage decay, the RAM is automati-

cally write-protected below 4.5 volts. As V falls below

approximately3.0volts, thepowerswitchingcircuitcon-

nects a lithium energy source to RAM to retain data.

During power-up, when V rises above approximately

3.0volts, the power switching circuit connects theexter-

nal V to the RAM and disconnects the lithium energy

030598 2/8

DS1217M

Number 499188-4. The 28-pin ribbon cable must be

right-justified, such that positions A1 and B1 are left dis-

connected. For applications where the cartridge is in-

stalledorremovedwithpowerapplied,bothgroundcon-

tacts (A1 and B1) on the card edge connector should be

grounded to further enhance data integrity. Access time

push-out may occur as the distance between the car-

tridge and the driving circuitry is increased.

REMOTE CONNECTION VIA A RIBBON

CABLE

Existing systems which contain 28-pin bytewide sock-

ets can be retrofitted using a 28-pin DIP plug. The DIP

plug, AMP Part Number 746616-2, can be inserted into

the28-pinsiteafterthememoryisremoved.Connection

to the cartridge is accomplished via a 28-pin cable con-

nected to a 30-contact card edge connector, AMP Part

CARTRIDGE NUMBERING Table 1

PART NO.

DENSITY

64K x 8

NO. OF BANKS

DS1217M 1/2-25

DS1217M 1-25

DS1217M 2-25

DS1217M 3-25

DS1217M 4-25

128K x 8

156K x 8

384K x 8

512K x 8

ADDRESS INPUT PATTERN Table 2

ADDRESS

BIT SEQUENCE

INPUTS

10 11 12 13 14 15

A10

A11

X = See Table 3

BANK SELECT TABLE Table 3

BANK

A8 BIT SEQUENCE

BANK

A8 BIT SEQUENCE

SELECTED

BANKS OFF

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

BANK 9

BANK 10

BANK 11

BANK 12

BANK 13

BANK 14

BANK 15

030598 3/8

DS1217M

ABSOLUTE MAXIMUM RATINGS*

Voltage on Connection Relative to Ground

Operation Temperature

-0.3V to + 7.0V

0°C to 70°C

Storage Temperature

-40°C to +70°C

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATION CONDITIONS

(0°C to 70°C)

PARAMETER

SYMBOL

MIN

4.5

2.2

0.0

TYP

MAX

UNITS

NOTES

Power Supply Voltage

Input High Voltage

Input Low Voltage

5.0

5.5

+0.8

DC ELECTRICAL CHARACTERISTICS

(0°C to 70°C; V_CC= 5V ± 10%)

PARAMETER

SYMBOL

MIN

-60

-10

TYP

MAX

UNITS

NOTES

Input Leakage Current

+60

µA

I/O Leakage Current

+10

µA

CE > V < V

Output Current @ 2.4V

Output Current @ 0.4V

Standby Current CE = 2.2V

Operating Current

-1.0

2.0

-2.0

3.0

CCS1

CCO1

100

CAPACITANCE

PARAMETER

(t_A=25°C)

SYMBOL

MIN

TYP

MAX

100

UNITS

NOTES

Input Capacitance

Input/Output Capacitance

100

OUT

030598 4/8

DS1217M

AC ELECTRICAL CHARACTERISTICS

(0°C to 70°C; V_CC= 5V+ 10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Read Cycle Time

250

Access Time

250

125

210

ACC

OE to Output Valid

CE to Output Valid

OE or CE to Output Active

Output High Z From Deselection

COE

125

Output Hold From

Address Change

Read Recovery Time

Write Cycle Time

250

170

Write Pulse Width

Address Setup Time

Write Recovery Time

Output High Z From WE

Output Active From WE

Data Setup Time

100

ODW

OEW

100

Data Hold Time From WE

030598 5/8

DS1217M

READ CYCLE (1)

ADDRESSES

ACC

COE

OUTPUT

DATA VALID

OUT

WRITE CYCLE 1 (2), (6), (7)

ADDRESSES

OEW

ODW

HIGH

IMPEDANCE

OUT

DATA IN

STABLE

WRITE CYCLE 2 (2), (8)

ADDRESSES

ODW

COE

OUT

DATA IN

STABLE

030598 6/8

DS1217M

POWER-DOWN/POWER-UP CONDITION

4.50V

3.2V

REC

DATA RETENTION TIME

LEAKAGE CURRENT I

SUPPLIED FROM LITHIUM CELL

POWER-DOWN/POWER-UP TIMING

(0° to 70°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

µs

NOTES

CE at VIH before Power-Down

slew from 4.5V to 0V

100

µs

(CE at V

)

slew from 0V to 4.5V

µs

(CE at V

)

CE at V after Power-Up

125

REC

(t_A=25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Expected Data Retention Time

years

WARNING:

Undernocircumstancesarenegativeundershoots, ofanyamplitude, allowedwhendeviceisinbatterybackupmode.

030598 7/8

DS1217M

NOTES:

1. WE is high for a read cycle.

2. OE = V or V . If OE = V during a write cycle, the output buffers remain in a high impedance state.

3. t

is specified as the logical AND of CE and WE. t

is measured from the latter of CE or WE going low to

the earlier of CE of WE going high.

4. t , t are measured from the earlier of CE or WE going high.

DH DS

5. These parameters are sampled with a 5 pF load and are not 100% tested.

6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the

output buffers remain in a high impedance state in this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition in Write Cycle 1, the

output buffers remain in a high impedance state in this period.

8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output

buffers remain in a high impedance state in this period.

9. Each DS1217M is marked with a 4-digit date code AABB. AA designates the year of manufacture. BB desig-

nates the week of manufacture. The expected t is defined as starting at the date of manufacture.

10.Removing and installing the cartridge with power applied may disturb data.

DC TEST CONDITIONS

Outputs Open

t Cycle = 250 ns

AC TEST CONDITIONS

Output Load: 100pF + 1TTL Gate

Input Pulse Levels: 0-3.0V

Timing Measurement Reference Levels

Input: 1.5V

All Voltages Are Referenced to Ground

Output: 1.5V

Input Pulse Rise and Fall Times: 5ns

030598 8/8

DS1217M1-25 [DALLAS]

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