DS1497_技术文档

DS1495/DS1497

RAMified Real Time Clock

FEATURES

PIN ASSIGNMENT

• Ideal for EISA bus PCs

A0

1

A2

A3

V

28

27

26

25

24

23

22

21

20

19

18

17

16

15

2

3

4

A1

X2

• Functionally compatible with MC146818 in 32 KHz

mode

DD

X1

SQW

A4

STBY

5

6

• Totally nonvolatile with over 10 years of operation in

the absence of power

D0

D1

D2

D3

D4

D5

D6

D7

A5

7

V

BAT

8

IRQ

• Self-contained subsystem includes lithium, quartz,

and support circuitry

9

RESET

RD

10

11

12

13

B

GND

• Counts seconds, minutes, hours, day of the week,

date, month, and year with leap year compensation

WR

XRAM

RTC

V

14

SS

• Binary or BCD representations of time, calendar, and

alarm

DS1495S 28-Pin SOIC (330 mil)

1

2

3

A0

A1

A2

A3

V

28

27

26

• 12- or 24-hour clock with AM and PM in 12-hour mode

• Daylight Savings Time option

X2

DD

4

5

6

7

X1

SQW

A4

25

24

• Interfacedwith software as 64 register/RAM locations

plus 8K x 8 of static RAM

STBY

D0

A5

23

22

21

20

19

18

17

16

15

–

14 bytes of clock and control registers

50 bytes of general and control registers

Separate 8K x 8 nonvolatile SRAM

V

D1

D2

D3

BAT

8

IRQ

9

RESET

RD

10

11

12

13

14

D4

• Programmable square wave output signal

• Bus-compatible interrupt signals (IRQ)

B

D5

D6

D7

GND

WR

XRAM

RTC

V

SS

• Three interrupts are separately software-maskable

and testable:

DS1495 28-Pin DIP (600 mil)

–

Time-of-day alarm once/second to once/day

Periodic rates from 122 µs to 500 ms

End-of-clock update cycle

1

A0

A1

28 A2

2

A3

V

27

26

3

NC

DD

4

SQW

A4

25

24

23

• 28-pin JEDEC footprint

5

STBY

D0

6

A5

• Available as chip (DS1495/DS1495S) or stand alone

module with embedded lithium battery and crystal

(DS1497)

D1

NC

7

22

21

20

19

D2

IRQ

RESET

RD

8

D3

D4

D5

D6

D7

9

10

11

12

13

14

ORDERING INFORMATION

NC

18

17

DS1495

DS1495S

DS1497

RTC Chip; 28–pin DIP

RTC Chip; 28–pin SOIC

RTC Module; 28–pin DIP

WR

XRAM

RTC

16

15

V

SS

DS1497 28-Pin Encapsulated Package (720 mil)

patents and other intellectual property rights, please refer to

Dallas Semiconductor databooks.

020894 1/19

DS1495/DS1497

cessible. Registers are selected by the A0 line. Data is

driven onto the data bus when RD is low. Data is re-

ceived from the bus when WR is pulsed low and then

high.

PIN DESCRIPTIONS

V , V – Busoperationalpowerissuppliedtothepart

DD SS

via these pins. The voltage level present on these pins

should be monitored to transition between operational

power and battery power.

SQW – Square Wave (output): Frequency selectable

output. Frequency is selected by setting register A bits

RSO-RS3. See Table 2 for frequencies that can be se-

lected.

D0-D7 – Data Bus (bidirectional): Data is written into

the device from the data bus if either XRAM or RTC is

asserted during a write cycle at the rising edge of a WR

pulse. Data is read from the device and driven onto the

data bus if either XRAM or RTC is asserted during a

read cycle when the RD signal is low.

XRAM–ExtendedRAMSelect(input): Whenthissig-

nal is asserted low, the extended RAM bytes are acces-

sible. The XRAM page register is selected when the A5

address line is high. A 32-byte page of RAM is accessi-

ble when A5 is low. A0-A4 select the bytes within the

page of RAM pointed to by the page register. Data is

driven onto the data bus when RD is low. Data is re-

ceived from the bus when WR is pulsed low and then

high.

A0-A5 – Address Bus (input): Various internal regis-

ters of the device are selected by these lines. When

RTC is asserted, A0 selects between the indirect ad-

dress register and RTC data register. When the XRAM

is asserted, A0-A5 addresses a 32–byte page of RAM.

When A5 is high, the RAM page register is accessible.

When A5 is low, A0-A4 address the 32-byte page of

RAM.

IRQ – Interrupt Request (output): The IRQ signal is

anactivelow,opendrainoutputthatisusedasaproces-

sor interrupt request. The IRQ output follows the state

of the IRQF bit (bit 7) in status register C. IRQ can be

asserted by the alarm, update ended, or periodic inter-

rupt functions depending on the configuration of

register B.

RD – Read Strobe (input): Data is read from the se-

lected register and driven onto the data bus by the de-

vice when this line is low and either RTC or XRAM is as-

serted.

WR – Write Strobe (input): Data is written into the de-

vice from the data bus on the rising edge after a low

pulse on this line when the device has been selected by

either the XRAM or RTC signals.

RESET – Reset (input): The reset signal is used to ini-

tialize certain registers to allow proper operation of the

RTC module. When RESET is low, the following oc-

curs.

STBY – Standby (input): Accesses to the device are

inhibited and outputs are tri-stated to a high impedance

statewhenthissignalisassertedlow. AlldatainRAMof

the device is preserved. The real time clock continues

to keep time.

1. The following register bits are cleared:

a. Periodic interrupt (PIE)

b. Alarm interrupt enable (AIE)

c. Update ended interrupt (UF)

d. Interrupt request flag (IRQF)

e. Periodic interrupt flag (PF)

f. Alarm interrupt flag (AF)

If a read or write cycle is in progress when the STBY sig-

nal is asserted low, the internal cycle will be terminated

wheneithertheexternalcyclecompletesorwhenthein-

g. Square wave output enable (SQWE)

h. Update ended interrupt enable (UIE)

ternalchipenablecondition(V is4.25volts, typical)is

DD

negated, whichever occurs first.

2. The IRQ pin is in the high impedance state.

3. The RTC is not processor accessible.

RTC – Real Time Clock Select (input): When this sig-

nal is asserted low, the real time clock registers are ac-

020894 2/19

DS1495/DS1497

WhenV fallsbelowtheCE

(4.25voltstypical), the

THR

ADDITIONAL PIN DESCRIPTION

(FOR DS1495, DS1495S)

DD

chip select inputs RTC and XRAM are forced to an inac-

tive state regardless of the state of the pin signals. This

puts the module into a write protected mode in which all

inputs are ignored and all outputs are in a high imped-

X1, X2 – Connectionsforastandard32.768KHzquartz

crystal, Daiwa part number DT-26S or equivalent. The

internal oscillator circuitry is designed for operation with

ance state. When V falls below 3.2 volts (typical), the

DD

a crystal having a specified load capacitance (C ) of

module is switched over to an internal power source in

the case of the DS1497, or to an external battery con-

L

6pF. The crystal is connected directly to the X1 and X2

pins. There is no need for external capacitors or resis-

tors. Note: X1 and X2 are very high impedance nodes.

It is recommended that they and the crystal be guard–

ringed with ground and that high frequency signals be

kept away from the crystal area. For more information

on crystal selection and crystal layout considerations,

please consult Application Note 58, “Crystal Consider-

ations with Dallas Real Time Clocks”.

nected to the V

and BGND pins in the case of the

BAT

DS1495 and DS1495S, so that power is not interrupted

to timekeeping and nonvolatile RAM functions.

AddressMap:Theregistersofthedeviceappearintwo

distinct address ranges. One set of registers is active

when RTC is asserted low and represents the real time

clock. ThesecondsetofregistersisactivewhenXRAM

is asserted low and represents the extended RAM.

V

BAT

– Battery input for any standard +3 volt lithium cell

or other energy source. Battery voltage must be held

between 2.5 and 3.7 volts for proper operation. The

nominal write protect trip point voltage at which access

to the real time clock and user RAM is denied is set by

RTC Address Map: The address map of the RTC mod-

ule is shown in Figure 2. The address map consists of

50 bytes of general purpose RAM, 10 bytes of RTC/cal-

endar information, and 4 bytes of status and control in-

formation. All 64 bytes can be accessed as read/write

registers except for the following:

the internal circuitry at 4.25 volts typical. A maximum

o

load of 1 µA at 25 C and 3.0V on V

in the absence of

BAT

power should be used to size the external energy

source.

1. Registers C and D are Read Only (status informa-

tion)

The battery should be connected directly to the V

BAT

2. Bit 7 of register A is Read Only

pin. Adiodemustnotbeplacedinserieswiththebattery

to the V pin. Furthermore, a diode is not necessary

3. Bit 7 of the “Seconds” byte (00) is Read Only

BAT

because reverse charging current protection circuitry is

provided internal to the device and has passed the

requirements of Underwriters Laboratories for UL list-

ing.

The first byte of the real time clock address map is the

RTC indirect address register, accessible when A0 is

low. The second byte is the RTC data register, accessi-

blewhen A0 is high. The function of the RTC indirect ad-

dress register is to point to one of the 64 RTC registers

that are indirectly accessible through the RTC data reg-

ister.

B

– Battery ground: This pin or pin 14 can be used

GND

for the battery ground return.

OPERATION

ExtendedRAM Address Map: The first 32 bytes of the

extended RAM represent one of 256 pages of general

purposenonvolatilememory. These 32 bytes on a page

are addressed by A0 through A4 when A5 is low. When

A5 is high, the XRAM page register is accessible. The

value in the XRAM page register points to one of 256

pages of nonvolatile memory available. The address of

the XRAM page register is dependent only on A5 being

high; thus, there are 31 aliases of this register in I/O

spaces. (See Figure 3.)

Power-Down/Power-Up: The real time clock will con-

tinue to operate and all of the RAM, time, and calendar

and alarm memory locations will remain non-volatile re-

gardless of the voltage level of V . When the voltage

level applied to the V input is greater than 4.25 volts

(typical), the module becomes accessible after 200 ms

provided that the oscillator and countdown chain have

been programmed to be running. This time period al-

lows the module to stabilize after power is applied.

DD

020894 3/19

DS1495/DS1497

checked for an alarm condition. If a read of the time and

calendardataoccursduringanupdate,aproblemexists

where seconds, minutes, hours, etc. may not correlate.

The probability of reading incorrect time and calendar

data is low. Several methods of avoiding any possible

incorrect time and calendar reads are covered later in

this text.

TIME, CALENDAR AND ALARM LOCATIONS

The time and calendar information is obtained by read-

ing the appropriate register bytes shown in Table 1. The

time, calendar, and alarm are set or initialized by writing

theappropriate register bytes. The contents of the time,

calendar, and alarm registers can be either Binary or

Binary-Coded Decimal (BCD) format. Table 1 shows

thebinaryandBCDformatsofthetwelvetime,calendar,

and alarm locations.

The three alarm bytes can be used in two ways. First,

when the alarm time is written in the appropriate hours,

minutes, and seconds alarm locations, the alarm inter-

ruptisinitiatedatthespecifiedtimeeachdayifthealarm

enable bit is high . The second method is to insert a

“don’tcare”stateinoneormoreofthethreealarmbytes.

The “don’t care” code is any hexadecimal value from C0

to FF. The two most significant bits of each byte set the

“don’t care” condition when at logic 1. An alarm will be

generatedeachhourwhenthe“don’tcare”bitsaresetin

the hours byte. Similarly, an alarm is generated every

minute with “don’t care” codes in the hours and minute

alarm bytes. The “don’t care” codes in all three alarm

bytes create an interrupt every second.

Beforewritingtheinternaltime,calendar,andalarmreg-

isters, the SET bit in Register B should be written to a

logic one to prevent updates from occurring while ac-

cess is being attempted. Also at this time, the data for-

mat (binary or BCD), should be set via the data mode bit

(DM) of Register B. All time, calendar, and alarm regis-

ters must use the same data mode. The set bit in Regis-

ter B should be cleared after the data mode bit has been

written to allow the real-time clock to update the time

and calendar bytes.

Onceinitialized, thereal-timeclockmakesallupdatesin

the selected mode. The data mode cannot be changed

without reinitializing the ten data bytes. The 24/12 bit

cannot be changed without reinitializing the hour loca-

tions. When the 12-hour format is selected, the high or-

der bit of the hours byte represents PM when it is a logic

one. Thetime,calendar, andalarmbytesarealwaysac-

cessible because they are double buffered. Once per

second the ten bytes are advanced by one second and

USER NONVOLATILE RAM - RTC

The 50 user nonvolatile RAM bytes are not dedicated to

any special function within the DS1495/DS1497. They

can be used by the application program as nonvolatile

memory and are fully available during the update cycle.

This memory is directly accessible in the RTC section.

020894 4/19

DS1495/DS1497

DS149X BLOCK DIAGRAM Figure 1

D E C O D E R

R E G I S T E R

I N D E X

020894 5/19

DS1495/DS1497

REAL TIME CLOCK RAM MAP Figure 2

RTC

INDIRECT ADDRESS REGISTER

RTC +1

RTC DATA REGISTER

14– BYTES

REAL TIME CLOCK

INDIRECT

ADDRESS

00

01

SECONDS

14–BYTES

RTC

SECONDS ALARM

0D

0E

13

14

02

03

MINUTES

MINUTES ALARM

50–BYTES

USER RAM

04

05

HOURS

HOURS ALARM

3F

63

06

DAY OF WEEK

07

08

DAY OF MONTH

MONTH

09

YEAR

0A

0B

REGISTER A

REGISTER B

0C

0D

REGISTER C

REGISTER D

EXTENDED RAM ADDRESS MAP Figure 3

XRAM

256 PAGES

PAGE FF

OF 32–BYTES

EXTENDED RAM

THRU

02

01

PAGE 00

XRAM + 1F

XRAM + 20

XRAM PAGE REGISTER

XRAM + 21

THRU

ALIASES OF

PAGE REGISTER

XRAM + 3F

020894 6/19

DS1495/DS1497

TIME, CALENDAR AND ALARM DATA MODES Table 1

RANGE

BINARY DATA MODE

ADDRESS

LOCATION

DECIMAL

RANGE

FUNCTION

BCD DATA MODE

00-59

0

1

2

3

4

Seconds

0-59

1-12

0-23

1-12

0-23

1-7

00-3B

Seconds Alarm

Minutes

00-3B

00-59

00-3B

00-59

Minutes Alarm

00-3B

00-59

Hours-12-hr Mode

Hours-24-hr Mode

Hours Alarm-12-hr

Hours Alarm-24-hr

01-0C AM, 81-8C PM

00-17

01-12AM,81-92PM

00-23

5

6

01-0C AM, 81-8C PM

00-17

01-12AM,81-92PM

00-23

Day of the Week

Sunday = 1

01-07

7

8

9

Date of the Month

Month

1-31

1-12

0-99

01-1F

01-0C

00-63

01-31

01-12

00-99

Year

Register B. The flag bit can be used in a polling mode

withoutenablingthecorrespondingenablebits. Whena

flagisset, anindicationisgiventosoftwarethataninter-

rupt event has occurred since the flag bit was last read.

However, care should be taken when using the flag bits

as they are cleared each time Register C is read.

Double latching is included with Register C so that bits

which are set remain stable throughout the read cycle.

All bits which are set (high) are cleared when read and

new interrupts which are pending during the read cycle

are held until after the cycle is completed. One, two, or

threebits can be set when reading Register C. Each uti-

lized flag bit should be examined when read to ensure

that no interrupts are lost.

INTERRUPTS

The RTC plus RAM includes three separate, fully auto-

matic sources of interrupt for a processor. The alarm in-

terrupt can be programmed to occur at rates from once

per second to once per day. The periodic interrupt can

be selected for rates from 500 ms to 122 µs. The up-

date-ended interrupt can be used to indicate to the pro-

gram that an update cycle is complete. Each of these

independent interrupt conditions is described in greater

detail in other sections of this text.

The application program can select which interrupts, if

any, are going to be used. Three bits in Register B en-

able the interrupts. Writing a logic 1 to an interrupt-en-

able bit permits that interrupt to be initiated when the

event occurs. A logic 0 in an interrupt-enable bit prohib-

its the IRQ pin from being asserted from that interrupt

condition. If an interrupt flag is already set when an in-

terrupt is enabled, IRQ is immediately set at an active

level, although the interrupt initiating the event may

haveoccurredmuchearlier. Asaresult, therearecases

where the program should clear such earlier initiated in-

terrupts before first enabling new interrupts.

The alternative flag bit usage method is with fully en-

abledinterrupts. Whenaninterruptflagbitissetandthe

corresponding interrupt enable bit is also set, the IRQ

pin is asserted low. IRQ is asserted as long as at least

oneofthethreeinterruptsourceshasitsflagandenable

bits both set. The IRQF bit in Register C is a one when-

ever the IRQ pin is being driven low. Determination that

the RTC initiated an interrupt is accomplished by read-

ing Register C. A logic one in bit 7 (IRQF bit) indicates

that one or more interrupts have been initiated by the

DS1495/DS1497. The act of reading Register C clears

all active flag bits and the IRQF bit.

When an interrupt event occurs, the relating flag bit is

set to logic 1 in Register C. These flag bits are set inde-

pendent of the state of the corresponding enable bit in

020894 7/19

DS1495/DS1497

Once the frequency is selected, the output of the SQW

pin can be turned on and off under program control with

the square wave enable bit (SQWE).

OSCILLATOR CONTROL BITS

When the DS1495/DS1497 is shipped from the factory,

the internal oscillator is turned off. This feature prevents

thelithium battery from being used until it is installed in a

system. A pattern of 010 in bits 4 through 6 of Register A

will turn the oscillator on and enable the countdown

chain. A pattern of 11X will turn the oscillator on, but

holds the countdown chain of the oscillator in reset. All

other combinations of bits 4 through 6 keep the oscilla-

tor off.

PERIODIC INTERRUPT SELECTION

The periodic interrupt will cause the IRQ pin to go to an

active state from once every 500 ms to once every

122 µs. This function is separate from the alarm inter-

rupt which can be output from once per second to once

per day. The periodic interrupt rate is selected using the

same Register A bits which select the square wave fre-

quency (see Table 1). Changing the Register A bits af-

fects both the square wave frequency and the periodic

interruptoutput. However, eachfunctionhasaseparate

enable bit in Register B. The SQWE bit controls the

square wave output. Similarly, the periodic interrupt is

enabled by the PIE bit in Register B. The periodic inter-

rupt can be used with software counters to measure in-

puts, create output intervals, or await the next needed

software function.

SQUARE WAVE OUTPUT SELECTION

Thirteen of the 15 divider taps are made available to a

1-of-15 selector, as shown in the block diagram of Fig-

ure 1. The first purpose of selecting a divider tap is to

generate a square wave output signal on the SQW pin.

The RS0-RS3 bits in Register A establish the square

wave output frequency. These frequencies are listed in

Table 2. The SQW frequency selection shares its

1-of-15 selector with the periodic interrupt generator.

PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 2

SELECT BITS REGISTER A

t

PERIODIC

SQW OUTPUT

FREQUENCY

PI

INTERRUPT RATE

RS3

0

RS2

0

RS1

0

RS0

0

None

0

1

3.90625 ms

7.8125 ms

122.070 µs

244.141 µs

488.281 µs

976.5625 µs

1.953125 ms

3.90625 ms

7.8125 ms

15.625 ms

31.25 ms

62.5 ms

256 Hz

128 Hz

8.192 KHz

4.096 KHz

2.048 KHz

1.024 KHz

512 Hz

256 Hz

128 Hz

64 Hz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32 Hz

1

0

16 Hz

1

0

1

125 ms

8 Hz

1

0

250 ms

4 Hz

1

500 ms

2 Hz

020894 8/19

DS1495/DS1497

ter C should be cleared before leaving the interrupt rou-

tine.

UPDATE CYCLE

The DS1495/DS1497 executes an update cycle once

per second regardless of the SET bit in Register B.

When the SET bit in Register B is set to one, the user

copy of the double buffered time, calendar, and alarm

bytes is frozen and will not update as the time incre-

ments. However, the time countdown chain continues

to update the internal copy of the buffer. This feature al-

lows time to maintain accuracy independent of reading

or writing the time, calendar, and alarm buffers and also

guarantees that time and calendar information is con-

sistent. The update cycle also compares each alarm

byte with the corresponding time byte and issues an

alarm if a match or if a “don’t care” code is present in all

three positions.

A second method uses the update-in-progress bit (UIP)

in Register A to determine if the update cycle is in prog-

ress. The UIP bit will pulse once per second. After the

UIP bit goes high, the update transfer occurs 244 µs lat-

er. If a low is read on the UIP bit, the user has at least

244 µs before the time/calendar data will be changed.

Therefore, the user should avoid interrupt service rou-

tines that would cause the time needed to read valid

time/calendar data to exceed 244 µs.

The third method uses a periodic interrupt to determine

if an update cycle is in progress. The UIP bit in Register

A is set high between the setting of the PF bit in Register

C (see Figure 3). Periodic interrupts that occur at a rate

There are three methods that can handle access of the

real-timeclockthatavoidanypossibilityofaccessingin-

consistent time and calendar data. The first method

uses the update-ended interrupt. If enabled, an inter-

rupt occurs after every update cycle that indicates that

over 999 ms are available to read valid time and date in-

formation. If this interrupt is used, the IRQF bit in Regis-

of greater than t

allow valid time and date informa-

BUC

tion to be reached at each occurrence of the periodic in-

terrupt. The reads should be complete within

(t /2+t

)toensurethatdataisnotreadduringtheup-

PI

BUC

date cycle.

UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 4

UIP BIT IN

REGISTER A

t

BUC

UF BIT IN

REGISTER C

t

PI/2

PF BIT IN

REGISTER C

t

PI

t

= Periodic interrupt time interval per Table 1.

PI

= Delay time before update cycle = 244 µs.

BUC

020894 9/19

DS1495/DS1497

transfer is inhibited and the program can initialize the

time and calendar bytes without an update occurring in

the midst of initializing. Read cycles can be executed in

asimilarmanner. SET is a read/write bit that is not modi-

fied by internal functions of the DS1495/DS1497.

REGISTERS

The DS1495/DS1497 has four control registers which

are accessible at all times, even during the update

cycle.

REGISTER A

PIE - The Periodic Interrupt Enable bit is a read/write bit

which allows the Periodic Interrupt Flag (PF) bit in Reg-

isterCtodrivetheIRQpin low. WhenthePIEbitissetto

one, periodic interrupts are generated by driving the

IRQ pin low at a rate specified by the RS3-RS0 bits of

Register A. A zero in the PIE bit blocks the IRQ output

from being driven by a periodic interrupt, but the Period-

ic Flag (PF) bit is still set at the periodic rate. PIE is not

modified by any internal DS1495/DS1497 functions but

is cleared by the hardware RESET signal.

MSB

LSB

BIT 0

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

UIP

DV2

DV1

DV0

RS3

RS2

RS1

RS0

UIP - The Update In Progress (UIP) bit is a status flag

that can be monitored. When the UIP bit is a one, the

update transfer will soon occur. When UIP is a zero, the

update transfer will not occur for at least 244 µs. The

time, calendar, and alarm information in RAM is fully

available for access when the UIP bit is zero. The UIP

bitisreadonly. WritingtheSETbitinRegisterBtoaone

inhibits any update transfer and clears the UIP status

bit.

AIE - The Alarm Interrupt Enable (AIE) bit is a read/write

bitwhich, whensettoaone, permitstheAlarmFlag(AF)

bit in register C to assert IRQ. An alarm interrupt occurs

foreachsecondthatthethreetimebytesequalthethree

alarm bytes including a don’t care alarm code of binary

11XXXXXX. When the AIE bit is set to zero, the AF bit

doesnotinitiatetheIRQsignal. Theinternalfunctionsof

the DS1495/DS1497 do not affect the AIE bit but is

cleared by RESET.

DV2, DV1, DV0 - These three bits are used to turn the

oscillator on or off and to reset the countdown chain. A

patternof010istheonlycombinationofbitsthatwillturn

the oscillator on and allow the RTC to keep time. A pat-

tern of 11X will enable the oscillator but holds the count-

down chain in reset. The next update will occur at 500

ms after a pattern of 010 is written to DV2, DV1, and

DV0.

UIE - The Update Ended Interrupt Enable (UIE) bit is a

read/write bit that enables the Update Ended Flag (UF)

bitinRegisterCtoassertIRQ. TheSETbitgoinghighor

the RESET pin going low clears the UIE bit.

RS3, RS2, RS1, RS0-Thesefourrate-selectionbitsse-

lect one of the 13 taps on the 15-stage divider or disable

thedivider output. The tap selected can be used to gen-

erateanoutputsquarewave(SQWpin)and/oraperiod-

ic interrupt. The user can do one of the following

SQWE - When the Square Wave Enable (SQWE) bit is

set to a one, a square wave signal at the frequency set

by the rate-selection bits RS3 through RS0 is driven out

on a SQW pin. When the SQWE bit is set to zero, the

SQW pin is held low. SQWE is a read/write bit and is

cleared by RESET.

1. Enable the interrupt with the PIE bit;

2. Enable the SQW output pin with the SQWE bit;

3. Enable both at the same time and the same rate; or

4. Enable neither.

DM - The Data Mode (DM) bit indicates whether time

and calendar information is in binary or BCD format.

The DM bit is set by the program to the appropriate for-

matandcanbereadasrequired. Thisbitisnotmodified

by internal functions. A one in DM signifies binary data

while a zero in DM specifies Binary Coded Decimal

(BCD) data.

Table 2 lists the periodic interrupt rates and the square

wave frequencies that can be chosen with the RS bits.

REGISTER B

MSB

LSB

BIT 7 BIT 6 BIT 5

BIT 4

BIT 3

BIT 2

BIT 1 BIT 0

24/12 - The 24/12 control bit establishes the format of

the hours byte. A one indicates the 24-hour mode and a

zero indicates the 12-hour mode. This bit is read/write.

SET

PIE

AIE

UIE

SQWE

DM

24/12

DSE

SET - When the SET bit is a zero, the update transfer

functions normally by advancing the counts once per

second.WhentheSETbitiswrittentoaone, anyupdate

020894 10/19

DS1495/DS1497

DSE - The Daylight Savings Enable (DSE) bit is a read/

write bit which enables two special updates when DSE

is set to one. On the first Sunday in April the time incre-

ments from 1:59:59 AM to 3:00:00 AM. On the last

Sunday in October when the time first reaches 1:59:59

AMitchangesto1:00:00AM. Thesespecialupdatesdo

not occur when the DSE bit is a zero. This bit is not af-

fected by internal functions.

AF – A one in the Alarm Interrupt Flag (AF) bit indicates

that the current time has matched the alarm time. If the

AIEbitisalsoaone, theIRQpinwillgolowandaonewill

appearintheIRQFbit. AreadofRegisterCoraRESET

will clear AF.

UF – The Update Ended Interrupt Flag (UF) bit is set af-

tereachupdatecycle. WhentheUIEbitissettoone,the

one in UF causes the IRQF bit to be a one which will as-

sert the IRQ pin. UF is cleared by reading Register C or

by RESET.

REGISTER C

MSB

LSB

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 0 THROUGH BIT 3 – These are reserved bits of the

statusRegisterC. Thesebitsalwaysreadzeroandcan-

not be written.

IRQF

PF

AF

UF

0

IRQF – The Interrupt Request Flag (IRQF) bit is set to a

one when one or more of the following are true:

REGISTER D

PF = PIE = 1

AF = AIE = 1

UF = UIE = 1

MSB

LSB

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

i.e., IRQF = (PF • PIE) + (AF • AIE) + (UF • UIE)

VRT

0

VRT – The Valid RAM and Time (VRT) bit is set to the

one state by Dallas Semiconductor Corporation prior to

shipment. Thisbitisnotwritableandshouldalwaysbea

one when read. If a zero is ever present, an exhausted

internal lithium energy source is indicated and both the

contents of the RTC data and RAM data are question-

able.

Any time the IRQF bit is a one, the IRQ pin is driven low.

All flag bits are cleared after Register C is read by the

program or when the RESET pin is low.

PF – The Periodic Interrupt Flag (PF) is a read-only bit

which is set to a one when an edge is detected on the

selected tap of the divider chain. The RS3 through RS0

bits establish the periodic rate. PF is set to a one inde-

pendent of the state of the PIE bit. When both PF and

PIE are ones, the IRQ signal is active and will set the

IRQF bit. The PF bit is cleared by a software read of

Register C or by RESET.

BIT 6 THROUGH BIT 0 –TheremainingbitsofRegister

D are reserved and not usable. They cannot be written

and, when read, they will always read zero.

020894 11/19

DS1495/DS1497

ABSOLUTE MAXIMUM RATINGS*

DD

Input Voltage

V

Pin Potential to Ground Pin

-0.3V to +7.0V

– 0.3 to V + 0.3V

V

SS

DD

Power Dissipation

Storage Temperature

500 mW

DS1497: –40°C to +70°C

DS1495: –55°C to +125°C

0°C to 70°C

Ambient Temperature

Soldering Temperature

260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(0°C to 70°C)

CHARACTERISTIC

Supply Voltage

TEST CONDITION

SYM

MIN

4.5

MAX UNITS NOTES

V

CC

5.5

V

Input High Voltage

Recognized as a High Signal Over

V

IH

2.2

V

0.3

+

V

DD

Recommended V and t Range

DD

A

Input Low Voltage

Battery Voltage

Recognized as a Low Signal Over

Recommended V and t Range

V

-0.3

2.5

0.8

V

IL

DD

A

V

BAT

3.7

V

DC ELECTRICAL CHARACTERISTICS

(V_DD= 5.0V + 10%, V_SS= 0V, t_A= 0° C to 70°C)

CHARACTERISTIC

TEST CONDITION

SYM

MIN

MAX

UNIT NOTES

Input Leakage

For any Single Pin: D0-7, RD, WR,

A0-5, XRAM, RTC, RESET

I

+1

µA

V =0V, V =V

IL

IH

DD

Output High Voltage

Output Low Voltage

V

=5.0V I

=1 mA

V

OH

2.4

V

DD

LOAD

V

= 5.0V I

= 2 mA

V

0.4

50

LOAD

OL

DD

Power Supply Current Outputs Unloaded

I

mA

µA

STBY pin Input Current STBY=V

I

+500

–1

DD

SS

STBY

AC SWITCHING CHARACTERISTICS

(0°C to 70°C; V_DD= 4.5V to 5.5V)

CHARACTERISTIC

Reset Pulse Width

Oscillator Startup

TEST CONDITION

SYM

MIN

MAX

UNIT NOTES

t

5

µs

s

RWL

From Software Enable Via DV Bits

t

1

2

RC

IRQ Release from RD

High

t

µs

IRDS

IRQ Release from

RESET Low

t

2

µs

IRR

020894 12/19

DS1495/DS1497

IRQ RELEASE DELAY

RD

V

HIGH

t

RWL

RESET

V

IRQ

HIGH

t

IRR

t

IRDS

OSCILLATOR START-UP

t

RC

SQW Pin

WR

V

HIGH

DV0–2

NOTE:

Timing assumes RS3-0 Bits = 0011, minimum t .

PI

020894 13/19

DS1495/DS1497

BUS TIMING

PARAMETER

(0°C to 70°C; V_DD= 4.5V to 5.5V)

SYM

MIN

395

200

TYP

MAX

UNIT

NOTES

Cycle Time

t

DC

ns

CYC

Pulse Width, RD/WR Low

PW

ns

RWL

F

Signal Rise and Fall Time, RTC,

XRAM, RD, WR

t , t

R

30

ns

Address Hold Time

t

20

50

0

ns

AH

Address Setup Time Before RD

Address Setup Time Before WR

t

ARS

t

AWS

RTC/XRAM Select Setup Time Be-

fore RD

t

50

CRS

RTC/XRAM Select Setup Time Be-

fore WR

t

0

ns

CWS

RTC/XRAM Select Hold Time After

RD or WR

t

20

CH

Read Data Hold Time

t

10

0

100

200

ns

DHR

Write Data Hold Time

t

DHW

Output Data Delay Time from RD

Write Data Setup Time

t

20

200

DDR

DSW

t

OUTPUT LOAD

+5 V

1.1KΩ

D.U.T.

50 pF

680Ω

020894 14/19

DS1495/DS1497

BUS READ/WRITE TIMING

t

CYC

VALID

A0-A5

t

F

R

RTC

XRAM

t

CWS

CH

t

F

R

WR

PW

RWL

t

AWS

t

AH

t

DSW

t

DATA BUS

WRITE

DATA

DHW

VALID

D0–D7

DATA BUS

READ

VALID

DATA

D0–D7

t

CRS

t

DDR

CH

t

RD

PW

RWL

t

ARS

DHR

t

AH

POWER-DOWN/ POWER-UP TIMING

(t_A= 25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

ns

NOTES

CE High to Power Fail

Recovery at Power Up

t

PF

0

t

150

ms

REC

V

CC

V

CC

V

CC

Slew Rate Power Down

Slew Rate Power Up

t

300

10

0

µs

F

4.0 <V < 4.5V

CC

t

FB

µs

3.0 <V < 4.0V

CC

t

R

4.5V>V >4.0V

CC

Expected Data Retention

t

10

years

DR

NOTE:

CE is chip enabled for access, an internal signal which is defined by (RD + WR) (XRAM + RTC).

CAPACITANCE

(t_A= 25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

12

UNITS

pF

NOTES

Input Capacitance

Output Capacitance

C

IN

C

12

pF

OUT

020894 15/19

DS1495/DS1497

GENERAL INFORMATION

PARAMETER

SYM

MIN

TYP

MAX

UNIT

NOTES

t

10

Years

Expected Data Retention @ 25°C

(DS1497 only)

DR

C

±1

Min/Mo

Clock Accuracy for t @ 25°C

Q

DR

(DS1497 only)

2

Clock Accuracy Temperature Coefficient

(DS1497)

K

.050

30

ppm/°C

0°C

Clock Temperature Coefficient

t

O

20

Turnover Temperature (DS1497 only)

Chip Enable Threshold (DS1497 only)

POWER–UP CONDITION

CE

4.5

V

THR

V

IH

t

REC

4.5V

4.25V

4.0V

V

CC

t

R

POWER FAIL

NOTE:

CE is an internal signal generated by the power switching reference in the DS149X products.

POWER–DOWN CONDITION

CE

V

IH

t

PF

t

F

V

CC

4.5V

4.25V

4.0V

V

t

DR

BAT

t

FB

POWER FAIL

020894 16/19

DS1495/DS1497

DS1495 28–PIN DIP

PKG

28–PIN

MIN

DIM

MAX

A IN.

MM

1.445

36.70

1.470

37.34

B

D

B IN.

MM

0.530

13.46

0.550

13.97

C IN.

MM

0.140

3.56

0.160

4.06

1

D IN.

MM

0.600

15.24

0.625

15.88

A

E IN.

MM

0.015

0.38

0.040

1.02

F IN.

MM

0.120

3.05

0.145

3.68

G IN.

MM

0.090

2.29

0.110

2.79

H IN.

MM

0.625

15.88

0.675

17.15

C

F

J IN.

MM

0.008

0.20

0.012

0.30

E

K

G

K IN.

MM

0.015

0.38

0.022

0.56

J

H

020894 17/19

DS1495/DS1497

DS1495S 28–PIN SOIC

K

G

PKG

28-PIN

MIN

DIM

MAX

A IN.

MM

0.706

17.93

0.728

18.49

B IN.

MM

0.338

8.58

0.350

8.89

C IN.

MM

0.086

2.18

0.110

2.79

D IN.

MM

0.020

0.58

0.050

1.27

E IN.

MM

0.002

0.05

0.014

0.36

F IN.

MM

0.090

2.29

0.124

3.15

0.050

1.27

BSC

G IN.

MM

C

H IN.

MM

0.460

11.68

0.480

12.19

A

J IN.

MM

0.006

0.15

0.013

0.33

E

K IN.

MM

0.014

0.36

0.020

0.51

B

H

F

0–8 deg. typ.

J

D

020894 18/19

DS1495/DS1497

DS1497 28–PIN 720 MIL FLUSH ENCAPSULATED

15

28

PKG

28-PIN

MIN

DIM

MAX

A

IN.

MM

1.520

38.61

1.540

39.12

B

C

D

E

F

IN.

MM

0.695

17.65

0.720

18.29

1

14

IN.

MM

0.350

8.89

0.375

9.52

A

IN.

MM

0.100

2.54

0.130

3.30

IN.

MM

0.015

0.38

0.030

0.76

IN.

MM

0.110

2.79

0.140

3.56

C

E

G

H

J

IN.

MM

0.090

2.29

0.110

2.79

IN.

MM

0.590

14.99

0.630

16.00

F

D

K

G

IN.

MM

0.008

0.20

0.012

0.30

13 EQUAL SPACES AT

.100 ± .010 TNA

K

IN.

MM

0.015

0.38

0.021

0.53

NOTE:

PINS 3, 4, 18 AND 22 ARE MISSING BY DESIGN.

J

H

B

020894 19/19


型号：	DS1497
厂家：	DALLAS SEMICONDUCTOR
描述：	RAMified Real Time Clock 分枝实时时钟时钟
文件：	总19页 (文件大小：197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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