DS1650ABL-70-IND [DALLAS]
Non-Volatile SRAM Module, 512KX8, 70ns, CMOS,;
| 型号： | DS1650ABL-70-IND |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Non-Volatile SRAM Module, 512KX8, 70ns, CMOS, 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1650Y/AB
DS1650Y/AB
Partitionable 4096K NV SRAM
FEATURES
PIN ASSIGNMENT
• 10 years minimum data retention in the absence of
A18
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
external power
2
A15
A17
WE
A13
A8
• Data is automatically protected during power loss
• Directly replaces 512K x 8 volatile static RAM
3
4
5
• Write protects selected blocks of memory when pro-
grammed
A6
6
A5
7
A9
• Unlimited write cycles
A4
8
A11
OE
A3
9
• Low-power CMOS
A2
10
11
12
13
14
15
16
A10
CE
• Read and write access times as fast as 70 ns
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
• Lithium energy source is electrically disconnected to
retainfreshness until power is applied for the firsttime
DQ0
DQ1
DQ2
GND
• Full +10% V operating range (DS1650Y)
CC
• Optional +5% V operating range (DS1650AB)
CC
32-PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
o
• Optional industrial temperature range of -40 C to
o
+85 C, designated IND
• JEDEC standard 32-pin DIP package
• Low Profile Module (LPM) package
NC
A15
A16
PFO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
–
Fits into standard 68–pin PLCC surface mount-
able socket
V
CC
WE
OE
CE
–
–
255 mils package height
Power Fail Output (PFO) warns system of
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
impending V power failure
CC
A4
A3
A2
A1
A0
34–PIN LOW PROFILE MODULE (LPM)
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
100495 1/12
DS1650Y/AB
output drivers within t
(Access Time) after the last
PIN DESCRIPTION
ACC
A0 - A18
DQ0 - DQ7
CE
WE
OE
–
–
–
–
–
–
–
–
–
Address Inputs
Data In/Data Out
Chip Enable
address input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access
times are not satisfied, then data access must be mea-
sured from the later occurring signal (CE or OE) and the
limiting parameter is either t for CE or t for OE rather
CO OE
than address access.
Write Enable
Output Enable
Power Fail Output (LPM only)
Power (+5V)
Ground
No Connect
PFO
V
CC
GND
NC
WRITE MODE
The DS1650 devices execute a write cycle whenever
the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling
edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising
edgeof CE or WE. All address inputs must be kept valid
throughout the write cycle. WE must return to the high
DESCRIPTION
The DS1650 4096K Nonvolatile SRAMs are
4,194,304-bit, fully static, nonvolatile SRAM organized
as 524,288 words by 8 bits. Each NV SRAM has a self-
contained lithium energy source and control circuitry
state for a minimum recovery time (t ) before another
WR
which constantly monitors V for an out-of-tolerance
cycle can be initiated. The OE control signal should be
kept inactive (high) during write cycles to avoid bus con-
tention. However, if the output drivers are enabled (CE
CC
condition. When such a condition occurs, the lithium
energy source is automatically switched on and write
protection is unconditionally enabled to prevent data
corruption. In addition, the device has the ability to
unconditionally write protect blocks of memory so that
inadvertent write cycles do not corrupt programs and
important data. There is no limit on the number of write
cycles that can be executed and no additional support
circuitry is required for microprocessor interfacing.
DIP–package DS1650 devices can be used in place of
existing512Kx8SRAMsdirectlyconformingtothepop-
ular bytewide 32–pin DIP standard. DS1650 devices in
the Low Profile Module package are specifically
designed for surface mount applications. DS1650 LPM
devices also have an additional pin, a Power Fail Out-
puts that can be used to warn a system of impending
and OE active) then WE will disable the outputs in t
from its falling edge.
ODW
DATA RETENTION MODE
The DS1650AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1650Y provides full functional capability
for V greater than 4.5 volts and write protects by 4.25
CC
volts. Data is maintained in the absence of V without
CC
any additional support circuitry. The nonvoltile static
RAMs constantly monitor V . Should the supply volt-
CC
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
falls below
CC
V
CC
power failure.
approximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power-up, when V rises above approximately
READ MODE
CC
The DS1650 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The
3.0 volts, the power switching circuit connects external
V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V exceeds
CC
unique address specified by the 19 address inputs (A -
4.75 volts for the DS1650AB and 4.5 volts for the
DS1650Y.
0
A
18
) defines which of the 524,288 bytes of data is to be
accessed. Valid data will be available to the eight data
100495 2/12
DS1650Y/AB
read cycles will load the partition register. Since there
are 16 protectable partitions, the size of each partition is
512K/16 or 32K x 8. Each partition is represented by
one of the 16 bits contained in the 21st through 24th
read cycles as defined by A15 through A18 and shown
in Table 2. A logical 1 in a bit location write protects the
corresponding partition. A logical 0 in a bit location dis-
ableswriteprotection. Forexample, ifduringthepattern
match sequence bit 22 on address pin A16 was a 1, this
would cause the partition register location for partition 5
to be set to a 1. This in turn would cause the DS1650
devices to internally inhibit WE for all write accesses
where A18 A17 A16 A15=0101. Note that while pro-
gramming the partition register, data which is being
accessed from the RAM should be ignored, since the
purpose of the 24 read cycles is to program the partition
register, not to access data from RAM.
FRESHNESS SEAL
Each DS1650 is shipped from Dallas Semiconductor
with its lithium energy source disconnected, guarantee-
ing full energy capacity. When V is first applied at a
CC
level greater than V , the lithium energy source is
TP
enabled for battery backup operation.
PARTITION PROGRAMMING MODE
The register controlling the partitioning logic is selected
by recognition of a specific binary pattern which is sent
on address lines A15 - A18. These address lines are
the four upper order address lines being sent to RAM.
The pattern is sent by 20 consecutive read cycles with
the exact pattern as shown in Table 1. Pattern matching
must be accomplished using read cycles; any write
cycles will reset the pattern matching circuitry. If this
pattern is matched perfectly, then the 21st through 24th
100495 3/12
DS1650Y/AB
PATTERN MATCH TO WRITE PARTITION REGISTER Table 1
1
1
1
1
1
2
0
1
1
1
3
1
1
1
0
4
1
1
1
0
5
1
1
0
0
6
1
0
0
1
7
0
0
1
1
8
0
1
1
1
9
1
1
1
0
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A15
A16
A17
A18
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FIRST BITS ENTERED
LAST BITS ENTERED
PARTITION REGISTER MAPPING Table 2
Bit number in pat-
Address
Pin
tern match
sequence
Address State Affected
Partition Number
PARTITION 0
PARTITION 1
PARTITION 2
PARTITION 3
PARTITION 4
PARTITION 5
PARTITION 6
PARTITION 7
PARTITION 8
PARTITION 9
PARTITION 10
PARTITION 11
PARTITION 12
PARTITION 13
PARTITION 14
PARTITION 15
(A
A
A
A )
18 17 16 15
A15
A16
A17
A18
A15
A16
A17
A18
A15
A16
A17
A18
A15
A16
A17
A18
BIT 21
BIT 21
BIT 21
BIT 21
BIT 22
BIT 22
BIT 22
BIT 22
BIT 23
BIT 23
BIT 23
BIT 23
BIT 24
BIT 24
BIT 24
BIT 24
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
100495 4/12
DS1650Y/AB
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–0.5V to +7.0V
0°C to 70°C, –40°C to +85°C for IND parts
Storage Temperature
Soldering Temperature
–40°C to +70°C, –40°C to +85°C for IND parts
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(tA: See Note 10)
PARAMETER
SYMBOL
MIN
4.5
TYP
5.0
MAX
5.5
UNITS
NOTES
DS1650Y Power Supply Voltage
DS1650AB Power Supply Voltage
Logic 1
V
CC
V
CC
V
V
V
V
4.75
2.2
5.0
5.25
V
IH
V
CC
Logic 0
V
IL
0.0
+0.8
(VCC=5V ± 10% for DS1650Y)
(tA: See Note 10) ( VCC=5V ± 5% for DS1650AB)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MIN
-1.0
-1.0
TYP
MAX
+1.0
+1.0
UNITS
NOTES
mA
Input Leakage Current
I/O Leakage Current
I
IL
mA
I
IO
CE > V < V
IH
CC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE = 2.2V
I
-1.0
2.0
mA
mA
mA
mA
mA
V
OH
I
14
OL
I
I
5.0
3.0
10.0
5.0
85
CCS1
CCS2
CCO1
Standby Current CE = V - 0.5V
CC
Operating Current
I
Write Protection Voltage
(DS1650Y)
V
4.25
4.50
4.37
4.62
4.5
TP
TP
Write Protection Voltage
(DS1650AB)
V
4.75
V
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
MIN
TYP
5
MAX
10
UNITS
pF
NOTES
Input Capacitance
C
IN
Input/Output Capacitance
C
5
10
pF
I/O
100495 5/12
DS1650Y/AB
(VCC=5V ± 5% for DS1650AB)
(tA: See Note 10) (VCC=5V ± 10% for DS1650Y)
AC ELECTRICAL CHARACTERISTICS
DS1650Y-70
DS1650AB–70
DS1650Y–85
DS1650Y-100
DS1650AB–85 DS1650AB–100
MIN
MAX
MIN
MAX
MIN
MAX
PARAMETER
SYMBOL
UNITS NOTES
Read Cycle Time
Access Time
t
70
85
100
ns
ns
ns
ns
RC
t
70
35
70
85
45
85
100
50
ACC
OE to Output Valid
CE to Output Valid
t
OE
t
100
CO
OE or CE to Output
Valid
t
5
5
5
5
5
5
ns
ns
ns
5
5
COE
Output High Z from
Deselection
t
t
25
30
35
OD
OH
Output Hold from
Address Change
Write Cycle Time
t
70
55
0
85
65
0
100
75
0
ns
ns
ns
WC
Write Pulse Width
Address Setup Time
Write Recovery Time
t
3
WP
t
AW
t
10
10
10
10
10
10
ns
ns
12
13
WR1
WR2
t
Output High Z from
WE
t
25
30
35
ns
ns
ns
5
5
4
ODW
Output Active from
WE
t
5
5
5
OEW
Data Setup Time
Data Hold Time
t
30
35
40
DS
t
t
5
5
5
5
5
5
ns
ns
12
13
DH1
DH2
100495 6/12
DS1650Y/AB
AC ELECTRICAL CHARACTERISTICS
(tA: See Note 10) (VCCI=4.50V to 5.50V)*
PARAMETER
Address Setup
Address Hold
Read Recovery
CE Pulse Width
SYMBOL
MIN
0
TYP
MAX
UNITS
ns
NOTES
t
AS
AH
RR
t
50
10
75
ns
t
ns
t
ns
CW
*For loading partition register
TIMING DIAGRAM: LOADING PARTITION REGISTER
V
V
IH
IH
A15–A18
BIT 1
BIT 2
BIT 24
t
AS
t
t
RR
AH
t
CW
CE
V
IH
V
V
IL
IL
OE
V
IH
WE
READ CYCLE
t
RC
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
ADDRESSES
t
OH
t
V
ACC
IH
V
IH
CE
OE
t
CO
V
IL
t
OD
V
IH
t
OE
V
IH
V
IL
t
OD
t
COE
t
COE
V
V
OUTPUT
DATA VALID
OH
OH
OL
D
OUT
V
V
OL
SEE NOTE 1
100495 7/12
DS1650Y/AB
WRITE CYCLE 1
ADDRESSES
t
WC
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
t
AW
CE
V
V
IL
IL
t
t
WR1
WP
WE
V
V
IH
IH
V
V
IL
IL
t
OEW
t
ODW
HIGH
IMPEDANCE
D
OUT
t
t
DH1
DS
V
V
V
IH
IL
IH
IL
D
DATA IN STABLE
IN
V
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
t
WC
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
ADDRESSES
CE
t
t
t
WR2
AW
WP
V
V
V
IH
IH
IH
V
V
IL
IL
V
IL
WE
V
V
IL
IL
t
COE
t
ODW
D
OUT
t
t
DH2
DS
V
V
IH
IH
DATA IN STABLE
D
IN
V
V
IL
IL
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
100495 8/12
DS1650Y/AB
POWER-DOWN/POWER-UP CONDITION
V
CC
V
TP
3.2V
t
F
t
R
t
t
REC
PD
CE, WE
LEAKAGE CURRENT
SUPPLIED FROM
LITHIUM CELL
DATA RETENTION
TIME
I
L
SEE NOTE 11
t
DR
POWER-DOWN/POWER-UP TIMING
(tA: See Note 10)
PARAMETER
CE, WE at V before Power-Down
SYMBOL
MIN
0
TYP
MAX
UNITS
ms
NOTES
t
11
IH
PD
ms
V
CC
slew from V to 0V
t
F
300
TP
(CE at V
)
IH
ms
V
CC
slew from 0V to V
t
R
0
TP
(CE at V
)
IH
CE, WE at V after Power-Up
t
25
125
ms
IH
REC
(tA = 25°C)
NOTES
9
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Expected Data Retention Time
t
10
years
DR
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = V or V . If OE = V during write cycle, the output buffers remain in a high impedance state.
IH
IL
IH
3. t
is specified as the logical AND of CE and WE. t
is measured from the latter of CE or WE going low to
WP
WP
the earlier of CE or WE going high.
4. t is measured from the earlier of CE or WE going high.
DS
100495 9/12
DS1650Y/AB
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers
remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers
remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output
buffers remain in a high impedance state during this period.
9. Each DS1650 has a built-in switch that disconnects the lithium source until V is first applied by the user.
CC
The expected t is defined as accumulative time in the absence of V starting from the time power is first
DR
CC
applied by the user.
10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial
products, this range is 0°C to 70°C. For industrial products (IND), this range is –40°C to +85°C.
11. In a power down condition the voltage on any pin may not exceed the voltage on V
.
CC
12.t
13.t
, t
are measured from WE going high.
are measured from CE going high.
WR1 DH1
, t
WR2 DH2
14.The power fail output signal (PFO) is driven active (V =0.4V) when the V trip point occurs. While active,
OL
CC
the PFO pin can sink 4 mA and will maintain a maximum output voltage of 0.4 volts. When inactive, the volt-
age output of PFO is 2.4 volts minimum and will source a current of 1 mA. This signal is only present on the
LPM package variations.
15.DS1650 modules are recognized by Underwriters Laboratory (U.L. ) under file E99151(R).
DC TEST CONDITIONS
AC TEST CONDITIONS
Outputs Open
t Cycle = 200 ns
All voltages are referenced to ground
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
DS1650 TTP–
SSS –
III
Operating Temperature Range
blank: 0° to 70°
IND: –40° to +85°C
Speed
70 ns
85 ns
100 ns
Access
70:
85:
100:
Package Type
Blank: 32–pin 600 mil DIP
L:
34–pin Low Profile Module
V
CC
Tolerance
AB: +5%
Y: +10%
100495 10/12
DS1650Y/AB
DS1650Y/AB NONVOLATILE SRAM, 32–PIN 740 MIL EXTENDED MODULE
PKG
32-PIN
MIN
1.680
DIM
MAX
A
IN.
1.700
43.18
MM
IN.
42.67
B
C
D
E
F
0.720
18.29
0.740
18.80
MM
1
IN.
0.355
9.02
0.375
9.52
A
MM
IN.
0.080
2.03
0.110
2.79
MM
IN.
MM
0.015
0.38
0.025
0.63
IN.
MM
0.120
3.05
0.160
4.06
C
G
H
J
IN.
MM
0.090
2.29
0.110
2.79
F
IN.
MM
0.590
14.99
0.630
16.00
D
K
G
IN.
MM
0.008
0.20
0.012
0.30
K
IN.
MM
0.015
0.38
0.021
0.53
J
E
H
B
100495 11/12
DS1650Y/AB
DS1650Y/AB 34–PIN LOW PROFILE MODULE (LPM)
PKG
INCHES
DIM
A
MIN
MAX
0.980
0.855
0.250
0.995
0.053
0.025
0.955
0.840
0.230
0.975
0.047
0.015
B
C
D
A
E
E
F
F
B
D
C
Suggested 68–pin PLCC surface mountable sockets
with leads on two sides only are:
McKenzie
34P–SMT–3
Harwin
Robinson Nugent
HIS–40001–04
PLCC–34–SMT
Dallas Semiconductor DS34PIN–PLC
For recommended prototype/breadboard sockets, con-
tact the Dallas Semiconductor factory.
100495 12/12
相关型号：
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