DS1707 [DALLAS]
3.3 and 5.0 Volt MicroMonitor; 3.3和5.0伏MicroMonitor
| 型号： | DS1707 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 3.3 and 5.0 Volt MicroMonitor |
| 文件： | 总9页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1707/DS1708
DS1707/DS1708
3.3 and 5.0 Volt MicroMonitor
FEATURES
PIN ASSIGNMENT
• Holds microprocessor in check during power tran-
PBRST
1
2
3
4
8
7
6
5
RST
RST
NC
sients
V
CC
• Automatically restarts microprocessor after power
failure
GND
IN
NMI
• Monitors pushbutton for external override
8–PIN DIP
(300 MIL)
• Accurate 5%, 10% or 20% resets for 3.3 systems and
PBRST
1
2
3
4
8
7
6
5
RST
RST
NC
5% or 10% resets for 5.0 volt systems
V
CC
• Eliminates the need for discrete components
• 20% tolerance compatible with 3.0 volt systems
GND
IN
NMI
8–PIN SOIC
(150 MIL)
• Pin compatible with the MAXIM MAX707/MAX708 in
8–pin DIP and 8–pin SOIC packages
PBRST
1
2
3
4
8
7
6
5
RST
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages
available
V
RST
NC
CC
GND
IN
NMI
• Industrial temperature range –40°C to +85°C
8–PIN µ–SOP
(118 MIL)
See Mech. Drawings
Section
DS1707 and DS1708_/R/S/T
PIN DESCRIPTION
PBRST
–
–
–
–
–
–
–
–
Pushbutton Reset Input
Power Supply
Ground
Input
Non–maskable Interrupt
No Connect
Active Low Reset Output
Active High Reset Output
V
CC
GND
IN
NMI
NC
RST
RST
DESCRIPTION
TheDS1707/DS17083.3or5.0VoltMicroMonitormoni-
tors three vital conditions for a microprocessor: power
supply, voltage sense, and external override. A preci-
sion temperature–compensated reference and
condition a non–maskable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When V returns to an in–tolerance condition,
CC
comparator circuit monitors the status of V
device and at an upstream point for maximum protec-
tion. When the sense input detects an out–of–tolerance
at the
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
CC
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
010996 1/9
DS1707/DS1708
The third function the DS1707/DS1708 performs is
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from ahigher
DC voltage level closer to the main system power input.
pushbutton reset control.
The DS1707/DS1708
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
Since the IN trip point V is 1.25 volts, the proper val-
TP
uesforR1andR2canbedeterminedbytheequationas
OPERATION
shown in Figure 5.
DS1707/DS1708 requires that the voltage at the IN pin
be limited to V . Therefore, the maximum allowable
Proper operation of the
Power Monitor
The DS1707/DS1708 detects out–of–tolerance power
CC
supply conditions and warns a processor–based sys-
voltage at the supply being monitored (V
) can also
MAX
tem of impending power failure. When V falls below
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply sys-
tem, maximizing the amount of time for system shut–
down between NMI and RST/RST.
CC
the minimum V tolerance, a comparator outputs the
CC
RST and RST signals. RST and RST are excellent con-
trol signals for a microprocessor, as processing is
stopped at the last possible moment of valid V . On
CC
power–up, RST and RST are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
When the supply being monitored decays to the voltage
sense point, the DS1707/DS1708 pulses the NMI out-
put to the active state for a minimum 200 µs. The NMI
power fail detection circuitry also has built–in hysteresis
of 100 µV. The supply must be below the voltage sense
point for approximately 5 µs before a low NMI will be
generated. In this way, power supply noise is removed
from the monitoring function, preventing false inter-
rupts. During a power–up, any detected IN pin levels
Pushbutton Reset
The DS1707/DS1708 provides an input pin for direct
connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally, this input is debounced and timed such that
RSTandRSTsignalsofatleast130msminimumwillbe
generated. The 130 ms delay commences as the push-
button reset input is released from the low level. The
pushbutton can be initiated by connecting the NMI out-
put to the PBRST input as shown in Figure 3.
below V by the comparator are disabled from gener-
TP
ating an interrupt until V rises to V
. As a result,
CCTP
CC
any potential NMI pulse will not be initiated until V
CC
reaches V
.
CCTP
Non–Maskable Interrupt
TheDS1707/DS1708 generates a non–maskable inter-
rupt (NMI) for early warning of a power failure. A preci-
sion comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an inter-
nal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
Connecting NMI to PBRST would allow the non–mask-
able interrupt to generate an automatic reset when an
out–of–tolerance condition occurred in a monitored
supply. An example is shown in Figure 3.
010996 2/9
DS1707/DS1708
MICROMONITOR BLOCK DIAGRAM Figure 1
IN
–
DIGITAL
SAMPLER
NMI
+
T.C.
REFERENCE
–
DIGITAL
SAMPLER
DIGITAL
DELAY
RST
RST
+
V
CC
LEVEL SENSE
AND
DEBOUNCE
PBRST
PUSHBUTTON RESET Figure 2
PBRST
RST
RST
NC
RST
INT0
V
CC
8051
µP
5V
DS1708
GND
IN
UPSTREAM
SUPPLY
VOLTAGE
NMI
PUSHBUTTON RESET CONTROLLED BY NMI Figure 3
µP
PBRST
RST
V
RST
CC
5V
RST
UPSTREAM
SUPPLY
VOLTAGE
DS1707
GND
IN
NC
NMI
010996 3/9
DS1707/DS1708
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
t
PDLY
PBRST
t
PB
V
IH
V
IL
t
RST
RST
RST
V
V
OH
OL
NON–MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5
PBRST
RST
RST
V
CC
V
SENSE
DS1708
GND
IN
NC
TO µP
R1
R2
NMI
VSENSE
R1 ) R2
VSENSE
+
x 1.25
VMAX
+
x VCC
R2
VTP
Example:
V
= 4.70 volts at the trip point
= 3.3 volts
SENSE
V
CC
10KΩ = R2
4.70
1.25
x 3.3 + 12.4 volts maximum
Therefore:
R1 ) 10K
4.5 +
x 1.25
R1 + 27.6KW
10K
010996 4/9
DS1707/DS1708
TIMING DIAGRAM: NON–MASKABLE INTERRUPT Figure 6
V
> 1.25V
IN
V
V
TP(MAX)
TP(MAX)
V
V
TP
TP
V
V
TP(MIN)
TP(MIN)
t
t
IPD
IPD
NMI
V
OH
V
OL
TIMING DIAGRAM: POWER DOWN Figure 7
t
F
V
CC
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
t
RPD
RST
RST SLEWS WITH V
CC
V
OH
V
RST
OL
010996 5/9
DS1707/DS1708
TIMING DIAGRAM: POWER UP Figure 8
t
R
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CC
t
RPU
RST
RST
V
V
OH
OL
RST
RST
010996 6/9
DS1707/DS1708
ABSOLUTE MAXIMUM RATINGS*
Voltage on V Pin Relative to Ground
–0.5V to +7.0V
CC
Voltage on I/O Relative to Ground
Operating Temperature
Storage Temperature
–0.5V to V +0.5V
–40°C to +85°C
–55°C to +125°C
CC
Soldering Temperature
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(–40°C to +85°C)
PARAMETER
SYMBOL
MIN
1.0
TYP
MAX
UNITS
NOTES
Supply Voltage
V
CC
5.5
V
V
1
PBRST Input High Level
V
IH
2.0
V
+0.3
1, 3
1, 4
CC
V
–0.5
CC
PBRST Input Low Level
V
IL
–0.03
+0.5
V
1
DC ELECTRICAL CHARACTERISTICS
(–40°C to +85°C; VCC=1.2V to 5.5V)
PARAMETER
SYMBOL
MIN
4.50
4.25
3.00
2.85
2.55
–1.0
TYP
4.65
4.40
3.08
2.93
2.63
MAX
4.75
4.50
3.15
3.00
2.70
+1.0
UNITS
V
NOTES
V
CC
V
CC
V
CC
V
CC
V
CC
Trip Point DS1707
Trip Point DS1708
Trip Point DS1708T
Trip Point DS1708S
Trip Point DS1708R
V
CCTP
V
CCTP
V
CCTP
V
CCTP
V
CCTP
1
1
1
1
1
2
3
3
3
V
V
V
V
Input Leakage
I
IL
µA
µA
mA
V
Output Current @ 2.4 volts
Output Current @ 0.4 volts
Output Voltage
I
350
OH
I
OL
10
V
OH
V
–0.1
CC
Operating Current
I
60
µA
5
@ V < 5.5 volts
CC
CC
Operating Current
I
50
µA
5
1
@ V < 3.6 volts
CC
CC
IN Input Trip Point
V
1.20
1.25
1.30
V
TP
CAPACITANCE
PARAMETER
(tA=25°C)
SYMBOL
MIN
TYP
MAX
UNITS
pF
NOTES
Input Capacitance
Output Capacitance
C
5
7
IN
C
pF
OUT
010996 7/9
DS1707/DS1708
AC ELECTRICAL CHARACTERISTICS
(–40°C to +85°C; VCC=1.2V to 5.5V)
PARAMETER
PBRST = V
SYMBOL
MIN
150
130
TYP
MAX
UNITS
ns
NOTES
t
PB
IL
Reset Active Time
t
205
5
285
8
ms
µs
RST
RPD
V
CC
V
CC
V
CC
V
CC
Detect to RST and RST
Slew Rate
t
7
6
t
F
20
130
0
µs
Detect to RST and RST
Slew Rate
t
205
285
ms
ns
RPU
t
R
PBRST Stable Low to RST and
RST
t
250
8
ns
PDLY
VIN Detect to NMI
t
5
µs
7
IPD
NOTES:
1. All voltages are referenced to ground.
2. PBRST is internally pulled up to V with an internal impedance of 40KΩ typical.
CC
3. V ꢀ 2.4 volts
CC
4. V < 2.4 volts
CC
5. Measured with outputs open and all inputs at V or ground.
CC
6. t = 5 µs
R
7. Noise immunity – pulses < 2 µs at V
minimum will not cause a reset.
CCTP
010996 8/9
DS1707/DS1708
PART MARKING CODES
8
1
7
6
5
4
ABCD
WWY
2
3
8–PIN µ–SOP
(118 MIL)
A, B, C and D represents the device type and tolerance.
ABCD
707_
708_
708R
708S
708T
–
–
–
–
–
DS1707
DS1708
DS1708R
DS1708S
DS1708T
WWY represents the device manufacturing Work
Week, and Year.
010996 9/9
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