DS17887N-3 [DALLAS]
Real Time Clock, Non-Volatile, 1 Timer(s), CMOS, PLASTIC, MODULE, DIP-24;
| 型号： | DS17887N-3 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Real Time Clock, Non-Volatile, 1 Timer(s), CMOS, PLASTIC, MODULE, DIP-24 时钟 外围集成电路 |
| 文件： | 总38页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS17885/DS17887
3 Volts/5 Volts Real Time Clock
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
Incorporates industry standard DS1287 PC clock
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
SQW
VBAUX
PWR
X1
plus enhanced features:
2
3
4
5
6
7
8
9
10
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ꢀ Y2K-compliant
RCLR
VBAT
IRQ
KS
RD
GND
WR
ꢀ +3 or +5V operation
ꢀ SMI recovery stack
ꢀ 64-bit silicon serial number
ꢀ Power control circuitry supports system
power-on from date/time alarm or key
closure
ALE
11
12
ꢀ 32 kHz output on power-up
ꢀ Crystal select bit allows RTC to operate with
6 pF or 12.5 pF crystal
CS
GND
DS17885 24-Pin DIP
DS17885S 24-Pin SOIC
ꢀ 114 bytes user NV RAM
ꢀ Auxiliary battery input
PWR
NC
NC
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
SQW
VBAUX
2
3
4
5
6
7
8
9
10
ꢀ 8 kbytes additional NV RAM
ꢀ RAM clear input
RCLR
NC
IRQ
KS
RD
NC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ꢀ Century register
ꢀ Date alarm register
ꢀ Compatible with existing BIOS for original
DS1287 functions
WR
ALE
ꢀ Available as chip (DS17885) or stand-alone
module with embedded battery and crystal
(DS17887)
11
12
CS
GND
DS17887 24-Pin
ꢀ Timekeeping algorithm includes leap year
compensation valid up to 2100
Encapsulated Package
IRQ
VBAT
RCLR
VBAUX
SQW
VCC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
KS
2
RD
3
GND
WR
4
5
ALE
CS
6
VCC
7
GND
GND
AD7
AD6
NC
PWR
X1
8
9
X2
10
11
12
13
14
NC
ADO
AD1
AD2
AD5
AD4
AD3
DS17885E 28-Pin TSOP
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070300
DS17885/DS17887
ORDERING INFORMATION
PART #
DESCRIPTION
DS17885XX-X RTC Chip
3
5
+3V operating range
+5V operating range
blank commercial temp range
N
industrial temp range
blank 24-pin DIP
E
S
28- pin TSOP
24- pin SOIC
DS17887X-X
RTC Module; 24-pin DIP
3
+3V operating range
+5V operating range
5
blank commercial temp range
industrial
PIN DESCRIPTION
X1
- Crystal Input
X2
- Crystal Output
RCLR
- RAM Clear Input
AD0-AD7 - Multiplexed Address/Data Bus
PWR
- Power-on Interrupt Output (open drain)
- Kickstart Input
KS
CS
ALE
- RTC Chip Select Input
- RTC Address Strobe
WR
RD
- RTC Write Data Strobe
- RTC Read Data Strobe
IRQ
- Interrupt Request Output (open drain)
- Square Wave Output
- +3 or +5V Main Supply
- Ground
SQW
VCC
GND
VBAT
VBAUX
NC
- Battery + Supply
- Auxiliary Battery Supply
- No Connect
DESCRIPTION
The DS17885/DS17887 is a real time clock (RTC) designed as a successor to the industry standard
DS1285, DS1385, DS1485, DS1585, and DS1685 PC real time clocks. This device provides the industry
standard DS1285 clock function with either +3.0 or +5.0-volt operation. The DS17885 also incorporates
a number of enhanced features, including a silicon serial number, power on/off control circuitry,
114 bytes of user NV SRAM plus 8 kbytes of additional NV RAM, and 32.768 kHz output for sustaining
power management activities.
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DS17885/DS17887
The DS17885/DS17887 power control circuitry allows the system to be powered on via an external
stimulus, such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin can be
triggered by one or either of these events, and can be used to turn on an external power supply. The PWR
pin is under software control, so that when a task is complete the system power can then be shut down.
The DS17885 is a clock/calendar chip with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.
The DS17887 incorporates the DS17885 chip, a 32.768 kHz crystal, and a lithium battery in a complete,
self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a
minimum of 10 years of timekeeping and data retention in the absence of VCC is guaranteed.
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS17885/DS17887. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCC - DC power is provided to the device on these pins. VCC is the +3-volt or +5-volt input.
SQW (Square Wave Output) - The SQW pin will provide a 32 kHz square wave output, tREC, after a
power-up condition has been detected. This condition sets the following bits enabling the 32 kHz output:
DV1=1, and E32K=1. A square wave will be output on this pin if either SQWE=1 or E32K=1. If
E32K=1, then 32 kHz will be output regardless of the other control bits. If E32K=0, then the output
frequency is dependent on the control bits in register A. The SQW pin can output a signal from one of
13 taps provided by the 15 internal divider stages of the real time clock. The frequency of the SQW pin
can be changed by programming Register A as shown in Table 2. The SQW signal can be turned on and
off using the SQWE bit in register B or the E32K bit in extended register 4Bh. A 32 kHz SQW signal is
output when the Enable 32 kHz (E32K) bit in extended register 4Bh is a logic 1, and VCC is above VPF. A
32 kHz square wave is also available when VCC is less than VPF if E32K=1, ABE=1, and voltage is
applied to the VBAUX pin.
AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS17885 since the
bus change from address to data occurs during the internal RAM access time. Addresses must be valid
prior to the latter portion of ALE, at which time the DS17885/DS17887 latches the address. Valid write
data must be present and held stable during the latter portion of the WR pulse. In a read cycle the
DS17885/DS17887 outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is
terminated and the bus returns to a high impedance state as RD transitions high. The address/data bus
also serves as a bi-directional data path for the external extended RAM.
ALE (RTC Address Strobe Input; active high) - A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS17885/DS17887.
RD (RTC Read Input; active low) - RD identifies the time period when the DS17885/DS17887 drives
the bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.
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DS17885/DS17887
WR (RTC Write Input; active low) - The WR signal is an active low signal. The WR signal defines
the time period during which data is written to the addressed register.
CS (RTC Chip Select Input; active low) - The Chip Select signal must be asserted low during a bus
cycle for DS17885/DS17887 to be accessed. CS must be kept in the active state during RD and WR
timing. Bus cycles which take place with ALE asserted but without asserting CS will latch addresses.
However, no data transfer will occur.
IRQ (Interrupt Request Output; open drain, active low) - The IRQ pin is an active low output of the
DS17885/DS17887 that can be tied to the interrupt input of a processor. The IRQ output remains low as
long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To
clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active
state.
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ pin is an open drain output and requires
an external pullup resistor. The voltage on the pull up supply should be no greater than VCC + 0.2 volt.
PWR (Power On Output; open drain, active low) - The PWR pin is intended for use as an on/off
control for the system power. With VCC voltage removed from the DS17885/DS17887, PWR may be
automatically activated from a Kickstart input via the KS pin or from a Wake-Up interrupt. Once the
system is powered on, the state of PWR can be controlled via bits in the Dallas registers. For 5-volt
operation, the voltage of the pull up supply should be no greater than 5.7 volts. For 3-volt operation, the
voltage on the pull up supply should be no greater than 3.9 volts.
KS (Kickstart Input; active low) - When VCC is removed from the DS17885/DS17887, the system can
be powered on in response to an active low transition on the KS pin, as might be generated from a key
closure. VBAUX must be present and Auxiliary Battery Enable bit (ABE) must be set to 1 if the Kickstart
function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the KS
pin can be used as an interrupt input.
RCLR (RAM Clear Input; active low) - If enabled by software, taking RCLR low will result in the
clearing of the 114 bytes of user RAM. When enabled, RCLR can be activated whether or not VCC is
present.
VBAUX - Auxiliary battery input required for kickstart and wake-up features. This input also supports
clock/ calendar and user RAM if VBAT is at lower voltage or is not present. A standard +3-volt lithium
cell or other energy source can be used. For 3-volt operation, VBAUX must be held between +2.5 and
+3.7 volts. For 5-volt operation, VBAUX must be held between +2.5 and +5.2 volts . If VBAUX is not going
to be used it should be grounded and auxiliary battery enable bit bank 1, register 4BH, should=0.
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DS17885/DS17887
DS17885/DS17887 BLOCK DIAGRAM Figure 1
5 of 38
DS17885/DS17887
DS17885 ONLY
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS17885 must
be used with a crystal that has a specified load capacitance of either 6 pF or 12.5 pF. The Crystal Select
(CS) bit in Extended Control Register 4B is used to select operation with a 6 pF or 12.5 pF crystal. The
crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors.
Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard-
ringed with ground and that high frequency signals be kept away from the crystal area.
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time Clocks.” The DS17885 can also be driven by an
external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
V
BAT - Battery input for any standard 3-volt lithium cell or other energy source. Battery voltage must be
held between 2.5 and 3.7 volts for proper operation.
POWER-DOWN/POWER-UP CONSIDERATIONS
The real time clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the
DS17885/DS17887 and reaches a level of greater than VPF (power fail trip point), the device becomes
accessible after tREC, provided that the oscillator is running and the oscillator countdown chain is not in
reset (see Register A). This time period allows the system to stabilize after power is applied.
The DS17885/DS17887 is available in either a 3-volt or a 5-volt device.
The 5-volt device is fully accessible and data can be written and read only when VCC is greater than
4.5 volts. When VCC is below 4.5 volts, read and writes are inhibited. However, the timekeeping
function continues unaffected by the lower input voltage. As VCC falls below the greater of VBAT and
VBAUX, the RAM and timekeeper are switched over to a lithium battery connected either to the VBAT pin
or VBAUX pin.
The 3-volt device is fully accessible and data can be written or read only when VCC is greater than
2.7 volts. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT and
VBAUX , the power supply is switched from VCC to the backup supply (the greater of
and VBAUX)
when VCC drops below VPF. If VPF is greater than VBAT and VBAUX, the power supplyVisBAsTwitched from
VCC to the backup supply when VCC drops below the larger of VBAT and VBAUX
.
When VCC falls below VPF, the chip is write-protected. With the possible exception of the KS , PWR ,
RCLR and SQW pins, all inputs are ignored and all outputs are in a high impedance state.
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DS17885/DS17887
RTC ADDRESS MAP
The address map for the RTC registers of the DS17885/DS17887 is shown in Figure 2. The address map
consists of the 14 clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and
4 bytes are used for control and status. All registers can be directly written or read except for the
following:
1. Registers C and D are read-only.
2. Bit-7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
DS17885 REAL TIME CLOCK ADDRESS MAP Figure 2
TIME, CALENDAR AND ALARM LOCATIONS
The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1.
The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents
of the time, calendar, and alarm registers can be either Binary or Binary-Coded Decimal (BCD) format.
Table 1 shows the binary and BCD formats of the ten time, calendar, and alarm locations that reside in
both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank
1 switching will be explained later in this text).
Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written
to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data
format (binary or BCD), should be set via the data mode bit (DM) of Register B. All time, calendar, and
alarm registers must use the same data mode. The set bit in Register B should be cleared after the data
mode bit has been written to allow the real time clock to update the time and calendar bytes.
Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be
changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing
the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents
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DS17885/DS17887
PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are
double buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm
condition. If a read of the time and calendar data occurs during an update, a problem exists where
seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendar
data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later
in this text.
The three time alarm bytes can be used in two ways. First, when the alarm time is written in the
appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified
time each day if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in
one or more of the three time alarm bytes. The “don’t care” code is any hexadecimal value from C0 to
FF. The two most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm
will be generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is
generated every minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care”
codes in all three time alarm bytes create an interrupt every second. The three time alarm bytes may be
used in conjunction with the date alarm as described in the Wake-up/Kickstart section. The century
counter will be discussed later in this text.
TIME, CALENDAR AND ALARM DATA MODES Table 1
ADDRESS
LOCATION
FUNCTION
DECIMAL
RANGE
RANGE
BINARY DATA MODE
BCD DATA MODE
OOH
01H
02H
03H
04H
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours 12-hr, Mode
Hours 24-hr, Mode
Hours Alarm 12-hr, Mode
Hours Alarm 24-hr, Mode
0-59
0-59
0-59
0-59
1-12
0-23
1-12
0-23
1-7
00-3B
00-3B
00-3B
00-59
00-59
00-59
00-3B
00-59
01-0C AM, 81-8C PM
00-17
01-0C AM, 81-8C PM
00-17
01-12 AM, 81-92 PM
00-23
01-12 AM, 81-92 PM
00-23
05H
06H
Days of the week
01-07
01-07
Sunday=1
07H
08H
09H
Date of Month
Month
Year
Century
Date Alarm
1-31
1-12
0-99
0-99
1-31
01-1F
01-0C
00-63
00-63
01-1F
01-31
01-12
00-99
00-99
01-31
BANK 1, 48H
BANK 1, 49H
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DS17885/DS17887
CONTROL REGISTERS
The four control registers; A, B, C, and D reside in both bank 0 and bank 1. These registers are
accessible at all times, even during the update cycle.
REGISTER A
MSB
LSB
BIT 0
RS0
BIT 7
UIP
BIT 6
DV2
BIT 5
DV1
BIT 4
DV0
BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1,
the update transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244
µs. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is
zero. The UIP bit is read-only. Writing the SET bit in Register B to a one inhibits any update transfer
and clears the UIP status bit.
DV2, DV1, DV0 - These bits are defined as follows:
DV2 = Countdown Chain
1 - resets countdown chain only if DV1=1
0 - countdown chain enabled
DV1 = Oscillator Enable
0 - oscillator off
1 - oscillator on, VCC power-up state
DV0 = Bank Select
0 - original bank
1 - extended registers
A pattern of 01X is the only combination of bits that will turn the oscillator on and allow the RTC to keep
time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update
will occur at 500 ms after a pattern of 01X is written to DV2, DV1, and DV0.
RS3, RS2, RS1, RS0 - These four rate-selection bits select one of the 13 taps on the 15-stage divider or
disable the divider output. The tap selected can be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user can do one of the following:
Enable the interrupt with the PIE bit;
Enable the SQW output pin with the SQWE or E32K bits;
Enable both at the same time and the same rate; or
Enable neither.
Table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the
RS bits.
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DS17885/DS17887
REGISTER B
MSB
LSB
BIT 0
DSE
BIT 7
SET
BIT 6
PIE
BIT 5
AIE
BIT 4
UIE
BIT 3
SQWE
BIT 2
DM
BIT 1
24/12
SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per
second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be
executed in a similar manner. SET is a read/write bit that is not modified by internal functions of the
DS17885/DS17887.
PIE - The Periodic Interrupt Enable bit is a read/write bit which allows the Periodic Interrupt Flag (PF)
bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated
by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the PIE bit
blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set
at the periodic rate. PIE is not modified by any internal DS17885/DS17887 functions.
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the Alarm
Flag (AF) bit in register C to assert IRQ . An alarm interrupt occurs for each second that the three time
bytes equal the three alarm bytes including a “don’t care” alarm code of binary 11XXXXXX. When the
AIE bit is set to 0, the AF bit does not initiate the IRQ signal. The internal functions of the
DS17885/DS17887 do not affect the AIE bit.
UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write bit that enables the Update End Flag
(UF) bit in Register C to assert IRQ . The SET bit going high clears the UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit is set to a 1 and E32K=0, a square wave signal at
the frequency set by the rate-selection bits RS3 through RS0 is driven out on the SQW pin. When the
SQWE bit is set to 0 and E32K=0, the SQW pin is held low. SQWE is a read/write bit. SQWE is set to a
1 when VCC is powered up.
DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit
is not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies Binary
Coded Decimal (BCD) data.
24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode
and a 0 indicates the 12-hour mode. This bit is read/write.
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when
DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On
the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions.
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DS17885/DS17887
REGISTER C
MSB
LSB
BIT 0
0
BIT 7
IRQF
BIT 6
PF
BIT 5
AF
BIT 4
UF
BIT 3
0
BIT 2
0
BIT 1
0
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
WF = WIE= 1
KF = KSE= 1
RF = RIE = 1
i.e., IRQF = (PF ● PIE) + (AF ● AIE) + (UF ● UIE) + (WF ● WIE) + (KF ● KSE) + (RF ● RIE)
Any time the IRQF bit is a 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after
Register C is read by the program.
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independently of the state of the PIE bit. When both PF and PIE are 1’s, the IRQ signal is active and will
set the IRQF bit. The PF bit is cleared by a software read of Register C.
AF - A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time.
If the AIE bit is also a 1, the IRQ pin will go low and a 1 will appear in the IRQF bit. A read of Register
C will clear AF.
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to
1, the one in UF causes the IRQF bit to be a 1, which will assert the IRQ pin. UF is cleared by reading
Register C.
BIT 3 THROUGH BIT 0 - These are unused bits of the status Register C. These bits always read 0 and
cannot be written.
REGISTER D
MSB
LSB
BIT 0
0
BIT 7
VRT
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the battery connected to the VBAT
pin or the battery connected to VBAUX, whichever is at a higher voltage. This bit is not writeable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated
and both the contents of the RTC data and RAM data are questionable.
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,
when read, they will always read 0.
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DS17885/DS17887
NONVOLATILE RAM - RTC
The general purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS17885/DS17887. They can be used by the application program as nonvolatile memory and are fully
available during the update cycle.
The user RAM is divided into two separate memory banks. When the bank 0 is selected, the 14 real time
clock registers and 114 bytes of user RAM are accessible. When bank 1 is selected, an additional
8 kbytes of user RAM are accessible through the extended RAM address and data registers.
INTERRUPT CONTROL
The DS17885/DS17887 includes six separate, fully automatic sources of interrupt for a processor:
1. Alarm interrupt
2. Periodic interrupt
3. Update-ended interrupt
4. Wake-up interrupt
5. Kickstart interrupt
6. RAM clear interrupt
The conditions which generate each of these independent interrupts are described in greater detail
elsewhere in this data sheet. This section describes the overall control of the interrupts.
The application software can select which interrupts, if any, are to be used. There are a total of 6 bits
including 3 bits in Register B and 3 bits in Extended Register B which enable the interrupts. The
extended register locations are described later. Writing a logic 1 to an interrupt enable bit permits that
interrupt to be initiated when the event occurs. A logic 0 in the interrupt enable bit prohibits the IRQ pin
from being asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is
enabled, IRQ will immediately be set at an active level, even though the event initiating the interrupt
condition may have occurred much earlier. As a result, there are cases where the software should clear
these earlier generated interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended
Register A. These flag bits are set regardless of the setting of the corresponding enable bit located either
in Register B or in Extended Register B. The flag bits can be used in a polling mode without enabling the
corresponding enable bits.
However, care should be taken when using the flag bits of Register C as they are automatically cleared to
0 immediately after they are read. Double latching is implemented on these bits so that bits which are set
remain stable throughout the read cycle. All bits which were set are cleared when read and new interrupts
which are pending during the read cycle are held until after the cycle is completed. One, 2, or 3 bits can
be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no
interrupts are lost.
The flag bits in Extended Register A are not automatically cleared following a read. Instead, each flag bit
can be cleared to 0 only by writing 0 to that bit.
When using the flag bits with fully enabled interrupts, the IRQ line will be driven low when an interrupt
flag bit is set and its corresponding enable bit is also set. IRQ will be held low as long as at least one of
the six possible interrupt sources has it s flag and enable bits both set. The IRQF bit in Register C is a
12 of 38
DS17885/DS17887
1 whenever the IRQ pin is being driven low as a result of one of the six possible active sources.
Therefore, determination that the DS17885/DS17887 initiated an interrupt is accomplished by reading
Register C and finding IRQF=1. IRQF will remain set until all enabled interrupt flag bits are cleared to 0.
SQUARE WAVE OUTPUT SELECTION
The SQW pin can be programmed to output a variety of frequencies divided down from the 32.768 kHz
crystal tied to X1 and X2. The square wave output is enabled and disabled via the SQWE bit in Register
B or the E32K bit in extended register 4Bh. If the square wave is enabled (SQWE=1 or E32K=1), then
the output frequency will be determined by the settings of the E32K bit in Extended Register 4Bh and by
the RS3-0 bits in Register A. If E32K=1, then a 32.768 kHz square wave will be output on the SQW pin
regardless of the settings of RS3-0 and SQWE.
If E32K = 0, then the square wave output frequency is determined by the RS3-0 bits. These bits control a
1-of-15 decoder which selects one of thirteen taps that divide the 32.768 kHz frequency. The RS3-0 bits
establish the SQW output frequency as shown in Table 2. In addition, RS3-0 bits control the periodic
interrupt selection as described below.
If E32K=1, and the Auxiliary Battery Enable bit (ABE, bank 1; register 04BH) is enabled, and voltage is
applied to VBAUX then the 32 kHz square wave output signal will be output on the SQW pin in the absence
of VCC. This facility is provided to clock external power management circuitry. If any of the above
requirements are not met, no square wave output signal will be generated on the SQW pin in the absence
of VCC.
A pattern of 01X in the DV2, DV1, and DV0, bits respectively, will turn the oscillator on and enable the
countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these
bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1.
A pattern of 11X will turn the oscillator on, but the oscillator’s countdown chain will be held in reset, as
it was in the DS1287. Any other bit combination for DV2 and DV1 will keep the oscillator off.
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once
every 122 µs. This function is separate from the alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate is selected using the same RS3-0 bits in Register A
which select the square wave frequency (see Table 2). Changing the bits affects both the square wave
frequency and the periodic interrupt output. However, each function has a separate enable bit in Register
B. The SQWE and E32K bits control the square wave output. Similarly, the periodic interrupt is enabled
by the PIE bit in Register B. The periodic interrupt can be used with software counters to measure inputs,
create output intervals, or await the next needed software function.
13 of 38
DS17885/DS17887
PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY
Table 2
EXT. REG. B SELECT BITS REGISTER A
tPI PERIODIC
INTERRUPT RATE
SQW OUTPUT
FREQUENCY
E32K
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
None
None
3.90625 ms
7.8125 ms
122.070 µs
244.141 µs
488.281 µs
976.5625 µs
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
256 Hz
128 Hz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
32.768 kHz
125 ms
250 ms
500 ms
X
X
X
X
*
*RS3-RS0 determine periodic interrupt rates as listed for E32K=0.
14 of 38
DS17885/DS17887
UPDATE CYCLE
The Serialized RTC executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, alarm
and elapsed time byte is frozen and will not update as the time increments. However, the time countdown
chain continues to update the internal copy of the buffer. This feature allows the time to maintain
accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that
time and calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all alarm
locations.
There are three methods that can handle access of the real time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every update cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244 µs later. If a low is read on the UIP bit, the user has at least 244 µs before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244 µs.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts
that occur at a rate of greater than tBUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within (tPI/ 2+tBUC) to ensure that data
is not read during the update cycle.
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
15 of 38
DS17885/DS17887
EXTENDED FUNCTIONS
The extended functions provided by the DS17885/DS17887 that are new to the RAMified RTC family
are accessed via a software controlled bank switching scheme, as illustrated in Figure 4. In bank 0, the
clock/calendar registers and 50 bytes of user RAM are in the same locations as for the DS1287. As a
result, existing routines implemented within BIOS, DOS, or application software packages can gain
access to the DS17885/DS17887 clock registers with no changes. Also in bank 0, an extra 64 bytes of
RAM are provided at addresses just above the original locations for a total of 114 directly addressable
bytes of user RAM.
When bank 1 is selected, the clock/calendar registers and the original 50 bytes of user RAM still appear
as bank 0. However, the Dallas registers which provide control and status for the extended functions will
be accessed in place of the additional 64 bytes of user RAM. The major extended functions controlled by
the Dallas registers are listed below:
1. 64-bit Silicon Serial Number
2. Century counter
3. RTC Write Counter
4. Date Alarm
5. Auxiliary Battery Control/Status
6. Wake-Up
7. Kickstart
8. RAM Clear Control/Status
9. 8-kbytes Extended RAM Access
The bank selection is controlled by the state of the DV0 bit in register A. To access bank 0 the DV0 bit
should be written to a 0. To access bank 1, DV0 should be written to a 1. Register locations designated
as reserved in the bank 1 map are reserved for future use by Dallas Semiconductor. Bits in these
locations cannot be written and will return a 0 if read.
SILICON SERIAL NUMBER
A unique 64-bit lasered serial number is located in bank 1, registers 40h - 47h. This serial number is
divided into three parts. The first byte in register 40h contains a model number to identify the device type
of the DS17885/DS17887. Registers 41h - 46h contain a unique binary number. Register 47h contains a
CRC byte used to validate the data in registers 40h - 46h. All 8 bytes of the serial number are read-only
registers.
The DS17885/DS17887 is manufactured such that no two devices will contain an identical number in
locations 41h - 47h.
CENTURY COUNTER
A register has been added in bank 1, location 48H, to keep track of centuries. The value is read in either
binary or BCD according to the setting of the DM bit.
RTC WRITE COUNTER
An 8-bit counter located in extended register bank 1, 5Eh, will count the number of times the RTC is
written to. This counter will be incremented on the rising edge of the WR signal every time that the CS
signal qualifies it. This counter is a read-only register and will roll-over after 256 RTC write pulses. This
counter can be used to determine if and how many RTC writes have occurred since the last time this
register was read.
16 of 38
DS17885/DS17887
AUXILIARY BATTERY
The VBAUX input is provided to supply power from an auxiliary battery for the DS17885/DS17887
kickstart, wake-up, and SQW output features in the absence of VCC. This power source must be available
in order to use these auxiliary features when no VCC is applied to the device.
The Auxiliary Battery Enable (ABE; bank 1, register 04BH) bit in extended control register B is used to
turn on and off the auxiliary battery for the above functions in the absence of VCC. When set to a 1,
VBAUX battery power is enabled, and when cleared to 0, VBAUX battery power is disabled to these
functions.
In the DS17885/DS17887, this auxiliary battery may be used as the primary backup power source for
maintaining the clock/calendar, user RAM, and extended external RAM functions. This occurs if the
V
BAT pin is at a lower voltage than VBAUX. If the DS17885 is to be backed-up using a single battery with
the auxiliary features enabled, then VBAUX should be used and VBAT should be grounded. If VBAUX is not
to be used, it should be grounded and ABE should be cleared to 0.
WAKE-UP/KICKSTART
The DS17885/DS17887 incorporates a wake-up feature which can power the system on at a
predetermined date and time through activation of the PWR output pin. In addition, the kickstart feature
can allow the system to be powered up in response to a low going transition on the KS pin, without
operating voltage applied to the VCC pin. As a result, system power may be applied upon such events as a
key closure, or modem ring detect signal. In order to use either the wake-up or the kickstart features, the
DS17885/DS17887 must have an auxiliary battery connected to the VBAUX pin and the oscillator must be
running and the countdown chain must not be in reset (Register A DV2, DV1, DV0 = 01X). If DV2,
DV1, and DV0 are not in this required state, the PWR pin will not be driven low in response to a kickstart
or wake-up condition, while in battery-backed mode.
The wake-up feature is controlled through the Wake-up Interrupt Enable bit in extended control register B
(WIE, bank 1, 04BH). Setting WIE to 1 enables the wake-up feature, clearing WIE to 0 disables it.
Similarly, the kickstart feature is controlled through the Kickstart Interrupt Enable bit in extended control
register B (KSE, bank 1, 04BH).
A wake-up sequence will occur as follows: When wake-up is enabled via WIE = 1 while the system is
powered down (no VCC voltage), the clock/calendar will monitor the current date for a match condition
with the date alarm register (bank 1, register 049H). In conjunction with the date alarm register, the
hours, minutes, and seconds alarm bytes in the clock/calendar register map (bank 0, registers 05H, 03H,
and 01H) are also monitored. As a result, a wake-up will occur at the date and time specified by the date,
hours, minutes, and seconds alarm register values. This additional alarm will occur regardless of the
programming of the AIE bit (bank 0, register B, 0BH). When the match condition occurs, the PWR pin
will automatically be driven low. This output can be used to turn on the main system power supply
which provides VCC voltage to the DS17885/DS17887 as well as the other major components in the
system. Also at this time, the Wake-Up flag (WF, bank 1, register 04AH) will be set, indicating that a
wake-up condition has occurred.
A kickstart sequence will occur when kickstarting is enabled via KSE = 1. While the system is powered
down, the KS input pin will be monitored for a low going transition of minimum pulse width tKSPW
.
When such a transition is detected, the PWR line will be pulled low, as it is for a wake-up condition.
17 of 38
DS17885/DS17887
Also at this time, the Kickstart Flag (KF, bank 1, register 04AH) will be set, indicating that a kickstart
condition has occurred.
The timing associated with both the wake-up and kickstarting sequences is illustrated in the Wake-Up /
Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing
associated with these functions is divided into 5 intervals, labeled 1-5 on the diagram.
The occurrence of either a kickstart or wake-up condition will cause the PWR pin to be driven low, as
described above. During interval 1, if the supply voltage on the DS17885/DS17887 VCC pin rises above
the greater of VBAT or VPF before the power on timeout period (tPOTO) expires, then PWR will remain at
the active low level. If VCC does not rise above the greater of VBAT or VPF in this time, then the PWR
output pin will be turned off and will return to its high impedance level. In this event, the IRQ pin will
also remain tri-stated. The interrupt flag bit (either WF or KF) associated with the attempted power on
sequence will remain set until cleared by software during a subsequent system power on.
If VCC is applied within the timeout period, then the system power on sequence will continue as shown in
intervals 2-5 in the timing diagram. During interval 2, PWR will remain active and IRQ will be driven to
its active low level, indicating that either WF or KF was set in initiating the power on. In the diagram KS
is assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit will be automatically
cleared to 0 in response to a successful power on. The PWR line will remain active as long as the PAB
remains cleared to 0.
At the beginning of interval 3, the system processor has begun code execution and clears the interrupt
condition of WF and/or KF by writing 0’s to both of these control bits. As long as no other interrupt
within the DS17885/DS17887 is pending, the IRQ line will be taken inactive once these bits are reset.
Execution of the application software may proceed. During this time, both the wake-up and kickstart
functions may be used to generate status and interrupts. WF will be set in response to a date, hours,
minutes, and seconds match condition. KF will be set in response to a low going transition on KS . If the
associated interrupt enable bit is set (WIE and/or KSE) then the IRQ line will driven active low in
response to enabled event. In addition, the other possible interrupt sources within the DS17885/DS17887
may cause IRQ to be driven low. While system power is applied, the on chip logic will always attempt to
drive the PWR pin active in response to the enabled kickstart or wake-up condition. This is true even if
PWR was previously inactive as the result of power being applied by some means other than wake-up or
kickstart.
The system may be powered down under software control by setting the PAB bit to a logic 1. This causes
the open-drain PWR pin to be placed in a high impedance state, as shown at the beginning of interval 4 in
the timing diagram. As VCC voltage decays, the IRQ output pin will be placed in a high impedance state
when VCC goes below VPF. If the system is to be again powered on in response to a wake-up or kickstart,
then the both the WF and KF flags should be cleared and WIE and/or KSE should be enabled prior to
setting the PAB bit.
During interval 5, the system is fully powered down. Battery backup of the clock calendar and
nonvolatile RAM is in effect and IRQ is tri-stated, and monitoring of wake-up and kickstart takes place.
If PRS=1, PWR stays active, otherwise if PRS=0 PWR is tri-stated.
18 of 38
DS17885/DS17887
RAM CLEAR
The DS17885/DS17887 provides a RAM clear function for the 114 bytes of user RAM. When enabled,
this function can be performed regardless of the condition of the VCC pin.
The RAM clear function is enabled or disabled via the RAM Clear Enable bit (RCE; bank 1, register
04BH). When this bit is set to a logic 1, the 114 bytes of user RAM will be cleared (all bits set to 1)
when an active low transition is sensed on the RCLR pin. This action will have no effect on either the
clock/calendar settings or upon the contents of the extended RAM. The RAM clear Flag (RF, bank 1,
register 04AH) will be set when the RAM clear operation has been completed. If VCC is present at the
time of the RAM clear and RIE=1, the IRQ line will also be driven low upon completion. The interrupt
condition can be cleared by writing a zero to the RF bit. The IRQ line will then return to its inactive high
level provided there are no other pending interrupts. Once the RCLR pin is activated, all read/write
accesses are locked out for a minimum recover time, specified as tREC in the Electrical Characteristics
section.
When RCE is cleared to 0, the RAM clear function is disabled. The state of the RCLR pin will have no
effect on the contents of the user RAM, and transitions on the RCLR pin have no effect on RF.
8k X 8 EXTENDED RAM
The DS17885/DS17887 provides 8k x 8 of on-chip SRAM which is controlled as nonvolatile storage
sustained from a lithium battery. On power-up, the RAM is taken out of write protect status by the
internal power OK signal (POK) generated from the write protect circuitry.
The on-chip 8k x 8 nonvolatile SRAM is accessed via the eight multiplexed address/data lines AD7 to
AD0. Access to the SRAM is controlled by three on-chip latch registers. Two registers are used to hold
the SRAM address, and the other register is used to hold read/write data. The SRAM address space is
from 00h to 01FFFh.
Access to the extended 8k x 8 RAM is controlled via three of the Dallas registers shown in Figure 4. The
Dallas registers in bank 1 must first be selected by setting the DV0 bit in register A to a logic 1. The
13-bit address of the RAM location to be accessed must be loaded into the extended RAM address
registers located at 50h and 51h. The least significant address byte should be written to location 50h, and
the most significant 5-bits (right-justified) should be loaded in location 51h. Data in the addressed
location may be read by performing a read operation from location 53h, or written to by performing a
write operation to location 53h. Data in any addressed location may be read or written repeatedly without
changing the address in location 50h and 51h.
To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment
the extended RAM address. To enable the burst mode feature, set the BME bit in the extended control
register 4Ah, to a logic 1. With burst mode enabled, write the extended RAM starting address location to
registers 50h and 51h. Then read or write the extended RAM data from/to register 53h. The extended
RAM address locations are automatically incremented on the rising edge of RD or WR only when
register 53h is being accessed. Refer to the Burst Mode Timing Waveform.
19 of 38
DS17885/DS17887
DS17885/DS17887 EXTENDED REGISTER BANK DEFINITION Figure 4
BANK 0
DV0 = 0
BANK 1
DV0 = 1
MSB
LSB
MSB
LSB
00
00
TIMEKEEPING AND CONTROL
50 BYTES - USER RAM
TIMEKEEPING AND CONTROL
50 BYTES - USER RAM
0D
0E
0D
0E
3F
40
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
MODEL NUMBER BYTE
1ST BYTESERIAL NUMBER
2ND BYTE SERIAL NUMBER
3RD BYTE SERIAL NUMBER
4TH BYTE SERIAL NUMBER
5TH BYTE SERIAL NUMBER
6TH BYTE SERIAL NUMBER
CRC BYTE
CENTURY BYTE
DATEALARM
EXTENDED CONTROL REG 4A
EXTENDED CONTROL REG 4B
RESERVED
RESERVED
RTC ADDRESS - 2
RTC ADDRESS - 3
EXTENDED RAM ADDR - LSB
EXTENDED RAM ADDR - MSB
RESERVED
EXTENDED
RAM
64 BYTES - USER RAM
8K X 8
EXTENDED RAM DATA PORT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RTC WRITE COUNTER
RESERVED
7F
7F
20 of 38
DS17885/DS17887
EXTENDED CONTROL REGISTERS
Two extended control registers are provided to supply controls and status information for the extended
features offered by the DS17885/DS17887. These are designated as extended control registers A and B
and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits
within these registers are described as follows.
EXTENDED CONTROL REGISTER 4A
MSB
LSB
BIT 0
KF
BIT 7
VRT2
BIT 6
INCR
BIT 5
BME
BIT 4
*
BIT 3
PAB
BIT 2
RF
BIT 1
WF
VRT2 - This status bit gives the condition of the auxiliary battery. It is set to a logic 1 condition when
the external lithium battery is connected to the VBAUX. If this bit is read as a logic 0, the external battery
should be replaced.
INCR - Increment in Progress status bit. This bit is set to a 1 when an increment to the time/date
registers is in progress and the alarm checks are being made. INCR will be set to a 1 at 122 µs before the
update cycle starts and will be cleared to 0 at the end of each update cycle.
BME - Burst Mode Enable. The burst mode enable bit allows the extended user RAM address registers
to automatically increment for consecutive reads and writes. When BME is set to a logic 1, the automatic
incrementing will be enabled and when BME is set to a logic 0, the automatic incrementing will be
disabled.
PAB - Power Active Bar control bit. When this bit is 0, the PWR pin is in the active low state. When
this bit is 1, the PWR pin is in the high impedance state. This bit can be written to a logic 1 or 0 by the
user. If either WF AND WIE = 1 OR KF AND KSE = 1, the PAB bit will be cleared to 0.
RF - Ram Clear Flag. This bit will be set to a logic 1 when a high to low transition occurs on the RCLR
input if RCE=1. The RF bit is cleared by writing it to a logic 0. This bit can also be written to a logic 1
to force an interrupt condition.
WF – Wake-up Alarm Flag - This bit is set to 1 when a wake-up alarm condition occurs or when the user
writes it to a 1. WF is cleared by writing it to a 0.
KF - Kickstart Flag - This bit is set to a 1 when a kickstart condition occurs or when the user writes it to a
1. This bit is cleared by writing it to a logic 0.
* Reserved bits. These bits are reserved for future use by Dallas Semiconductor. They can be read and
written, but have no effect on operation.
21 of 38
DS17885/DS17887
EXTENDED CONTROL REGISTER 4B
MSB
LSB
BIT 0
KSE
BIT 7
ABE
BIT 6
E32K
BIT 5
CS
BIT 4
RCE
BIT 3
PRS
BIT 2
RIE
BIT 1
WIE
ABE - Auxiliary Battery Enable. This bit when written to a logic 1 will enable the VBAUX pin for
extended functions.
E32K - Enable 32.768 kHz output. This bit when written to a logic 1 will enable the 32.768 kHz
oscillator frequency to be output on the SQW pin. E32K is set to a one when VCC is powered up.
CS - Crystal Select Bit. When CS is set to a 0, the oscillator is configured for operation with a crystal
that has a 6 pF specified load capacitance. When CS=1, the oscillator is configured for a 12.5 pF crystal.
CS is disabled in the DS17887 module and should be set to CS=0.
RCE - RAM Clear Enable bit. When set to a 1, this bit enables a low level on RCLR to clear all
114 bytes of user RAM. When RCE = 0, RCLR and the RAM clear function are disabled.
PRS - PAB Reset Select Bit. When set to a 0 the PWR pin will be set hi-Z when the DS17885 goes into
power fail. When set to a 1, the PWR pin will remain active upon entering power fail.
RIE - Ram Clear Interrupt Enable. When RIE is set to a 1, the IRQ pin will be driven low when a RAM
clear function is completed.
WIE – Wake-up Alarm Interrupt Enable. When VCC voltage is absent and WIE is set to a 1, the PWR pin
will be driven active low when a wake-up condition occurs, causing the WF bit to be set to 1. When VCC
is then applied, the IRQ pin will also be driven low. If WIE is set while system power is applied, both
IRQ and PWR will be driven low in response to WF being set to 1. When WIE is cleared to a 0, the WF
bit will have no effect on the PWR or IRQ pins.
KSE - Kickstart Interrupt Enable. When VCC voltage is absent and KSE is set to a 1, the PWR pin will be
driven active low when a kickstart condition occurs ( KS pulsed low), causing the KF bit to be set to 1.
When VCC is then applied, the IRQ pin will also be driven low. If KSE is set to 1 while system power is
applied, both IRQ and PWR will be driven low in response to KF being set to 1. When KSE is cleared to
a 0, the KF bit will have no effect on the PWR or IRQ pins.
22 of 38
DS17885/DS17887
SYSTEM MAINTENANCE INTERRUPT (SMI) RECOVERY STACK
An SMI recovery register stack is located in the extended register bank, locations 4Eh and 4Fh. This
register stack, shown below, can be used by the BIOS to recover from an SMI occurring during an RTC
read or write.
The RTC address is latched on the falling edge of the ALE signal. Each time an RTC address is latched,
the register address stack is pushed. The stack is only four registers deep, holding the three previous RTC
addresses in addition to the current RTC address being accessed. The following waveform illustrates
how the BIOS could recover the RTC address when an SMI occurs.
1. The RTC address is latched.
2. An SMI is generated before an RTC read or write occurs.
3. RTC address 0Ah is latched and the address from "1" is pushed to the “RTC Address - 1” stack
location. This step is necessary to change the bank select bit, DV0=1.
4. RTC address 4Eh is latched and the address from “1” is pushed to location 4Eh, “RTC Address - 2”
while 0Ah is pushed to the “RTC Address - 1” location. The data in this register, 4Eh, is the RTC
address lost due to the SMI.
23 of 38
DS17885/DS17887
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Storage Temperature
-0.3V to +7.0V
-40°C to +85°C
Soldering Temperature
260°C for 10 seconds (DIP) See Note 13
See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
Operating Range
Range
Temperature
0°C to +70°C
-40°C to +85°C
VCC
Commercial
3V ± 10% or 5V ± 10%
3V ± 10% or 5V ± 10%
Industrial
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Over the operating range
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Power Supply Voltage 5-Volt
Operation
VCC
4.5
5.0
5.5
V
1
Power Supply Voltage 3-Volt
Operation
VCC
2.7
3.0
3.7
V
1
Input Logic 1
Input Logic 0
Battery Voltage
VIH
VIL
2.3
-0.3
2.5
2.5
VCC+0.3
0.6
V
V
V
V
1
1
1
1
VBAT
VBAUX
3.7
Auxiliary Battery Voltage;
VCC=5.0V
5.2
Auxiliary Battery Voltage;
VCC=3.0V
VBAUX
2.5
3.7
V
1
24 of 38
DS17885/DS17887
DC ELECTRICAL CHARACTERISTICS
Over the operating range (5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Average VCC Power Supply
Current
ICC1
25
50
mA
2,3
CMOS Standby Current
(CS =VCC-0.2V)
ICC2
IIL
1
3
mA
2,3
Input Leakage Current
(any input)
-1
+1
+1
µA
Output Leakage Current
IOL
-1
6
µA
Output Logic 1 Voltage
(IOUT = -1.0 mA)
VOH
2.4
V
Output Logic 0 Voltage
(IOUT = +2.1 mA)
VOL
0.4
4.5
V
Power Fail Trip Point
Battery Switch Voltage
VPF
4.25
-1
4.37
V
V
4
9
VSW
VBAT,
VBAUX
Battery Leakage OSC ON
Battery Leakage OSC OFF
I/O Leakage
IBAT1
IBAT2
ILO
0.50
0.7
0.4
12
12
5
µA
µA
µA
mA
0.050
+1
IOLPWR
10.0
1
PWR Output @ 0.4V
IRQ Output @ 0.4V
IOLIRQ
2.1
mA
1
25 of 38
DS17885/DS17887
DC ELECTRICAL CHARACTERISTICS
Over the operating range (3V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Average VCC Power Supply
Current
ICC1
15
30
mA
2,3
CMOS Standby Current
(CS =VCC-0.2V)
ICC2
IIL
0.5
2
mA
2,3
Input Leakage Current
(any input)
-1
+1
+1
µA
Output Leakage Current
IOL
-1
6
µA
Output Logic 1 Voltage
@ -0.4 mA
VOH
2.4
V
Output Logic 0 Voltage
@ +0.8 mA
VOL
0.4
V
Power Fail Trip Point
Battery Leakage OSC ON
Battery Leakage OSC OFF
I/O Leakage
VPF
IBAT1
IBAT2
ILO
2.5
-1
2.6
0.50
0.050
2.7
0.7
0.4
+1
4
V
4
12
12
5
µA
µA
µA
mA
IOLPWR
1
PWR Output @ 0.4V
IRQ Output @ 0.4V
IOLIRQ
0.8
mA
1
26 of 38
DS17885/DS17887
RTC AC TIMING CHARACTERISTICS
Over the operating range (3V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Cycle Time
tCYC
360
DC
ns
ns
PWRWL
200
Pulse Width, RD / WR Low
PWRWH
150
ns
Pulse Width, RD / WR High
Input Rise and Fall Time
tR, tF
tCS
30
90
ns
ns
Chip Select Setup Time
Before WR or RD
20
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
tCH
tDHR
tDHW
tASL
0
10
0
ns
ns
ns
ns
Muxed Address Valid Time to
ALE Fall
40
Muxed Address Hold Time to
ALE fall
tAHL
tASD
10
30
ns
ns
RD or WR High Setup to
ALE Rise
Pulse Width ALE High
PWASH
tASED
40
30
ns
ns
ALE Low Setup to RD
or WR Fall
Output Data Delay Time from
RD
tDDR
20
70
200
2
ns
7
Data Setup Time
tDSW
tIRD
ns
µs
IRQ Release from RD
AC TEST CONDITIONS
Output Load: 50 pF
Input Pulse Levels: 0-3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
27 of 38
DS17885/DS17887
RTC AC TIMING CHARACTERISTICS
Over the operating range (5V)
PARAMETER
Cycle Time
SYMBOL
MIN
TYP
MAX
UNITS NOTES
tCYC
PWRWL
240
120
DC
ns
ns
Pulse Width, RD / WR Low
PWRWH
80
ns
Pulse Width, RD / WR High
Input Rise and Fall Time
Chip Select Setup Time
Before WR or RD
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
tR, tF
tCS
30
50
ns
ns
20
tCH
tDHR
tDHW
tASL
0
10
0
ns
ns
ns
ns
Muxed Address Valid Time to
20
ALE Fall
Muxed Address Hold Time to
ALE fall
tAHL
tASD
10
25
ns
ns
RD or WR High Setup to
ALE Rise
Pulse Width ALE High
PWASH
tASED
40
30
ns
ns
ALE Low Setup to RD
or WR Fall
Output Data Delay Time from
RD
tDDR
20
30
120
2
ns
7
Data Setup Time
tDSW
tIRD
ns
µs
IRQ Release from RD
AC TEST CONDITIONS
Output Load: 50 pF
Input Pulse Levels: 0-3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
28 of 38
DS17885/DS17887
DS17885/DS17887 BUS TIMING FOR READ CYCLE TO RTC AND RTC
REGISTERS
DS17885/DS17887 BUS TIMING FOR WRITE CYCLE TO RTC AND RTC
REGISTERS
29 of 38
DS17885/DS17887
POWER-UP POWER-DOWN TIMING 5-VOLT DEVICE
(tA=25°C)
PARAMETER
CS High to Power-Fail
Recovery at Power-up
VCC Slew Rate Power-down
SYMBOL
MIN
TYP
MAX
UNITS NOTES
tPF
0
ns
tREC
tF
150
ms
µs
300
10
0
4.0≤ VCC ≤ 4.5V
VCC Slew Rate Power-down
VCC Slew Rate Power-up
Expected Data Retention
tFB
3.0≤ VCC ≤ 4.0V
tR
µs
µs
≥
≥
4.5 VCC 4.0V
tDR
10
years
10,11
POWER-UP POWER-DOWN TIMING 3 VOLT DEVICE
(tA=25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
tPF
0
ns
CS High to Power-Fail
Recovery at Power-up
tREC
150
ms
VCC Slew Rate Power-down
tF
300
0
µs
2.5≤ VCC ≤ 3.0V
VCC Slew Rate Power-up
tR
µs
≥
≥
3.0 VCC 2.5V
Expected Data Retention
tDR
10
years
10,11
Warning:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
back-up mode.
CAPACITANCE
PARAMETER
(tA=25°C)
UNITS NOTES
SYMBOL
CIN
MIN
TYP
TYP
MAX
12
12
Input Capacitance
Output Capacitance
pF
pF
COUT
WAKE-UP/KICKSTART TIMING
(tA=25°C)
UNITS NOTES
µs
PARAMETER
SYMBOL
tKSPW
tPOTO
MIN
MAX
Kickstart Input Pulse width
Wake-up/Kickstart Power On
Timeout
2
2
seconds
8
30 of 38
DS17885/DS17887
POWER-UP CONDITION 3 VOLT DEVICE
POWER-DOWN CONDITION 3 VOLT DEVICE
31 of 38
DS17885/DS17887
POWER-UP CONDITION 5.0 VOLT DEVICE
POWER-DOWN CONDITION 5.0 VOLT DEVICE
32 of 38
DS17885/DS17887
WAKE-UP/KICKSTART TIMING
NOTE:
Time intervals shown above are referenced in Wake-up/Kickstart section.
* This condition can occur with the 3-volt device.
33 of 38
DS17885/DS17887
BURST MODE TIMING WAVEFORM
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Write protection trip point occurs during power fail prior to switchover from VCC to VBAT
5. Applies to the AD0-AD7 pins, and the SQW pin when each is in a high impedance state.
6. The IRQ and PWR pins are open drain.
.
7. Measured with a load of 50 pF + 1 TTL gate.
8. Wakeup kickstart timeout generated only when the oscillator is enabled and the countdown chain is
not reset.
9. VSW is determined by the larger of VBAT and VBAUX
.
10. The DS17887 will keep time to an accuracy of ±1 minute per month during data retention time for
the period of tDR.
11. tDR is the amount of time that the internal battery can power the internal oscillator and internal
registers of the DS17887.
12. IBAT1 and IBAT2 are measured at VBAT = 3.5V.
13. Real Time Clock Modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
34 of 38
DS17885/DS17887
DS17885 24-PIN DIP
PKG
DIM
A IN
MM
B IN
MM
C IN
MM
D IN
MM
E IN
MM
F IN
MM
G IN
MM
H IN
MM
J IN
MM
K IN
MM
24-PIN
MIN
1.245
31.62
0.530
13.46
0.140
3.56
MAX
1.270
32.25
0.550
13.97
0.160
4.06
0.600
15.24
0.015
0.380
0.120
3.05
0.625
15.88
0.050
1.27
0.145
3.68
0.090
2.29
0.110
2.79
0.625
15.88
0.008
0.20
0.675
17.15
0.012
0.30
0.015
0.38
0.022
0.56
35 of 38
DS17885/DS17887
DS17885 24-PIN SOIC
The chamfer on the body is optional. If it is not present, a terminal 1 identifier must be positioned so that
½ or more of its area is contained in the hatched zone.
PKG
DIM
A IN
MM
A1 IN
MM
A2 IN
MM
b IN
MM
C IN
MM
D IN
MM
e IN
MM
E1 IN
MM
H IN
MM
L IN
MM
Θ
24-PIN
MIN
0.094
2.38
0.004
0.102
0.089
2.26
0.013
0.33
0.009
0.229
0.598
15.19
MAX
0.105
2.68
0.012
0.30
0.095
2.41
0.020
0.51
0.013
0.33
0.612
15.54
0.050 BSC
1.27 BSC
0.290
0.300
7.62
0.416
10.57
0.040
1.02
8°
7.37
0.398
10.11
0.016
0.40
0°
36 of 38
DS17885/DS17887
DS17885 28-PIN TSOP
PKG
28-PIN
DIM
MIN
-
MAX
1.20
-
1.02
0.27
0.20
13.60
11.90
8.10
A
0.05
0.91
0.18
0.15
13.20
11.70
7.90
A1
A2
b
c
D
D1
E
0.55 BSC
0.30 0.70
0.80 BSC
e
L
L1
56-G5003-000
37 of 38
DS17885/DS17887
DS17887 REAL TIME CLOCK PLUS RAM
NOTE:
Pins 2, 3, 16 and 20 are missing by design.
PKG
DIM
A IN
MM
B IN
MM
C IN
MM
D IN
MM
E IN
MM
F IN
MM
G IN
MM
H IN
MM
J IN
MM
K IN
MM
24-PIN
MIN
1.320
33.53
0.720
18.29
0.345
8.76
MAX
1.335
33.91
0.740
18.80
0.370
9.40
0.100
2.54
0.130
3.30
0.015
0.38
0.030
0.76
0.100
2.79
0.140
3.56
0.110
2.79
0.630
16.00
0.012
0.30
0.021
0.53
0.090
2.29
0.590
14.99
0.008
0.20
0.015
0.38
38 of 38
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