DS1845E-010 [DALLAS]

Dual NV Potentiometer and Memory; 双路，非易失电位器和存储器


型号：	DS1845E-010
厂家：	DALLAS SEMICONDUCTOR
描述：	Dual NV Potentiometer and Memory 双路，非易失电位器和存储器转换器电位器数字电位计存储光电二极管
文件：	总13页 (文件大小：102K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS1845

Dual NV Potentiometer and Memory

www.dalsemi.com

FEATURES

PIN ASSIGNMENT

ꢀ Two linear taper potentiometers

− DS1845-010 one 10k, 100 position &

one 10k, 256 position

SDA

SCL

Vcc

− DS1845-050 one 10k, 100 position &

one 50k, 256 postition

− DS1845-100 one 10k, 100 position &

one 100k, 256 position

GND

ꢀ 256 bytes of EEPROM memory

ꢀ Access to data and potentiometer control via

a 2-wire interface

ꢀ External Write Enable pin to protect data and

potentiometer settings

14-Pin TSSOP (173 mil)

14-Pin Flip Chip (100 x 100 mils)

16-BALL STPBGA (4 x 4 mm)

See Mech. Drawing Section

ꢀ Nonvolatile wiper storage in 2 bytes of

address space

ꢀ Operates from 3V or 5V supplies

ꢀ Packaging: Flip Chip Package, 16-ball

STPBGA, 14-pin TSSOP

ꢀ Industrial operating temperature: -40ºC to

+85ºC

PIN DESCRIPTION

V_CC

- 3V or 5V Power Supply Input

GND

SDA

- Ground

- 2-wire Serial Data

Input/Output

ꢀ Programming temperature: 0ºC to +70ºC

SCL

- 2-wire Serial Clock Input

- Write Protect Input

A0, A1, A2 - Address Inputs

H0, H1

L 0, L1

W0, W1

- High-End of Potentiometer

- Low-End of Potentiometer

- Wiper Terminal of

Potentiometer

DESCRIPTION

The DS1845 Dual NV Potentiometer and Memory consists of one=100-position linear taper

potentiometer, one=256-position linear taper potentiometer, 256 bytes of EEPROM memory, and a 2-wire

interface. The device provides an ideal method for setting bias voltages and currents in control

applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration

or calibration data for a specific system or device as well as provide control of the potentiometer wiper

settings. Any type of user information may reside in the first 248 bytes of this memory. The next two

addresses of EEPROM memory are for potentiometer settings and the remaining 6 bytes of memory are

reserved. These reserved and potentiometer registers should not be used for data storage. Access to this

EEPROM is via an industry standard 2-wire bus. The interface I/O pins consist of SDA and SCL. The

wiper position of the DS1845, as well as EEPROM data, can be hardware write-protected using the Write

Protect (WP) input pin.

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051900

DS1845

DS1845 BLOCK DIAGRAM Figure 1

248 BYTES

VCC

GND

EEPROM

MEMORY

2-WIRE

INTERFACE

POTENTIOMETER 0

6 RESERVED

BYTES

CONTROL

SDA

100

Position

Pot

SCL

1 BYTE WIPER

SETTING

POT 0

DATA

POTENTIOMETER 1

1 BYTE WIPER

SETTING

POT 1

256

Position

Pot

Up to eight DS1845s can be installed on a single 2-wire bus. Access to an individual device is achieved

by using a device address that is determined by the logic levels of address pins A0 though A2.

Additionally, the DS1845 will operate from 3 volt or 5 volt supplies. Three package options are

available: Flip Chip Package, 16-ball STPBGA and 14-pin TSSOP.

PIN DESCRIPTIONS

V_CC- Power Supply Terminal. The DS1845 will support supply voltages ranging from +2.7 to +5.5 volts.

GND - Ground Terminal.

SDA - 2-wire serial data interface. The serial data pin is for serial data transfer to and from the DS1845.

The pin is open drain and may be wire-ORed with other open drain or open collector interfaces.

SCL - 2-wire serial clock interface. The serial clock input is used to clock data into the DS1845 on rising

edges and clock data out on falling edges.

WP - Write Protect. Write Protect must be connected to GND before either the data in memory or

potentiometer wiper settings may be changed. Write Protect is pulled high internally and must be either

left open or connected to V_CCif write protection is desired.

A0, A1, A2 - Address Inputs. These input pins specify the address of the device when used in a multi-

dropped configuration. Up to eight individual DS1845s may be addressed on a single 2-wire bus.

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DS1845

H0, H1 – These are the high-end terminals of the potentiometers. For both potentiometers, it is not

required that these terminals be connected to a potential greater than the low-end terminal of the

potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power supply

voltage, V_CC, or go below ground.

L0, L1 – These are the low-end terminals of the potentiometers. It is not required that these terminals be

connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the

potentiometers cannot exceed the power-supply voltage, V_CC, or go below ground.

W0, W1 - Wiper of the Potentiometer. This pin is the wiper terminal of the potentiometer. The bytes in

EEPROM memory locations F8h and F9h determine each wiper’s setting. Voltage applied to either

wiper terminal cannot exceed the power-supply voltage, V_CC, or go below ground.

MEMORY ORGANIZATION

The DS1845’s serial EEPROM is internally organized with 256 words of 1 byte each. Each word requires

an 8-bit address for random word addressing. The byte at address F9h determines the wiper setting for

potentiometer 0, which contains 100 positions. Writing values above 63h to this address sets the wiper to

its uppermost position. The byte at address F8h determines the wiper setting for potentiometer 1, which

contains 256 positions (00h to FFh). Address locations FAh though FFh are reserved and should not be

written.

DEVICE OPERATION

Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device.

Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high

periods will indicate a start or stop conditions depending on the conditions discussed below. Refer to the

timing diagram Fig 2 for further details.

Start Condition: A high-to-low transition of SDA with SCL high is a start condition which must

precede any other command. Refer to the timing diagram Fig 2 for further details.

Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read

sequence, the stop command places the DS1845 into a low-power mode. Refer to the timing diagram Fig

2 for further details.

Acknowledge: All address and data byte are transmitted via a serial protocol. The DS1845 pulls the

SDA line low during the ninth clock pulse to acknowledge that it has received each word.

Standby Mode: The DS1845 features a low-power mode that is automatically enabled after power-on,

after a stop command, and after the completion of all internal operations.

2-Wire Interface Reset: After any interruption in protocol, power loss, or system reset, the following

steps reset the DS1845.

1. Clock up to nine cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition while SDA is high.

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DS1845

Device Addressing: The DS1845 must receive an 8-bit device address word following a start condition

to enable a specific device for a read or write operation. The address word is clocked into the DS1845

MSB to LSB. The address word consists of Ah (1010) followed by A2, A1, and A0 then the R/W

(READ/WRITE) bit. If the R/W bit is high, a read operation is initiated. The R/W is low, a write

operation is initiated. For a device to become active, the values of A2, A1 and A0 must be the same as

the hard-wired address pins on the DS1845. Upon a match of written and hard-wired addresses, the

DS1845 will output a zero for one clock cycle as an acknowledge. If the address does not match the

DS1845 returns to a low-power mode.

Write Operations: After receiving a matching address byte with the R/W bit set low, the device goes

into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the

device to define the address where the data is to be written. After the reception of this byte, the DS1845

will transmit a zero for one clock cycle to acknowledge the receipt of the address. The master must then

transmit an 8-bit data word to be written into this address. The DS1845 will again transmit a zero for one

clock cycle to acknowledge the receipt of the data. At this point the master must terminate the write

operation with a stop condition. The DS1845 then enters an internally timed write process T_wto the

EEPROM memory. All inputs are disabled during this byte write cycle.

The DS1845 is capable of an 8-byte page write. A page write is initiated the same way as a byte write,

but the master does not send a stop condition after the 1^stbyte. Instead, after the slave acknowledges

receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence.

The master must terminate the write cycle with a stop condition or the data clocked into the DS1845 will

not be latched into permanent memory.

Acknowledge Polling: Once the internally-timed write has started and the DS1845 inputs are disabled,

acknowledge polling can be initiated. The process involves transmitting a start condition followed by the

device address. The R/W bit signifies the type of operation that is desired. The read or write sequence

will only be allowed to proceed if the internal write cycle has completed and the DS1845 responds with a

zero.

Read Operations: After receiving a matching address byte with the R/W bit set high, the device goes

into the read mode of operation. There are three read operations: current address read, random read and

sequential address read.

CURRENT ADDRESS READ

The DS1845 has an internal address register that maintains the address used during the last read or write

operation, incremented by one. This data is maintained as long as V_CCis valid. If the most recent

address was the last byte in memory, then the register resets to the first address. This address stays valid

between operations as long as power is available.

Once the device address is clocked in and acknowledged by the DS1845 with the R/W bit set to high, the

current address data word is clocked out. The master does not respond with a zero, but does generate a

stop condition afterwards.

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DS1845

RANDOM READ

A random read requires a dummy byte write sequence to load in the data word address. Once the device

and data address bytes are clocked in by the master, and acknowledged by the DS1845, the master must

generate another start condition. The master now initiates a current address read by sending the device

address with the read/write bit set high. The DS1845 will acknowledge the device address and serially

clocks out the data byte.

SEQUENTIAL ADDRESS READ

Sequential reads are initiated by either a current address read or a random address read. After the master

receives the first data byte, the master responds with an acknowledge. As long as the DS1845 receives

this acknowledge after a byte is read, the master may clock out additional data words from the DS1845.

After reaching address FFh, it resets to address 00h.

The sequential read operation is terminated when the master initiates a stop condition. The master does

not respond with a zero.

For a more detailed description of 2-wire theory of operation, refer to the following section.

2-WIRE SERIAL PORT OPERATION

The 2-wire serial port interface supports a bi-directional data transmission protocol with device

addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as

a receiver. The device that controls the message is called a “master.” The devices that are controlled by

the master are “slaves.” The bus must be controlled by a master device that generates the serial clock

(SCL), controls the bus access, and generates the START and STOP conditions. The DS1845 operates as

a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2. Timing diagrams for

the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is

provided in the AC Electrical Characteristics table for 2-wire serial communications.

The following bus protocol has been defined:

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH

defines a START condition.

Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is

HIGH defines the STOP condition.

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DS1845

Data valid: The state of the data line represents valid data when, after a START condition, the data line

is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed

during the LOW period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3

detail how data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit,

two types of data transfer are possible.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9^th

bit.

Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)

are defined. The DS1845 works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse which is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is a stable LOW during the HIGH period of the acknowledge related clock pulse.

Of course, setup and hold times must be taken into account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

1. Data transfer from a master transmitter to a slave receiver. The 1^stbyte transmitted by the master is

the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit

after each received byte.

2. Data transfer from a slave transmitter to a master receiver. The master transmits the 1^stbyte (the

command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a

number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit

after all received bytes other than the last byte. At the end of the last received byte, a ‘not

acknowledge’ can be returned.

The master device generates all serial clock pulses and the START and STOP conditions. A transfer is

ended with a STOP condition or with a repeated START condition. Since a repeated START condition is

also the beginning of the next serial transfer, the bus will not be released.

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DS1845

The DS1845 may operate in the following two modes:

1. Slave receiver mode: Serial data and clock are received through SDA and SCL respectively. After

each byte is received, an acknowledge bit is transmitted. START and STOP conditions are

recognized as the beginning and end of a serial transfer. Address recognition is performed by

hardware after reception of the slave (device) address and direction bit.

2. Slave transmitter mode: The 1^stbyte is received and handled as in the slave receiver mode. However,

in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is

transmitted on SDA by the DS1845 while the serial clock is input on SCL. START and STOP

conditions are recognized as the beginning and end of a serial transfer.

3. Slave Address: command/control byte is the 1^stbyte received following the START condition from

the master device. The command/control byte consists of a 4-bit control code. For the DS1845, this is

set as 1010 binary for read/write operations. The next 3 bits of the command/ control byte are the

device select bits or slave address (A2, A1, A0). They are used by the master device to select which

of eight devices is to be accessed. When reading or writing the DS1845, the device-select bits must

match the device-select pins (A2, A1, A0). The last bit of the command/control byte (R/W) defines

the operation to be performed. When set to a 1 a read operation is selected, and when set to a 0 a write

operation is selected.

Following the START condition, the DS1845 monitors the SDA bus checking the device type identifier

being transmitted. Upon receiving the 1010 control code, the appropriate device address bits, and the

read/write bit, the slave device outputs an acknowledge signal on the SDA line.

WRITE PROTECT

An external pin WP (write protect) protects EEPROM data and potentiometer position from alteration in

an application. This pin must be open or tied high to protect data from alteration.

READING AND WRITING THE POTENTIOMETER VALUES

Reading from and writing to the potentiometers consists of a standard read or write to EEPROM memory

at the addresses F8h and F9h. The 8-bit value at address F9h controls the wiper setting for potentiometer

0, which has 100 positions. The 8-bit value at address F8h controls the wiper setting of potentiometer 1,

which has 256 positions. Potentiometer 1 may be set to any value between 00h and FFh. 00h sets the

wiper of potentiometer 1 to its lowest value and FFh sets the wiper to its highest. Potentiometer 0 may be

set to any value between 00h and 63h. A value of 00h sets the wiper of potentiometer 0 to its lowest

position and 63h sets the wiper to its highest position. Any hexadecimal value is a valid address. Setting

a value greater than the upper limit of the potentiometer’s range, 64h or greater for potentiometer 0, will

result in setting the wiper to its highest position, but the MSB will be ignored.

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DS1845

2- WIRE PROTOCOL DATA TRANSFER PROTOCOL Figure 2

2-WIRE AC CHARACTERISTICS Figure 3

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DS1845

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

Operating Temperature

-1.0V to +6.0V

-40°C to +85°C; Industrial

0°C to +70°C

Programming Temperature

Storage Temperature

-55°C to +125°C

Soldering Temperature

See J-STD-020A specification

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(-40°C to +85°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

5.5

UNITS

NOTES

Supply Voltage

V_CC

+2.7

Input Logic 1

Input Logic 0

Resistor Inputs

V_IH

.7 V_CC

V_CC+0.5

.3 V_CC

V_CC+0.5

1,3

V_IL

GND-0.5

1,3

L,H,W

1,19

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DS1845

DC ELECTRICAL CHARACTERISTICS

(-40°C to +85°C; V_CC=2.7V to 5.5V)

PARAMETER

SYMBOL CONDITION

MIN

TYP

MAX

UNITS NOTES

Supply Current

Active

I_CC

0.5

16,17

Input Leakage

Wiper Resistance

I_LI

-1

µA

R_W

Ω

500

250

1000

500

Wiper Current

Input Logic 1

Input Logic 0

I_W

V_IH

0.7 V_CC

GND-0.5

0.7 V_CC

V_CC+0.5

0.3 V_CC

V_CC+0.5

0.3 V_CC

+10

1,2

V_IL

Input Logic levels

A0, A1, A2

Input Logic 1

Input Logic 0 GND-0.5

0.4<V_I/O

<0.9V_DD

Input Current each

I/O pin

-10

µA

I_stby

Standby Current

Low Level Output

Voltage (SDA)

V_OL1

V_OL2

3 mA sink

current

0.0

0.4

0.6

6 mA sink

current

I/O Capacitance

C_I/O

t_SP

Pulse width of spikes

which must be

Fast Mode

suppressed by the

input filter

WP Internal Pull Up

Resistance, R_wp

R_wp

100

kΩ

ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C; V_CC=2.7V to 5.5V)

PARAMETER

SYMBOL CONDITION

MIN

TYP

MAX

UNITS NOTES

End-to-End

-20

+20

Resistance

Absolute Linearity

Relative Linearity

-0.5

+0.5

LSB

kHz

-0.25

+0.25

-3 dB Cutoff

frequency

f_cutoff

ppm/°C

Temperature

Coefficient

750

10 of 13

DS1845

AC ELECTRICAL CHARACTERISTICS

(-40 C to 85 C, Vcc=2.7V to 5.5V)

PARAMETER

SYMBOL CONDITION MIN

TYP MAX UNITS NOTES

SCL clock frequency

400

100

kHz

*,6

SCL

Bus free time between

STOP and START

condition

1.3

4.7

*,6

µs

BUF

Hold time (repeated)

START condition

Low period of SCL clock

0.6

4.0

1.3

4.7

0.6

4.0

*,7,6

*,6

*,6,8

*,6

*,9

µs

HD:STA

LOW

High period of SCL clock

Data hold time

HIGH

0.9

HD:DAT

Data set-up time

100

250

0.6

4.7

20+0.1

SU:DAT

Start set-up time

µs

SU:STA

Rise time of both SDA

and SCL signals

300

1000

Fall time of both SDA

and SCL signals

20+0.1

300

*,9

Set-up time for STOP

condition

Capacitive load for each

bus line

EEPROM write time

* fast mode

0.6

4.0

µs

SU:STO

400

T_W

** standard mode

NOTES:

1. All voltages are referenced to ground.

2. I_STBYspecified with for V_CCequal 3.0V and 5.0V and control port logic pins are driven to the

appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of

ground or V_CCfor the corresponding inactive state.

3. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V_CCis switched off.

4. Address Inputs, A0, A1, and A2, should be tied to either V_CCor GND depending on the desired

address selections.

5. I_STBYspecified with for V_CCequal 3.0V and 5.0V and control port logic pins are driven to the

appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of

ground or V_CCfor the corresponding inactive state.

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DS1845

6. A fast mode device can be used in a standard mode system, but the requirement t

SU:DAT

> 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the

next data bit to the SDA line t_RMAX+ t

= 1000 + 250 = 1250 ns before the SCL line is

SU:DAT

released.

7. After this period, the first clock pulse is generated.

8. The maximum t

the SCL signal.

has only to be met if the device does not stretch the LOW period (t

LOW

) of

HD:DAT

9. C - total capacitance of one bus line in picofarads, timing referenced to (0.9(V ) and (0.1)(V ).

10. EEPROM write begins after a stop condition occurs.

11. Resistor inputs can not go beneath GND by more than 0.5V or above V_CCby more that 0.5V.

12. The –3 dB cutoff frequency for the DS1845 is 1 MHz (10k/10k version).

13. Absolute linearity is used to measure expected wiper voltage as determined by wiper position. The

DS1845 is specified to provide an absolute linearity of ± 0.5 LSB (10k/10k version), ±1 LSB(10k/50k

version), and ± 1.5 LSB (10k/100k) version.

14. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper

positions. The DS1845 is specified to have a relative linearity of ± 0.25 dB.

15. When used as a rheostat or variable resister the temperature coefficient applies: 650 ppm/°C. When

used as a voltage divider or potentiometer, the effective temperature coefficient approaches

30 ppm/°C.

16. I_CCspecified with SDA pin open.

17. Maximum Icc is dependent on clock rates.

18. Valid for V_CC= 5V only.

19. Valid at 25°C only.

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DS1845

ORDERING INFORMATION

ORDERING

NUMBER

DS1845E-010

DS1845E-010/T&R

DS1845X-010

DS1845B-010

PACKAGE

ORERATING

TEMPERATURE

-40ºC TO +85ºC

VERSION

Pot 0/Pot 1

10 kΩ/10 kΩ

10 kΩ/50 kΩ

10 kΩ/100 kΩ

14 PIN TSSOP (173 MIL)

14 PIN TSSOP/TAPE & REEL

14 PIN FLIP CHIP

16 BALL STPBGA (4X4 MM)

14 PIN TSSOP (173 MIL)

14 PIN TSSOP/TAPE & REEL

14 PIN FLIP CHIP

16 BALL STPBGA (4X4 MM)

14 PIN TSSOP (173 MIL)

14 PIN TSSOP/TAPE & REEL

14 PIN FLIP CHIP

DS1845E-050

DS1845E-050/T&R

DS1845X-050

DS1845B-050

DS1845E-100

DS1845E-100/T&R

DS1845X-100

DS1845B-100

16 BALL STPBGA (4X4 MM)

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DS1845E-010 [DALLAS]

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