DS21Q44T [DALLAS]
Enhanced QUAD E1 FRAMER; 增强型四E1成帧器
| 型号： | DS21Q44T |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Enhanced QUAD E1 FRAMER |
| 文件： | 总105页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS21Q44
Enhanced QUAD E1 FRAMER
www.dalsemi.com
FEATURES
FUNCTIONAL DIAGRAM
ꢀ Four E1 (CEPT or PCM-30) /ISDN-PRI
framing transceivers
ꢀ All four framers are fully independent;
transmit and receive sections of each framer
are fully independent
Elastic
Store
Receive
Framer
Elastic
Store
Transmit
Formatter
ꢀ
Frames to FAS, CAS, CCS, and CRC4 formats
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
ꢀ Each of the four framers contain dual two–
frame elastic store slip buffers that can
connect to asynchronous backplanes up to
8.192 MHz
Control Port
ꢀ 8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
ꢀ Easy access to Si and Sa bits
ꢀ Extracts and inserts CAS signaling
ꢀ Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
ACTUAL SIZE
QUAD
E1
FRAMER
ꢀ Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
ORDERING INFORMATION
DS21Q44T (00 C to 700 C)
ꢀ
Integral HDLC controller with 64-byte buffers
configurable for Sa bits or DS0 operation
DS21Q44TN
(-400 C to +850 C)
ꢀ Detects and generates AIS, remote alarm,
and remote multiframe alarms
ꢀ Pin compatible with DS21Q42 Enhanced
Quad T1 Framer
ꢀ 3.3V supply with 5V tolerant I/O; low power
CMOS
ꢀ Available in 128–pin TQFP package
ꢀ IEEE 1149.1 support
DESCRIPTION
The DS21Q44 E1 is an enhanced version of the DS21Q43 Quad E1 Framer. The DS21Q44 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q44 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, and
I.431 as well as ETS 300 011 and ETS 300 233.
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031600
DS21Q44
1. INTRODUCTION
The DS21Q44 is a superset version of the popular DS21Q43 Quad E1 framer offering the new features
listed below. All of the original features of the DS21Q43 have been retained and software created for the
original device is transferable to the DS21Q44.
New Features
ꢀ Additional hardware signaling capability including:
– receive signaling reinsertion to a backplane multiframe sync
– availability of signaling in a separate PCM data stream
– signaling freezing
– interrupt generated on change of signaling data
ꢀ Per–channel code insertion in both transmit and receive paths
ꢀ Full HDLC controller with 64–byte buffers in both transmit and receive paths. Configurable for Sa
bits or DS0 access
ꢀ RCL, RLOS, RRA, and RUA1 alarms now interrupt on change of state
ꢀ 8.192 MHz clock synthesizer
ꢀ Ability to monitor one DS0 channel in both the transmit and receive paths
ꢀ Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233
ꢀ Automatic RAI generation to ETS 300 011 specifications
ꢀ IEEE 1149.1 support
Functional Description
The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as
detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If
needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz
clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side in each framer is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission.
Reader’s Note:
This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 us frame,
there are 32 eight–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first. These
32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical
to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made up of
eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS
CAS
MF
Si
Frame Alignment Signal
Channel Associated Signaling
Multiframe
CRC4
CCS
Sa
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
International bits
E-bit
CRC4 Error Bits
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DS21Q44
DS21Q44 ENHANCED QUAD E1 FRAMER Figure 1-1
3 of 105
DS21Q44
TABLE OF CONTENTS
1. INTRODUCTION .............................................................................................................................. 2
2. DS21Q44 PIN DESCRIPTION ......................................................................................................... 7
3. DS21Q44 PIN FUNCTION DESCRIPTION ................................................................................ 13
4. DS21Q44 REGISTER MAP............................................................................................................. 20
5. PARALLEL PORT........................................................................................................................... 24
6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 24
7. STATUS AND INFORMATION REGISTERS............................................................................. 34
8. ERROR COUNT REGISTERS....................................................................................................... 40
9. DS0 MONITORING FUNCTION................................................................................................... 43
10. SIGNALING OPERATION ............................................................................................................ 45
10.1 PROCESSOR BASED SIGNALING........................................................................................ 45
10.2 HARDWARE BASED SIGNALING........................................................................................ 48
11. PER–CHANNEL CODE GENERATION AND LOOPBACK ................................................... 49
11.1 TRANSMIT SIDE CODE GENERATION............................................................................... 49
11.1.1 Simple Idle Code Insertion and Per-Channel Loopback................................................... 49
11.1.2 Per-Channel Code Insertion.............................................................................................. 50
11.2 RECEIVE SIDE CODE GENERATION .................................................................................. 51
12. CLOCK BLOCKING REGISTERS............................................................................................... 52
13. ELASTIC STORES OPERATION ................................................................................................ 53
13.1 RECEIVE SIDE......................................................................................................................... 54
13.2 TRANSMIT SIDE ..................................................................................................................... 54
14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................... 54
14.1 HARDWARE SCHEME ........................................................................................................... 54
14.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME..................................... 55
14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME............................... 57
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DS21Q44
15. HDLC CONTROLLER FOR THE SA BITS OR DS0 ................................................................. 59
15.1 GENERAL OVERVIEW........................................................................................................... 59
15.2 HDLC STATUS REGISTERS .................................................................................................. 60
15.3 BASIC OPERATION DETAILS............................................................................................... 61
15.4 HDLC REGISTER DESCRIPTION.......................................................................................... 62
16. INTERLEAVED PCM BUS OPERATION ................................................................................... 69
17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 72
17.1 DESCRIPTION.......................................................................................................................... 72
17.2 TAP CONTROLLER STATE MACHINE................................................................................ 73
17.3 INSTRUCTION REGISTER AND INSTRUCTIONS ............................................................. 75
17.4 TEST REGISTERS.................................................................................................................... 77
18. TIMING DIAGRAMS...................................................................................................................... 82
19. OPERATING PARAMETERS ...................................................................................................... 92
20. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 105
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DS21Q44
DOCUMENT REVISION HISTORY
Revision Notes
12-22-98
Initial Release
6 of 105
DS21Q44
2. DS21Q44 PIN DESCRIPTION
Pin Description Sorted by Pin Number Table 2-1
PIN
SYMBOL
TYPE DESCRIPTION
1
2
3
4
5
6
7
8
9
TCHBLK0
TPOS0
O
O
O
O
O
I
Transmit Channel Block from Framer 0
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 0
Receive Link Data from Framer 0
Receive Link Clock from Framer 0
Receive Clock for Framer 0
Receive Bipolar Data for Framer 0
Receive Bipolar Data for Framer 0
Receive Signaling Output from Framer 0
[Receive Channel Clock from Framer 0]
Receive Channel Block from Framer 0
Receive System Clock for Elastic Store in Framer 0
Receive Sync for Framer 0
Receive Serial Data from Framer 0
Signal Ground
Positive Supply Voltage
RESERVED - must be left unconnected for normal operation
[Receive Multiframe Sync from Framer 0]
Receive Frame Sync from Framer 0
JTAG Reset
[Receive Loss of Sync/Loss of Transmit clock from Framer 0]
Transmit Clock for Framer 0
Transmit Link Clock from Framer 0
Transmit Sync for Framer 0
Transmit Link Data for Framer 0
Address Bus Bit 0; LSB
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
TNEG0
RLINK0
RLCLK0
RCLK0
RNEG0
RPOS0
I
I
RSIG0
O
[O]
O
I
I/O
O
-
[RCHCLK0]
RCHBLK0
RSYSCLK0
RSYNC0
RSER0
10
11
12
13
14
15
16
VSS
VDD
-
-
SPARE1
[RMSYNC0]
RFSYNC0
JTRST*
[RLOS/LOTC0]
TCLK0
TLCLK0
TSYNC0
TLINK0
A0
[O]
O
I
[O]
I
O
I/O
I
I
I
17
18
19
20
21
22
23
24
25
26
27
28
29
A1
A2
A3
A4
I
I
I
I
A5
Address Bus Bit 5
Address Bus Bit 6; MSB or Address Latch Enable (Address
Strobe)
A6/ALE (AS)
I
30
31
32
33
34
INT*
TSYSCLK1
TSER1
TSSYNC1
TSIG1
[TCHCLK1]
TCHBLK1
TPOS1
O
I
I
I
I
[O]
O
O
O
Receive Alarm Interrupt for all Four Framers
Transmit System Clock for Elastic Store in Framer 1
Transmit Serial Data for Framer 1
Transmit Sync for Elastic Store in Framer 1
Transmit Signaling Input for Framer 1
[Transmit Channel Clock from Framer 1]
Transmit Channel Block from Framer 1
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 1
35
36
37
TNEG1
7 of 105
DS21Q44
PIN
SYMBOL
TYPE DESCRIPTION
38
39
40
41
42
43
RLINK1
RLCLK1
RCLK1
RNEG1
RPOS1
O
O
I
I
I
O
[O]
O
I
I
I
Receive Link Data from Framer 1
Receive Link Clock from Framer 1
Receive Clock for Framer 1
Receive Bipolar Data for Framer 1
Receive Bipolar Data for Framer 1
Receive Signaling output from Framer 1
[Receive Channel Clock from Framer 1]
Receive Channel Block from Framer 1
Receive System Clock for Elastic Store in Framer 1
Address Bus Bit 7
RSIG1
[RCHCLK1]
RCHBLK1
RSYSCLK1
A7
FMS
RSYNC1
RSER1
44
45
46
47
48
49
50
Framer Mode Select
Receive Sync for Framer 1
Receive Serial Data from Framer 1
JTAG Test Mode Select
I/O
O
I
JTMS
[RMSYNC1]
RFSYNC1
JTCLK
[O]
O
I
[Receive Multiframe Sync from Framer 1]
Receive Frame Sync from Framer 1
JTAG Test Clock
51
52
[RLOS/LOTC1]
TCLK1
[O]
I
O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
[O]
O
O
O
O
O
I
[Receive Loss of Sync/Loss of Transmit clock from Framer 1]
Transmit Clock for Framer 1
Transmit Link Clock from Framer 1
Transmit Sync for Framer 1
Transmit Link Data for Framer 1
3-state Control for all Output and I/O Pins
Framer Select 0 for Parallel Control Port
Framer Select 1 for Parallel Control Port
Chip Select
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TLCLK1
TSYNC1
TLINK1
TEST
FS0
FS1
CS*
BTS
Bus Type Select for Parallel Control Port
Read Input (Data Strobe)
Write Input (Read/Write)
RD*/(DS*)
WR*/(R/W*)
MUX
TSYSCLK2
TSER2
TSSYNC2
TSIG2
[TCHCLK2]
TCHBLK2
TPOS2
Non-Multiplexed or Multiplexed Bus Select
Transmit System Clock for Elastic Store in Framer 2
Transmit Serial Data for Framer 2
Transmit Sync for Elastic Store in Framer 2
Transmit Signaling Input for Framer 2
[Transmit Channel Clock from Framer 2]
Transmit Channel Block from Framer 2
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 2
Receive Link Data from Framer 2
Receive Link Clock from Framer 2
Receive Clock for Framer 2
Receive Bipolar Data for Framer 2
Receive Bipolar Data for Framer 2
Receive Signaling Output from Framer 2
[Receive Channel Clock from Framer 2]
Signal Ground
69
70
71
72
73
74
75
76
77
TNEG2
RLINK2
RLCLK2
RCLK2
RNEG2
RPOS2
RSIG2
[RCHCLK2]
VSS
I
I
O
[O]
-
78
8 of 105
DS21Q44
PIN
SYMBOL
TYPE DESCRIPTION
79
80
81
82
83
84
VDD
RCHBLK2
RSYSCLK2
RSYNC2
RSER2
-
O
I
I/O
O
I
Positive Supply Voltage
Receive Channel Block from Framer 2
Receive System Clock for Elastic Store in Framer 2
Receive Sync for Framer 2
Receive Serial Data from Framer 2
JTAG Test Data Input
JTDI
[RMSYNC2]
RFSYNC2
JTDO
[RLOS/LOTC2]
TCLK2
TLCLK2
TSYNC2
TLINK2
TSYSCLK3
TSER3
TSSYNC3
TSIG3
[TCHCLK3]
TCHBLK3
TPOS3
[O]
O
O
[O]
I
O
I/O
I
I
I
I
I
[Receive Multiframe Sync from Framer 2]
Receive Frame Sync from Framer 2
JTAG Test Data Output
[Receive Loss of Sync/Loss of Transmit clock from Framer 2]
Transmit Clock for Framer 2
Transmit Link Clock from Framer 2
Transmit Sync for Framer 2
Transmit Link Data for Framer 2
Transmit System Clock for Elastic Store in Framer 3
Transmit Serial Data for Framer 3
Transmit Sync for Elastic Store in Framer 3
Transmit Signaling Input for Framer 3
[Transmit Channel Clock from Framer 3]
Transmit Channel Block from Framer 3
Transmit Bipolar Data from Framer 3
Transmit Bipolar Data from Framer 3
Receive Link Data from Framer 3
Receive Link Clock from Framer 3
Receive Clock for Framer 3
Receive Bipolar Data for Framer 3
Receive Bipolar Data for Framer 3
Receive Signaling Output from Framer 3
[Receive Channel Clock from Framer 3]
Receive Channel Block from Framer 3
Receive System Clock for Elastic Store in Framer 3
Receive Sync for Framer 3
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
O
O
O
O
O
I
TNEG3
RLINK3
RLCLK3
RCLK3
RNEG3
RPOS3
I
I
RSIG3
O
[O]
O
I
I/O
O
O
[O]
O
-
[RCHCLK3]
RCHBLK3
RSYSCLK3
RSYNC3
RSER3
104
105
106
107
108
Receive Serial Data from Framer 3
8 MHz Clock
[Receive Multiframe Sync from Framer 3]
Receive Frame Sync from Framer 3
Signal Ground
8MCLK
[RMSYNC3]
RFSYNC3
VSS
109
110
111
112
VDD
CLKSI
-
I
Positive Supply Voltage
8MCLK Clock Reference Input
[RLOS/LOTC3]
TCLK3
[O]
I
O
I/O
I
[Receive Loss of Sync/Loss of Transmit clock from Framer 3]
Transmit Clock for Framer 3
Transmit Link Clock from Framer 3
Transmit Sync for Framer 3
Transmit Link Data for Framer 3
Data Bus Bit or Address/Data Bit 0; LSB
Data Bus Bit or Address/Data Bit 1
113
114
115
116
117
118
TLCLK3
TSYNC3
TLINK3
D0 or AD0
D1 or AD1
I/O
I/O
9 of 105
DS21Q44
PIN
SYMBOL
TYPE DESCRIPTION
119
120
121
122
123
124
125
126
127
128
D2 or AD2
D3 or AD3
D4 or AD4
D5 or AD5
D6 or AD6
D7 or AD7
TSYSCLK0
TSER0
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
Data Bus Bit or Address/Data Bit 2
Data Bus Bit or Address/Data Bit 3
Data Bus Bit or Address/Data Bit 4
Data Bus Bit or Address/Data Bit 5
Data Bus Bit or Address/Data Bit 6
Data Bus Bit or Address/Data Bit 7; MSB
Transmit System Clock for Elastic Store in Framer 0
Transmit Serial Data for Framer 0
Transmit Sync for Elastic Store in Framer 0
Transmit Signaling Input for Framer 0
[Transmit Channel Clock from Framer 0]
TSSYNC0
TSIG0
[TCHCLK0]
[O]
Note:
1. Brackets [ ] indicate pin function when the DS21Q44 is configured for emulation of the DS21Q43,
(FMS = 1).
Pin Description Sorted by Pin Function, FMS = 0 Table 2-2
PIN
SYMBOL
TYPE
DESCRIPTION
108
23
24
25
26
27
28
29
8MCLK
O
I
I
I
I
I
I
I
8 MHz Clock
A0
A1
A2
A3
A4
Address Bus Bit 0; LSB
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Address Bus Bit 5
A5
A6/ALE (AS)
Address Bus Bit 6; MSB or Address Latch Enable (Address
Strobe)
46
61
112
60
A7
BTS
CLKSI
CS*
I
I
I
Address Bus Bit 7
Bus Type Select for Parallel Control Port
8MCLK Clock Reference Input
Chip Select
I
117
118
119
120
121
122
123
124
47
D0 or AD0
D1 or AD1
D2 or AD2
D3 or AD3
D4 or AD4
D5 or AD5
D6 or AD6
D7 or AD7
FMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Data Bus Bit or Address/Data Bit 0; LSB
Data Bus Bit or Address/Data Bit 1
Data Bus Bit or Address/Data Bit 2
Data Bus Bit or Address/Data Bit 3
Data Bus Bit or Address/Data Bit 4
Data Bus Bit or Address/Data Bit 5
Data Bus Bit or Address/Data Bit 6
Data Bus Bit or Address/Data Bit 7; MSB
Framer Mode Select
58
59
30
52
FS0
FS1
INT*
JTCLK
I
I
O
I
Framer Select 0 for Parallel Control Port
Framer Select 1 for Parallel Control Port
Receive Alarm Interrupt for all Four Framers
JTAG Test Clock
10 of 105
DS21Q44
PIN
SYMBOL
TYPE
DESCRIPTION
84
86
50
18
64
10
44
80
104
6
40
74
100
62
17
51
85
109
5
39
73
99
4
38
72
98
7
41
75
101
8
42
76
102
13
49
83
107
9
43
77
103
12
48
82
JTDI
JTDO
JTMS
JTRST*
MUX
I
O
I
I
I
O
O
O
O
I
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select
JTAG Reset
Non-Multiplexed or Multiplexed Bus Select
Receive Channel Block from Framer 0
Receive Channel Block from Framer 1
Receive Channel Block from Framer 2
Receive Channel Block from Framer 3
Receive Clock for Framer 0
RCHBLK0
RCHBLK1
RCHBLK2
RCHBLK3
RCLK0
RCLK1
RCLK2
RCLK3
RD*/(DS*)
RFSYNC0
RFSYNC1
RFSYNC2
RFSYNC3
RLCLK0
RLCLK1
RLCLK2
RLCLK3
RLINK0
RLINK1
RLINK2
RLINK3
RNEG0
RNEG1
RNEG2
RNEG3
RPOS0
RPOS1
RPOS2
RPOS3
RSER0
RSER1
RSER2
RSER3
RSIG0
RSIG1
RSIG2
RSIG3
RSYNC0
RSYNC1
RSYNC2
I
I
I
I
Receive Clock for Framer 1
Receive Clock for Framer 2
Receive Clock for Framer 3
Read Input (Data Strobe)
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
I/O
I/O
I/O
Receive Frame Sync from Framer 0
Receive Frame Sync from Framer 1
Receive Frame Sync from Framer 2
Receive Frame Sync from Framer 3
Receive Link Clock from Framer 0
Receive Link Clock from Framer 1
Receive Link Clock from Framer 2
Receive Link Clock from Framer 3
Receive Link Data from Framer 0
Receive Link Data from Framer 1
Receive Link Data from Framer 2
Receive Link Data from Framer 3
Receive Bipolar Data for Framer 0
Receive Bipolar Data for Framer 1
Receive Bipolar Data for Framer 2
Receive Bipolar Data for Framer 3
Receive Bipolar Data for Framer 0
Receive Bipolar Data for Framer 1
Receive Bipolar Data for Framer 2
Receive Bipolar Data for Framer 3
Receive Serial Data from Framer 0
Receive Serial Data from Framer 1
Receive Serial Data from Framer 2
Receive Serial Data from Framer 3
Receive Signaling Output from Framer 0
Receive Signaling output from Framer 1
Receive Signaling Output from Framer 2
Receive Signaling Output from Framer 3
Receive Sync for Framer 0
Receive Sync for Framer 1
Receive Sync for Framer 2
11 of 105
DS21Q44
PIN
SYMBOL
TYPE
DESCRIPTION
Receive Sync for Framer 3
Receive System Clock for Elastic Store in Framer 0
Receive System Clock for Elastic Store in Framer 1
Receive System Clock for Elastic Store in Framer 2
Receive System Clock for Elastic Store in Framer 3
RESERVED - must be left unconnected for normal operation
Transmit Channel Block from Framer 0
Transmit Channel Block from Framer 1
Transmit Channel Block from Framer 2
Transmit Channel Block from Framer 3
Transmit Clock for Framer 0
Transmit Clock for Framer 1
Transmit Clock for Framer 2
Transmit Clock for Framer 3
3-state Control for all Output and I/O Pins
Transmit Link Clock from Framer 0
Transmit Link Clock from Framer 1
Transmit Link Clock from Framer 2
Transmit Link Clock from Framer 3
Transmit Link Data for Framer 0
106
11
45
81
105
16
1
35
69
95
19
53
87
113
57
20
54
88
114
22
56
90
116
3
RSYNC3
RSYSCLK0
RSYSCLK1
RSYSCLK2
RSYSCLK3
SPARE1
TCHBLK0
TCHBLK1
TCHBLK2
TCHBLK3
TCLK0
TCLK1
TCLK2
TCLK3
TEST
TLCLK0
TLCLK1
TLCLK2
TLCLK3
TLINK0
TLINK1
TLINK2
TLINK3
TNEG0
I/O
I
I
I
I
-
O
O
O
O
I
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
Transmit Link Data for Framer 1
Transmit Link Data for Framer 2
Transmit Link Data for Framer 3
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 3
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 3
Transmit Serial Data for Framer 0
Transmit Serial Data for Framer 1
Transmit Serial Data for Framer 2
Transmit Serial Data for Framer 3
Transmit Signaling Input for Framer 0
Transmit Signaling Input for Framer 1
Transmit Signaling Input for Framer 2
Transmit Signaling Input for Framer 3
Transmit Sync for Elastic Store in Framer 0
Transmit Sync for Elastic Store in Framer 1
Transmit Sync for Elastic Store in Framer 2
Transmit Sync for Elastic Store in Framer 3
Transmit Sync for Framer 0
37
71
97
2
TNEG1
TNEG2
TNEG3
TPOS0
TPOS1
TPOS2
TPOS3
TSER0
TSER1
TSER2
TSER3
TSIG0
TSIG1
TSIG2
TSIG3
36
70
96
126
32
66
92
128
34
68
94
127
33
67
93
21
55
TSSYNC0
TSSYNC1
TSSYNC2
TSSYNC3
TSYNC0
TSYNC1
Transmit Sync for Framer 1
12 of 105
DS21Q44
PIN
SYMBOL
TYPE
DESCRIPTION
Transmit Sync for Framer 2
Transmit Sync for Framer 3
Transmit System Clock for Elastic Store in Framer 0
Transmit System Clock for Elastic Store in Framer 1
Transmit System Clock for Elastic Store in Framer 2
Transmit System Clock for Elastic Store in Framer 3
Positive Supply Voltage
Positive Supply Voltage
Positive Supply Voltage
Signal Ground
Signal Ground
89
115
125
31
65
91
15
79
111
14
78
TSYNC2
TSYNC3
TSYSCLK0
TSYSCLK1
TSYSCLK2
TSYSCLK3
VDD
I/O
I/O
I
I
I
I
-
-
-
-
-
-
I
VDD
VDD
VSS
VSS
110
63
VSS
WR*/(R/W*)
Signal Ground
Write Input (Read/Write)
3. DS21Q44 PIN FUNCTION DESCRIPTION
TRANSMIT SIDE PINS
Signal Name:
TCLK
Signal Description:
Signal Type:
Transmit Clock
Input
A 2.048 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
TSER
Signal Description:
Signal Type:
Transmit Serial Data
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
TCHCLK
Signal Description:
Signal Type:
Transmit Channel Clock
Output
A 256 KHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q43 emulation).
Signal Name:
TCHBLK
Signal Description:
Signal Type:
Transmit Channel Block
Output
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384 Kbps (H0), 768
Kbps, 1920 bps (H12) or ISDN–PRI . Also useful for locating individual channels in drop–and–insert
applications, for external per–channel loopback, and for per–channel conditioning. See Section 12 for
details.
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DS21Q44
Signal Name:
TSYSCLK
Signal Description:
Signal Type:
Transmit System Clock
Input
1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.
Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up
to 8.192 MHz.
Signal Name:
TLCLK
Signal Description:
Signal Type:
Transmit Link Clock
Output
4 KHz to 20 KHz demand clock for the TLINK input. See Section 14 for details.
Signal Name:
TLINK
Signal Description:
Signal Type:
Transmit Link Data
Input
If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination
of the Sa bit positions (Sa4 to Sa8). See Section 14 for details.
Signal Name:
TSYNC
Signal Description:
Signal Type:
Transmit Sync
Input /Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. This pin can
also be programmed to output either a frame or multiframe pulse. Always synchronous with TCLK.
Signal Name:
TSSYNC
Signal Description:
Signal Type:
Transmit System Sync
Input
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit side elastic store. Always synchronous with TSYSCLK.
Signal Name:
TSIG
Signal Description:
Signal Type:
Transmit Signaling Input
Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM E1 data stream.
Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic store is enabled. This function is available when
FMS = 0.
Signal Name:
TPOS
Signal Description:
Signal Type:
Transmit Positive Data Output
Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (TCR1.7) control bit.
Signal Name:
TNEG
Signal Description:
Signal Type:
Transmit Negative Data Output
Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter.
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DS21Q44
RECEIVE SIDE PINS
Signal Name:
RLINK
Signal Description:
Signal Type:
Receive Link Data
Output
Updated with full recovered E1 data stream on the rising edge of RCLK.
Signal Name:
RLCLK
Signal Description:
Signal Type:
Receive Link Clock
Output
A 4 KHz to 20 KHz clock for the RLINK output. Used for sampling Sa bits.
Signal Name:
RCLK
Signal Description:
Signal Type:
Receive Clock Input
Input
2.048 MHz clock that is used to clock data through the receive side framer.
Signal Name:
RCHCLK
Signal Description:
Signal Type:
Receive Channel Clock
Output
A 256 KHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q43 emulation).
Signal Name:
RCHBLK
Signal Description:
Signal Type:
Receive Channel Block
Output
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
Signal Name:
RSER
Signal Description:
Signal Type:
Receive Serial Data
Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:
RSYNC
Signal Description:
Signal Type:
Receive Sync
Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC
multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
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DS21Q44
Signal Name:
RFSYNC
Signal Description:
Signal Type:
Receive Frame Sync
Output
An extracted 8 KHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.
Signal Name:
RMSYNC
Signal Description:
Signal Type:
Receive Multiframe Sync
Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If
the receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK. This function is available when FMS = 1 (DS21Q43 emulation).
Signal Name:
RSYSCLK
Signal Description:
Signal Type:
Receive System Clock
Input
1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied low
in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz.
Signal Name:
RSIG
Signal Description:
Signal Type:
Receive Signaling Output
Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
This function is available when FMS = 0.
Signal Name:
RLOS/LOTC
Signal Description:
Signal Type:
Receive Loss of Sync / Loss of Transmit Clock
Output
A dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either
toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5 usec. This function is available when FMS = 1 (DS21Q43
emulation).
Signal Name:
CLKSI
Signal Description:
Signal Type:
8 MHz Clock Reference
Input
A 2.048 MHz reference clock used in the generation of 8MCLK. This function is available when
FMS = 0.
Signal Name:
8MCLK
Signal Description:
Signal Type:
8 MHz Clock
Output
A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is
available when FMS = 0.
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DS21Q44
Signal Name:
RPOS
Signal Description:
Signal Type:
Receive Positive Data Input
Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
Signal Name:
RNEG
Signal Description:
Signal Type:
Receive Negative Data Input
Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
PARALLEL CONTROL PORT PINS
Signal Name:
INT*
Signal Description:
Signal Type:
Interrupt
Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the FDL Status Register. Active low, open drain output.
Signal Name:
FMS
Signal Description:
Signal Type:
Framer Mode Select
Input
Set low to select DS21Q44 feature set. Set high to select DS21Q43 emulation.
Signal Name:
MUX
Signal Description:
Signal Type:
Bus Operation
Input
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
Signal Description:
Signal Type:
D0 TO D7 / AD0 TO AD7
Data Bus or Address/Data Bus
Input /Output
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX
= 1), serves as a 8–bit multiplexed address / data bus.
Signal Name:
Signal Description:
Signal Type:
A0 TO A5, A7
Address Bus
Input
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.
Signal Name:
ALE (AS) / A6
Signal Description:
Signal Type:
Address Latch Enable (Address Strobe) or A6
Input
In non–multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive–going edge.
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DS21Q44
Signal Name:
BTS
Signal Description:
Signal Type:
Bus Type Select
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name:
RD* (DS*)
Signal Description:
Signal Type:
Read Input (Data Strobe)
Input
RD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing
diagrams in section 19 .
Signal Name:
Signal Description:
Signal Type:
FS0 AND FS1
Framer Selects
Input
Selects which of the four framers to be accessed.
Signal Name:
CS*
Signal Description:
Signal Type:
Chip Select
Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name:
WR* (R/W*)
Signal Description:
Signal Type:
Write Input (Read/Write)
Input
WR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name:
TEST
Signal Description:
Signal Type:
3–State Control
Input
Set high to 3–state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board level testing.
Signal Name:
JTRST*
Signal Description:
Signal Type:
IEEE 1149.1 Test Reset
Input
This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this pin should be held low. This function is
available when FMS = 0.
Signal Name:
JTMS
Signal Description:
Signal Type:
IEEE 1149.1 Test Mode Select
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined
IEEE 1149.1 states. If not used, this pin should be pulled high. This function is available when FMS = 0.
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DS21Q44
Signal Name:
JTCLK
Signal Description:
Signal Type:
IEEE 1149.1 Test Clock Signal
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this pin should be tied to VSS. This function is available when FMS = 0.
Signal Name:
JTDI
Signal Description:
Signal Type:
IEEE 1149.1 Test Data Input
Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. If not used, this pin
should be pulled high. This function is available when FMS = 0.
Signal Name:
JTDO
Signal Description:
Signal Type:
IEEE 1149.1 Test Data Output
Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected. This function is available when FMS = 0.
SUPPLY PINS
Signal Name:
VDD
Signal Description:
Signal Type:
Positive Supply
Supply
2.97 to 3.63 volts.
Signal Name:
Signal Description:
Signal Type:
0.0 volts.
VSS
Signal Ground
Supply
19 of 105
DS21Q44
4. DS21Q44 REGISTER MAP
Register Map Sorted by Address Table 4-1
REGISTER
ADDRESS
00
R/W
R
R
R
R
REGISTER NAME
BPV or Code Violation Count 1
BPV or Code Violation Count 2
CRC4 Error Count 1 / FAS Error Count 1
CRC4 Error Count 2
E-Bit Count 1 / FAS Error Count 2
E-Bit Count 2
Status 1
Status 2
Receive Information
Test 2
Not used
ABBREVIATION
VCR1
01
02
03
04
05
06
07
08
VCR2
CRCCR1
CRCCR2
EBCR1
EBCR2
SR1
R
R
R/W
R/W
R/W
R/W
–
–
–
–
–
SR2
RIR
09
TEST2 (set to 00h)
(set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
IDR
0A
0B
0C
0D
0E
0F
10
11
12
13
14
Not used
Not used
Not used
Not used
R
Device ID
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
Receive Control 1
Receive Control 2
Transmit Control 1
Transmit Control 2
Common Control 1
Test 1
Interrupt Mask 1
Interrupt Mask 2
Not used
Not used
Common Control 2
Common Control 3
Transmit Sa Bit Control
Common Control 6
Synchronizer Status
Receive Non-Align Frame
Transmit Align Frame
Transmit Non-Align Frame
Transmit Channel Blocking 1
Transmit Channel Blocking 2
Transmit Channel Blocking 3
Transmit Channel Blocking 4
Transmit Idle 1
RCR1
RCR2
TCR1
TCR2
CCR1
15
16
17
18
TEST1 (set to 00h)
IMR1
IMR2
(set to 00H)
(set to 00H)
CCR2
19
–
1A
1B
1C
1D
1E
1F
20
21
22
23
24
R/W
R/W
R/W
R/W
R
CCR3
TSaCR
CCR6
SSR
RNAF
TAF
TNAF
TCBR1
TCBR2
TCBR3
TCBR4
TIR1
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
25
26
27
Transmit Idle 2
TIR2
20 of 105
DS21Q44
REGISTER
ADDRESS
28
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
REGISTER NAME
Transmit Idle 3
Transmit Idle 4
Transmit Idle Definition
Receive Channel Blocking 1
Receive Channel Blocking 2
Receive Channel Blocking 3
Receive Channel Blocking 4
Receive Align Frame
Receive Signaling 1
ABBREVIATION
TIR3
TIR4
TIDR
RCBR1
RCBR2
RCBR3
RCBR4
RAF
29
2A
2B
2C
2D
2E
2F
30
R
RS1
31
R
Receive Signaling 2
RS2
32
R
Receive Signaling 3
RS3
33
R
Receive Signaling 4
RS4
34
R
Receive Signaling 5
RS5
35
R
Receive Signaling 6
RS6
36
R
Receive Signaling 7
RS7
37
R
Receive Signaling 8
RS8
38
R
Receive Signaling 9
RS9
39
R
R
R
R
R
R
R
Receive Signaling 10
Receive Signaling 11
Receive Signaling 12
Receive Signaling 13
Receive Signaling 14
Receive Signaling 15
Receive Signaling 16
Transmit Signaling 1
Transmit Signaling 2
Transmit Signaling 3
Transmit Signaling 4
Transmit Signaling 5
Transmit Signaling 6
Transmit Signaling 7
Transmit Signaling 8
Transmit Signaling 9
Transmit Signaling 10
Transmit Signaling 11
Transmit Signaling 12
Transmit Signaling 13
Transmit Signaling 14
Transmit Signaling 15
Transmit Signaling 16
Transmit Si Bits Align Frame
Transmit Si Bits Non-Align Frame
Transmit Remote Alarm Bits
Transmit Sa4 Bits
RS10
RS11
RS12
RS13
RS14
RS15
RS16
TS1
TS2
TS3
TS4
TS5
3A
3B
3C
3D
3E
3F
40
41
42
43
44
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
45
46
47
48
TS6
TS7
TS8
TS9
49
TS10
TS11
TS12
TS13
TS14
TS15
TS16
TSiAF
TSiNAF
TRA
4A
4B
4C
4D
4E
4F
50
51
52
53
TSa4
21 of 105
DS21Q44
REGISTER
ADDRESS
54
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
REGISTER NAME
Transmit Sa5 Bits
Transmit Sa6 Bits
Transmit Sa7 Bits
Transmit Sa8 Bits
Receive Si bits Align Frame
Receive Si bits Non-Align Frame
Receive Remote Alarm Bits
Receive Sa4 Bits
Receive Sa5 Bits
Receive Sa6 Bits
ABBREVIATION
TSa5
TSa6
TSa7
TSa8
RSiAF
RSiNAF
RRA
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
RSa4
RSa5
RSa6
RSa7
RSa8
TC1
R
R
R
Receive Sa7 Bits
Receive Sa8 Bits
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit Channel 1
Transmit Channel 2
Transmit Channel 3
Transmit Channel 4
Transmit Channel 5
Transmit Channel 6
Transmit Channel 7
Transmit Channel 8
Transmit Channel 9
Transmit Channel 10
Transmit Channel 11
Transmit Channel 12
Transmit Channel 13
Transmit Channel 14
Transmit Channel 15
Transmit Channel 16
Transmit Channel 17
Transmit Channel 18
Transmit Channel 19
Transmit Channel 20
Transmit Channel 21
Transmit Channel 22
Transmit Channel 23
Transmit Channel 24
Transmit Channel 25
Transmit Channel 26
Transmit Channel 27
Transmit Channel 28
Transmit Channel 29
Transmit Channel 30
Transmit Channel 31
Transmit Channel 32
61
62
63
64
65
66
67
68
TC2
TC3
TC4
TC5
TC6
TC7
TC8
TC9
69
TC10
TC11
TC12
TC13
TC14
TC15
TC16
TC17
TC18
TC19
TC20
TC21
TC22
TC23
TC24
TC25
TC26
TC27
TC28
TC29
TC30
TC31
TC32
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
22 of 105
DS21Q44
REGISTER
ADDRESS
80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
REGISTER NAME
Receive Channel 1
Receive Channel 2
Receive Channel 3
Receive Channel 4
Receive Channel 5
Receive Channel 6
Receive Channel 7
Receive Channel 8
ABBREVIATION
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
81
82
83
84
85
86
87
88
Receive Channel 9
RC9
89
Receive Channel 10
Receive Channel 11
Receive Channel 12
Receive Channel 13
Receive Channel 14
Receive Channel 15
Receive Channel 16
Receive Channel 17
Receive Channel 18
Receive Channel 19
Receive Channel 20
Receive Channel 21
Receive Channel 22
Receive Channel 23
Receive Channel 24
Receive Channel 25
Receive Channel 26
Receive Channel 27
Receive Channel 28
Receive Channel 29
Receive Channel 30
Receive Channel 31
Receive Channel 32
Transmit Channel Control 1
Transmit Channel Control 2
Transmit Channel Control 3
Transmit Channel Control 4
Receive Channel Control 1
Receive Channel Control 2
Receive Channel Control 3
Receive Channel Control 4
Common Control 4
Transmit DS0 Monitor
Common Control 5
Receive DS0 Monitor
RC10
RC11
RC12
RC13
RC14
RC15
RC16
RC17
RC18
RC19
RC20
RC21
RC22
RC23
RC24
RC25
RC26
RC27
RC28
RC29
RC30
RC31
RC32
TCC1
TCC2
TCC3
TCC4
RCC1
RCC2
RCC3
RCC4
CCR4
TDS0M
CCR5
RDS0M
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
R/W
R
23 of 105
DS21Q44
REGISTER
ADDRESS
AC
AD
AE
AF
R/W
R/W
–
–
–
REGISTER NAME
ABBREVIATION
TEST3 (set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
HCR
Test 3
Not used
Not used
Not used
B0
B1
B2
B3
B4
B5
B6
B7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
HDLC Control Register
HDLC Status Register
HSR
HIMR
RHIR
RHFR
IBO
THIR
THFR
RDC1
HDLC Interrupt Mask Register
Receive HDLC Information Register
Receive HDLC FIFO Register
Interleave Bus Operation Register
Transmit HDLC Information Register
Transmit HDLC FIFO Register
Receive HDLC DS0 Control Register 1
Receive HDLC DS0 Control Register 2
Transmit HDLC DS0 Control Register 1
Transmit HDLC DS0 Control Register 2
Not used
B8
B9
RDC2
TDC1
TDC2
BA
BB
BC
BD
BE
(set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
–
–
–
Not used
Not used
Not used
BF
Notes:
1. Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all
zeros) on power– up initialization to insure proper operation.
2. Register banks CxH, DxH, ExH, and FxH are not accessible.
5. PARALLEL PORT
The DS21Q44 is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS21Q44 can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 19 for more details.
6. CONTROL, ID AND TEST REGISTERS
The operation of each framer within the DS21Q44 is configured via a set of ten control registers.
Typically, the control registers are only accessed when the system is first powered up. Once a channel in
the DS21Q44 has been initialized, the control registers will only need to be accessed when there is a
change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and six Common Control Registers (CCR1 to CCR6).
Each of the ten registers are described in this section.
There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a one indicating that the DS21Q44 is present. The T1 pin–for–pin compatible version of the
DS21Q44 is the DS21Q42 and it also has an ID register at address 0Fh and the user can read the MSB to
determine which chip is present since in the DS21Q42 the MSB will be set to a zero and in the DS21Q44
it will be set to a one. The lower four bits of the IDR are used to display the die revision of the chip.
24 of 105
DS21Q44
Power–Up Sequence
The DS21Q44 does not automatically clear its register space on power–up. After the supplies are stable,
each of the four framer’s register space should be configured for operation by writing to all of the internal
registers. This includes setting the Test and all unused registers to 00Hex.
This can be accomplished using a two-pass approach on each framer within the DS21Q44.
1. Clear framer’s register space by writing 00H to the addresses 00H through 0BFH.
2. Program required registers to achieve desired operating mode.
Note:
When emulating the DS21Q43 feature set (FMS = 1), the full address space (00H through 0BFH) must be
initialized. DS21Q43 emulation require address pin A7 to be used.
Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero
to a one (this step can be skipped if the elastic stores are disabled).
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
(LSB)
T1E1
0
0
POSITION
IDR.7
0
ID3
ID2
ID1
ID0
SYMBOL
NAME AND DESCRIPTION
T1E1
T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
ID3
IDR.3
Chip Revision Bit 3. MSB of a decimal code that represents the
chip revision.
ID2
ID1
ID0
IDR.1
IDR.2
IDR.0
Chip Revision Bit 2.
Chip Revision Bit 1.
Chip Revision Bit 0. LSB of a decimal code that represents the
chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
POSITION
RCR1.7
–
–
FRC
SYNCE
RESYNC
SYMBOL
RSMF
NAME AND DESCRIPTION
RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6=1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSYNC Mode Select.
RSM
RCR1.6
0 = frame mode (see the timing in Section 18)
1 = multiframe mode (see the timing in Section 18)
25 of 105
DS21Q44
SYMBOL
POSITION
NAME AND DESCRIPTION
RSIO
RCR1.5
RSYNC I/O Select. (note: this bit must be set to zero when
RCR2.1=0).
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled)
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
Frame Resync Criteria.
–
–
FRC
RCR1.4
RCR1.3
RCR1.2
0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non–FAS is received in error 3
consecutive times
SYNCE
RCR1.1
RCR1.0
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
Resync. When toggled from low to high, a resync is initiated.
Must be cleared and set again for a subsequent resync.
RESYNC
SYNC/RESYNC CRITERIA Table 6–1
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N and
N + 2, and FAS not present in FAS received
frame N + 1
Three consecutive incorrect
G.706
4.1.1
4.1.2
Alternate (RCR1.2=1) the
above criteria is met or three
consecutive incorrect bit 2 of
non–FAS received
CRC4
CAS
Two valid MF alignment
words found within 8 ms
915 or more CRC4 code
words out of 1000 received in 4.2 and 4.3.2
error
Two consecutive MF
alignment words received in
G.706
Valid MF alignment word
found and previous timeslot
G.732 5.2
16 contains code other than all error
zeros
26 of 105
DS21Q44
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
POSITION
RCR2.7
Sa5S
Sa4S
RBCS
RESE
–
SYMBOL
Sa8S
NAME AND DESCRIPTION
Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit
position; set to zero to force RLCLK low during Sa8 bit
position. See Section 18 for timing details.
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
–
RCR2.6
RCR2.5
RCR2.4
RCR2.3
RCR2.2
RCR2.1
RCR2.0
Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit
position; set to zero to force RLCLK low during Sa7 bit
position. See Section 18 for timing details.
Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit
position; set to zero to force RLCLK low during Sa6 bit
position. See Section 18 for timing details.
Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit
position; set to zero to force RLCLK low during Sa5 bit
position. See Section 18 for timing details.
Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit
position; set to zero to force RLCLK low during Sa4 bit
position. See Section 18 for timing details.
Receive Side Backplane Clock Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
Receive Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Not Assigned. Should be set to zero when written.
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)
(LSB)
ODF
TFPT
T16S
POSITION
TCR1.7
TUA1
TSiS
TSA1
TSM
TSIO
SYMBOL
ODF
NAME AND DESCRIPTION
Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG=0
Transmit Timeslot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
TFPT
T16S
TCR1.6
TCR1.5
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
Transmit Timeslot 16 Data Select.
0 = sample timeslot 16 at TSER pin
1 = source timeslot 16 from TS0 to TS15 registers
27 of 105
DS21Q44
SYMBOL
POSITION
NAME AND DESCRIPTION
TUA1
TCR1.4
Transmit Unframed All Ones.
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOS and TNEG
Transmit International Bit Select.
0 = sample Si bits at TSER pin
TSiS
TCR1.3
1 = source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TSA1
TSM
TCR1.2
CR1.1
Transmit Signaling All Ones.
0 = normal operation
1 = force timeslot 16 in every frame to all ones
TSYNC Mode Select.
0 = frame mode (see the timing in Section 18)
1 = CAS and CRC4 multiframe mode (see the timing in Section
18)
TSIO
TCR1.0
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
Notes:
See Figure 18–15 for more details about how the Transmit Control Registers affect the operation of the
DS21Q44.
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
POSITION
TCR2.7
Sa5S
Sa4S
ODM
AEBE
PF
SYMBOL
NAME AND DESCRIPTION
Sa8S
Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK
pin; set to zero to not source the Sa8 bit. See Section 18 for
timing details.
Sa7S
Sa6S
Sa5S
Sa4S
TCR2.6
TCR2.5
TCR2.4
TCR2.3
Sa7 Bit Select. Set to one to source the Sa7 bit from the TLINK
pin; set to zero to not source the Sa7 bit. See Section 18 for
timing details.
Sa6 Bit Select. Set to one to source the Sa6 bit from the TLINK
pin; set to zero to not source the Sa6 bit. See Section 18 for
timing details.
Sa5 Bit Select. Set to one to source the Sa5 bit from the TLINK
pin; set to zero to not source the Sa5 bit. See Section 18 for
timing details.
Sa4 Bit Select. Set to one to source the Sa4 bit from the TLINK
pin; set to zero to not source the Sa4 bit. See Section 18 for
timing details.
28 of 105
DS21Q44
SYMBOL
POSITION
NAME AND DESCRIPTION
Output Data Mode.
ODM
TCR2.2
0 = pulses at TPOSO and TNEGO are one full TCLKO period
wide
1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide
AEBE
PF
TCR2.1
TCR2.0
Automatic E–Bit Enable.
0 = E–bits not automatically set in the transmit direction
1 = E–bits automatically set in the transmit direction
Function of RLOS/LOTC Pin.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB)
(LSB)
FLB
THDB3
TG802
POSITION
CCR1.7
TCRC4
RSM
RHDB3
RG802
RCRC4
SYMBOL
FLB
NAME AND DESCRIPTION
Framer Loopback.
0=loopback disabled
1=loopback enabled
Transmit HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
Transmit G.802 Enable. See Section 18 for details.
0=do not force TCHBLK high during bit 1 of timeslot 26
1=force TCHBLK high during bit 1 of timeslot 26
Transmit CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
Receive Signaling Mode Select.
0=CAS signaling mode
1=CCS signaling mode
Receive HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
THDB3
TG802
TCRC4
RSM
CCR1.6
CCR1.5
CCR1.4
CCR1.3
CCR1.2
CCR1.1
CCR1.0
RHDB3
RG802
RCRC4
Receive G.802 Enable. See Section 18 for details.
0=do not force RCHBLK high during bit 1 of timeslot 26
1=force RCHBLK high during bit 1 of timeslot 26
Receive CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
29 of 105
DS21Q44
FRAMER LOOPBACK
When CCR1.7 is set to a one, the framer will enter a Framer LoopBack (FLB) mode. See Figure 1–1 for
more details. This loopback is useful in testing and debugging applications. In FLB, the framer will loop
data from the transmit side back to the receive side. When FLB is enabled, the following will occur:
1. Data will be transmitted as normal at TPOS and TNEG.
2. Data input via RPOS and RNEG will be ignored.
3. The RCLK output will be replaced with the TCLK input.
CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)
(MSB)
(LSB)
ECUS
VCRFS
AAIS
POSITION
CCR2.7
ARA
RSERC
LOTCMC
RFF
RFE
SYMBOL
NAME AND DESCRIPTION
ECUS
Error Counter Update Select. See Section 8 for details.
0=update error counters once a second
1=update error counters every 62.5 ms (500 frames)
VCR Function Select. See Section 8 for details.
0=count BiPolar Violations (BPVs)
1=count Code Violations (CVs)
Automatic AIS Generation.
0=disabled
1=enabled
VCRFS
AAIS
CCR2.6
CCR2.5
CCR2.4
CCR2.3
CCR2.2
ARA
Automatic Remote Alarm Generation.
0=disabled
1=enabled
RSERC
LOTCMC
RSER Control.
0=allow RSER to output data as received under all conditions
1=force RSER to one under loss of frame alignment conditions
Loss of Transmit Clock Mux Control. Determines whether
the transmit side formatter should switch to the ever present
RCLK if the TCLK should fail to transition (see Figure 1–1).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stops
RFF
RFE
CCR2.1
CCR2.0
Receive Force Freeze. Freezes receive side signaling at RSIG
(and RSER if CCR3.3=1); will override Receive Freeze Enable
(RFE). See Section 10 or details.
0=do not force a freeze event
1=force a freeze event
Receive Freeze Enable. See Section 10 for details.
0=no freezing of receive signaling data will occur
1=allow freezing of receive signaling data at RSIG (and RSER
if CCR3.3=1).
30 of 105
DS21Q44
AUTOMATIC ALARM GENERATION
The DS21Q44 can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS
generation is enabled (CCR2.5 = 1), the framer monitors the receive side to determine if any of the
following conditions are present: loss of receive frame synchronization, AIS alarm (all one’s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
framer will transmit an AIS alarm.
When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive side to
determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm
(all one’s) reception, loss of receive carrier or if CRC4 multiframe synchronization (if enabled) cannot be
found within 128 ms of FAS synchronization. If any one (or more) of the above conditions is present,
then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a
constant Remote Alarm will be transmitted if the framer cannot find CRC4 multiframe synchronization
within 400 ms as per G.706.
It is an illegal state to have both CCR2.4 and CCR2.5 set to one at the same time.
CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
POSITION
CCR3.7
–
RSRE
THSE
TBCS
RCLA
SYMBOL
NAME AND DESCRIPTION
TESE
Transmit Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
TCBFS
TIRFS
CCR3.6
CCR3.5
Transmit Channel Blocking Registers (TCBR) Function
Select.
0=TCBRs define the operation of the TCHBLK output pin
1=TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select. See Section
11 for details.
0=TIRs define in which channels to insert idle code
1=TIRs define in which channels to insert data from RSER
(i.e., Per Channel Loopback function)
–
CCR3.4
CCR3.3
Not Assigned. Should be set to zero when written.
Receive Side Signaling Re–Insertion Enable. See Section 10
for details.
RSRE
0=do not re–insert signaling bits into the data stream presented
at the RSER pin
1=re–insert the signaling bits into data stream presented at the
RSER pin
THSE
CCR3.2
Transmit Side Hardware Signaling Insertion Enable. See
Section 10 for details.
0=do not insert signaling from the TSIG pin into the data
stream presented at the TSER pin
1=insert signaling from the TSIG pin into the data stream
31 of 105
DS21Q44
SYMBOL
TBCS
POSITION
CCR3.1
NAME AND DESCRIPTION
presented at the TSER pin
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
RCLA
CCR3.0
Receive Carrier Loss (RCL) Alternate Criteria.
0=RCL declared upon 255 consecutive zeros (125 us)
1=RCL declared upon 2048 consecutive zeros (1 ms)
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
(MSB)
(LSB)
RLB
–
–
POSITION
CCR4.7
TCM4
TCM3
TCM2
TCM1
TCM0
SYMBOL
RLB
NAME AND DESCRIPTION
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
–
–
CCR4.6
CCR4.5
CCR4.4
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that deter-mines which transmit channel data will appear in the
TDS0M register. See Section 9 or details.
TCM4
TCM3
TCM2
TCM1
TCM0
CCR4.3
CCR4.2
CCR4.1
CCR4.0
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
(MSB)
(LSB)
–
RESALGN TESALGN
RCM4
NAME AND DESCRIPTION
Not Assigned. Should be set to zero when written
Receive Elastic Store Align. Setting this bit from a zero to a
one may force the receive elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if
the pointer separation is already greater or equal to half a frame.
If pointer separation is less then half a frame, the command will
be executed and data will be disrupted. Should be toggled after
RSYSCLK has been applied and is stable. Must be cleared and
set again for a subsequent align. See Section 13 for details.
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
–
CCR5.7
CCR5.6
RESALGN
32 of 105
DS21Q44
SYMBOL
POSITION
NAME AND DESCRIPTION
TESALGN
CCR5.5
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 13
for details.
RCM4
CCR5.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)
(MSB)
(LSB)
–
–
–
–
–
TCLKSRC
RESR
TESR
SYMBOL
POSITION
NAME AND DESCRIPTION
–
–
–
–
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
CCR6.2
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Transmit Clock Source Select. This function allows the user
to internally select RCLK as the clock source for the transmit
side formatter.
–
TCLKSRC
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this bit
set high.
Transmit Elastic Store Reset. Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this bit
set high.
RESR
TESR
CCR6.1
CCR6.0
33 of 105
DS21Q44
7. STATUS AND INFORMATION REGISTERS
There is a set of seven registers per framer that contain information on the current real time status of a
framer in the DS21Q44, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register
(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.
The specific details on the four registers pertaining to the HDLC controller are covered in Section 15 but
they operate the same as the other status registers in the DS21Q44 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The
Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and
a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again (or in the case of the
RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still
present).
The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The byte
written to the register will inform the framer which bits the user wishes to read and have cleared. The user
will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a
zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written
to a bit location, the read register will be updated with the latest information. When a zero is written to a
bit position, the read register will not be updated and the previous value will be held. A write to the status
and information registers will be immediately followed by a read of the same register. The read result
should be logically AND’ed with the mask byte that was just written and this value should be written
back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write–read– write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q44 with higher–order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and
HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 15.
The interrupts caused by four of the alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act
differently than the interrupts caused by other alarms and events in SR1 and SR2 (namely RSA1, RDMA,
RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). These four alarm interrupts
will force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive
according to the set/clear criteria in Table 7-1). The INT* pin will be allowed to return high (if no other
interrupts are present) when the user reads the alarm bit that caused the interrupt to occur. If the alarm is
still present, the register bit will remain set.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
34 of 105
DS21Q44
ISR: INTERRUPT STATUS REGISTER (Any address from 0C0 Hex to 0FF Hex)
(MSB)
(LSB)
F3HDLC
F3SR
F2HDLC
POSITION
ISR.7
F2SR
F1HDLC
F1SR
F0HDLC
F0SR
SYMBOL
NAME AND DESCRIPTION
F3HDLC
FRAMER 3 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F3SR
ISR.6
ISR.5
FRAMER 3 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 2 HDLC CONTROLLER INTERRUPT
REQUEST.
F2HDLC
0 = No interrupt request pending.
1 = Interrupt request pending.
F2SR
ISR.4
ISR.3
FRAMER 2 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 1 HDLC CONTROLLER INTERRUPT
REQUEST.
F1HDLC
0 = No interrupt request pending.
1 = Interrupt request pending.
F1SR
ISR.2
ISR.1
FRAMER 1 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 0 HDLC CONTROLLER INTERRUPT
REQUEST.
F0HDLC
0 = No interrupt request pending.
1 = Interrupt request pending.
F0SR
ISR.0
FRAMER 0 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
35 of 105
DS21Q44
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB)
(LSB)
TESF
TESE
LORC
POSITION
RIR.7
RESF
RESE
CRCRC
FASRC
CASRC
SYMBOL
TESF
NAME AND DESCRIPTION
Transmit Side Elastic Store Full. Set when the transmit side
elastic store buffer fills and a frame is deleted.
Transmit Side Elastic Store Empty. Set when the transmit
side elastic store buffer empties and a frame is repeated.
Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2µs (3µs ± 1µs).
Receive Side Elastic Store Full. Set when the receive side
elastic store buffer fills and a frame is deleted.
Receive Side Elastic Store Empty. Set when the receive side
elastic store buffer empties and a frame is repeated.
CRC Resync Criteria Met. Set when 915/1000 code words are
received in error.
TESE
RIR.6
LORC
RESF
RIR.5
RIR.4
RESE
RIR.3
CRCRC
FASRC
CASRC
RIR.2
RIR.1
FAS Resync Criteria Met. Set when 3 consecutive FAS words
are received in error.
CAS Resync Criteria Met. Set when 2 consecutive CAS MF
alignment words are received in error.
RIR.0
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB)
(LSB)
CSC5
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
SYMBOL
POSITION
NAME AND DESCRIPTION
CSC5
CSC4
CSC3
CSC2
CSC0
SSR.7
SSR.6
SSR.5
SSR.4
SSR.3
CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.
CRC4 Sync Counter Bit 4.
CRC4 Sync Counter Bit 3.
CRC4 Sync Counter Bit 2.
CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next
to LSB is not accessible.
FASSA
CASSA
CRC4SA
SSR.2
SSR.1
SSR.0
FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CAS MF Sync Active. Set while the synchronizer is searching
for the CAS MF alignment word.
CRC4 MF Sync Active. Set while the synchronizer is
searching for the CRC4 MF alignment word.
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DS21Q44
CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter
is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the
amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests
that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be
abandoned and proper action taken. The CRC4 Sync Counter will rollover.
SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB)
(LSB)
RSA1
RDMA
RSA0
POSITION
SR1.7
RSLIP
RUA1
RRA
RCL
RLOS
SYMBOL
NAME AND DESCRIPTION
RSA1
Receive Signaling All Ones / Signaling Change. Set when
over a full MF, the content of timeslot 16 contains less than
three zeros. This alarm is not disabled in the CCS signaling
mode. A change in the contents of RS1 through RS16 from one
multiframe to the next will cause RSA1 and RSA0 to be set.
Receive Distant MF Alarm. Set when bit–6 of timeslot 16 in
frame 0 has been set for two consecutive multiframes. This
alarm is not disabled in the CCS signaling mode.
Receive Signaling All Zeros / Signaling Change. Set when
over a full MF, timeslot 16 contains all zeros. A change in the
contents of RS1 through RS16 from one multiframe to the next
will cause RSA1 and RSA0 to be set.
RDMA
RSA0
SR1.6
SR1.5
RSLIP
RUA1
RRA
SR1.4
SR1.3
SR1.2
SR1.1
SR1.0
Receive Side Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
Receive Unframed All Ones. Set when an unframed all ones
code is received at RPOS and RNEG.
Receive Remote Alarm. Set when a remote alarm is received
at RPOS and RNEG.
Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1)
consecutive zeros have been detected at RPOS and RNEG.
Receive Loss of Sync. Set when the device is not synchronized
to the receive E1 stream.
RCL
RLOS
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ALARM CRITERIA Table 7-1
ALARM
SET CRITERIA
CLEAR CRITERIA
ITU
SPEC.
G.732
4.2
over 16 consecutive frames
(one full MF) timeslot 16
over 16 consecutive frames
(one full MF) timeslot 16
RSA1
(receive signaling all ones)
contains less than three zeros contains three or more zeros
over 16 consecutive frames
(one full MF) timeslot 16
contains all zeros
over 16 consecutive frames
(one full MF) timeslot 16
contains at least a single one
G.732
5.2
RSA0
(receive signaling all zeros)
bit 6 in timeslot 16 of frame bit 6 in timeslot 16 of frame
O.162
2.1.5
RDMA
(receive distant multiframe
alarm)
0 set to one for two
0 set to zero for two
consecutive MF
consecutive MF
less than three zeros in two
frames (512–bits)
bit 3 of non–align frame set
more than two zeros in two
frames (512–bits)
bit 3 of non–align frame set
O.162
1.6.1.2
O.162
2.1.4
RUA1
(receive unframed all ones)
RRA
(receive remote alarm)
to one for three consecutive to zero for three consecutive
occasions
occasions
255 (or 2048) consecutive
zeros received
in 255–bit times, at least 32
ones are received
G.775 /
G.962
RCL
(receive carrier loss)
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB)
(LSB)
RMF
RAF
TMF
POSITION
SR2.7
SEC
TAF
LOTC
RCMF
TSLIP
SYMBOL
RMF
NAME AND DESCRIPTION
Receive CAS Multiframe. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
Used to alert the host that signaling data is available.
Receive Align Frame. Set every 250 s at the beginning of
align frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
Transmit Multiframe. Set every 2 ms (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the
host that signaling data needs to be updated.
One Second Timer. Set on increments of one second based on
RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms
instead of once a second.
Transmit Align Frame. Set every 250 s at the beginning of
align frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
RAF
TMF
SEC
SR2.6
SR2.5
SR2.4
SR2.3
SR2.2
TAF
LOTC
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9 s). Will force the
LOTC pin high if enabled via TCR2.0.
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SYMBOL
POSITION
NAME AND DESCRIPTION
RCMF
SR2.1
Receive CRC4 Multiframe. Set on CRC4 multiframe
boundaries; will continue to be set every 2 ms on an arbitrary
boundary if CRC4 is disabled.
TSLIP
SR2.0
Transmit Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)
(MSB)
(LSB)
RSA1
RDMA
RSA0
POSITION
IMR1.7
RSLIP
RUA1
RRA
RCL
RLOS
SYMBOL
RSA1
NAME AND DESCRIPTION
Receive Signaling All Ones / Signaling Change.
0=interrupt masked
1=interrupt enabled
RDMA
RSA0
RSLIP
RUA1
RRA
IMR1.6
IMR1.5
IMR1.4
IMR1.3
IMR1.2
IMR1.1
IMR1.0
Receive Distant MF Alarm.
0=interrupt masked
1=interrupt enabled
Receive Signaling All Zeros / Signaling Change.
0=interrupt masked
1=interrupt enabled
Receive Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
Receive Unframed All Ones.
0=interrupt masked
1=interrupt enabled
Receive Remote Alarm.
0=interrupt masked
1=interrupt enabled
Receive Carrier Loss.
0=interrupt masked
1=interrupt enabled
RCL
RLOS
Receive Loss of Sync.
0=interrupt masked
1=interrupt enabled
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IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB)
(LSB)
RMF
RAF
TMF
POSITION
IMR2.7
SEC
TAF
LOTC
RCMF
TSLIP
SYMBOL
RMF
NAME AND DESCRIPTION
Receive CAS Multiframe.
0=interrupt masked
1=interrupt enabled
Receive Align Frame.
0=interrupt masked
1=interrupt enabled
Transmit Multiframe.
0=interrupt masked
1=interrupt enabled
One Second Timer.
0=interrupt masked
1=interrupt enabled
Transmit Align Frame.
0=interrupt masked
1=interrupt enabled
Loss Of Transmit Clock.
0=interrupt masked
1=interrupt enabled
Receive CRC4 Multiframe.
0=interrupt masked
1=interrupt enabled
RAF
TMF
IMR2.6
IMR2.5
IMR2.4
IMR2.3
IMR2.2
IMR2.1
IMR2.0
SEC
TAF
LOTC
RCMF
TSLIP
Transmit Side Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
8. ERROR COUNT REGISTERS
There are a set of four counters in each framer that record bipolar or code violations, errors in the CRC4
SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four
counters are automatically updated on either one second boundaries (CCR2.7=0) or every 62.5 ms
(CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt
from the one second timer to determine when to read these registers. The user has a full second (or 62.5
ms) to read the counters before the data is lost. All four counters will saturate at their respective
maximum counts and they will not rollover.
BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16–bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words
are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161.
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DS21Q44
Code violations are defined as consecutive bipolar violations of the same polarity. In most applications,
the framer should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on a E1 line would have to be
greater than 10** –2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB)
V15
V7
(LSB)
V8
V0
V14
V6
V13
V5
V12
V4
V11
V3
V10
V2
V9
V1
VCR1
VCR2
SYMBOL
POSITION
VCR1.7
VCR2.0
NAME AND DESCRIPTION
MSB of the 16–bit code violation count
LSB of the 10–bit code violation count
V15
V0
CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10–bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is
disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of
multiframe sync occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)
(note 1)
CRC7
(LSB)
CRC8
CRC0
(note 1)
CRC6
(note 1)
CRC5
(note 1)
CRC4
(note 1)
CRC3
(note 1)
CRC2
CRC9
CRC1
CRCCR1
CRCCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
CRC9
CRC0
CRCCR1.1
CRCCR2.0
MSB of the 10–Bit CRC4 error count
LSB of the 10–Bit CRC4 error count
Note:
1. The upper six bits of CRCCR1 at address 02 are the most significant bits of the 12–bit FAS error
counter.
E–Bit Counter
E–bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10–bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E–bit is set to zero. Since the maximum E–bit count in a one second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
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EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB)
(note 1)
EB7
(LSB)
EB8
EB0
(note 1)
EB6
(note 1)
EB5
(note 1)
EB4
(note 1)
EB3
(note 1)
EB2
EB9
EB1
EBCR1
EBCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
EB9
EB0
EBCR1.1
EBCR2.0
MSB of the 10–Bit E–Bit Error Count
LSB of the 10–Bit E–Bit Error Count
Note:
The upper six bits of EBCR1 at address 04 are the least significant bits of the 12–bit FAS error counter.
FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12–bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is
disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS
alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS
word error count in a one second period is 4000, this counter cannot saturate.
FASCR1: FAS ERROR COUNT REGISTER 1 (Address=02 Hex)
FASCR2: FAS ERROR COUNT REGISTER 2 (Address=04 Hex)
(MSB)
FAS11
FAS5
(LSB)
(note 2) FASCR1
(note 1) FASCR2
FAS10
FAS4
FAS9
FAS3
FAS8
FAS2
FAS7
FAS1
FAS6
FAS0
(note 2)
(note 1)
SYMBOL
POSITION
NAME AND DESCRIPTION
FAS11
FAS0
FASCR1.7
FASCR2.2
MSB of the 12–Bit FAS Error Count
LSB of the 12–Bit FAS Error Count
Notes:
1. The lower two bits of FASCR1 at address 02 are the most significant bits of the 10–bit CRC4 error
counter.
2. The lower two bits of FASCR2 at address 04 are the most significant bits of the 10–bit E–Bit counter.
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DS21Q44
9. DS0 MONITORING FUNCTION
Each framer in the DS21Q44 has the ability to monitor one DS0 64Kbps channel in the transmit direction
and one DS0 channel in the receive direction at the same time. In the transmit direction the user will
determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4
register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor
(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate E1 channel. Channels 1 through 32 map to register values 0 through
31. For example, if DS0 channel 6 (timeslot 5) in the transmit direction and DS0 channel 15 (timeslot 14)
in the receive direction needed to be monitored, then the following values would be programmed into
CCR4 and CCR5:
TCM4 = 0
TCM3 = 0
TCM2 = 1
TCM1 = 0
TCM0 = 1
RCM4 = 0
RCM3 = 1
RCM2 = 1
RCM1 = 1
RCM0 = 0
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
[Repeated here from section 6 for convenience]
(MSB)
(LSB)
RLB
–
–
POSITION
CCR4.7
TCM4
TCM3
TCM2
TCM1
TCM0
SYMBOL
RLB
NAME AND DESCRIPTION
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
–
–
CCR4.6
CCR4.5
CCR4.4
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that deter-mines which transmit channel data will appear in the
TDS0M register. See Section 9 or details.
TCM4
TCM3
TCM2
TCM1
TCM0
CCR4.3
CCR4.2
CCR4.1
CCR4.0
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=A9 Hex)
(MSB)
(LSB)
B1
B2
B3
POSITION
TDS0M.7
B4
B5
B6
B7
B8
SYMBOL
B1
NAME AND DESCRIPTION
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be transmitted).
B2
B3
B4
B5
B6
B7
B8
TDS0M.6
TDS0M.5
TDS0M.4
TDS0M.3
TDS0M.2
TDS0M.1
TDS0M.0
Transmit DS0 Channel Bit 2.
Transmit DS0 Channel Bit 3.
Transmit DS0 Channel Bit 4.
Transmit DS0 Channel Bit 5.
Transmit DS0 Channel Bit 6.
Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex)
[Repeated here from section 6 for convenience]
(MSB)
(LSB)
–
RESALGN TESALGN
RCM4
NAME AND DESCRIPTION
Not Assigned. Should be set to zero when written
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
–
CCR5.7
CCR5.6
RESALGN
Receive Elastic Store Align. Setting this bit from a zero to a
one may force the receive elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if
the pointer separation is already greater or equal to half a frame.
If pointer separation is less then half a frame, the command will
be executed and data will be disrupted. Should be toggled after
RSYSCLK has been applied and is stable. Must be cleared and
set again for a subsequent align. See Section 13 for details.
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 13
for details.
TESALGN
CCR5.5
RCM4
CCR5.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
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SYMBOL
POSITION
NAME AND DESCRIPTION
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = AB Hex)
(MSB)
(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL
POSITION
NAME AND DESCRIPTION
B1
RDS0M.7
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit
to be received).
B2
B3
B4
B5
B6
B7
B8
RDS0M.6
RDS0M.5
RDS0M.4
RDS0M.3
RDS0M.2
RDS0M.1
RDS0M.0
Receive DS0 Channel Bit 2.
Receive DS0 Channel Bit 3.
Receive DS0 Channel Bit 4.
Receive DS0 Channel Bit 5.
Receive DS0 Channel Bit 6.
Receive DS0 Channel Bit 7.
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be received).
10. SIGNALING OPERATION
Each framer in the DS21Q44 contains provisions for both processor based (i.e., software based) signaling
bit access and for hardware based access. Both the processor based access and the hardware based access
can be used simultaneously if necessary. The processor based signaling is covered in Section 10.1 and the
hardware based signaling is covered in Section 10.2.
10.1 PROCESSOR BASED SIGNALING
The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the framer. Each of the 30 voice channels has four
signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the voice channel
associated with a particular signaling bit. The voice channel numbers have been assigned as described in
the ITU documents. Please note that this is different than the channel numbering scheme (1 to 32) that is
used in the rest of the data sheet. For example, voice channel 1 is associated with timeslot 1 (Channel 2)
and voice Channel 30 is associated with timeslot 31 (Channel 32). There is a set of 16 registers for the
receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to TS16). The signaling registers
are detailed below.
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RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex)
(MSB)
0
(LSB)
X
0
0
0
X
Y
X
RS1 (30)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
B(7)
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
B(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
B(22)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
B(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
B(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
RS2 (31)
RS3 (32)
RS3 (33)
RS5 (34)
RS6 (35)
RS7 (36)
RS8 (37)
RS9 (38)
RS10 (39)
RS11 (3A)
RS12 (3B)
RS13 (3C)
RS14 (3D)
RS15 (3E)
RS16 (3F)
SYMBOL
POSITION
NAME AND DESCRIPTION
X
Y
A(1)
D(30)
RS1.0/1/3
RS1.2
RS2.7
Spare Bits.
Remote Alarm Bit (integrated and reported in SR1.6).
Signaling Bit A for Channel 1
Signaling Bit D for Channel 30.
RS16.0
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The
bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the
Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2 ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been
loaded with data. The user has 2 ms to retrieve the data before it is lost. The signaling data reported in
RS1 to RS16 is also available at the RSIG and RSER pins.
Three status bits in Status Register 1 (SR1) monitor the contents of registers RS1 through RS16. Status
monitored includes all zeros detection, all ones detection and a change in register contents. The Receive
Signaling All Zeros status bit (SR1.5) is set when over a full multi-frame, RS1 through RS16 contain all
zeros. The Receive Signaling All Ones status bit (SR1.7) is set when over a full multi-frame, RS1 through
RS16 contain less than three zeros. A change in the contents of RS1 through RS16 from one multiframe
to the next will cause RSA1 (SR1.7) and RSA0 (SR1.5) status bits to be set at the same time.
The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting either
the IMR1.7 or IMR1.5 bit. Once a signaling change has been detected, the user has at least 1.75 ms to
read the data out of the RS1 to RS16 registers before the data will be lost.
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DS21Q44
TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex)
(MSB)
0
(LSB)
X
0
0
0
X
Y
X
TS1 (40)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
B(7)
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
B(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
B(22)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
B(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
B(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
TS2 (41)
TS3 (42)
TS4 (43)
TS5 (44)
TS6 (45)
TS7 (46)
TS8 (47)
TS9 (48)
TS10 49)
TS11(4A)
TS12 (4B)
TS13 (4C)
TS14 (4D)
TS15 (4E)
TS16 (4F)
SYMBOL
POSITION
NAME AND DESCRIPTION
X
Y
A(1)
D(30)
TS1.0/1/3
TS1.2
TS2.7
Spare Bits.
Remote Alarm Bit (integrated and reported in SR1.6).
Signaling Bit A for Channel 1
Signaling Bit D for Channel 30.
TS16.0
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be
inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the framer
will load the values present in the Transmit Signaling Register into an outgoing signaling shift register
that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2.5)
to know when to update the signaling bits. The bit will be set every 2 ms and the user has 2 ms to update
the TSR’s before the old data will be retransmitted. ITU specifications recommend that the ABCD
signaling not be set to all zeros because they will emulate a CAS multiframe alignment word.
The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble.
The upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe
synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit
should be set to a one. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three
remaining bits in TS1 are the spare bits. If they are not used, they should be set to one. In CCS signaling
mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be
informed when the signaling registers need to be loaded with data. The user has 2 ms to load the data
before the old data will be retransmitted.
Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) to
deter-mine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the
corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pin (the
corresponding bit in the TCBRs=0). See the Transmit Data Flow diagram in Section 18 for more details.
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DS21Q44
10.2 HARDWARE BASED SIGNALING
Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in
a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode is always enabled. In
this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then
the backplane clock (RSYSCLK) must be 2.048 MHz. The ABCD signaling bits are output on RSIG in
the lower nibble of each channel. The RSIG data is updated once a multiframe (2 ms) unless a freeze is in
effect. See the timing diagrams in Section 18 for some examples.
The other hardware based signaling operating mode called signaling re–insertion can be invoked by
setting the RSRE control bit high (CCR3.3=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data be re–aligned at the RSER output according to this applied
multiframe boundary. in this mode, the elastic store must be enabled the backplane clock must be 2.048
MHz.
The signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE
control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit
(CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization,
carrier loss, or slip has occurred.
The 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the
RSIG pin (and at the RSER pin if RSRE=1 via CCR3.3). When freezing is enabled (RFE=1), the
signaling data will be held in the last known good state until the corrupting error condition subsides.
When the error condition sub-sides, the signaling data will be held in the old state for an additional 3 ms
to 5 ms before being allowed to be updated with new signaling data.
Transmit Side
Via the THSE control bit (CCR3.2), the DS21Q44 can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
hardware signaling insertion capabilities of each framer are available whether the transmit side elastic
store is enabled or disabled. If the transmit side elastic store is enabled, the backplane clock (TSYSCLK)
must be 2.048 MHz.
When hardware signaling insertion is enabled on a framer (THSE=1), then the user must enable the
Transmit Channel Blocking Register Function Select (TCBFS) control bit (CCR3.6=1). This is needed so
that the CAS multiframe alignment word, multiframe remote alarm, and spare bits can be added to
timeslot 16 in frame 0 of the multiframe. The TS1 register should be programmed with the proper
information. If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from
TSER (or TSIG if CCR3.2=1) and a one implies that signaling data for that channel is to be sourced from
the Transmit Signaling (TS) registers. See definition below.
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DS21Q44
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
CH20
CH24
CH28
CH32
(LSB)
CH1*
CH5
CH9
CH13
CH4
CH8
CH12
CH16
CH19
CH23
CH27
CH31
CH3
CH7
CH11
CH15
CH18
CH22
CH26
CH30
CH2
CH6
CH10
CH14
CH17*
CH21
CH25
CH29
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
Note:
*=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and
from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user
wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this
application, the following bits and registers would be programmed as follows:
CONTROL BITS
THSE=1 (CCR3.2)
TCBFS=1 (CCR3.6)
T16S=1(TCR1.5)
REGISTER VALUES
TS1=0Bh (MF alignment word, remote alarm etc.)
TCBR1=03h (source timeslot 16, frame 1 data)
TCBR2=01h (source voice Channel 5 signaling data from TS6)
TCBR3=04h (source voice Channel 10 signaling data from TS11)
TCBR4=00h
11. PER–CHANNEL CODE GENERATION AND LOOPBACK
Each framer in the DS21Q44 can replace data on a channel–by–channel basis in both the transmit and
receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section
11.1. The receive direction is from the E1 line to the backplane and is covered in Section 11.2.
11.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 11.1.1 was a
feature contained in the original DS21Q43 while the second method which is covered in Section 11.1.2 is
a new feature of the DS21Q44.
11.1.1 Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
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DS21Q44
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC. There are no restrictions on which channels can be looped back or on how many channels can
be looped back.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per–Channel Loopback]
(MSB)
CH8
CH16
CH24
CH32
(LSB)
CH1
CH9
CH17
CH25
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
SYMBOLS
CH1 - 32
POSITIONS
NAME AND DESCRIPTION
Transmit Idle Code Insertion Control Bits.
TIR1.0 - 4.7
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
Notes:
If CCR3.5=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 1–1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR0
TIDR.7
TIDR.0
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
11.1.2 Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 32 E1 channels.
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DS21Q44
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
TC1 (60)
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
C0
TC1.7
TC1.0
MSB of the Code (this bit is transmitted first)
LSB of the Code (this bit is transmitted last)
TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER
(Address=A0 to A3 Hex)
(MSB)
CH8
CH16
CH24
CH32
(LSB)
CH1
CH9
CH17
CH25
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
TCC1 (A0)
TCC2 (A1)
TCC3 (A2)
TCC4 (A3)
SYMBOL
CH1 - 32
POSITION
NAME AND DESCRIPTION
Transmit Code Insertion Control Bits
TCC1.0 - 4.7
0 = do not insert data from the TC register into the transmit data
stream
1 = insert data from the TC register into the transmit data
stream
11.2 RECEIVE SIDE CODE GENERATION
On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of
the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code
placed in the Receive Channel Registers (RC1 to RC32). This method allows a different 8–bit code to be
placed into each of the 32 E1 channels.
RC1 TO RC32: RECEIVE CHANNEL REGISTERS (Address=80 to 9F Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
RC1 (80)
SYMBOL
POSITION
RC1.7
NAME AND DESCRIPTION
MSB of the Code (this bit is sent first to the backplane)
LSB of the Code (this bit is sent last to the backplane)
C7
C0
RC1.0
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DS21Q44
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
(MSB)
CH8
CH16
CH24
CH32
(LSB)
CH1
CH9
CH17
CH25
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
RCC1 (A4)
RCC2 (A5)
RCC3 (A6)
RCC4 (A7)
SYMBOL
CH1 - 32
POSITION
NAME AND DESCRIPTION
RCC1.0 - 4.7
Receive Code Insertion Control Bits
0 = do not insert data from the RC register into the receive data
stream
1 = insert data from the RC register into the receive data stream
12. CLOCK BLOCKING REGISTERS
The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit
Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins
respectively. (The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either
high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD
controller in ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and
TCHBLK pin will be held high during the entire corresponding channel time. See the timing in Section
18 for an example. The TCBRs have alternate mode of use. Via the CCR3.6 bit, the user has the option to
use the TCBRs to determine on a channel by channel basis, which signaling bits are to be inserted via the
TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pins
(the corresponding bit in the TCBR=0). See the timing in Section 18 for an example.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING
REGISTERS (Address=2B to 2E Hex)
(MSB)
CH8
CH16
CH24
CH32
(LSB)
CH1
CH9
CH17
CH25
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
RCBR1 (2B)
RCBR2 (2C)
RCBR3 (2D)
RCBR4 (2E)
SYMBOLS
CH1 - 32
POSITIONS
RCBR1.0 - 4.7
NAME AND DESCRIPTION
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
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DS21Q44
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING
REGISTERS (Address=22 to 25 Hex)
(MSB)
CH8
CH16
CH24
CH32
(LSB)
CH1
CH9
CH17
CH25
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
SYMBOLS
CH1 - 32
POSITIONS
TCBR1.0 - 4.7
NAME AND DESCRIPTION
Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
Note:
If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER (or TSIG
if CCR3.2=1) and a one implies that signaling data for that channel is to be sourced from the Transmit
Signaling (TS) registers. See definition below.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
CH20
CH24
CH28
CH32
(LSB)
CH1*
CH5
CH9
CH13
CH4
CH8
CH12
CH16
CH19
CH23
CH27
CH31
CH3
CH7
CH11
CH15
CH18
CH22
CH26
CH30
CH2
CH6
CH10
CH14
CH17*
CH21
CH25
CH29
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
*=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
13. ELASTIC STORES OPERATION
Each framer in the DS21Q44 contains dual two–frame (512 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 MHz or
2.048 MHz. The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full
controlled slip capability which is necessary for this second purpose. Both elastic stores within a framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to
them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or
disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048 MHz
backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset (CCR6.0
& CCR6.1) function forces the elastic stores to a depth of one frame unconditionally. Data is lost during
the reset. The second method, the Elastic Store Align ( CCR5.5 & CCR5.6) forces the elastic store depth
to a minimum depth of half a frame only if the current pointer separation is already less then half a frame.
If a realignment occurs data is lost. In both mechanisms, independent resets are provided for both the
receive and transmit elastic stores.
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DS21Q44
13.1 RECEIVE SIDE
If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2 =0) or 2.048 MHz (RCR2.2=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a
pulse on frame/multiframe boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame
boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe
boundary, then RCR1.6 must be set to one. The DS21Q44 will always indicate frame boundaries via the
RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then either CAS
(RCR1.7=0) or CRC4 (RCR1.7=1) multiframe boundaries will be indicated via the RMSYNC output. If
the user selects to apply a 1.544 MHz clock to the RSYSCLK pin, then every fourth channel of the
received E1 data will be deleted and a F–bit position (which will be forced to one) will be inserted. Hence
Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the
received E1 data stream. Also, in 1.544 MHz applications, the RCHBLK output will not be active in
Channels 25 through 32 (or in other words, RCBR4 is not active). See Section 18 for timing details. If the
512–bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full
frame of data (256–bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a one. If the
buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a one.
13.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544 MHz (CCR3.1=0) or 2.048 MHz (CCR3.1=1) clock can be applied
to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192 MHz. If the user
selects to apply a 1.544 MHz clock to the TSYSCLK pin, then the data sampled at TSER will be ignored
every fourth channel. Hence Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and
28) will be ignored. The user must supply a 8 KHz frame sync pulse to the TSSYNC input. See Section
18 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0 bit and the
direction of the slip is reported in the RIR.6 and RIR.7 bits.
14. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
Each framer in the DS21Q44 provides for access to both the Sa and the Si bits via three different
methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The
first method is discussed in Section 14.1. The second involves using the internal RAF/RNAF and
TAF/TNAF registers and is discussed in Section 14.2 The third method which is covered in Section 14.3
involves an expanded version of the second method and is one of the features added to the DS21Q44
from the original DS21Q43 definition.
14.1 HARDWARE SCHEME
On the receive side, all of the received data is reported at the RLINK pin. Via RCR2, the user can control
the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can
be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will
identify the Si bits. See Section 18 for detailed timing.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see
Section 14.2 for details) or from the external TLINK pin. Via TCR2, the framer can be programmed to
source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits
through the framer without them being altered, then the device should be set up to source all five Sa bits
via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the
TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data flow
diagram in Section 18 for examples.
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DS21Q44
14.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME
On the receive side, the RAF and RNAF registers will always report the data as it received in the
Additional and International bit locations. The RAF and RNAF registers are updated with the setting of
the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to
read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if the framer is programmed: (1) to source the Si bits from the
TSER pin, (2) in the CRC4 mode, or (3) have automatic E–bit insertion enabled. Data in the Sa bit
position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to one (please see Section 14.1
for details). Please see the register descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram
in Section 14 for more details.
RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)
(MSB)
(LSB)
Si
0
0
1
1
0
1
1
SYMBOL
POSITION
NAME AND DESCRIPTION
Si
0
0
1
1
0
1
1
RAF.7
RAF.6
RAF.5
RAF.4
RAF.3
RAF.2
RAF.1
RAF.0
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit
Frame Alignment Signal Bit.
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RNAF: RECEIVE NON–ALIGN FRAME REGISTER (Address=1F Hex)
(MSB)
(LSB)
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
SYMBOL
POSITION
NAME AND DESCRIPTION
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
RNAF.7
RNAF.6
RNAF.5
RNAF.4
RNAF.3
RNAF.2
RNAF.1
RNAF.0
International Bit.
Frame Non–Alignment Signal Bit.
Remote Alarm.
Additional Bit 4.
Additional Bit 5.
Additional Bit 6.
Additional Bit 7.
Additional Bit 8.
TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex)
(MSB)
(LSB)
Si
0
0
1
1
0
1
1
[Must be programmed with the seven bit FAS word; the DS21Q44 does not automatically set these bits]
SYMBOL
POSITION
NAME AND DESCRIPTION
Si
0
0
1
1
0
1
1
TAF.7
TAF.6
TAF.5
TAF.4
TAF.3
TAF.2
TAF.1
TAF.0
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
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TNAF: TRANSMIT NON–ALIGN FRAME REGISTER (Address=21 Hex)
(MSB)
(LSB)
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
[Bit 2 must be programmed to one; the DS21Q44 does not automatically set this bit]
SYMBOL
POSITION
NAME AND DESCRIPTION
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
TNAF.7
TNAF.6
TNAF.5
TNAF.4
TNAF.3
TNAF.2
TNAF.1
TNAF.0
International Bit.
Frame Non–Alignment Signal Bit.
Remote Alarm (used to transmit the alarm).
Additional Bit 4.
Additional Bit 5.
Additional Bit 6.
Additional Bit 7.
Additional Bit 8.
14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4
Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these
registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first
received. Please see the register descriptions below and the Transmit Data Flow diagram in Section 18 for
more details. On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to
TSa8) that via the Transmit Sa Bit Control Register (TSaCR), can be programmed to insert both Si and Sa
data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status
Register 2 (SR2.5). The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to
update the data or else the old data will be retransmitted. The MSB of each register is the first bit
transmitted. Please see the register descriptions below and the Transmit Data Flow diagram in Section 18
for more details.
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REGISTER
NAME
ADDRESS
(HEX)
58
FUNCTION
The eight Si bits in the align frame.
RSiAF
RSiNAF
RRA
59
5A
5B
5C
5D
5E
5F
50
51
52
53
54
55
56
57
The eight Si bits in the non–align frame.
The eight reportings of the receive remote alarm (RA).
The eight Sa4 reported in each CRC4 multiframe.
The eight Sa5 reported in each CRC4 multiframe.
The eight Sa6 reported in each CRC4 multiframe.
The eight Sa7 reported in each CRC4 multiframe.
The eight Sa8 reported in each CRC4 multiframe.
The eight Si bits to be inserted into the align frame.
The eight Si bits to be inserted into the non–align frame.
The eight settings of remote alarm (RA).
RSa4
RSa5
RSa6
RSa7
RSa8
TSiAF
TSiNAF
TRA
TSa4
The eight Sa4 settings in each CRC4 multiframe.
The eight Sa5 settings in each CRC4 multiframe.
The eight Sa6 settings in each CRC4 multiframe.
The eight Sa7 settings in each CRC4 multiframe.
The eight Sa8 settings in each CRC4 multiframe.
TSa5
TSa6
TSa7
TSa8
TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address=1C Hex)
(MSB)
(LSB)
SiAF
SiNAF
RA
POSITION
TSaCR.7
Sa4
Sa5
Sa6
Sa7
Sa8
SYMBOL
SiAF
NAME AND DESCRIPTION
International Bit in Align Frame Insertion Control Bit.
0=do not insert data from the TSiAF register into the transmit
data stream.
1=insert data from the TSiAF register into the transmit data
stream.
SiNAF
RA
TSaCR.6
TSaCR.5
TSaCR.4
International Bit in Non–Align Frame Insertion Control Bit.
0=do not insert data from the TSiNAF register into the transmit
data stream.
1=insert data from the TSiNAF register into the transmit data
stream.
Remote Alarm Insertion Control Bit.
0=do not insert data from the TRA register into the transmit data
stream.
1=insert data from the TRA register into the transmit data
stream.
Additional Bit 4 Insertion Control Bit.
Sa4
0=do not insert data from the TSa4 register into the transmit data
stream.
1=insert data from the TSa4 register into the transmit data
stream.
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SYMBOL
POSITION
NAME AND DESCRIPTION
Sa5
TSaCR.3
Additional Bit 5 Insertion Control Bit.
0=do not insert data from the TSa5 register into the transmit data
stream.
1=insert data from the TSa5 register into the transmit data
stream.
Sa6
Sa7
Sa8
TSaCR.2
TSaCR.1
TSaCR.0
Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit data
stream.
1=insert data from the TSa6 register into the transmit data
stream.
Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit data
stream.
1=insert data from the TSa7 register into the transmit data
stream.
Additional Bit 8 Insertion Control Bit.
0=do not insert data from the TSa8 register into the transmit data
stream.
1=insert data from the TSa8 register into the transmit data
stream.
15. HDLC Controller for the Sa Bits or DS0
Each framer in the DS21Q44 has the ability to extract/insert data from/ into the Sa bit positions (Sa4 to
Sa8) or from/to any multiple of DS0 channels Each framer contains a complete HDLC controller and this
operation is covered in Section 15.1.
15.1 General Overview
Each framer contains a complete HDLC controller with 64–byte buffers in both the transmit and receive
directions. The HDLC controller performs all the necessary overhead for generating and receiving a
HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to
the HDLC data stream.
There are eleven registers that the host will use to operate and control the operation of the HDLC
controller. A brief description of the registers is shown in Table 15-1.
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HDLC CONTROLLER REGISTER LIST Table 15-1
NAME
FUNCTION
HDLC Control Register (HCR)
HDLC Status Register (HSR)
general control over the HDLC controller
key status information for both transmit and receive
directions
HDLC Interrupt Mask Register (HIMR)
allows/stops status bits to/from causing an interrupt
Receive HDLC Information Register status information on receive HDLC controller
(RHIR)
Receive HDLC FIFO Register (RHFR)
access to 64–byte HDLC FIFO in receive direction
Receive HDLC DS0 Control Register 1
(RDC1)
controls the HDLC function when used on DS0 channels
Receive HDLC DS0 Control Register 2
(RDC2)
Transmit HDLC Information Register status information on transmit HDLC controller
(THIR)
Transmit HDLC FIFO Register (THFR)
Transmit HDLC DS0 Control Register 1
(TDC1)
access to 64–byte HDLC FIFO in transmit direction
controls the HDLC function when used on DS0 channels
Transmit HDLC DS0 Control Register 2
(TDC2)
15.2 HDLC Status Registers
Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be
set to a one. Some of the bits in these three status registers are latched and some are real time bits that are
not latched. Section 15.4 contains register descriptions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred
again. The real time bits report the current instantaneous conditions that are occurring and the history of
these bits is not latched.
Like the other status registers in the framer, the user will always proceed a read of any of the three
registers with a write. The byte written to the register will inform the framer which of the latched bits the
user wishes to read and have cleared (the real time bits are not affected by writing to the status register).
The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read
and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with current value and it will be cleared. When a
zero is written to a bit position, the read register will not be updated and the previous value will be held.
A write to the status and information registers will be immediately followed by a read of the same
register. The read result should be logically AND’ed with the mask byte that was just written and this
value should be written back into the same register to insure that bit does indeed clear. This second write
step is necessary because the alarms and events in the status registers occur asynchronously in respect to
their access via the parallel port. This write–read–write (for polled driven access) or write–read (for
interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll
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certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS21Q44 with higher–order software languages.
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low
when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
15.3 Basic Operation Details
As a basic guideline for interpreting and sending HDLC messages, the following sequences can be
applied:
Receive a HDLC Message
1. Enable RPS interrupts.
2. Wait for interrupt to occur.
3. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.
4. Read RHIR to obtain REMPTY status.
A. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
A1. If CBYTE=0 then skip to step 5
A2. If CBYTE=1 then skip to step 7
B. If REMPTY=1, then skip to step 6
5. Repeat step 4.
6. Wait for interrupt, skip to step 4.
7. If POK=0, then discard whole packet, if POK=1, accept the packet.
8. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register.
2. Enable either the THALF or TNF interrupt.
3. Read THIR to obtain TFULL status.
A. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when
the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to step
6)
B. If TFULL=1, then skip to step 5
4. Repeat step 3.
5. Wait for interrupt, skip to step 3.
6. Disable THALF or TNF interrupt and enable TMEND interrupt.
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
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15.4 HDLC Register Description
HCR: HDLC CONTROL REGISTER (Address=B0 Hex)
(MSB)
(LSB)
–
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL
POSITION
NAME AND DESCRIPTION
–
HCR.7
HCR.6
Not Assigned. Should be set to zero.
RHR
Receive HDLC Reset. A 0 to 1 transition will reset the receive
HDLC controller. Must be cleared and set again for a subsequent
reset.
TFS
THR
HCR.5
HCR.4
HCR.3
Transmit Flag/Idle Select.
0 = 7Eh.
1 = FFh.
Transmit HDLC Reset. A 0 to 1 transition will reset the
transmit HDLC controller. Must be cleared and set again for a
subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed by
7Eh or FFh flags/idle until a new packet is initiated by writing
new data into the FIFO. Must be cleared and set again for a
subsequent abort to be sent.
TABT
TEOM
HCR.2
Transmit End of Message. Should be set to a one just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when the
last byte has been transmitted.
TZSD
HCR.1
HCR.0
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation).
1 = disable the zero stuffer.
TCRCD
Transmit CRC Defeat.
0 = enable CRC generation (normal operation).
1 = disable CRC generation.
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HSR: HDLC STATUS REGISTER (Address=B1 Hex)
(MSB)
(LSB)
–
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
–
RPE
HSR.7
HSR.6
Not Assigned. Should be set to zero.
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as a
CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
RPS
RHALF
RNE
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
Receive Packet Start. Set when the HDLC controller detects an
opening byte. The setting of this bit prompts the user to read the
RHIR register for details.
Receive FIFO Half Full. Set when the receive 64–byte FIFO
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
Receive FIFO Not Empty. Set when the receive 64–byte FIFO
has at least one byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half way point. The setting of this bit
prompts the user to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO
has at least one byte available. The setting of this bit prompts the
user to read the THIR register for details.
THALF
TNF
TMEND
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this bit
prompts the user to read the THIR register for details.
Note:
The RPE, RPS, and TMEND bits are latched and will be cleared when read.
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HIMR: HDLC INTERRUPT MASK REGISTER (Address=B2 Hex)
(MSB)
(LSB)
–
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
–
RPE
HIMR.7
HIMR.6
Not Assigned. Should be set to zero.
Receive Packet End.
0 = interrupt masked.
1 = interrupt enabled.
Receive Packet Start.
0 = interrupt masked.
1 = interrupt enabled.
Receive FIFO Half Full.
0 = interrupt masked.
1 = interrupt enabled.
Receive FIFO Not Empty.
0 = interrupt masked.
1 = interrupt enabled.
Transmit FIFO Half Empty.
0 = interrupt masked.
1 = interrupt enabled.
Transmit FIFO Not Full.
0 = interrupt masked.
1 = interrupt enabled.
Transmit Message End.
0 = interrupt masked.
RPS
RHALF
RNE
HIMR.5
HIMR.4
HIMR.3
HIMR.2
HIMR.1
HIMR.0
THALF
TNF
TMEND
1 = interrupt enabled.
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RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=B3 Hex)
(MSB)
(LSB)
RABT
RCRCE
ROVR
RVM
REMPTY
POK
CBYTE
OBYTE
SYMBOL
POSITION
NAME AND DESCRIPTION
RABT
RHIR.7
Abort Sequence Detected. Set whenever the HDLC controller
sees 7 or more ones in a row.
RCRCE
ROVR
RHIR.6
RHIR.5
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to write
a byte into an already full receive FIFO.
RVM
REMPTY
POK
RHIR.4
RHIR.3
RHIR.2
Valid Message. Set when the HDLC controller has detected and
checked a complete HDLC packet.
Empty. A real–time bit that is set high when the receive FIFO is
empty.
Packet OK. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a valid message (and
hence no abort was seen, no overrun occurred, and the CRC was
correct).
CBYTE
OBYTE
RHIR.1
RHIR.0
Closing Byte. Set when the byte available for reading in the
receive FIFO at RFDL is the last byte of a message (whether the
message was valid or not).
Opening Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the first byte of a message.
Note:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
RHFR: RECEIVE HDLC FIFO REGISTER (Address=B4 Hex)
(MSB)
(LSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
SYMBOL
POSITION
NAME AND DESCRIPTION
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
RHFR.7
RHFR.6
RHFR.5
RHFR.4
RHFR.3
RHFR.2
RHFR.1
RHFR.0
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
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THIR: TRANSMIT HDLC INFORMATION REGISTER (Address=B6 Hex)
(MSB)
(LSB)
–
–
–
–
–
EMPTY
TFULL
TUDR
SYMBOL
POSITION
NAME AND DESCRIPTION
–
–
–
–
–
THIR.7
THIR.6
THIR.5
THIR.4
THIR.3
THIR.2
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
TEMPTY
Transmit FIFO Empty. A real–time bit that is set high when
the FIFO is empty.
TFULL
TUDR
THIR.1
THIR.0
Transmit FIFO Full. A real–time bit that is set high when the
FIFO is full.
Transmit FIFO Underrun. Set when the transmit FIFO
unwantedly empties out and an abort is automatically sent.
Note:
The TUDR bit is latched and will be cleared when read.
THFR: TRANSMIT HDLC FIFO REGISTER (Address=B7 Hex)
(MSB)
(LSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
SYMBOL
POSITION
NAME AND DESCRIPTION
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
THFR.7
THFR.6
THFR.5
THFR.4
THFR.3
THFR.2
THFR.1
THFR.0
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
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RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address=B8 Hex)
(MSB)
(LSB)
RHS
RSaDS
RDS0M
POSITION
RDC1.7
RD4
RD3
RD2
RD1
RD0
SYMBOL
RHS
NAME AND DESCRIPTION
Receive HDLC source
0 = Sa bits defined by RCR2.3 to RCR2.7.
1 = Sa bits or DS0 channels defined by RDC1 (see bits defined
below).
RSaDS
RDC1.6
RDC1.5
Receive Sa Bit / DS0 Select.
0 = route Sa bits to the HDLC controller. RD0 to RD4 defines
which Sa bits are to be routed. RD4 corresponds to Sa4, RD3 to
Sa5, RD2 to Sa6, RD1 to Sa7 and RD0 to Sa8.
1 = route DS0 channels into the HDLC controller. RDC1.5 is
used to determine how the DS0 channels are selected.
DS0 Selection Mode.
RDS0M
0 = utilize the RD0 to RD4 bits to select which single DS0
channel to use.
1 = utilize the RCHBLK control registers to select which DS0
channels to use.
RD4
RD3
RD2
RD1
RD0
RDC1.4
RDC1.3
RDC1.2
RDC1.1
RDC1.0
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
DS0 Channel Select Bit 3.
DS0 Channel Select Bit 2.
DS0 Channel Select Bit 1.
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
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RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address=B9 Hex)
(MSB)
(LSB)
RDB8
SYMBOL
RDB8
RDB7
RDB6
RDB5
RDB4
RDB3
RDB2
RDB1
RDB7
RDB6
POSITION
RDC2.7
RDC2.6
RDC2.5
RDC2.4
RDC2.3
RDC2.2
RDC2.1
RDC2.0
RDB5
RDB4
RDB3
RDB2
RDB1
NAME AND DESCRIPTION
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop
this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop
this bit from being used.
TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = BA Hex)
(MSB)
THE
(LSB)
TD0
TSaDS
TDS0M
POSITION
TDC1.7
TD4
TD3
TD2
TD1
SYMBOL
NAME AND DESCRIPTION
Transmit HDLC Enable.
THE
0 = disable HDLC controller (no data inserted by HDLC
controller into the transmit data stream)
1 = enable HDLC controller to allow insertion of HDLC data
into either the Sa position or multiple DS0 channels as defined
by TDC1 (see bit definitions below).
TSaDS
TDC1.6
Transmit Sa Bit / DS0 Select. This bit is ignored if TDC1.7 is
set to zero.
0 = route Sa bits from the HDLC controller. TD0 to TD4 defines
which Sa bits are to be routed. TD4 corresponds to Sa4, TD3 to
Sa5, TD2 to Sa6, TD1 to Sa7 and TD0 to Sa8.
1 = route DS0 channels from the HDLC controller. TDC1.5 is
used to determine how the DS0 channels are selected.
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SYMBOL
POSITION
NAME AND DESCRIPTION
DS0 Selection Mode.
TDS0M
TDC1.5
0 = utilize the TD0 to TD4 bits to select which single DS0
channel to use.
1 = utilize the TCHBLK control registers to select which DS0
channels to use.
TD4
TD3
TD2
TD1
TD0
TDC1.4
TDC1.3
TDC1.2
TDC1.1
TDC1.0
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
DS0 Channel Select Bit 3.
DS0 Channel Select Bit 2.
DS0 Channel Select Bit 1.
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = BB Hex)
(MSB)
TDB8
(LSB)
TDB1
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
SYMBOL
TDB8
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
POSITION
NAME AND DESCRIPTION
TDC2.7
TDC2.6
TDC2.5
TDC2.4
TDC2.3
TDC2.2
TDC2.1
TDC2.0
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop
this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop
this bit from being used.
16. INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21Q44 can be configured to allow each framer’s data and
signaling busses to be multiplexed into higher speed data and signaling busses eliminating external
hardware saving board space and cost.
The interleaved PCM bus option supports two bus speeds and interleave modes. The 4.096 MHz bus
speed allows two framers to share a common bus. The 8.192 MHz bus speed allows all four of the
DS21Q44’s framers to share a common bus. Framers can interleave their data either on byte or frame
boundaries. Framers that share a common bus must be configured through software and require several
device pins to be connected together externally (see figures 16-1 & 16-2). Each framer’s elastic stores
must be enabled and configured for 2.048 MHz operation. The signal RSYNC must be configured as an
input on each framer.
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DS21Q44
For all bus configurations, one framer will be configured as the master device and the remaining framers
on the shared bus will be configured as slave devices. Refer to the IBO register description below for
more detail. In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 18-1
shows the DS21Q44 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus
2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are
programmed as slave devices. In the 8.192 MHz bus configuration there is one master and three slaves.
Figure 18-2 shows the DS21Q44 configured to support a 8.192 MHz bus. Framer 0 is programmed as the
master device. Framers 1, 2 and 3 are programmed as slave devices. Consult timing diagrams in section
18 for additional information.
When using the frame interleave mode, all framers that share an interleaved bus must have receive signals
(RPOS & RNEG) that are synchronous with each other. The received signals must originate from the
same clock reference. This restriction does not apply in the byte interleave mode.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = B5 Hex)
(MSB)
(LSB)
–
–
–
–
IBOEN
INTSEL
MSEL0
MSEL1
SYMBOL
POSITION
NAME AND DESCRIPTION
–
–
–
–
IBO.7
IBO.6
IBO.5
IBO.4
IBO.3
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Interleave Bus Operation Enable
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
Interleave Type Select
IBOEN
INTSEL
IBO.2
0 = Byte interleave.
1 = Frame interleave.
MSEL0
MSEL1
IBO.1
IBO.0
Master Device Bus Select Bit 0 See table 16-1.
Master Device Bus Select Bit 1 See table 16-1.
Master Device Bus Select Table 16-1
MSEL1
MSEL0
Function
0
0
1
1
0
1
0
1
Slave device.
Master device with 1 slave device (4.096 MHz bus rate)
Master device with 3 slave devices (8.192 MHz bus rate)
Reserved
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DS21Q44
4.096 MHz Interleaved Bus External Pin Connection Example Figure 16-1
FRAMER 0
FRAMER 1
FRAMER 2
FRAMER 3
RSYSCLK0
TSYSCLK0
RSYNC0
TSSYNC0
RSER0
RSYSCLK1
TSYSCLK1
RSYNC1
TSSYNC1
RSER1
RSYSCLK2
TSYSCLK2
RSYNC2
TSSYNC2
RSER2
RSYSCLK3
TSYSCLK3
RSYNC3
TSSYNC3
RSER3
TSER0
TSER1
TSER2
TSER3
RSIG0
RSIG1
RSIG2
RSIG3
TSIG0
TSIG1
TSIG2
TSIG3
SYSCLK
SYNC INPUT
RSER
SYSCLK
SYNC INPUT
RSER
TSER
TSER
RSIG
RSIG
TSIG
TSIG
Bus 2
Bus 1
8.192 MHz Interleaved Bus External Pin Connection Example Figure 16-2
FRAMER 0
FRAMER 1
FRAMER 2
FRAMER 3
RSYSCLK0
TSYSCLK0
RSYNC0
TSSYNC0
RSER0
RSYSCLK1
TSYSCLK1
RSYNC1
TSSYNC1
RSER1
RSYSCLK2
TSYSCLK2
RSYNC2
TSSYNC2
RSER2
RSYSCLK3
TSYSCLK3
RSYNC3
TSSYNC3
RSER3
TSER0
TSER1
TSER2
TSER3
RSIG0
RSIG1
RSIG2
RSIG3
TSIG0
TSIG1
TSIG2
TSIG3
SYSCLK
SYNC INPUT
RSER
TSER
RSIG
TSIG
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DS21Q44
17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
17.1 Description
The DS21Q44 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP,
and IDCODE. See Figure 17-1 for a block diagram. The DS21Q44 contains the following items which
meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The JTAG feature is only available when the DS21Q44 feature set is selected (FMS = 0). The JTAG
feature is disabled when the DS21Q44 is configured for emulation of the DS21Q43 (FMS = 1).
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and JTDO. See
the pin descriptions for details.
Boundary Scan Architecture Figure 17-1
Boundary Scan
Register
Identification
Register
Bypass
Register
MUX
Instruction
Register
Select
Test Access Port
Output Enable
Controller
+V
+V
+V
10K
10K
10K
JTDO
JTRST
JTDI
JTMS
JTCLK
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DS21Q44
17.2 TAP Controller State Machine
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine.
Please see Figure 17.2 for details on each of the states described below.
TAP Controller
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK.
Test-Logic-Reset
Upon power up of the DS21Q44, the TAP Controller will be in the Test-Logic-Reset state. The
Instruction register will contain the IDCODE instruction. All system logic of the DS21Q44 will operate
normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
Test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller
into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK
moves the controller to the Select-IR
Capture-DR
Data may be parallel-loaded into the Test Data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-
DR state if JTMS is low or it will go to the Exit1-DR state if JTMS is high.
Shift-DR
The Test Data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a Test Register
selected by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR
state, and terminate the scanning process. A rising edge on JTCLK with JTMS low will put the controller
in the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All Test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is low. A
rising edge on JTCLK with JTMS high will put the controller in the Exit2-DR state.
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DS21Q44
Exit2-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS low will enter the Shift-
DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of
the Test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle
state. With JTMS high, the controller will enter the Select-DR-Scan state.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this
state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-IR state and will
initiate a scan sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the
controller back into the Test-Logic-Reset state.
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller
will enter the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the
Shift-IR state.
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel registers, as well as
all Test registers remain at their previous states. A rising edge on JTCLK with JTMS high will move the
controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low will keep the controller in the
Shift-IR state while moving data one stage thorough the instruction shift register.
Exit1-IR
A rising edge on JTCLK with JTMS low will put the controller in the Pause-IR state. If JTMS is high on
the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning
process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS high, a rising edge on JTCLK
will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is
low during a rising edge on JTCLK.
Exit2-IR
A rising edge on JTCLK with JTMS low will put the controller in the Update-IR state. The controller will
loop back to Shift-IR if JTMS is high during a rising edge of JTCLK in this state.
Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the
falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the
current instruction. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle
state. With JTMS high, the controller will enter the Select-DR-Scan state.
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DS21Q44
TAP Controller State Machine Figure 17-2
Test Logic
Reset
1
0
1
1
1
Run Test/
Idle
Select
DR-Scan
Select
IR-Scan
0
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
1
0
1
1
1
Exit DR
Exit IR
0
0
Pause DR
Pause IR
0
0
1
1
0
0
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
0
0
1
1
17.3 Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift the data
one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-
IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS21Q44 with their respective operational binary codes are shown in Table 17-1.
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DS21Q44
Instruction Codes For The DS21Q44 IEEE 1149.1 Architecture Table 17-1
Instruction
Selected Register
Boundary Scan
Instruction Code
SAMPLE/PRELOAD
BYPASS
010
111
000
011
100
001
Bypass
EXTEST
CLAMP
HIGHZ
IDCODE
Boundary Scan
Boundary Scan
Boundary Scan
Device Identification
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS21Q44 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS21Q44 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS21Q44. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The next
11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits
for the device and 4 bits for the version. See Table 17-2. Table 17-3 lists the device ID codes for the
DS21Q42 and DS21Q44 devices.
ID Code Structure Table 17-2
MSB
Version
(Contact Factory)
LSB
“1”
Device ID
(See Table 17-3)
JEDEC
“00010100001”
Contents
Length
4 bits
16bits
11bits
1bit
76 of 105
DS21Q44
Device ID Codes Table 17-3
DEVICE
DS21Q42
DS21Q44
16-BIT NUMBER
0000h
0001h
HIGHZ
All digital outputs of the DS21Q44 will be placed in a high impedance state. The BYPASS register will
be connected between JTDI and JTDO.
CLAMP
All digital outputs of the DS21Q44 will output data from the boundary scan parallel output while
connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP
instruction.
17.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21Q44 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital
I/O cells and is 126 bits in length. Table 17-4 shows all of the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state.
Boundary Scan Register Description Table 17-4
DEVICE
PIN
SCAN
REGISTER BIT
SYMBOL
TYPE
CONTROL BIT
DESCRIPTION
1
2
3
4
5
6
7
8
81
80
79
78
77
76
75
74
TCHBLK0
TPOS0
O
O
O
O
O
I
TNEG0
RLINK0
RLCLK0
RCLK0
RNEG0
RPOS0
I
I
77 of 105
DS21Q44
DEVICE
PIN
SCAN
REGISTER BIT
SYMBOL
TYPE
CONTROL BIT
DESCRIPTION
9
10
11
-
73
72
71
70
RSIG0
O
O
I
RCHBLK0
RSYSCLK0
RSYNC0.cntl
-
0 = RSYNC0 an input
1 = RSYNC0 an output
12
13
14
15
16
17
18
19
20
-
69
68
-
RSYNC0
RSER0
I/O
O
-
-
-
O
I
I
O
-
VSS
VDD
-
67
66
-
65
64
63
SPARE1
RFSYNC0
JTRST*
TCLK0
TLCLK0
TSYNC0.cntl
0 = TSYNC0 an input
1 = TSYNC0 an output
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
TSYNC0
TLINK0
A0
I/O
I
I
I
I
I
I
I
I
O
I
I
I
I
O
O
O
O
O
I
A1
A2
A3
A4
A5
A6/ALE (AS)
INT*
TSYSCLK1
TSER1
TSSYNC1
TSIG1
TCHBLK1
TPOS1
TNEG1
RLINK1
RLCLK1
RCLK1
RNEG1
RPOS1
RSIG1
RCHBLK1
RSYSCLK1
A7
I
I
O
O
I
I
I
FMS
78 of 105
DS21Q44
DEVICE
PIN
SCAN
REGISTER BIT
SYMBOL
TYPE
CONTROL BIT
DESCRIPTION
-
35
RSYNC1.cntl
-
0 = RSYNC1 an input
1 = RSYNC1 an output
48
49
50
51
52
53
54
-
34
33
-
32
-
31
30
29
RSYNC1
RSER1
JTMS
RFSYNC1
JTCLK
TCLK1
I/O
O
I
O
I
I
O
-
TLCLK1
TSYNC1.cntl
0 = TSYNC1 an input
1 = TSYNC1 an output
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
-
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
TSYNC1
TLINK1
TEST
I/O
I
I
I
I
I
I
I
I
I
I
I
I
FS0
FS1
CS*
BTS
RD*/(DS*)
WR*/(R/W*)
MUX
TSYSCLK2
TSER2
TSSYNC2
TSIG2
TCHBLK2
TPOS2
I
O
O
O
O
O
I
I
I
O
-
-
TNEG2
RLINK2
RLCLK2
RCLK2
RNEG2
RPOS2
RSIG2
VSS
VDD
8
7
6
-
-
5
4
3
RCHBLK2
RSYSCLK2
RSYNC2.cntl
O
I
-
0 = RSYNC2 an input
1 = RSYNC2 an output
82
83
84
85
2
1
-
RSYNC2
RSER2
JTDI
RFSYNC2
I/O
O
I
0
O
79 of 105
DS21Q44
DEVICE
PIN
SCAN
REGISTER BIT
SYMBOL
TYPE
CONTROL BIT
DESCRIPTION
86
87
88
-
-
JTDO
TCLK2
TLCLK2
O
I
O
-
125
124
123
TSYNC2.cntl
0 = TSYNC2 an input
1 = TSYNC2 an output
89
90
91
92
93
94
95
96
97
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
TSYNC2
TLINK2
TSYSCLK3
TSER3
TSSYNC3
TSIG3
TCHBLK3
TPOS3
TNEG3
RLINK3
RLCLK3
RCLK3
RNEG3
RPOS3
I/O
I
I
I
I
I
O
O
O
O
O
I
I
I
O
O
I
98
99
100
101
102
103
104
105
-
RSIG3
RCHBLK3
RSYSCLK3
RSYNC3.cntl
-
0 = RSYNC3 an input
1 = RSYNC3 an output
106
107
108
109
110
111
112
113
114
-
104
103
102
101
-
RSYNC3
RSER3
8MCLK
RFSYNC3
VSS
VDD
CLKSI
TCLK3
TLCLK3
TSYNC3.cntl
I/O
O
O
O
-
-
I
I
O
-
-
100
99
98
97
0 = TSYNC3 an input
1 = TSYNC3 an output
115
116
-
96
95
94
TSYNC3
TLINK3
BUS.cntl
I/O
I
-
0 = D0-D7 or AD0-AD7 are
inputs
1 = D0-D7 or AD0-AD7 are
outputs
117
118
119
93
92
91
D0 or AD0
D1 or AD1
D2 or AD2
I/O
I/O
I/O
80 of 105
DS21Q44
DEVICE
PIN
SCAN
REGISTER BIT
SYMBOL
TYPE
CONTROL BIT
DESCRIPTION
120
121
122
123
124
125
126
127
128
90
89
88
87
86
85
84
83
82
D3 or AD3
D4 or AD4
D5 or AD5
D6 or AD6
D7 or AD7
TSYSCLK0
TSER0
I/O
I/O
I/O
I/O
I/O
I
I
I
I
TSSYNC0
TSIG0
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DS21Q44
18. TIMING DIAGRAMS
RECEIVE SIDE TIMING Figure 18-1
14 15 16
1
2
6
7
8
9
10 11 12 13 14 15 16
1
2
6
3
4
5
3
4
5
FRAME#
1
RSYNC /
RFSYNC
2
3
RSYNC
RLCLK
4
RLINK
Notes:
1. RSYNC in the frame mode (RCR1.6 = 0)
2. RSYNC in the multiframe mode (RCR1.6 = 1)
3. RLCLK is programmed to output just the Sa4 bit
4. RLINK will always output all five Sa bits as well as the rest of the receive data stream
5. This diagram assumes the CAS MF begins with the FAS word
RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) Figure 18-2
RCLK
CHANNEL 1
CHANNEL 2
CHANNEL 1
1
RPOS, RNEG
LSB
LSB Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 32
CHANNEL 2
RSER
MSB
LSB Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
RSYNC / RFSYNC
RSIG
CHANNEL 32
CHANNEL 1
CHANNEL 2
B
A
C
Sa5
D
Note 5
RCHCLK
2
RCHBLK
RLINK
Sa4 Sa5 Sa6 Sa7 Sa8
3
RLCLK
Notes:
1. There is a 6 RCLK delay from RPOS, RNEG to RSER
2. RCHBLK is programmed to block channel 2
3. RLINK is programmed to output the Sa4 bit
4. Shown is a non-align frame boundary
5. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1
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DS21Q44
RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 18-3
RSYSCLK
CHANNEL 23/31
CHANNEL 24/32
CHANNEL 1/2
1
LSB MSB
MSB
LSB
F
RSER
2
RSYNC / RMSYNC
3
RSYNC
RCHCLK
4
RCHBLK
Notes:
1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is
mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one)
2. RSYNC is in the output mode (RCR1.5 = 0)
3. RSYNC is in the input mode (RCR1.5 = 1)
4. RCHBLK is programmed to block channel 24
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 18-4
RSYSCLK
CHANNEL 31
CHANNEL 32
CHANNEL 1
LSB MSB
LSB MSB
RSER
1
RSYNC / RMSYNC
2
RSYNC
CHANNEL 31
CHANNEL 32
CHANNEL 1
A
C
D
A
B
B
C
D
RSIG
Note 4
RCHCLK
RCHBLK
3
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0)
2. RSYNC is in the input mode (RCR1.5 = 1)
3. RCHBLK is programmed to block channel 1
4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1
83 of 105
DS21Q44
RECEIVE SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING
Figure 18-5
RSYNC
1
RSER
FR1 CH32
FR1 CH32
FR0 CH1
FR0 CH1
FR1 CH1
FR1 CH1
FR0 CH2
FR0 CH2
FR1 CH2
FR1 CH2
1
RSIG
2
RSER
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
2
RSIG
BIT DETAIL
SYSCLK
3
RSYNC
FRAMER 1, CHANNEL 1
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
D/B
LSB MSB
LSB
D/B
RSER
FRAMER 1, CHANNEL 1
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
A
A
A
B
C/A
D/B
B
C/D
B
C/D
RSIG
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 1).
84 of 105
DS21Q44
RECEIVE SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 18-6
RSYNC
1
FR0 CH1-32
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR0 CH1-32
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR1 CH1-32
RSER
1
FR1 CH1-32
RSIG
2
RSER
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32
2
RSIG
BIT DETAIL
SYSCLK
3
RSYNC
FRAMER 0, CHANNEL 2
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
D/B
LSB
D/B
LSB MSB
RSER
FRAMER 0, CHANNEL 2
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
A
A
A
B
C/A
D/B
B
C/D
B
C/D
RSIG
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 1).
TRANSMIT SIDE TIMING Figure 18-7
TRANSMIT SIDE TIMING Figure 13.5
FRAME#
14 15 16
1
2
6
7
8
9
10 11 12 13 14 15 16
1
2
6
3
4
5
3
4
5
1
TSYNC
2
TSYNC
TLCLK
TLINK
3
3
Notes:
1. TSYNC in the frame mode (TCR1.1 = 0)
2. TSYNC in the multiframe mode (TCR1.1 = 1)
3. TLINK is programmed to source just the Sa4 bit
4. This diagram assumes both the CAS MF and the CRC4 begin with the align frame
85 of 105
DS21Q44
TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) Figure 18-8
TCLK
CHANNEL 1
CHANNEL 2
Sa4 Sa5 Sa6 Sa7 Sa8
A
MSB
LSB MSB
LSB
Si
1
TSER
CHANNEL 32
CHANNEL 1
1
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
A
MSB
LSB
Si
1
TPOS, TNEG
2
TSYNC
3
TSYNC
TSIG
CHANNEL 1
CHANNEL 2
A
B
B
C
D
C
D
Note 6
TCHCLK
TCHBLK
TLCLK
TLINK
4
5
5
Don't Care
Don't Care
Notes:
1. There is a 5 TCLK delay from TSER to TPOS and TNEG
2. TSYNC is in the input mode (TCR1.0 = 0)
3. TSYNC is in the output mode (TCR1.0 = 1)
4. TCHBLK is programmed to block channel 2
5. TLINK is programmed to source the Sa4 bits
6. The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with
the CAS multiframe alignment nibble (0000)
7. Shown is a non-align frame boundary
TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 18-9
TSYSCLK
CHANNEL 23
CHANNEL 24
CHANNEL 1
LSB
MSB
LSB MSB
TSER
TSSYNC
TCHCLK
TCHBLK1
F-Bit
Notes:
1. TCHBLK is programmed to block channel 23
2. The F-bit position is ignored by the DS2154
86 of 105
DS21Q44
TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 18-10
TSYSCLK
CHANNEL 31
CHANNEL 32
CHANNEL 1
CHANNEL 1
LSB MSB
LSB MSB
TSER
TSSYNC
TSIG
CHANNEL 31
CHANNEL 32
A
B
A
C
C
D
B
D
A
TCHCLK
TCHBLK1
Notes:
1. TCHBLK is programmed to block channel 31
G.802 TIMING Figure 18-11
G.802 TIMING Figure 13.9
TIMESLOT #
3031 0 1 2 3 4 5 6 7 8 910111213141516171819202122232425262728293031 0 1 2 3 4
RSYNC/TSYNC
RCHCLK/TCHCLK
1
RCHBLK/TCHBLK
Notes:
1. RCHBLK or TCHBLK is programmed to pulse high during timeslots
1 to 15, 17 to 25, and during bit 1 of timeslot 26
detail
RCLK / RSYSCLK
TCLK / TSYSCLK
Timeslot 25
Timeslot 26
RSER/TSER
RCHCLK/TCHCLK
RCHBLK/TCHBLK
LSB MSB
87 of 105
DS21Q44
TRANSMIT SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING
Figure 18-12
TSSYNC
1
FR1 CH32
FR0 CH1
FR0 CH1
FR1 CH1
FR1 CH1
FR0 CH2
FR0 CH2
FR1 CH2
FR1 CH2
TSER
1
FR1 CH32
TSIG
2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
TSER
2
TSIG
BIT DETAIL
SYSCLK
TSSYNC
TSER
FRAMER 1, CHANNEL 1
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
D/B
LSB MSB
LSB
D/B
FRAMER 1, CHANNEL 1
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
A
A
A
B
C/A
D/B
B
C/D
B
C/D
TSIG
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
88 of 105
DS21Q44
TRANSMIT SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 18-13
TSSYNC
1
FR0 CH1-32
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR0 CH1-32
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR1 CH1-32
TSER
1
FR1 CH1-32
TSIG
TSER2
TSIG2
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32
BIT DETAIL
SYSCLK
TSSYNC
TSER
FRAMER 0, CHANNEL 2
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
D/B
LSB
D/B
LSB MSB
FRAMER 0, CHANNEL 2
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
A
A
A
B
C/A
D/B
B
C/D
B
C/D
TSIG
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
89 of 105
DS21Q44
DS21Q44 FRAMER SYNCHRONIZATION FLOWCHART Figure 18-14
Power Up
RLOS = 1
FAS Search
FASSA = 1
RLOS = 1
FAS Sync
Criteria Met
FASSA = 0
Resync if
RCR1.0 = 0
Increment CRC4
Sync Counter;
CRC4SA = 0
8ms
Time
Out
CRC4 Multiframe Search
(if enabled via CCR1.0)
CRC4SA = 1
CAS Multiframe Search
(if enabled via CCR1.3)
CASSA = 1
CAS Sync
Criteria Met
CASSA = 0
CRC4 Sync Criteria
Met; CRC4SA = 0;
Reset CRC4
Sync Declared
RLOS = 0
Sync Counter
Set FASRC
(RIR.1)
Check for FAS
Framing Error
(depends on RCR1.2)
FAS Resync
Criteria Met
Check for >=915
Out of 1000
CRC4 Word Errors
If CRC4 is on
(CCR1.0 = 1)
CRC4 Resync
Criteria Met
(RIR.2)
CAS Resync
Criteria Met;
Set CASRC
(RIR.0)
If CAS is on
(CCR1.3 = 0)
Check for CAS
MF Word Error
90 of 105
DS21Q44
DS21Q44 TRANSMIT DATA FLOW Figure 18-15
TSER
HDLC
ENGINE
RSER
(note #1)
&
TDATA
TSIG
1
TLINK
TCBR1/2/3/4
0
Hardware
Signaling
Insertion
CCR3.5
CCR3.2
TNAF.0-4
0
0
1
1
SaDataSource
MUX
(TDC1)
DS0 Data
Source MUX
(TDC1/2)
TAF
TNAF.5-7
1
TC1 to TC32
1
0
0
Per-Channel Code
TAF/TNAF Bit
MUX
Generation
(TCC1/2/3/4)
0
1
Timeslot 0
Pass-Through
(TCR1.6)
1
0
Si Bit Insertion
Control
(TCR1.3)
Receive Side
CRC4 Error
Detector
CRC4 Multiframe
Alignment Word
Generation (CCR.4)
0
1
E-Bit Generation
(TCR2.1)
0
1
Sa Bit Insertion
Control (TCR2.3
thruTCR2.7)
TSiAF
TSiNAF
TRA
TIDR
0
1
TSa4toTSa8
AutoRemoteAlarm
Generation (CCR2.4)
TIRFunction Select
(CCR3.5)
0
1
Sa Bit Insertion
Control Register
(TSaCR)
AIS
Generation
TS1 toTS16
0
1
Idle Code / Channel
InsertionControl via
TIR1/2/3/4
0
1
Transmit Signaling
All Ones
(TCR1.2)
TCBR1/2/3/4
CCR3.6
0
1
Signaling Bit
InsertionControl
Code Word
Generation
TCR1.5
0
1
CRC4 Enable
(CCR1.4)
KEY:
AIS
Generation
= Register
DS0 Monitor
0
= Device Pin
= Selector
1
Transmit Unframed All
Ones (TCR1.4) or
Auto AIS (CCR2.5)
NOTES:
1. TCLKshouldbetiedtoRCLKandTSYNCshouldbetiedtoRFSYNCfor
data to be properly sourced fromRSER.
2. Auto Remote Alarmif enabled will only overwrite bit 3 of timeslot 0 in the
TPOS,
TNEG
Not Align Frames if the alarmneeds to be sent.
91 of 105
DS21Q44
19. OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Non-Supply Pin Relative to Ground
Supply Voltage
Operating Temperature for DS21Q44T
Operating Temperature for DS21Q44TN
Storage Temperature
–1.0V to +5.5V
–.3V to +3.63V
0ºC to 70ºC
–40ºC to +85ºC
–55ºC to +125ºC
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0ºC to 70ºC for DS21Q44T;
0ºC to +85ºC for DS21Q44TN)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Logic 1
Logic 0
Supply
VIH
VIL
VDD
2.0
–0.3
2.97
5.5
+0.8
3.63
V
V
V
CAPACITANCE
(tA =25ºC)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
Output Capacitance
CIN
COUT
5
7
pF
pF
DC CHARACTERISTICS
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q44T;
-40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q44TN)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Current @ 3.3V
Input Leakage
Output Leakage
Output Current (2.4V)
Output Current (0.4V)
IDD
IIL
ILO
IOH
IOL
75
mA
µA
µA
mA
mA
1
2
3
–1.0
+1.0
1.0
–1.0
+4.0
Notes:
1. TCLK=RCLK=TSYSCLK=RSYSCLK=2.048 MHz; outputs open circuited.
2. 0.0V < V IN < V DD .
3. Applied to INT* when 3–stated.
92 of 105
DS21Q44
AC CHARACTERISTICS – MULTIPLEXED
PARALLEL PORT (MUX=1)
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q44T
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q44TN)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Cycle Time
Pulse Width, DS low or
RD* high
t CYC
PW EL
200
100
ns
ns
Pulse Width, DS high or
RD* low
PW EH
100
ns
Input Rise/Fall times
R/W* Hold Time
R/W* Set Up time
before DS high
t R , t F
t RWH
t RWS
20
ns
ns
ns
10
50
CS*, FSO or FS1 Set
Up time before DS,
WR* or RD* active
CS*, FSO or FS1 Hold
time
t CS
20
0
ns
ns
t CH
Read Data Hold time
Write Data Hold time
Muxed Address valid to
AS or ALE fall
t DHR
t DHW
t ASL
10
0
15
50
ns
ns
ns
Muxed Address Hold
time
Delay time DS, WR* or
RD* to AS or ALE rise
Pulse Width AS or ALE
high
Delay time, AS or ALE
to DS, WR* or RD*
Output Data Delay time
from DS or RD*
Data Set Up time
t AHL
t ASD
10
20
30
10
20
50
ns
ns
ns
ns
ns
ns
PW ASH
t ASED
t DDR
80
t DSW
See Figures 19-1 to 19-3 for details.
93 of 105
DS21Q44
AC CHARACTERISTICS – NON–MULTIPLEXED
PARALLEL PORT (MUX=0 )
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q44T;
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q44TN)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Set Up Time for A0 to
A7, FS0 or FS1 Valid to
CS* Active
t 1
0
ns
Set Up Time for CS*
Active to either RD*,
WR*, or DS* Active
Delay Time from either
RD* or DS* Active to
Data Valid
Hold Time from either
RD*, WR*, or DS*
Inactive to CS* Inactive
Hold Time from CS*
Inactive to Data Bus 3–
state
Wait Time from either
WR* or DS* Active to
Latch Data
Data Set Up Time to
either WR* or DS*
Inactive
t 2
t 3
t 4
t 5
t 6
t 7
t 8
t 9
0
ns
ns
ns
ns
ns
ns
ns
ns
75
20
0
5
75
10
10
10
Data Hold Time from
either WR* or DS*
Inactive
Address Hold from
either WR* or DS*
inactive
See Figures 19–4 to 19–7 for details.
94 of 105
DS21Q44
AC CHARACTERISTICS – RECEIVE SIDE
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q44T;
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q44TN)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
RCLK Period
RCLK Pulse Width
t CP
t CH
t CL
t SP
t SP
488
ns
ns
ns
ns
ns
ns
ns
ns
75
75
122
122
50
RSYSCLK Period
648
488
1
2
RSYSCLK Pulse Width
t SH t SL
50
20
RSYNC Set Up to
t SU
t SH –5
RSYSCLK Falling
RSYNC Pulse Width
RPOS/RNEG Set UP to
RCLK Falling
t PW
t SU
50
20
ns
ns
RPOS/RNEG Hold From
RCLK Falling
RSYSCLK/RCLKI Rise
and Fall Times
t HD
t R , t F
t D1
20
ns
ns
ns
ns
25
50
50
Delay RCLK to RSER,
RSIG, RLINK Valid
Delay RCLK to RCHCLK,
RSYNC, RCHBLK,
RFSYNC, RLCLK
Delay RSYSCLK to
RSER, RSIG Valid
Delay RSYSCLK to
RCHCLK, RCHBLK,
RMSYNC, RSYNC
t D2
t D3
t D4
50
50
ns
ns
See Figures 19-8 to 18-10 for details.
Notes:
1. RSYSCLK = 1.544 MHz.
2. RSYSCLK = 2.048 MHz.
95 of 105
DS21Q44
AC CHARACTERISTICS – TRANSMIT SIDE
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q44T;
–40ºC to +85ºC; ; VDD = 2.97 to 3.63V for DS21Q44TN)
PARAMETER
TCLK Period
SYMBOL
t CP
MIN
TYP
488
MAX
UNITS
ns
NOTES
TCLK Pulse Width
t CH
t CL
75
75
ns
ns
TCLKI Pulse Width
TSYSCLK Period
t LH
t LL
t SP
t SP
75
75
122
122
50
ns
ns
ns
ns
648
448
1
2
TSYSCLK Pulse Width
t SH
ns
t SL
50
ns
TSYNC or TSSYNC Set
Up to TCLK or TSYSCLK
falling
t SU
20
t CH –5
or
t SH –5
ns
TSYNC or TSSYNC Pulse
Width
TSER, TSIG, TLINK Set
Up to TCLK, TSYSCLK
Falling
t PW
t SU
50
20
ns
ns
TSER, TSIG, TLINK Hold
from TCLK, TSYSCLK
Falling
t HD
20
ns
TCLK or TSYSCLK Rise
and Fall Times
Delay TCLK to TPOS,
TNEG Valid
Delay TCLK to TCHBLK,
TCHBLK, TSYNC,
TLCLK
t R , t F
t DD
25
50
50
ns
ns
ns
t D2
Delay TSYSCLK to
TCHCLK, TCHBLK
t D3
75
ns
See Figures 19–11 to 19–13 for details.
Notes:
1. TSYSCLK = 1.544 MHz.
2. TSYSCLK = 2.048 MHz.
96 of 105
DS21Q44
INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) Figure 19-1
t
CYC
ALE
PW
ASH
t
ASD
WR*
t
ASED
t
ASD
PW
EH
RD*
CS*
t
t
CH
PW
EL
CS
t
t
ASL
t
DHR
DDR
AD0-AD7
t
AHL
INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 19-2
t
CYC
ALE
PW
ASH
t
ASD
t
RD*
ASED
t
ASD
PW
EH
t
WR*
CS*
t
CH
CS
PW
EL
t
t
ASL
DHW
AD0-AD7
t
t
AHL
DSW
97 of 105
DS21Q44
MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) Figure 19-3
PW
ASH
AS
PW
EH
t
t
ASD
ASED
DS
PW
EL
t
CYC
t
t
RWS
RWH
R/W*
t
DDR
t
t
ASL
DHR
AD0-AD7
(read)
t
t
t
CH
AHL
CS
CS*
t
DSW
t
ASL
t
AD0-AD7
(write)
t
DHW
AHL
INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 19-4
A0 to A7,
FS0, FS1
Address Valid
Data Valid
D0 to D7
WR*
t5
5ns min. / 20ns max.
t1
0ns min.
t2
CS*
t3
t4
0ns min.
0ns min.
75ns max.
RD*
98 of 105
DS21Q44
INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0) Figure 19-5
A0 to A7,
FS0, FS1
Address Valid
D0 to D7
t7
t8
10ns 10ns
min. min.
RD*
CS*
WR*
t1
0ns min.
t2
t6
t4
0ns min.
0ns min.
75ns min.
MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0) Figure 19-6
MOTOROLA BUS READ AC TIMING (BTS = 1 / MUX = 0) Figure 16.12
A0 to A7,
FS0, FS1
Address Valid
Data Valid
D0 to D7
t5
5ns min. / 20ns max.
R/W*
t1
0ns min.
CS*
t2
t2
t3
t4
t4
0ns min.
0ns min.
0ns min.
0ns min.
75ns max.
DS*
t3
75ns max.
1
DS
Notes:
1. The signal DS is active high when emulating the DS21Q43 (FMS = 1)
.
99 of 105
DS21Q44
MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0) Figure 19-7
A0 to A7,
FS0, FS1
Address Valid
D0 to D7
R/W*
CS*
10ns
min.
10ns
min.
t7
t8
t1
0ns min.
t4
t2
t2
t6
0ns min.
0ns min.
75ns min.
DS*
t6
0ns min.
75ns min.
1
DS
Notes:
1. The signal DS is active high when emulating the DS21Q43 (FMS = 1)
.
100 of 105
DS21Q44
RECEIVE SIDE AC TIMING Figure 19-8
RECEIVE SIDE AC TIMING Figure 14.4
RCLK
t
D1
MSB of
Channel 1
RSER / RSIG
RCHCLK
t
D2
t
D2
RCHBLK
t
t
D2
D2
RFSYNC / RMSYNC
1
RSYNC
t
D2
2
RLCLK
t
D1
Sa4 to Sa8
Bit Position
RLINK
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0).
2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship
between RLCLK and RSYNC or RFSYNC is implied.
101 of 105
DS21Q44
RECEIVE SYSTEM SIDE AC TIMING Figure 19-9
t
t
SL
SH
t
t
F
R
RSYSCLK
t
t
SP
D3
MSB of
Channel 1
RSER/ RSIG
t
D4
RCHCLK
RCHBLK
t
D4
t
t
D4
D4
RMSYNC
1
RSYNC
t
HD
t
SU
2
RSYNC
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0)
2. RSYNC is in the input mode (RCR1.5 = 1)
RECEIVE LINE INTERFACE AC TIMING Figure 19-10
t
t
CL
CH
t
t
F
R
RCLK
t
CP
t
SU
RPOS, RNEG
t
HD
102 of 105
DS21Q44
TRANSMIT SIDE AC TIMING Figure 19-11
t
CP
t
t
CL
CH
t
t
F
R
TCLK
t
SU
TSER / TSIG
t
t
HD
D2
TCHCLK
TCHBLK
t
D2
t
D2
t
1
TSYNC
TSYNC
t
HD
SU
2
t
D2
5
TLCLK
t
HD
TLINK
Notes:
t
SU
1. TSYNC is in the output mode (TCR1.0 = 1).
2. TSYNC is in the input mode (TCR1.0 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between
TLCLK/TLINK and TSYNC is implied.
103 of 105
DS21Q44
TRANSMIT SYSTEM SIDE AC TIMING Figure 19-12
t
SP
t
t
SL
SH
t
t
F
R
TSYSCLK
TSER
t
SU
t
t
D3
HD
TCHCLK
TCHBLK
t
D3
t
HD
t
SU
TSSYNC
Notes:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 19-13
t
CP
t
t
CL
CH
t
t
R
F
TCLK
TPOS, TNEG
t
DD
104 of 105
DS21Q44
20. 128-Pin TQFP Package Specifications
105 of 105
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