DS2251T [DALLAS]
128k Soft Microcontroller Module; 128K软微控制器模块
| 型号： | DS2251T |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 128k Soft Microcontroller Module |
| 文件： | 总20页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2251(T)
128k Soft Microcontroller Module
www.dalsemi.com
FEATURES
ꢀ 8051-compatible microcontroller adapts to its
PIN ASSIGNMENT
task
-
-
-
-
-
32K, 64K, or 128K bytes of nonvolatile
SRAM for program and/or data storage
In-system programming via on-chip serial
port
Capable of modifying its own program or
data memory in the end system
Provides separate Byte-wide bus for
peripherals
Performs CRC-16 check of NV RAM
memory
ꢀ High-reliability operation
-
Maintains all nonvolatile resources for
over 10 years in the absence of power
Power-fail reset
Early Warning Power-fail Interrupt
Watchdog Timer
Lithium backed memory remembers
system state
-
-
-
-
-
Precision reference for power monitor
ꢀ Fully 8051-compatible
-
-
-
-
128 bytes scratchpad RAM
Two timer/counters
On-chip serial port
32 parallel I/O port pins
ꢀ Permanently powered real time clock
72-Pin SIMM
DESCRIPTION
The DS2251T 128k Soft Microcontroller Module is an 8051-compatible microcontroller module based on
nonvolatile RAM technology. It is designed for systems that need large quantities of nonvolatile memory.
Like other members of the Secure Microcontroller family, it provides full compatibility with the 8051
instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can
program, then reprogram the microcontroller while in-system. The application software can even change
its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc.
In addition, by using NV RAM, the DS2251T is ideal for data logging applications. The powerful real
time clock includes interrupts for time stamp and date. It keeps time to one-hundredth of seconds using its
onboard 32 kHz crystal.
1 of 20
011800
DS2251T
The DS2251T provides the benefits of NV RAM without using I/O resources. Between 32 kbytes and 128
kbytes of onboard NV RAM are available. A non-multiplexed Byte-wide address and data bus is used for
memory access. This bus, which is available at the connector, can perform all memory access and also
provide decoded chip enables for off-board memory mapped peripherals. This leaves the 32 I/O port pins
free for application use.
The DS2251T provides high-reliability operation in portable systems or systems with unreliable power.
These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and
Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room
temperature in the absence of power.
A user loads programs into the DS2251T via its on-chip serial Bootstrap loader. This function supervises
the loading of software into NV RAM, validates it, then becomes transparent to the user. Software is
stored in onboard CMOS SRAM. Using its internal Partitioning, the DS2251T can divide a common
RAM into user-selectable program and data segments. This Partition can be selected at program loading
time, but can be modified anytime later. The microprocessor will decode memory access to the SRAM,
access memory via its Byte-wide bus and write-protect the memory portion designated as program
(ROM).
ORDERING INFORMATION
MAX CRYSTAL
PART NUMBER
RAM SIZE
TIMEKEEPING?
SPEED
16 MHz
16 MHz
16 MHz
DS2251T-32-16
DS2251T-64-16
DS2251T-128-16
32 kbytes
64 kbytes
128 kbytes
Yes
Yes
Yes
Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book.
This data sheet provides ordering information, pinout, and electrical specifications.
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DS2251T
DS2251(T) BLOCK DIAGRAM Figure 1
3 of 20
DS2251T
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
19 XTAL2
20 GND
21 P2.0
22 P2.1
23 P2.2
24 P2.3
25 P2.4
26 P2.5
27 P2.6
28 P2.7
37 P0.2
38 P0.1
39 P0.0
40 VCC
41 BA0
42 BA1
43 BA2
44 BA3
45 BA4
46 BA5
47 BA6
48 BA7
49 BA8
50 BA9
51 BA10
52 BA11
53 BA12
54 BA13
55
INTB
56 BD0
57 BD1
58 BD2
59 BD3
60 BD4
61 BD5
62 BD6
63 BD7
10 P3.0 RXD
11 P3.1 TXD
64
65
66
67
68
69
R/ W
PF
29
30 ALE
31
PSEN
12
13
P3.2 INT0
P3.3 INT1
PE3
PROG
PE4
14 P3.4 T0
15 P3.5 T1
32 P0.7
33 P0.6
34 P0.5
35 P0.4
36 P0.3
INTP
INTA
16
17
70 SQW
P3.6 WR
P3.7 RD
71
VRST
18 XTAL1
72 BA15
PIN DESCRIPTION
PIN
DESCRIPTION
39-32
P0.0 - P0.7. General purpose I/O Port 0. This port is open-drain and cannot drive a logic 1.
It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus.
When used in this mode, it does not require pullups.
1-8
P1.0 - P1.7. General purpose I/O Port 1.
21-28
P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address
bus.
10
11
12
13
P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on-
board UART. This pin should NOT be connected directly to a PC COM port.
P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on-
board UART. This pin should NOT be connected directly to a PC COM port.
P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External
Interrupt 0.
P3.3 INT1 . General purpose I/O port pin 3.3. Also serves as the active low External
Interrupt 1.
14
15
P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
4 of 20
DS2251T
PIN
DESCRIPTION
16
P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded bus
operation.
17
9
P3.7 RD . General purpose I/O port pin. Also serves as the read strobe for Expanded bus
operation.
RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This
pin is pulled down internally, can be left unconnected if not used. An RC power-on reset
circuit is not needed and is NOT recommended.
29
30
PSEN - Program Store Enable. This active low signal is used to enable an external program
memory when using the Expanded bus. It is normally an output and should be unconnected
if not used.
ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded
Address/Data bus on Port 0. This pin is normally connected to the clock input on a ‘373
type transparent latch.
19, 18 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
20
40
72
GND - Logic ground.
VCC - +5V.
BA15 - Monitor test point to reflect the logical value of A15. Not needed for memory
access.
54-41
BA13 - 0. Byte-wide Address bus bits 13-0. This bus is combined with the non-multiplexed
data bus (BD7-0) to access onboard NV SRAM and off-board peripherals. Peripheral
decoding is performed using PE3 and PE4 . These are on 16k boundaries, so BA14 or BA15
are not needed. Read/write access is controlled by R/ W . BA13-0 connect directly to
memory mapped peripherals.
63-56
64
BD7 - 0. Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the
non-multiplexed address bus (BA14-0) to access on-board NV SRAM and off-board
peripherals.
R/ W - Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide
bus. It is controlled by the memory map and Partition. The blocks selected as Program
(ROM) will be write-protected. This signal is also used for the write enable to off-board
peripherals.
66
67
31
PE3 - Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any
type of peripheral function.
PE4 - Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any
type of peripheral function.
PROG - Invokes the Bootstrap loader on a falling edge. This signal should be debounced so
that only one edge is detected. If connected to ground, the micro will enter Bootstrap
loading on power-up. This signal is pulled up internally.
5 of 20
DS2251T
PIN
DESCRIPTION
71
VRST - This I/O pin (open-drain with internal pullup) indicates that the power supply (VCC)
has fallen below the VCCMIN level and the micro is in a reset state. When this occurs, the
DS2251T will drive this pin to a logic 0. Because the micro is lithium backed, this signal is
guaranteed even when VCC=0V. Because it is an I/O pin, it will also force a reset if pulled
low externally. This allows multiple parts to synchronize their power-down resets.
65
PF - This output goes to a logic 0 to indicate that the micro has switched to lithium backup.
It corresponds to VCC < VLI. Because the micro is lithium backed, this signal is guaranteed
even when VCC=0V.
55
68
69
70
INTB - INTB from the real time clock. This output may be connected to a micro interrupt
input.
INTP - INTP from the real time clock. This open-drain output requires a pullup and may be
connected to a micro interrupt input.
INTA - INTA from the real time clock. This output may be connected to a micro interrupt
input.
SQW - SQW output from the DS1283 Real Time Clock. Can be programmed to output an
1024 Hz square wave.
INSTRUCTION SET
The DS2251T executes an instruction set that is object code compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS2251T.
A complete description of the instruction set and operation are provided in the User’s Guide section of the
Secure Microcontroller Data Book.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the DS2251T. The entire 64k of program and 64k of
data are available to the Byte-wide bus. This preserves the I/O ports for application use. The user controls
the portion of memory that is actually mapped to the Byte-wide bus by selecting the Program Range and
Data Range. Any area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 and 2.
An alternate configuration allows dynamic Partitioning of a 64k space as shown in Figure 3. Selecting
PES=1 provides access to the real time clock on the DS2251T and enables PE3 and PE4 for peripheral
access as shown in Figure 4. These selections are made using Special Function Registers. The memory
map and its controls are covered in detail in the User’s Guide section of the Secure Microcontroller Data
Book.
6 of 20
DS2251T
DS2251T MEMORY MAP IN NON-PARTITIONABLE MODE (PM=1) Figure 2
DS2251T MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3
7 of 20
DS2251T
DS2251T MEMORY MAP WITH (PES=1) Figure 4
POWER MANAGEMENT
The DS2251T monitors VCC to provide Power-fail Reset, early warning Power-fail Interrupt, and switch-
over to lithium backup. It uses an internal band-gap reference in determining the switch points. These are
called VPFW, VCCMIN, and VLI respectively. When VCC drops below VPFW, the DS2251T will perform an
interrupt vector to location 2Bh if the power-fail warning is enabled. Full processor operation continues
regardless. When power falls further to VCCMIN, the DS2251T invokes a reset state. No further code
execution will be performed unless power rises back above VCCMIN. All decoded chip enables and the
R/ W signal go to an inactive (logic 1) state. The VRST signal will be driven to a logic 0. VCC is still the
power source at this time. When VCC drops further to below VLI, internal circuitry will switch to the built-
in lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile
states will be retained. PF will be driven to a logic 0. The User’s Guide has more information on this
topic. The trip points VCCMIN and VPFW are listed in the electrical specifications.
8 of 20
DS2251T
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Voltage on VCC Relative to Ground
Operating Temperature
-0.3V to (VCC + 0.5V)
-0.3V to +6.0V
-40°C to +85°C
-55°C to +125°C
260°C for 10 seconds
Storage Temperature2
Soldering Temperature
1This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
2Storage temperature is defined as the temperature of the device when VCC=0V and VLI=0V. In this state
the contents of SRAM are not battery-backed and are undefined.
DC CHARACTERISTICS
PARAMETER
(tA=0˚C to70˚C; VCC=5V ± 10%)
SYMBOL MIN TYP
MAX
UNITS NOTES
Input Low Voltage
VIL
VIH1
VIH2
VOL1
-0.3
2.0
3.5
+0.8
V
V
V
V
1
1
Input High Voltage
VCC+0.3
VCC+0.3
0.45
1
Input High Voltage RST, XTAL1 PROG
Output Low Voltage
0.15
1, 7
@ IOL=1.6 mA (Ports 1, 2, 3, PF )
Output Low Voltage
@ IOL=3.2 mA (Ports 0, ALE, PSEN ,
BA13-0, BD7-0, R/ W , PE 3-4)
VOL2
VOH1
0.15
4.8
0.45
V
V
1
1
Output High Voltage
@ IOH= -80 µA (Ports 1, 2, 3)
2.4
2.4
Output High Voltage
@ IOH=-400 µA (Ports 0, ALE, PSEN ,
PF , BA13-0, BD7-0, R/ W , PE 3-4)
VOH2
IIL
4.8
V
1
Input Low Current VIN = 0.45V
(Ports 1, 2, 3)
-50
µA
µA
µA
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
ITL
-500
Input Leakage Current
IIL
±10
0.45 < VIN < VCC (Port 0)
RST Pulldown Resistor
RRE
RVR
40
150
kΩ
kΩ
kΩ
V
4.7
40
VRST Pullup Resistor
RPR
PROG Pullup Resistor
Power-Fail Warning Voltage
Minimum Operating Voltage
Operating Current @ 16 MHz
Idle Mode Current @ 12 MHz
Stop Mode Current
VPFW
VCCmin
ICC
4.25 4.37
4.00 4.12
4.50
4.25
45
1
1
2
3
4
V
mA
mA
µA
IIDLE
ISTOP
9 of 20
7.0
80
DS2251T
PARAMETER
SYMBOL MIN TYP
MAX
UNITS NOTES
Pin Capacitance
CIN
10
pF
V
5
1
Reset Trip Point in Stop Mode
w/BAT=3.0V
w/BAT=3.3V
4.0
4.4
4.25
4.65
AC CHARACTERISTICS: EXPANDED
BUS MODE TIMING SPECIFICATIONS
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
1
2
3
4
5
PARAMETER
SYMBOL
MIN
MAX
UNITS
MHz
ns
Oscillator Frequency
1/tCLK
1.0
16 (-16)
ALE Pulse Width
tALPW
2tCLK -40
tCLK -40
tCLK -35
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr. In
tAVALL
tAVAAV
tALLVI
ns
ns
@ 12 MHz
@ 16 MHz
4tCLK -150
4tCLK -90
ns
6
7
8
tALLPSL
tPSPW
tCLK -25
ns
ns
ALE Low to PSEN Low
PSEN Pulse Width
3tCLK -35
tPSLVI
3tCLK -150
3tCLK -90
ns
ns
PSEN Low to Valid Instr. In
@ 12 MHz
@ 16 MHz
9
tPSIV
tPSIX
tPSAV
tAVVI
0
ns
ns
ns
Input Instr. Hold after PSEN Going High
Input Instr. Float after PSEN Going High
Address Hold after PSEN Going High
10
11
tCLK -20
tCLK -8
12 Address Valid to Valid Instr. In @ 12 MHz
@ 16 MHz
5tCLK -150
5tCLK -90
ns
ns
13
14
15
16
tPSLAZ
tRDPW
tWRPW
tRDLDV
0
ns
ns
ns
PSEN Low to Address Float
RD Pulse Width
6tCLK -100
6tCLK -100
WR Pulse Width
5tCLK -165
5tCLK -105
ns
ns
RD Low to Valid Data In
@ 12 MHz
@ 16 MHz
17
18
tRDHDV
tRDHDZ
tALLVD
0
ns
ns
Data Hold after RD High
Data Float after RD High
2tCLK -70
19 ALE Low to Valid Data In
@ 12 MHz
@ 16 MHz
8CLK -150
8tCLK -90
ns
ns
20 Valid Addr. to Valid Data In
@ 12 MHz
@ 16 MHz
tAVDV
9tCLK -165
9tCLK -105
ns
ns
21
22
23
24
tALLRDL
tAVRDL
tDVWRL
tDVWRH
3tCLK -50
4tCLK -130
tCLK -60
3tCLK +50
ns
ns
ns
ns
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Going Low
7tCLK -150
Data Valid to WR High
@ 12 MHz
10 of 20
DS2251T
UNITS
ns
#
PARAMETER
SYMBOL
MIN
7tCLK -90
MAX
@ 16 MHz
25
26
27
tWRHDV
tRDLAZ
tCLK -50
tCLK -40
ns
ns
ns
Data Valid after WR High
RD Low to Address Float
RD or WR High to ALE High
0
tRDHALH
tCLK +50
EXPANDED PROGRAM MEMORY READ CYCLE
11 of 20
DS2251T
EXPANDED DATA MEMORY READ CYCLE
EXPANDED DATA MEMORY WRITE CYCLE
12 of 20
DS2251T
AC CHARACTERISTICS (cont'd)
EXTERNAL CLOCK DRIVE
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
28 External Clock High Time
29 External Clock Low Time
30 External Clock Rise Time
31 External Clock Fall Time
@ 12 MHz
@ 16 MHz
tCLKHPW
20
15
ns
ns
@ 12 MHz
@ 16 MHz
tCLKLPW
tCLKR
20
15
ns
ns
@ 12 MHz
@ 16 MHz
20
15
ns
ns
@ 12 MHz
@ 16 MHz
tCLKF
20
15
ns
ns
EXTERNAL CLOCK TIMING
AC CHARACTERISTICS (cont'd)
POWER CYCLING TIMING
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
32 Slew Rate from VCCMIN to 3.3V
33 Crystal Startup Time
tF
130
µs
tCSU
tPOR
(note 6)
21504
34 Power-On Reset Delay
tCLK
13 of 20
DS2251T
POWER CYCLE TIMING
AC CHARACTERISTICS (cont'd)
SERIAL PORT TIMING - MODE 0
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
35 Serial Port Cycle Time
tSPCLK
12tCLK
µs
36 Output Data Setup to Rising Clock Edge
37 Output Data Hold after Rising Clock Edge
38 Clock Rising Edge to Input Data Valid
39 Input Data Hold after Rising Clock Edge
tDOCH
10tCLK -133
2tCLK -117
ns
tCHDO
ns
tCHDV
10tCLK -133
ns
tCHDIV
0
ns
14 of 20
DS2251T
SERIAL PORT TIMING - MODE 0
AC CHARACTERISTICS (cont'd)
PARALLEL PROGRAM LOAD TIMING
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
41
45
tCEPW
4tCLK-35
4tCLK-30
ns
Pulse Width of PE 3-4
tCEHDA
ns
Byte-wide Address Hold after PE 3-4 High
During MOVX
46
47
48
49
50
tCELDA
tDACEH
tCEHDV
tAVRWL
tRWLDV
4tCLK-35
1tCLK+40
10
ns
ns
ns
ns
ns
Delay from Byte-wide Address Valid PE 3-4
Low During MOVX
Byte-wide Data Setup to PE 3-4 High During
MOVX (read)
Byte-wide Data Hold after PE 3-4 High
During MOVX (read)
3tCLK-35
20
Byte-wide Address Valid to R/ W Active
During MOVX (write)
Delay from R/ W Low to Valid Data Out
During MOVX (write)
51
52
53
tCEHDV
tRWHDV
tRWLPW
1tCLK-15
0
ns
ns
ns
Valid Data Out Hold Time from PE 3-4 High
Valid Data Out Hold Time from R/ W High
Write Pulse Width (R/ W Low Time)
6tCLK-20
15 of 20
DS2251T
BYTE-WIDE BUS TIMING
RPC AC CHARACTERISTICS - DBB READ
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
54
55
56
57
58
59
tAR
0
ns
CS , A0 Setup to RD
CS , A0 Hold After RD
RD Pulse Width
tRA
0
ns
tRR
160
ns
tAD
130
130
85
ns
CS , A0 to Data Out Delay
RD to Data Out Delay
RD to Data Float Delay
tRD
0
ns
tRDZ
ns
RPC AC CHARACTERISTICS - DBB READ
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
60
tAW
0
ns
CS , A0 Setup to WR
CS , Hold After WR
A0, Hold After WR
WR Pulse Width
61A
61B
62
tWA
0
ns
tWA
20
20
130
20
ns
tWW
ns
63
tDW
ns
Data Setup to WR
Data Hold After WR
64
tWD
ns
16 of 20
DS2251T
AC CHARACTERISTICS - DMA
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
65
66
67
68
tACC
0
0
0
ns
ns
ns
ns
DACK to WR or RD
RD or WR to DACK
DACK to Data Valid
RD or WR to DRQ Cleared
tCAC
tACD
130
110
tCRQ
RPC TIMING MODE 16
AC CHARACTERISTICS - PROG
(tA=0˚C to70˚C; VCC=5V ± 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
CLKS
CLKS
69
70
tPRA
48
PROG Low to Active
PROG High to Inactive
tPRI
48
17 of 20
DS2251T
RPC TIMING MODE 16 (cont'd)
NOTES:
1. All voltages are referenced to ground.
2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR
tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC.
,
3. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10
ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = VSS.
4. Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not
connected; RST = XTAL1 = VSS.
5. Pin capacitance is measured with a test frequency - 1 MHz, tA = 25°C.
6. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from
the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for a worst case specification on this time.
7. PF pin operation is specified with VBAT ≥ 3.0V.
18 of 20
DS2251T
PACKAGE DRAWING
PKG
DIM
A
INCHES
MIN
MAX
4.255
3.989
1.005
0.405
0.255
4.245
3.979
0.995
0.395
0.245
B
C
D
E
F
0.050 BSC
G
H
0.075
0.245
0.085
0.255
I
1.750 BSC
J
0.120
2.120
2.245
0.057
-
0.130
2.130
2.255
0.067
0.275
0.145
0.054
K
L
M
N
O
P
-
0.047
19 of 20
DS2251T
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/13/95 and 08/13/96 version of the DS2251T data
sheet. Please review this summary carefully.
1. Change VCC slew rate definition to reference 3.3V instead of VLI.
2. Add minimum value to PCB thickness.
The following represent the key differences between 08/15/96 and 05/29/97 version of the DS2251T data
sheet. Please review this summary carefully.
1. PF signal moved from VOL2 test specification to VOL1. (PCND73001)
The following represent the key differences between 05/28/97 and 11/08/99 version of the DS2251T data
sheet. Please review this summary carefully. (PCN I80903)
1. Correct Absolute Maximum Ratings to reflect changes to DS5001FP microprocessor.
2. Add note clarifying that SRAM contents are not defined under storage temperature conditions.
The following represent the key differences between 11/08/99 and 01/18/00 version of the DS2251T data
sheet. Please review this summary carefully.
1. Document converted from interleaf to Microsoft Word.
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