DS2252T-128-16 [DALLAS]
Secure Microcontroller Module; 安全微控制器模块
| 型号： | DS2252T-128-16 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Secure Microcontroller Module |
| 文件： | 总14页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2252T
DS2252T
Secure Microcontroller Module
FEATURES
PACKAGE OUTLINE
• 8051 compatible microcontroller for secure/sensitive
applications
–
32K, 64K, or 128K bytes of nonvolatile SRAM
for program and/or data storage
1
20
21
40
–
–
In–system programming via on–chip serial port
Capable of modifying its own program or data
memory in the end system
40-Pin SIMM
• Firmware Security Features:
–
–
–
–
–
–
Memory stored in encrypted form
Encryption using on–chip 64–bit key
Automatic true random key generator
SDI Self Destruct Input
DESCRIPTION
The DS2252T is an 8051 compatible microcontroller
based on nonvolatile RAM technology. It is designed for
systems that need to protect memory contents from dis-
closure. This includes key data, sensitive algorithms,
andproprietaryinformationofalltypes. Likeothermem-
bers of the Secure Microcontroller family, it provides full
compatibility with the 8051 instruction set, timers, serial
port, and parallel I/O ports. By using NVRAM instead of
ROM, the user can program, then reprogram the micro-
controller while in–system. This allows frequent chang-
ing of sensitive processes with minimal effort. The
DS2252T provides an array of mechanisms to prevent
an attacker from examining the memory. It is designed
to resist all levels of threat including observation, analy-
sis, and physical attack. As a result, a massive effort
would be required to obtain any information about
memory contents. Furthermore, the “Soft” nature of the
DS2252T allows frequent modification of secure
information. This minimizes that value of any informa-
tion that is obtained.
Improved security over previous generations
Protects memory contents from piracy
• Crashproof Operation
–
Maintains all nonvolatile resources for over 10
years in the absence of power
–
–
–
–
Power–fail Reset
Early Warning Power–fail Interrupt
Watchdog Timer
Precision reference for power monitor
• Fully 8051 Compatible
–
–
–
–
128 bytes scratchpad RAM
Two timer/counters
On–chip serial port
32 parallel I/O port pins
• Permanently powered real time clock
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
121395 1/14
DS2252T
Using a security system based on the DS5002FP, the
DS2252T protects the memory contents from disclo-
sure. It loads program memory via its serial port and
encrypts it in real–time prior to storing it in SRAM. Once
encrypted, the RAM contents and the program flow are
unintelligible. The real data exists only inside the pro-
cessor chip after being decrypted. Any attempt to dis-
cover the on–chip data, encryption keys, etc., results in
its destruction. Extensive use of nonvolatile lithium
backed technology create a microcontroller that retains
data for over 10 years at room temperature, but which
can be erased instantly if tampered with. The DS2252T
even interfaces directly to external tamper protection
hardware.
Power–fail Reset, Power–fail Interrupt, and Watchdog
Timer. All nonvolatile memory and resources are main-
tained for over 10 years at room temperature in the
absence of power.
A user loads programs into the DS2252T via its on–chip
Serial Bootstrap Loader. This function supervises the
loading of software into NVRAM, validates it, then
becomes transparent to the user. It also manages the
loading of new encryption keys automatically. Software
is stored in on–board CMOS SRAM. Using its internal
Partitioning, the DS2252T can divide a common RAM
into user selectable program and data segments. This
Partition can be selected at program loading time, but
can be modified anytime later. The microcontroller will
decode memory access to the SRAM, access memory
viaitsByte–widebusandwrite–protectthememorypor-
tion designated as program (ROM).
The DS2252T provides a permanently powered real
time lock with interrupts for time stamp and date. It
keeps time to one hundredth of a second using its on–
board 32 KHz crystal.
A detailed summary of the security features is provided
in the User’s Guide section of the Secure Microcontrol-
ler data book. An overview is also available in the
DS5002FP data sheet.
Like other Secure Microcontrollers in the family, the
DS2252T provides crashproof operation in portable
systems or systems with unreliable power. These fea-
tures include the ability to save the operating state,
ORDERING INFORMATION
PART NUMBER
DS2252T–32–16
RAM SIZE
32K bytes
64K bytes
128K bytes
MAX CRYSTAL SPEED
16 MHz
TIMEKEEPING?
Yes
Yes
Yes
DS2252T–64–16
DS2252T–128–16
16 MHz
16 MHz
Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data
sheet provides ordering information, pinout, and electrical specifications.
121395 2/14
DS2252T
DS2252T BLOCK DIAGRAM Figure 1
DS2252T
+3V
V
CC
V
CCO
RST
BYTE–WIDE
ADDRESS BUS
ALE
32K OR 128K
SRAM
XTAL1
XTAL2
GND
BYTE–WIDE
DATA BUS
DS5002FP
PROG
SDI
CE1
R/W
P0.0–0.7
P1.0–1.7
P2.0–2.7
P3.0–3.7
32K
SRAM
(–64 only)
CE2
PE1
DS1283
REAL TIME
CLOCK
P3.2
INTP
121395 3/14
DS2252T
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
P1.0
11
12
13
14
15
16
17
18
19
20
P1.5
21
22
23
24
25
26
27
28
29
30
P3.1 TXD
ALE
31
32
33
34
35
36
37
38
39
40
P3.6 WR
P2.4
V
CC
P0.4
P1.1
P0.0
P1.2
P0.1
P1.3
P0.2
P1.4
P0.3
P1.6
P3.2 INT0
PROG
P3.7 RD
P2.3
P0.5
P1.7
P3.3 INT1
P2.7
XTAL2
P2.2
P0.6
RST
P3.4 T0
P2.6
XTAL1
P2.1
P0.7
P3.0 RXD
SDI
P3.5 T1
P2.5
GND
P2.0
PIN DESCRIPTION
PIN
DESCRIPTION
4, 6, 8, 10,
P0.0 – P0.7. General purpose I/O Port 0. This port is open–drain and can not drive a logic 1.
12, 14, 16, 18 It requires external pull–ups. Port 0 is also the multiplexed Expanded Address/Data bus.
When used in this mode, it does not require pull–ups.
1, 3, 5, 7, 9, P1.0 – P1.7. General purpose I/O Port 1.
11, 13, 15
40, 38, 36,
34, 32, 30,
28, 26
P2.0 – P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address
bus.
19
21
23
25
P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on
board UART. This pin should NOT be connected directly to a PC COM port.
P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on
board UART. This pin should NOT be connected directly to a PC COM port.
P3.2 INT0. General purpose I/O port pin 3.2. Also serves as the active low External Interrupt
0. This pin is also connected to the INTP output of the DS1283 Real Time Clock.
P3.3 INT1. General purpose I/O port pin 3.3. Also serves as the active low External
Interrupt 1.
27
29
31
P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus
operation.
33
17
P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus
operation.
RST – Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally, can be left unconnected if not used. An RC power–on reset circuit
is not needed and is NOT recommended.
22
ALE – Address Latch Enable. Used to de–multiplex the multiplexed Expanded Address/Data
bus on Port 0. This pin is normally connected to the clock input on a ’373 type transparent
latch.
121395 4/14
DS2252T
PIN
DESCRIPTION
35, 37
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the
input to an inverting amplifier and XTAL2 is the output.
39
2
GND – Logic ground.
V
CC
– +5V.
24
PROG – Invokes the Bootstrap loader on a falling edge. This signal should be debounced so
that only one edge is detected. If connected to ground, the microcontroller will enter Boot-
strap loading on power up. This signal is pulled up internally.
20
SDI – Self Destruct Input. A logic 1 applied to this input causes a hardware unlock. This
involves the destruction of Encryption Keys, Vector RAM, and the momentary removal of
power from V
. This pin should be grounded if not used.
CCO
are available to the Byte–wide bus. This preserves the
I/O ports for application use. An alternate configuration
allows dynamic Partitioning of a 64K space as shown in
Figure 3. Any data area not mapped into the NVRAM is
reached via the Expanded bus on Ports 0 and 2. Off–
board program memory is not available for security rea-
sons. Selecting PES=1 provides access to the Real–
time Clock as shown in Figure 4. These selections are
made using Special Function Registers. The memory
map and its controls are covered in detail in the User’s
Guide section of the Secure Microcontroller Data Book.
INSTRUCTION SET
The DS2252T executes an instruction set that is object
code compatible with the industry standard 8051 micro-
controller. As a result, software development packages
such as assemblers and compilers that have been writ-
ten for the 8051 are compatible with the DS2252T. A
completedescriptionoftheinstructionsetandoperation
are provided in the User’s Guide section of the Secure
Microcontroller Data Book.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the
DS2252T. The entire 64K of program and 64K of data
121395 5/14
DS2252T
DS2252T MEMORY MAP IN NON–PARTITIONABLE MODE (PM=1) Figure 2
PROGRAM MEMORY
DATA MEMORY (MOVX)
FFFFh
64K
NVRAM
PROGRAM
NVRAM
DATA
0000h
DS2252T MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3
PROGRAM MEMORY
DATA MEMORY (MOVX)
FFFFh
NVRAM
DATA
PARTITION
NVRAM
PROGRAM
0000h
NOTE: PARTITIONABLE MODE IS NOT SUPPORTED ON THE 128KB VERSION OF THE DS2252T.
LEGEND:
=
=
NVRAM MEMORY
= NOT AVAILABLE
EXPANDED BUS (PORTS 0 AND 2)
121395 6/14
DS2252T
DS2252T MEMORY MAP WITH (PES=1) Figure 4
PROGRAM MEMORY
FFFFh
DATA MEMORY (MOVX)
64K
C000h
PARTITION
8000h
NVRAM
PROGRAM
4000h
0000h
16K
REAL–TIME
CLOCK
NOT ACCESSIBLE
performed unless power rises back above V
. All
POWER MANAGEMENT
CCMIN
The DS2252T monitors V
to provide Power–fail
decoded chip enables and the R/W signal go to an inac-
tive (logic 1) state. V is still the power source at this
CC
Reset, early warning Power–fail Interrupt, and switch
over to lithium backup. It uses an internal band–gap ref-
erence in determining the switch points. These are
CC
time. When V drops further to below V , internal cir-
CC
LI
cuitry will switch to the built–in lithium cell for power. The
majority of internal circuits will be disabled and the
remaining nonvolatile states will be retained. The
User’sGuidehasmoreinformationonthistopic.Thetrip
called V
, V
, and V respectively. When V
PFW CCMIN LI CC
drops below V
, the DS2252T will perform an inter-
PFW
rupt vector to location 2Bh if the power fail warning was
enabled. Full processor operation continues regard-
pointsV
andV
arelistedintheelectricalspec-
PFW
CCMIN
less. When power falls further to V
, the DS2252T
ifications.
CCMIN
invokes a reset state. No further code execution will be
121395 7/14
DS2252T
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–0.3V to +7.0V
0°C to 70°C
Storage Temperature
Soldering Temperature
–40°C to +70°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
DC CHARACTERISTICS
PARAMETER
(tA=0°C to 70°C; VCC=5V ± 10%)
SYMBOL
MIN
–0.3
2.0
TYP
MAX
UNITS
NOTES
Input Low Voltage
V
IL
+0.8
V
V
V
1
1
1
Input High Voltage
V
V
V
+0.3
IH1
IH2
CC
CC
Input High Voltage (RST, XTAL1,
PROG)
V
3.5
+0.3
Output Low Voltage
V
V
0.15
0.15
4.8
0.45
0.45
V
V
1
1
1
1
OL1
OL2
OH1
OH2
@ I =1.6 mA (Ports 1, 2, 3)
OL
Output Low Voltage
@ I =3.2 mA (Ports 0, ALE)
OL
Output High Voltage
V
V
2.4
2.4
V
@ I =–80 µA (Ports 1, 2, 3)
OH
Output High Voltage
4.8
V
@ I =–400 µA (Ports 0, ALE)
OH
Input Low Current V =0.45V
(Ports 1, 2, 3)
I
–50
–500
±10
µA
µA
µA
IN
IL
Transition Current; 1 to 0
I
TL
V
IN
=2.0V (Ports 1, 2, 3)
Input Leakage Current
0.45<V <V (Port 0)
I
IL
IN
CC
RST Pulldown Resistor
Power Fail Warning Voltage
Minimum Operating Voltage
Operating Current @ 16 MHz
Idle Mode Current @ 12 MHz
Stop Mode current
R
40
150
4.50
4.25
45
KΩ
V
RE
V
PRW
4.25
4.00
4.37
4.12
1
1
4
5
6
7
1
V
V
CCMIN
I
mA
mA
µA
pF
V
CC
I
7.0
80
IDLE
I
STOP
Pin Capacitance
C
10
IN
Reset Trip Point in Stop Mode
w/BAT=3.0V
w/BAT=3.3V
4.0
4.4
4.25
4.65
SDI Input Low Voltage
SDI Input High Voltage
SDI Input High Voltage
SDI Pull–Down Resistor
V
0.4
V
V
1
ILS
IHS
IHS
SDI
V
V
R
2.0
2.0
25
V
CC
1, 2
1, 2
3.5
60
V
KΩ
121395 8/14
DS2252T
AC CHARACTERISTICS
PARAMETER
(tA = 0°C to70°C; VCC=0V to 5V)
SYMBOL
MIN
TYP
MAX
UNITS
µs
NOTES
SDI Pulse Reject
SDI Pulse Accept
t
2
3
3
SPR
t
10
µs
SPA
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
(tA = 0°C to70°C; VCC = 5V + 10%)
#
1
2
3
4
PARAMETER
SYMBOL
MIN
MAX
UNITS
MHz
ns
Oscillator Frequency
ALE Pulse Width
1/t
1.0
16 (–16)
CLK
ALPW
AVALL
AVAAV
t
2t
–40
CLK
Address Valid to ALE Low
Address Hold After ALE Low
t
t
t
–40
ns
CLK
CLK
CLK
CLK
t
–35
ns
14 RD Pulse Width
15 WR Pulse Width
t
6t
6t
–100
–100
ns
RDPW
t
ns
WRPW
RDLDV
16 RD Low to Valid Data In @12 MHz
@16 MHz
t
5t
5t
–165
–105
ns
ns
CLK
CLK
17 Data Hold after RD High
18 Data Float after RD High
t
0
ns
ns
RDHDV
t
2t
CLK
–70
RDHDZ
19 ALE Low to Valid Data In @12 MHz
@16 MHz
t
8t
8t
–150
ns
ns
ALLVD
CLK
–90
CLK
20 Valid Addr. to Valid Data In @12 MHz
@16 MHz
t
9t
CLK
9t
CLK
–165
–105
ns
ns
AVDV
21 ALE Low to RD or WR Low
22 Address Valid to RD or WR Low
23 Data Valid to WR Going Low
t
3t
–50
3t
CLK
+50
ns
ns
ns
ALLRDL
CLK
t
4t
t
–130
–60
AVRDL
CLK
CLK
CLK
t
DVWRL
24 Data Valid to WR High @12 MHz
@16 MHz
t
7t
–150
–90
ns
ns
DVWRH
7t
CLK
25 Data Valid after WR High
26 RD Low to Address Float
27 RD or WR High to ALE High
t
t
–50
ns
ns
ns
WRHDV
CLK
t
0
RDLAZ
t
t
–40
t
+50
RDHALH
CLK
CLK
121395 9/14
DS2252T
EXPANDED DATA MEMORY READ CYCLE
2
27
ALE
19
21
14
26
RD
16
18
3
17
4
A7–A0
(Rn OR DPL)
A7–A0
(PCL)
INSTR
IN
DATA IN
PORT 0
22
20
PORT 2
P2.7–P2.0 OR A15–A8 FROM DPH
A15–A8 FROM PCH
EXPANDED DATA MEMORY WRITE CYCLE
27
ALE
21
15
WR
23
25
4
24
3
A7–A0
(Rn OR DPL)
A7–A0
(PCL)
INSTR
IN
PORT 0
DATA OUT
22
PORT 2
P2.7–P2.0 OR A15–A8 FROM DPH
A15–A8 FROM PCH
121395 10/14
DS2252T
AC CHARACTERISTICS (cont’d)
EXTERNAL CLOCK DRIVE
(tA = 0°C to70°C; VCC = 5V + 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
28 External Clock High Time @12 MHz
@16 MHz
t
20
15
ns
ns
CLKHPW
29 External Clock Low Time @12 MHz
@16 MHz
t
20
15
ns
ns
CLKLPW
30 External Clock Rise Time @12 MHz
@16 MHz
t
20
15
ns
ns
CLKR
31 External Clock Fall Time @12 MHz
@16 MHz
t
20
15
ns
ns
CLKF
EXTERNAL CLOCK TIMING
28
29
30
31
1
AC CHARACTERISTICS (cont’d)
POWER CYCLING TIMING
(tA = 0°C to70°C; VCC = 5V + 10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
32 Slew Rate from V
to V
t
F
130
µs
CCMIN
LI
33 Crystal Start up Time
34 Power On Reset Delay
t
(note 8)
21504
CSU
POR
t
t
CLK
121395 11/14
DS2252T
POWER CYCLE TIMING
V
CC
V
PFW
V
CCMIN
V
LI
32
INTERRUPT
SERVICE
ROUTINE
33
CLOCK
OSC
34
INTERNAL
RESET
LITHIUM
CURRENT
AC CHARACTERISTICS (cont’d)
SERIAL PORT TIMING – MODE 0
(tA = 0°C to70°C; VCC = 5V + 10%)
#
PARAMETER
SYMBOL
MIN
12t
MAX
UNITS
µs
35 Serial Port Clock Cycle Time
t
SPCLK
CLK
36 Output Data Setup to Rising Clock Edge
37 Output Data Hold after Rising Clock Edge
38 Clock Rising Edge to Input Data Valid
39 Input Data Hold after Rising Clock Edge
t
10t
–133
ns
DOCH
CHDO
CLK
t
2t
CLK
–117
ns
t
10t
–133
ns
CHDV
CLK
t
0
ns
CHDIV
121395 12/14
DS2252T
SERIAL PORT TIMING – MODE 0
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
35
CLOCK
36
37
DATA OUT
0
1
2
3
4
5
6
7
SET TI
WRITE TO
SBUF REGISTER
39
38
SET RI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
NOTES:
1. All voltage referenced to ground.
2. SDI should be taken to a logic high when V =+5V, and to approximately 3V when V <3V.
CC
CC
3. SDI is deglitched to prevent accidental destruction. The pulse must be longer than t
to pass the deglitch-
SPR
er, but SDI is not guaranteed unless it is longer than t
.
SPA
4. Maximum operating I is measured with all output pins disconnected; XTAL1 driven with t
,
CLKR
CC
t
=10 ns, V = 0.5V; XTAL2 disconnected; RST = PORT0 = V
.
CC
CLKF
IL
5. Idle mode I
is measured with all output pins disconnected; XTAL1 driven with t
, t
= 10 ns,
IDLE
CLKR CLKF
V
IL
= 0.5V; XTAL2 disconnected; PORT0 = V , RST = V
.
SS
CC
6. Stop mode I
is measured with all output pins disconnected; PORT0 = V ; XTAL2 not connected;
CC
STOP
RST = XTAL1 = V
.
SS
7. Pin capacitance is measured with a test frequency – 1 MHz, t = 25°C.
A
8. Crystal start–up time is the time required to get the mass of the crystal into vibrational motion from the time
that power is first applied to the circuit until the first clock pulse is produced by the on–chip oscillator. The
user should check with the crystal vendor for a worst case specification on this time.
121395 13/14
DS2252T
PACKAGE DRAWING
P
(SIDE B)
(SIDE A)
O
N
A
U1B
U1A
U3
U2
J
(SIDE B)
C
M
D
C
L
E
G
I
I
H
K
L
F
PKG
DIM
A
40–PIN
MIN
MAX
2.655
2.389
1.005
0.405
0.255
2.645
2.379
0.995
0.395
0.245
B
C
D
E
F
0.050 BSC
G
H
0.075
0.085
0.255
0.245
I
0.950 BSC
J
0.120
1.320
1.445
0.057
–
0.130
1.330
1.455
0.067
0.300
0.165
0.054
K
L
M
N
O
P
–
–
121395 14/14
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